Page 1
anyCAP® 100 mA
C
www.BDTIC.com/ADI
FEATURES
±1.2% accuracy over line and load regulations @ 25°C
Ultralow dropout voltage: 120 mV typical @ 100 mA
Requires only C
anyCAP LDOs are stable with all types of capacitors
(including ML
Current and thermal limiting
Low noise
Low shutdown current: 1 μA
2.8 V to 12 V supply range
−20°C to +85°C ambient temperature range
Several fixed voltage options
Ultrasmall 5-lead SOT-23 package
Excellent line and load regulations
APPLICATIONS
Cellular telephones
Notebook, palmtop computers
Battery-powered systems
PCMCIA regulator
Bar code scanners
Camcorders, cameras
= 0.47 μF for stability
OUT
CC)
Low Dropout Linear Regulator
ADP3309
FUNCTIONAL BLOCK DIAGRAM
ADP3309
CC
g
m
BANDGAP
OUTIN
R1
R2
REF
ERR/N
Q1
THERMAL
PROTECTION
Q2
SD
DRIVER
GND
Figure 1.
00141-001
GENERAL DESCRIPTION
The ADP3309 is a member of the ADP330x family of precision
low dropout anyCAP voltage regulators. It is pin-for-pin and
functionally compatible with National’s LP2981, but offers
performance advantages. The ADP3309 stands out from
conventional LDOs with a novel architecture and an enhanced
process. Its patented design requires only a 0.47 μF output
capacitor for stability. This device is stable with any type of
capacitor regardless of its equivalent series resistance (ESR)
value, including ceramic types for space restricted applications.
The ADP3309 achieves ±1.2% accuracy at room temperature
and ±2.2% overall accuracy over temperature, line, and load
regulations. The dropout voltage of the ADP3309 is only
120 mV (typical) at 100 mA. This device also includes a current
limit and a shutdown feature. In shutdown mode, the ground
current is reduced to ~1 μA.
The ADP3309 operates with a wide input voltage range from
2.8 V t
o 12 V and delivers a load current in excess of 100 mA.
The ADP3309 anyCAP LDO offers a wide range of output
voltages.
4
V
IN
0.47µF
ERR/NC
C1
ADP3309-3.3
1
IN
+
–
3
OFF
SD
Figure 2. Typical Application Circuit
ON
OUT
GND
5
+
C2
0.47µF
–
2
V
= 3.3V
OUT
00141-002
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
Page 2
ADP3309
www.BDTIC.com/ADI
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Typical Performance Characteristics ............................................. 6
Theory of Operation ........................................................................ 9
Application Information................................................................ 10
REVISION HISTORY
12/06—Rev. B to Rev. C
Change to Table 1 ............................................................................. 3
Updated Outline Dimensions....................................................... 12
Changes to the Ordering Guide.................................................... 12
7/04—Rev. A to Rev. B.
Changes to the Ordering Guide...................................................... 3
Updated Outline Dimensions......................................................... 8
12/00—Rev. 0 to Rev. A
9/98—Revision 0: Initial Version
Capacitor Selection: anyCAP.................................................... 10
Thermal Overload Protection .................................................. 10
Calculating Junction Temperature ........................................... 10
Printed Circuit Board Layout Consideration......................... 10
Shutdown Mode ......................................................................... 10
Error Flag Dropout Detector .................................................... 10
Application Circuits ....................................................................... 11
Crossover Switch ........................................................................ 11
Higher Output Current ............................................................. 11
Constant Dropout Post Regulator............................................ 11
Outline Dimensions ....................................................................... 12
Ordering Guide .......................................................................... 12
Rev. C | Page 2 of 12
Page 3
ADP3309
www.BDTIC.com/ADI
SPECIFICATIONS
@ TA = −20°C to +85°C, VIN = 7 V, CIN = 0.47 μF, C
options.
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
Output Voltage Accuracy V
I
V
I
Line Regulation
Load Regulation
Ground Current I
I
Ground Current in Dropout I
Dropout Voltage V
I
I
I
Shutdown Threshold V
Off 0.3 V
Shutdown Pin Input Current I
5 < VSD ≤ 12 V @ VIN = 12 V 9 μA
Ground Current in Shutdown Mode IQ VSD = 0 V, VIN = 12 V, TA = 25°C 0.005 1 μA
V
Output Current in Shutdown Mode I
T
Error Pin Output Leakage IEL VEO = 5 V 13 μA
Error Pin Output Low Voltage V
Peak Load Current I
Output Noise @ 5 V Input V
1
Ambient temperature of 85°C corresponds to a junction temperature of 125°C under typical full load test conditions.
= 0.47 μF, unless otherwise noted.1 The following specifications apply to all voltage
OUT
VIN = V
OUT
= 0.1 mA to 100 mA, TA = 25°C
L
= V
IN
= 0.1 mA to 100 mA
L
V
= V
ΔV
OUT
ΔV
IN
ΔV
OUT
ΔI
L
IL = 100 mA 0.8 2.0 mA
GND
VIN = 2.4 V, IL = 0.1 mA 0.9 1.7 mA
GND
V
DROP
On 2.0 V
THSD
0 < VSD ≤ 5 V 1 μA
SDIN
TA = 25°C @ VIN = 12 V 2 μA
OSD
EOL
VIN = V
LDPK
f = 10 Hz to 100 kHz 100 μV rms
NOISE
IN
= 25°C
T
A
I
= 0.1 mA to 100 mA, TA = 25°C 0.06 mV/mA
L
= 0.1 mA 0.19 0.3 mA
L
= 98% of V
OUT
= 100 mA 0.12 0.25 V
L
= 10 mA 0.025 0.07 V
L
= 1 mA 0.004 0.015 V
L
= 0 V, VIN = 12 V, TA = 85°C 0.01 3 μA
SD
= 85°C @ VIN = 12 V 4 μA
A
I
= 400 μA 0.12 0.3 V
SINK
+ 0.3 V to 12 V, −1.2 +1.2 %
OUTNOM
+ 0.3 V to 12 V, −2.2 +2.2 %
OUTNOM
+ 0.3 V to 12 V,
OUTNOM
OUTNOM
+ 1 V, TA = 25°C 150 mA
OUTNOM
0.02 mV/V
Rev. C | Page 3 of 12
Page 4
ADP3309
www.BDTIC.com/ADI
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Input Supply Voltage −0.3 V to +16 V
Shutdown Input Voltage −0.3 V to +16 V
Power Dissipation Internally Limited
Operating Ambient Temperature Range −55°C to +125°C
Operating Junction Temperature Range −55°C to +125°C
θ
JA
θ
JC
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering 10 sec) 300°C
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
190°C/W
92°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. C | Page 4 of 12
Page 5
ADP3309
www.BDTIC.com/ADI
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
GND
SD
IN
ADP3309
2
TOP VIEW
(Not to Scale)
3
5
3
OUT
ERR/NC
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 IN Regulator Input.
2 GND Ground Pin.
3
Active Low Shutdown Pin. Connect to ground to disable the regulator output. When shutdown is not used, this
SD
pin should be connected to the input pin.
4
/NC Open Collector. Output that goes low to indicate the output is about to go out of regulation. This pin can be left
ERR
open. (NC = No Connect).
5 OUT
Output of the Regulator. Fixed 2.5 V, 2.7 V, 2.85 V, 2.9 V, 3.0
a 0.47 μF or larger capacitor.
NC = NO CONNECT
Figure 3. Pin Configuration
00141-003
V, 3.3 V, or 3.6 V output voltage. Bypass to ground with
Rev. C | Page 5 of 12
Page 6
ADP3309
www.BDTIC.com/ADI
TYPICAL PERFORMANCE CHARACTERISTICS
3.302
3.301
3.300
3.299
IL = 0mA
IL = 10mA
V
= 3.3V
OUT
900
IL = 0 TO 100mA
750
600
3.298
OUTPUT VOLTAGE (V)
3.297
3.296
3.295
3.3 4 5 6 7 8 9 10 11 12 13 14
IL = 50mA
IL = 100mA
INPUT VOLTAGE (V)
Figure 4. Line Regulation: Output Voltage vs. Supply Voltage
3.302
V
= 3.3V
OUT
V
= 7V
3.301
3.300
3.299
3.298
OUTPUT VOLTAGE (V)
3.297
3.296
3.295
0 102030405060708090100
OUTPUT LOAD (mA)
IN
Figure 5. Output Voltage vs. Load Current
450
GROUND CURRENT (µA)
300
150
0 25 50 75 100
00141-004
OUTPUT L OAD (mA)
00141-007
Figure 7. Quiescent Current vs. Load Current
0.2
0.1
0
–0.1
–0.2
OUTPUT VO LTAGE (%)
–0.3
–0.4
00141-005
–45 –25 –5 15 35 55 75 95 115 135
IL = 50mA
IL = 100mA
TEMPERATURE (° C)
IL = 0mA
00141-008
Figure 8. Output Voltage Variation % vs. Temperature
1150
900
650
400
GROUND CURRENT (µA)
150
0
0 1. 2 2.4 3.6 4.8 6. 0 7.2 8.4 9.6 10.8 12.0
INPUT VOLTAG E (V)
V
OUT
= 0mA
I
L
= 3.3V
00141-006
Figure 6. Quiescent Current vs. Supply Voltage
Rev. C | Page 6 of 12
1250
1000
750
500
GROUND CURRENT (µA)
250
0
–25 –5 15 35 55 75 95 115 13 5
IL = 100mA
IL = 0mA
TEMPERATURE (° C)
VIN = 7V
Figure 9. Quiescent Current vs. Temperature
00141-009
Page 7
ADP3309
www.BDTIC.com/ADI
120
96
3.32
3.31
3.30
V
= 3.3V
OUT
72
48
INPUT/OUTPUT VOLTAGE (mV)
24
0
025
50751
OUTPUT LO AD (mA)
Figure 10. Dropout Voltage vs. Output Current
5
4
3
2
INPUT/OUTPUT VOLTAGE (V)
1
0
01234321 0
INPUT VOLTAGE (V)
V
R
OUT
= 33Ω
L
= 3.3V
Figure 11. Power-Up/Power-Down
00
00141-010
00141-011
3.29
3.28
VOLTS
V
7.50
7.00
0 40 80 120 160 200 240 280 320 360 400
IN
TIME (µs)
RL = 33Ω
C
= 0.47µF
L
Figure 13. Line Transient Response
3.32
V
= 3.3V
3.31
3.30
3.29
3.28
VOLTS
7.50
7.00
0 20 40 60 80 100 120 140 160 180 200
OUT
RL = 3.3kΩ
C
= 0.47µF
L
V
IN
TIME (µs)
Figure 14. Line Transient Response
00141-013
00141-014
8
VSD = V
IN
CL = 0.47µF
7
R
= 33Ω
L
V
= 3.3V
OUT
6
5
4
3
2
INPUT/OUTPUT VOLTAGE (V)
1
0
0 20 40 60 80 100 120 140 160 180 200
V
V
OUT
TIME (µs)
IN
Figure 12. Power-Up Overshoot
00141-012
Rev. C | Page 7 of 12
3.32
V
= 3.3V
OUT
= 0.47µF
C
L
3.31
3.30
VOLTSmA
3.29
3.28
I
100
10
0 100 200 300 400 500
OUT
TIME (µs)
Figure 15. Load Transient
00141-015
Page 8
ADP3309
√
www.BDTIC.com/ADI
VOLTSmA
3.32
3.31
3.30
3.29
V
OUT
C
L
= 3.3V
= 4.7µF
4
3.3V
3
2
1
V
OUT
R
= 33Ω
L
C
= 0.47µF
L
= 3.3V
3.28
I
100
10
0 100 200 300 400 500
OUT
TIME (µs)
Figure 16. Load Transient
300
I
= 3.3V
OUT
V
OUT
TIME (Seconds)
200
100
0
4
2
VOLTS mA
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
V
OUT
Figure 17. Short-Circuit Current
VOLTS
0
3
V
0
00141-016
0102030405
TIME (µs)
SD
0
00141-019
Figure 19. Turn-Off
0
a. 0.47µF , RL = 33kΩ
–10
b. 0.47µF , R
c. 10µF, R
–20
d. 10µF, R
–30
–40
–50
–60
b
–70
RIPPLE REJECT ION (dB)
–80
–90
–100
00141-017
10 100 1k 10k 100k 1M 10M
a c
d
= 33Ω
L
= 33kΩ
L
= 33Ω
L
FREQUENCY (Hz)
Figure 20. Power Supply Ripple Reject
V
= 3.3V
OUT
b
d
a
c
00141-020
ion
4
3
CL = 0.47µF
2
CL = 4.7µF
1
VOLTS
0
3
0
0 20 40 60 80 100
TIME (µs)
V
OUT
3.3V
V
= 3.3V
OUT
= 33Ω
R
L
V
SD
3V
00141-018
Figure 18. Turn-On
10
V
Hz)
VOLTAGE NOISE SPECTRAL DENSIT Y (µV/
0.1
0.01
= 3.3V, CL = 0.47µF
OUT
I
= 1mA
L
1
100 1k 10k 100k
FREQUENCY (Hz)
Figure 21. Output Noise Density
00141-021
Rev. C | Page 8 of 12
Page 9
ADP3309
www.BDTIC.com/ADI
THEORY OF OPERATION
The ADP3309 anyCAP LDO uses a single control loop for
regulation and reference functions. The output voltage is sensed
by a resistive voltage divider consisting of R1 and R2, which is
varied to provide the available output voltage option. Feedback
is taken from this network by way of a series diode (D1) and a
second resistor divider (R3 and R4) to the input of an amplifier.
INPUT
Q1
NONINVERTING
WIDEBAND
DRIVER
ADP3309
COMPENSATION
CAPACITOR
g
m
Figure 22. Functional Block Diagram
PTAT
V
OS
ATTENUATI ON
(V
BANDGAP/VOUT
R4
GND
D1
R3
PTAT
CURRENT
OUTPUT
R1
)
(a)
R2
R
C
LOAD
LOAD
A very high gain error amplifier is used to control this loop. The
amplifier is constructed in such a way that at equilibrium, it
produces a large, temperature proportional input offset voltage
that is repeatable and very well controlled. The temperature
proportional offset voltage is combined with the complementary
diode voltage to form a virtual band gap voltage, implicit in the
network, although it never appears explicitly in the circuit.
Ultimately, this patented design makes it possible to control the
loop with only one amplifier. This technique also improves the
noise characteristics of the amplifier by providing more
flexibility on the trade-off of noise sources that leads to a low
noise design.
The R1, R2 divider is chosen in the same ratio as the band gap
oltage to the output voltage. Although the R1, R2 resistor
v
divider is loaded by the diode (D1), and a second divider
consisting of R3 and R4, the values can be chosen to produce a
temperature stable output.
00141-022
The patented amplifier controls a new and unique noninverting
iver that drives the pass transistor (Q1). The use of this
dr
special noninverting driver enables the frequency compensation
to include the load capacitor in a pole splitting arrangement to
achieve reduced sensitivity to the value, type, and ESR of the
load capacitance.
Most LDOs place very strict requirements on the range of ESR
val
ues for the output capacitor because they are difficult to
stabilize due to the uncertainty of load capacitance and
resistance. Moreover, the ESR value, required to keep
conventional LDOs stable, changes depending on load and
temperature. These ESR limitations make designing with LDOs
more difficult because of their unclear specifications and
extreme variations over temperature.
This is no longer true with the ADP3309 anyCAP LDO. It can
b
e used with virtually any capacitor, with no constraint on the
minimum ESR. This innovative design allows the circuit to be
stable with just a small 0.47 μF capacitor on the output.
Additional advantages of the design scheme include superior
line noise rejection and very high regulator gain, which leads to
excellent line, and load regulation. An impressive ±2.2%
accuracy is guaranteed over line, load, and temperature.
Additional features of the circuit include current limit and
th
ermal shutdown. Compared to the standard solutions that
give warning after the output has lost regulation, the ADP3309
provides improved system performance by enabling the
ERR
pin to give warning before the device loses regulation.
As the chip’s temperature rises above 165°C, the circuit activates
a
soft thermal shutdown, indicated by a signal low on the
ERR
pin, to reduce the current to a safe level.
Rev. C | Page 9 of 12
Page 10
ADP3309
www.BDTIC.com/ADI
APPLICATION INFORMATION
CAPACITOR SELECTION: anyCAP
Output Capacitors: As with any micropower device, output
transient response is a function of the output capacitance. The
ADP3309 is stable with a wide range of capacitor values, types,
and ESR (anyCAP). A capacitor as low as 0.47 μF is all that is
needed for stability. However, larger capacitors can be used if
high output current surges are anticipated. The ADP3309 is
stable with extremely low ESR capacitors (ESR ≈ 0), such as
multilayer ceramic capacitors (MLCC) or OSCON.
Input Bypass Capacitor: An input bypass capacitor is not
equired. However, for applications where the input source is
r
high impedance or far from the input pin, a bypass capacitor is
recommended. Connecting a 0.47 μF capacitor from the input
pin (Pin 1) to ground reduces the circuit’s sensitivity to PC
board layout. If a bigger output capacitor is used, the input
capacitor must be 1 μF minimum.
THERMAL OVERLOAD PROTECTION
The ADP3309 is protected against damage due to excessive
power dissipation by its thermal overload protection circuit,
which limits the die temperature to a maximum of 165°C.
Under extreme conditions (that is, high ambient temperature
and power dissipation) where die temperature starts to rise
above 165°C, the output current is reduced until the die
temperature has dropped to a safe level. The output current is
restored when the die temperature is reduced.
Current and thermal limit protections are intended to protect
he device against accidental overload conditions. For normal
t
operation, device power dissipation should be externally limited
so that junction temperatures do not exceed 125°C.
CALCULATING JUNCTION TEMPERATURE
Device power dissipation is calculated as follows:
P
= (VIN – V
D
where:
is the load current.
I
LOAD
is the ground current.
I
GND
V
is the input voltage.
IN
is the output voltage.
V
OUT
Assuming I
V
OUT
LOAD
= 3.3 V, device power dissipation is
= (5.0 − 3.3) 100 mA + 5.0 × 2 mA = 180 mW
P
D
ΔT = T
– TA = PD × θJA = 0.18 × 190 = 34.2°C
J
With a maximum junction temperature of 125°C, this yields a
max
imum ambient temperature of ~90°C.
) I
OUT
LOAD
= 100 mA, I
+ (VIN) I
GND
= 2 mA, VIN = 5.0 V, and
GND
PRINTED CIRCUIT BOARD LAYOUT CONSIDERATION
Surface-mount components rely on the conductive traces or
pads to transfer heat away from the device. Appropriate PC
board layout techniques should be used to remove heat from
the immediate vicinity of the package.
The following general guidelines will be helpful when designing
a b
oard layout:
board traces with larger cross section areas remove
1. PC
more heat. For optimum results, use PC boards with
thicker copper and/or wider traces.
ncrease the surface area exposed to open air so heat can be
2. I
removed by convection or forced air flow.
3. D
o not use solder mask or silk screen on the heat
dissipating traces because it increases the junction to
ambient thermal resistance of the package.
SHUTDOWN MODE
Applying a TTL high signal to the shutdown pin or tying it to
the input pin turns the output on. Pulling the shutdown pin
down to a TTL low signal or tying it to ground turns the output
off. In shutdown mode, quiescent current is reduced to less
than 1 μA.
ERROR FLAG DROPOUT DETECTOR
The ADP3309 maintains its output voltage over a wide range of
load, input voltage, and temperature conditions. If the output is
about to lose regulation, for example, by reducing the supply
voltage below the combined regulated output and dropout
voltages, the
ERR
pin will be activated. The
open collector that will be driven low.
ERR
Once set, the
or flag’s hysteresis keeps the output low until
a small margin of operating range is restored either by raising
the supply voltage or reducing the load.
ERR
output is an
Rev. C | Page 10 of 12
Page 11
ADP3309
V
V
www.BDTIC.com/ADI
APPLICATION CIRCUITS
CROSSOVER SWITCH
The circuit in Figure 23 shows that two ADP3309s can be used
to form a mixed supply voltage system. The output switches
between two different levels selected by an external digital
input. Output voltages can be any combination of voltages from
the
Ordering Guide of the data sheet.
V
= 4V TO 12V
IN
OUTPUT SEL ECT
4V
0V
1µF
C1
IN OUT
ADP3309-2.7
SD
IN OUT
+
ADP3309-3.3
SD
GND
+
GND
Figure 23. Crossover Switch
HIGHER OUTPUT CURRENT
The ADP3309 can source up to 100 mA without any heat sink
or pass transistor. If higher current is needed, an appropriate
pass transistor can be used, as in Figure 24, to increase the
o
utput current to 1 A.
= 2.5V TO 3. 5V
IN
C1
100µF
10V
R1
120Ω
I
LIM
ADP3000-ADJ
= 2.7V/3.3V
OUT
C2
0.47µF
00141-023
L1
6.8µF
V
IN
SW2GND
SW1
FB
D1
1N5817
Figure 25. Constant Dropout Post Regulator
C2
100µF
10V
2N3906
= 4V TO 8V
V
IN
MJE253*
47µF
C1
R1
50Ω
IN
ADP3309-3.3
SD
GND
*AAVID531002 HE AT SINK IS USED
OUT
ERR
V
= 3.3V @ 1A
OUT
+
C2
10µF
Figure 24. Higher Output Current Linear Regulator
CONSTANT DROPOUT POST REGULATOR
The circuit in Figure 25 provides high precision with low
dropout for any regulated output voltage. It significantly
reduces the ripple from a switching regulator while providing a
constant dropout voltage, which limits the power dissipation of
the LDO to 30 mW. The ADP3000 used in this circuit is a
switching regulator in the step-up configuration.
ADP3309-3.3
V
C3
2.2µF
= 3.3V @ 100mA
OUT
Q1
R2
30.1kΩ
1%
R3
124kΩ
1%
IN OUT
SD
GND
Q2
2N3906
R4
274kΩ
+
00141-024
00141-025
Rev. C | Page 11 of 12
Page 12
ADP3309
www.BDTIC.com/ADI
OUTLINE DIMENSIONS
2.90 BSC
5
1.60 BSC
123
PIN 1
1.30
1.15
0.90
0.15 MAX
COMPLIANT TO JEDEC STANDARDS MO-178-AA
Figure 26. 5-Lead Small Outline Transistor Package [SOT-23]
4
2.80 BSC
0.95 BSC
1.90
BSC
1.45 MAX
0.50
SEATING
0.30
PLANE
Dim
ensions shown in millimeters
(RJ-5)
0.22
0.08
10°
5°
0°
0.60
0.45
0.30
ORDERING GUIDE
Model Temperature Range Voltage Output Package Description Package Option Branding
ADP3309ART-2.5-RL −20°C to +85°C 2.5 V 5-Lead SOT-23 RJ-5 LDE
ADP3309ART-2.5-RL7 −20°C to +85°C 2.5 V 5-Lead SOT-23 RJ-5 LDE
ADP3309ARTZ-2.5RL7
ADP3309ART-2.7-RL −20°C to +85°C 2.7 V 5-Lead SOT-23 RJ-5
ADP3309ART-2.7-RL7 −20°C to +85°C 2.7 V 5-Lead SOT-23 RJ-5
ADP3309ARTZ-2.7-R7
ADP3309ART-2.85-R7 −20°C to +85°C 2.85 V 5-Lead SOT-23 RJ-5
ADP3309ART-2.85-RL −20°C to +85°C 2.85 V 5-Lead SOT-23 RJ-5
ADP3309ARTZ-2.85R7
ADP3309ART-2.9-RL −20°C to +85°C 2.9 V 5-Lead SOT-23 RJ-5
ADP3309ART-2.9-RL7 −20°C to +85°C 2.9 V 5-Lead SOT-23 RJ-5
ADP3309ARTZ-2.9-R7
ADP3309ART-3-REEL −20°C to +85°C 3.0 V 5-Lead SOT-23 RJ-5
ADP3309ART-3-REEL7 −20°C to +85°C 3.0 V 5-Lead SOT-23 RJ-5
ADP3309ARTZ-3REEL7
ADP3309ART-3.3-RL −20°C to +85°C 3.3 V 5-Lead SOT-23 RJ-5
ADP3309ART-3.3-RL7 −20°C to +85°C 3.3 V 5-Lead SOT-23 RJ-5
ADP3309ARTZ-3.3-R7
ADP3309ART-3.6-RL −20°C to +85°C 3.6 V 5-Lead SOT-23 RJ-5
ADP3309ART-3.6-RL7 −20°C to +85°C 3.6 V 5-Lead SOT-23 RJ-5
ADP3309ARTZ-3.6-R7
1
Z = Pb-free part, # denotes lead-free product may be top or bottom marked.
1
−20°C to +85°C 2.5 V 5-Lead SOT-23 RJ-5 LDE#
DNC
DNC
1
−20°C to +85°C 2.7 V 5-Lead SOT-23 RJ-5 L1P
DVC
DVC
1
−20°C to +85°C 2.85 V 5-Lead SOT-23 RJ-5 L1R
DWC
DWC
1
−20°C to +85°C 2.9 V 5-Lead SOT-23 RJ-5 L1S
DPC
DPC
1
−20°C to +85°C 3.0 V 5-Lead SOT-23 RJ-5 DPC#
DRC
DRC
1
−20°C to +85°C 3.3 V 5-Lead SOT-23 RJ-5 L1Q
DTC
DTC
1
−20°C to +85°C 3.6 V 5-Lead SOT-23 RJ-5 L1T
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C00141-0-12/06(C)
Rev. C | Page 12 of 12
Loading...