Page 1
High Accuracy anyCAP™
V
OUT
= +3.3V
V
IN
+
–
ADP3307-3.3
NR
OUT
ERR
ON
OFF
SD
GND
R1
330kV
IN
E
OUT
C2
0.47mF
C1
0.47mF
a
FEATURES
0.8% Accuracy Over Line and Load Regulations @ +258C
Ultralow Dropout Voltage: 120 mV Typical @ 100 mA
Requires only C
anyCAP = Stable with All Types of Output Capacitors
(Including MLCC)
Current and Thermal Limiting
Low Noise
Dropout Detector
Low Shutdown Current: 1 mA
3.0 V to 12 V Supply Range
–208C to +858C Ambient Temperature Range
Several Fixed Voltage Options
Ultrasmall SOT-23-6 (RT-6) Package
Excellent Line and Load Regulations
APPLICATIONS
Cellular Telephones
Notebook, Palmtop Computers
Battery Powered Systems
PCMCIA Regulator
Bar Code Scanners
Camcorders, Cameras
= 0.47 mF for Stability
O
100 mA Low Dropout Linear Regulator
ADP3307
FUNCTIONAL BLOCK DIAGRAM
ADP3307
M
BANDGAP
REF
OUT
R1
NR
R2
ERR
SD
IN
THERMAL
PROTECTION
Q2
Q1
CC
DRIVER G
GND
GENERAL DESCRIPTION
The ADP3307 is a member of the ADP330x family of precision
low dropout anyCAP voltage regulators. The ADP3307 stands
out from the conventional LDOs with a novel architecture and
an enhanced process. Its patented design requires only a 0.47 µF
output capacitor for stability. This device is stable with any type
of capacitor regardless of its ESR (Equivalent Series Resistance)
value, including ceramic types (MLCC) for space restricted
applications. The ADP3307 achieves exceptional accuracy of
±0.8% at room temperature and ±1.4% overall accuracy over
temperature, line and load regulations. The dropout voltage of
the ADP3307 is only 120 mV (typical) at 100 mA.
The ADP3307 operates with a wide input voltage range from
3.0 V to 12 V and delivers a load current in excess of 100 mA.
It features an error flag that signals when the device is about to
anyCAP is a trademark of Analog Devices, Inc.
Figure 1. Typical Application Circuit
lose regulation or when the short circuit or thermal overload
protection is activated. Other features include shutdown and
optional noise reduction capabilities. The ADP330x anyCAP
LDO family offers a wide range of output voltages and output
current levels from 50 mA to 300 mA:
ADP3300 (50 mA, SOT-6)
ADP3307 (100 mA, SOT)
ADP3301 (100 mA, SO-8)
ADP3302 (100 mA, Dual Output)
ADP3303 (200 mA)
ADP3306 (300 mA)
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1997
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
Page 2
ADP3307–SPECIFICA TIONS
(@ TA = –208C to +858C, VIN = 7 V, CIN = 0.47 mF, C
= 0.47 mF, unless
OUT
otherwise noted)1 The following specifications apply to all voltage options.
Parameter Symbol Conditions Min Typ Max Units
OUTPUT VOLTAGE ACCURACY V
OUT
VIN = V
I
T
V
OUTNOM
= 0.1 mA to 100 mA
L
= +25°C –0.8 +0.8 %
A
= V
IN
OUTNOM
+ 0.3 V to 12 V
+ 0.3 V to 12 V
IL = 0.1 mA to 100 mA –1.4 +1.4 %
∆V
∆V
∆V
∆I
GND
O
IN
O
L
LINE REGULATION V
LOAD REGULATION I
GROUND CURRENT I
IN
= V
OUTNOM
+ 0.3 V to 12 V
TA = +25°C 0.02 mV/V
= 0.1 mA to 100 mA
L
TA = +25°C 0.06 mV/mA
IL = 100 mA 0.76 2.0 mA
IL = 0.1 mA 0.19 0.3 mA
GROUND CURRENT IN DROPOUT I
GND
VIN = 2.5 V
IL = 0.1 mA 0.6 1.2 mA
V
DROPOUT VOLTAGE V
DROP
= 98% of V
OUT
OUTNOM
IL = 100 mA 0.126 0.22 V
I
= 10 mA 0.025 0.07 V
L
IL = 1 mA 0.004 0.015 V
SHUTDOWN THRESHOLD V
THSD
ON 2.0 0.75 V
OFF 0.75 0.3 V
SHUTDOWN PIN INPUT CURRENT I
SDIN
0 < VSD, < 5 V 1 µA
5 < VSD ≤ 12 V @ VIN = 12 V 22 µA
GROUND CURRENT IN SHUTDOWN I
Q
MODE T
VSD = 0 V, VIN = 12 V
= +25°C 0.005 1 µA
A
V
= 0 V, VIN = 12 V
SD
TA = +85°C 0.01 3 µA
OUTPUT CURRENT IN SHUTDOWN I
OSD
TA = +25°C @ VIN = 12 V 2 µA
MODE TA = +85°C @ VIN = 12 V 4 µA
ERROR PIN OUTPUT LEAKAGE I
EL
VEO = 5 V 13 µA
ERROR PIN OUTPUT
“LOW” VOLTAGE V
PEAK LOAD CURRENT I
OUTPUT NOISE @ 3.3 V OUTPUT V
EOL
LDPK
NOISE
I
= 400 µA 0.12 0.3 V
SINK
VIN = V
OUTNOM
+ 1 V 170 mA
f = 10 Hz–100 kHz
C
= 0 100 µV rms
NR
CNR = 10 nF, CL = 10 µF30µV rms
NOTES
1
Ambient temperature of +85°C corresponds to a junction temperature of 125°C under typical full load test conditions.
Specifications subject to change without notice.
–2–
REV. 0
Page 3
ADP3307
ABSOLUTE MAXIMUM RATINGS*
Input Supply Voltage . . . . . . . . . . . . . . . . . . . –0.3 V to +16 V
Shutdown Input Voltage . . . . . . . . . . . . . . . . –0.3 V to +16 V
Error Flag Output Voltage . . . . . . . . . . . . . . . –0.3 V to +16 V
Noise Bypass Pin Voltage . . . . . . . . . . . . . . . . –0.3 V to +5 V
Power Dissipation . . . . . . . . . . . . . . . . . . . .Internally Limited
Operating Ambient Temperature Range . . . –55°C to +125°C
Operating Junction Temperature Range . . . –55°C to +125°C
θ
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230°C/W
JA
θ
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W
JC
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 10 s) . . . . . . . . .+300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
*This is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged.
ORDERING GUIDE
Output Package Marking
Model Voltage Option Code
ADP3307ART-2.7 2.7 V RT-6 LTC
ADP3307ART-3 3.0 V RT-6 LUC
ADP3307ART-3.2 3.2 V RT-6 LVC
ADP3307ART-3.3 3.3 V RT-6 LWC
Contact the factory for the availability of other output voltage options.
Other Members of anyCAP Family
1
PIN FUNCTION DESCRIPTIONS
Pin Name Function
1 GND Ground Pin.
2 NR Noise Reduction Pin. Used for further reduc-
tion of the output noise. (See text for details.)
No connection if not used.
3 SD Active Low Shutdown Pin. Connect to ground
to disable the regulator output. When shutdown is not used, this pin should be connected to the input pin.
4 OUT Output of the Regulator, fixed 2.7 V, 3.0 V,
3.2 V or 3.3 V output voltage. Bypass to
ground with a 0.47 µF or larger capacitor.
5 IN Regulator Input.
6 ERR Open Collector Output that goes low to indi-
cate that the output is about to go out of
regulation.
PIN CONFIGURATION
GND
NR
SD
1
ADP3307
2
TOP VIEW
(Not to Scale)
3
6
ERR
5
IN
4
OUT
Output Package
Model Current Options
2
Comments
ADP3300 50 mA SOT-23-6 High Accuracy
ADP3301 100 mA SO-8 High Accuracy
ADP3302 100 mA SO-8 Dual Output
ADP3303 200 mA SO-8 High Accuracy
ADP3306 300 mA SO-8, TSSOP-14 High Accuracy,
High Current
NOTES
1
See individual data sheets for detailed ordering information.
2
SO = Small Outline, SOT-23 = Surface Mount, TSSOP = Thin Shrink Small
Outline.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADP3307 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–3–REV. 0
Page 4
ADP3307
TEMPERATURE – 8C
GROUND CURRENT – mA
1000
800
0
–25 –5 135
15 35 55 75 95 115
600
400
200
TIME – ms
INPUT/OUTPUT VOLTAGE – Volts
8.0
5.0
0
0 20 200
40 60 80 100 120 140 160 180
7.0
6.0
3.0
1.0
4.0
2.0
VSD = V
IN
CL = 0.47mF
R
L
= 32V
V
OUT
= 3.2V
V
IN
V
OUT
–Typical Performance Characteristics
3.202
3.201
3.200
3.199
3.198
3.197
OUTPUT VOLTAGE – Volts
3.196
3.195
3.3 4 145678910111213
IL = 0mA
IL = 10mA
IL = 50mA
IL = 100mA
INPUT VOLTAGE – Volts
V
= 3.2V
OUT
Figure 2. Line Regulation Output
Voltage vs. Supply Voltage
900
750
600
450
GROUND CURRENT – mA
300
IL = 0 TO 100mA
3.202
V
= 3.2V
OUT
V
3.201
3.200
3.199
3.198
3.197
OUTPUT VOLTAGE – Volts
3.196
3.195
20 30 40 50 60 70 80 90
0 10 100
OUTPUT LOAD – mA
IN
= 7V
Figure 3. Output Voltage vs. Load
Current Up to 100 mA
0.2
0.1
0.0
–0.1
–0.2
OUTPUT VOLTAGE – %
–0.3
IL = 50mA
IL = 100mA
IL = 0
800
640
480
320
GROUND CURRENT – mA
160
0
0 1.2 12.02.4 3.6 4.8 6.0 7.2 8.4 9.6 10.8
INPUT VOLTAGE – Volts
V
= 3.2V
OUT
= 0
I
L
Figure 4. Quiescent Current vs. Supply Voltage—3.2 V (Both Outputs)
150
0 25 100
50 75
OUTPUT LOAD – mA
Figure 5. Ground Current vs. Load
Current
120
96
72
48
24
INPUT/OUTPUT VOLTAGE – mV
0
0 25 10050 75
OUTPUT LOAD – mA
Figure 8. Dropout Voltage vs.
Output Current
–0.4
–45 –25 135–5 15 35 75 95 11555
Figure 6. Output Voltage Variation %
vs. Temperature
5
4
3
2
1
INPUT/OUTPUT VOLTAGE – Volts
0
01 0
Figure 9. Power-Up/Power-Down
TEMPERATURE – 8C
V
= 3.2V
OUT
R
= 32V
L
234321
INPUT VOLTAGE – Volts
–4–
Figure 7. Quiescent Current vs.
Temperature
Figure 10. Power-Up Overshoot
REV. 0
Page 5
ADP3307
3.220
3.210
3.200
3.190
3.180
VOLTS
7.5
7.0
V
= 3.2V
OUT
RL = 32V
C
= 0.47mF
L
V
IN
0 40 400
80 120 160 200 240 280 320 360
TIME – ms
Figure 11. Line Transient Response
3.220
V
= 3.2V
OUT
= 4.7mF
C
3.210
L
3.200
VOLTSmA
3.190
3.180
100
10
3.220
3.210
3.200
3.190
3.180
VOLTS
7.5
7.0
V
= 3.2V
OUT
RL = 3.2kV
= 0.47mF
C
L
V
IN
40 60 80 100 120 140 160 180
0 20 200
TIME – ms
Figure 12. Line Transient Response
300
200
mA
100
0
4
2
VOLTS
0
V
= 3.2V
OUT
I
OUT
V
OUT
3.220
V
= 3.2V
OUT
C
= 0.47mF
L
100
10
0 100 500
200 300 400
TIME – ms
VOLTSmA
3.210
3.200
3.190
3.180
Figure 13. Load Transient
4
CL = 0.47mF
3
2
1
VOLTS
0
3
0
CL = 4.7mF
3V
V
OUT
R
L
V
3.2V
= 3.2V
= 32V
OUT
V
SD
0 100 500
200 300 400
TIME – ms
Figure 14. Load Transient
4
3.2V
3
2
1
VOLTS
0
3
0
010 50
20 30 40
TIME – ms
V
= 3.2V
OUT
R
= 32V
L
CL = 0.47mF
V
SD
Figure 17. Turn Off
01 5234
0.5 4.51.5 2.5 3.5
TIME – sec
Figure 15. Short Circuit Current
0
a. 0.47mF, RL = 33kV
–10
b. 0.47mF, R
c. 10mF, RL = 33kV
–20
d. 10mF, R
–30
–40
–50
–60
–70
RIPPLE REJECTION – dB
–80
–90
a
–100
10 100 10M1k 10k 1M
db
c
= 33V
L
= 33V
L
FREQUENCY – Hz
a
100k
V
= 3.3V
OUT
b
d
c
Figure 18. Power Supply Ripple
Rejection
0 20 10040 60 80
TIME – ms
Figure 16. Turn On
10
V
= 5V, CL = 0.47mF
OUT
IL = 1mA, CNR = 0
1
V
= 3.3V, CL = 0.47mF
OUT
= 1mA, CNR = 0
I
L
0.1
V
= 2.7– 5.0V, CL = 0.47mF
OUT
IL = 1mA, CNR = 10nF
V
OUT
= 1mA, CNR = 10nF
I
0.01
100 1k 100k10k
VOLTAGE NOISE SPECTRAL DENSITY – mV Hz
L
FREQUENCY – Hz
0.47mF BYPASS
PIN 5 TO PIN 1
= 2.7– 5.0V, CL = 4.7mF
Figure 19. Output Noise Density
–5–REV. 0
Page 6
ADP3307
THEORY OF OPERATION
The ADP3307 anyCAP LDO uses a single control loop for
regulation and reference functions. The output voltage is sensed
by a resistive voltage divider consisting of R1 and R2 which is
varied to provide the available output voltage option. Feedback
is taken from this network by way of a series diode (D1) and a
second resistor divider (R3 and R4) to the input of an amplifier.
INPUT
Q1
NONINVERTING
WIDEBAND
DRIVER
ADP3307
COMPENSATION
CAPACITOR
PTAT
V
G
M
ATTENUATION
(V
BANDGAP/VOUT
OS
R4
GND
D1
R3
PTAT
CURRENT
OUTPUT
R1
)
R2
(a)
R
LOAD
C
LOAD
Figure 20. Functional Block Diagram
A very high gain error amplifier is used to control this loop. The
amplifier is constructed in such a way that at equilibrium it
produces a large, temperature proportional input “offset voltage” that is repeatable and very well controlled. The gained up
temperature proportional offset voltage is combined with the
diode voltage to form a “virtual bandgap” voltage, implicit in
the network, although it never appears explicitly in the circuit.
Ultimately, this patented design makes it possible to control the
loop with only one amplifier. This technique also improves the
noise characteristics of the amplifier by providing more flexibility on the trade-off of noise sources that leads to a low noise
design.
The R1, R2 divider is chosen in the same ratio as the bandgap
voltage to the output voltage. Although the R1, R2 resistor
divider is loaded by the diode D1, and a second divider consisting of R3 and R4, the values are chosen to produce a temperature stable output.
The patented amplifier controls a new and unique noninverting
driver that drives the pass transistor, Q1. The use of this special
noninverting driver enables the frequency compensation to
include the load capacitor in a pole splitting arrangement to
achieve reduced sensitivity to the value, type and ESR of the
load capacitance.
Most LDOs place strict requirements on the range of ESR values for the output capacitor because they are difficult to stabilize
due to the uncertainty of load capacitance and resistance.
Moreover, the ESR value, required to keep conventional LDOs
stable, changes depending on load and temperature. These
ESR limitations make designing with conventional LDOs more
difficult because of their unclear specifications and the dependence of ESR over temperature.
This is no longer true with the ADP3307 anyCAP LDO. It can
be used with virtually any good quality capacitor, with no constraint on the minimum ESR. The innovative design allows the
circuit to be stable with just a small 0.47 µF capacitor on the
output. Additional advantages of the design scheme include
superior line noise rejection and very high regulator gain that
lead to excellent line and load regulation. An impressive ±1.4%
accuracy is guaranteed over line, load and temperature.
Additional features of the circuit include current limit, thermal
shutdown and noise reduction. Compared to the standard solutions that give warning after the output has lost regulation, the
ADP3307 provides improved system performance by enabling
the ERR pin to give warning before the device loses regulation.
As the chip’s temperature rises above 165°C, the circuit activates a soft thermal shutdown, indicated by a signal low on the
ERR pin, to reduce the current to a safe level.
To reduce the noise gain of the loop, the node of the main divider network (a) is made available at the noise reduction (NR)
pin which can be bypassed with a small capacitor (10 nF–100 nF).
APPLICATION INFORMATION
Capacitor Selection: anyCAP
Output Capacitors: as with any micropower device, output
transient response is a function of the output capacitance. The
ADP3307 is stable with a wide range of capacitor values, types
and ESR (anyCAP). A capacitor as low as 0.47 µF is all that is
needed for stability. However, larger capacitors can be used if
high output current surges are anticipated. There is an upper
limit on the size of the output capacitor. The ADP3307 is stable
with extremely low ESR capacitors (ESR ≈ 0), such as multilayer ceramic capacitors (MLCC) or OSCON.
Input Bypass Capacitor: an input bypass capacitor is not required; however, for applications where the input source is high
impedance or far from the input pins, a bypass capacitor is
recommended. Connecting a 0.47 µF capacitor from the input
to ground reduces the circuit’s sensitivity to PC board layout. If
a bigger output capacitor is used, the input capacitor should be
1 µF minimum.
Noise Reduction
A noise reduction capacitor (CNR) can be used to further reduce
the noise by 6 dB–10 dB (Figure 21). Low leakage capacitors in
10 nF–100 nF range provide the best performance. As the noise
reduction capacitor increases the high frequency loop-gain of
the regulator, the circuit requires a larger output capacitor if it is
used. The recommended value is 4.7 µF, as shown in Figure 21.
Since the noise reduction pin (NR) is internally connected to a
high impedance node, any connection to this node should be
carefully done to avoid noise pick up from external sources. The
pad connected to this pin should be as small as possible. Long
PC board traces are not recommended.
–6–
REV. 0
Page 7
ADP3307-2.7
ADP3307-3.3
+
OUTIN
SD
GND
+
IN
OUT
SD
GND
C1
1.0mF
C2
0.47mF
V
OUT
= 2.7V/3.3V
V
IN
= 4V TO 12V
OUTPUT SELECT
4V
0V
OFF
NR
OUT
ERR
ON
GND
V
IN
C1
1mF
ADP3307-3.3
IN
+
SD
C
NR
10nF
R1
330k
E
OUT
V
= 3.3V
OUT
+
C2
4.7mF
Figure 21. Noise Reduction Circuit
Thermal Overload Protection
The ADP3307 is protected against damage due to excessive
power dissipation by its thermal overload protection circuit,
which limits the die temperature to a maximum of 165°C. Under extreme conditions (i.e., high ambient temperature and
power dissipation), where die temperature starts to rise above
165°C, the output current is reduced until the die temperature
has dropped to a safe level. Output current is restored when the
die temperature is reduced.
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For normal
operation, device power dissipation should be externally limited
so that junction temperatures will not exceed 125°C.
Calculating Junction Temperature
Device power dissipation is calculated as follows:
= (VIN – V
P
D
Where I
and V
Assuming I
V
= 3.3 V, device power dissipation is:
OUT
and I
LOAD
are input and output voltages respectively.
OUT
LOAD
= (5.5 – 3.3) 0.1 + 5.5 × 2 mA = 0.231 W
P
D
∆T = T
are load current and ground current, V
GND
= 100 mA, I
– TA = PD × θJA = 0.231 × 165 = 38°C
J
) I
OUT
GND
+ (VIN) I
LOAD
= 2 mA, VIN = 5.5 V and
GND
With a maximum junction temperature of 125°C, this yields a
maximum ambient temperature of ~72°C.
Printed Circuit Board Layout Consideration
Surface mount components rely on the conductive traces or
pads to transfer heat away from the device. Appropriate PC
board layout techniques should be used to remove heat from the
immediate vicinity of the package.
The following general guidelines will be helpful when designing
a board layout:
1. PC board traces with larger cross section areas will remove
more heat. For optimum results, use PC boards with thicker
copper and wider traces.
2. Increase the surface area exposed to open air so heat can be
removed by convection or forced air flow.
3. Do not use solder mask or silkscreen on the heat dissipating
traces because it will increase the junction-to-ambient thermal resistance of the package.
ADP3307
Shutdown Mode
Applying a TTL high signal to the shutdown pin or tying it to
the input pin will turn the output ON. Pulling the shutdown pin
down to a TTL low level or tying it to ground will turn the
output OFF. In shutdown mode, quiescent current is reduced
to less than 1 µA.
Error Flag Dropout Detector
The ADP3307 will maintain its output voltage over a wide
range of load, input voltage and temperature conditions. If the
output is about to lose regulation, for example, by reducing the
supply voltage below the combined regulated output and dropout voltages, the ERR pin will be activated. The ERR output is
an open collector that will be driven low.
Once set, the ERRor flag’s hysteresis will keep the output low
until a small margin of operating range is restored either by
raising the supply voltage or reducing the load.
APPLICATIONS CIRCUITS
Crossover Switch
The circuit in Figure 22 shows that two ADP3307s can be used
to form a mixed supply voltage system. The output switches
between two different levels selected by an external digital input.
Output voltages can be any combination of voltages from the
Ordering Guide of the data sheet.
IN
Figure 22. Crossover Switch
Higher Output Current
The ADP3307 can source up to 100 mA without any heatsink
or pass transistor. If higher current is needed, an appropriate
pass transistor can be used, as in Figure 23, to increase the
output current to 1 A.
= 4V TO 8V
V
IN
C1
47mF
*AAVID531002 HEAT SINK IS USED
MJE253*
R1
50V
IN
ADP3307-3.3
SD
GND
OUT
ERR
Figure 23. High Output Current Linear Regulator
V
= 3.3V@1A
OUT
+
C2
10mF
–7–REV. 0
Page 8
ADP3307
Constant Dropout Post Regulator
The circuit in Figure 24 provides high precision with low dropout for any regulated output voltage. It significantly reduces the
ripple from a switching regulator while providing a constant
VIN = 2.5V TO 3.5V
100mF
10V
L1
6.8mH
C1
R1
120V
I
LIM
ADP3000-ADJ
SW2GND
V
IN
SW1
FB
D1
1N5817
C2
100mF
10V
Figure 24. Constant Dropout Post Regulator
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
6-Lead Plastic Surface Mount
(RT-6)
dropout voltage, which limits the power dissipation of the LDO
to 30 mW. The ADP3000 used in this circuit is a switching
regulator in the step-up configuration.
ADP3307-3.3
+
3.3V@100mA
C3
2.2mF
2N3906
Q1
R2
30.1kV
1%
R3
124kV
1%
IN OUT
SD
GND
Q2
2N3906
R4
274kV
C3234–8–12/97
0.071 (1.80)
0.059 (1.50)
0.051 (1.30)
0.035 (0.90)
PIN 1
0.059 (0.15)
0.000 (0.00)
0.122 (3.10)
0.106 (2.70)
1
0.075 (1.90)
2
BSC
0.020 (0.50)
0.010 (0.25)
4 5 6
0.118 (3.00)
0.098 (2.50)
3
0.037 (0.95) BSC
0.057 (1.45)
0.035 (0.90)
SEATING
PLANE
0.009 (0.23)
0.003 (0.08)
10°
0°
0.022 (0.55)
0.014 (0.35)
PRINTED IN U.S.A.
–8–
REV. 0
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