Datasheet ADP3212, NCP3218 Datasheet (ON Semiconductor)

7-Bit Programmable,

S

3-Phase, Mobile CPU

ynchronous Buck

Controller

FEATURES

Single-chip solution

Fully compatible with the Intel® IMVP-6.5™ specifications

Selectable 1- , 2-, or 3-phase operation with up to 1 MHz per

phase switching frequency
Phase 1 and Phase 2 Integrated MOSFET drivers
Input Voltage Range of 3.3 V to 22 V
Guaranteed ±8 mV worst-case differentially sensed core

voltage error over temperature
Automatic power-saving mode maximizes efficiency with

light load during deeper sleep operation
Active current balancing between output phases
Independent current limit and load line setting inputs for

additional design flexibility
Built-in power-good blanking supports

voltage identification (VID) on-the-fly transients
7-bit, digitally programmable DAC with 0.3 V to 1.5 V output
Short-circuit protection with programmable latch-off delay
Clock enable output delays the CPU clock until the core

voltage is stable
Output power or current monitor options
48-lead QFN 6x6mm (NCP3218)
48-lead QFN 7x7mm (ADP3212)

APPLICATIONS

Notebook power supplies for next-generation Intel processors

ADP3212/NCP3218

GENERAL DESCRIPTION

The ADP3212/NCP3218 is a highly efficient, multiphase,
synchronous buck switching regulator controller. With its
integrated drivers, the ADP3212/NCP3218 is optimized for
converting the notebook battery voltage into the core supply
voltage required by high performance Intel processors. An internal
7-bit DAC is used to read a VID code directly from the processor
and to set the CPU core voltage to a value within the range of

0.3 V to 1.5 V. The ADP3212/NCP3218 is programmable for 1-,
2-, or 3-phase operation. The output signals ensure interleaved
2- or 3-phase operation.

The ADP3212/NCP3218 uses a multimode architecture run at a
programmable switching frequency and optimized for efficiency
depending on the output current requirement. The
ADP3212/NCP3218 switches between single- and multi-phase
operation to maximize efficiency with all load conditions. The chip
includes a programmable load line slope function to adjust the
output voltage as a function of the load current so that the core
voltage is always optimally positioned for a load transient. The
ADP3212/NCP3218 also provides accurate and reliable short­circuit protection, adjustable current limiting, and a delayed
power-good output. The IC supports on-the-fly output voltage
changes requested by the CPU.

The ADP3212/NCP3218 are specified over the extended
commercial temperature range of -40°C to 100°C. The ADP3212
is available in a 48-lead QFN 7x7mm 0.5 mm pitch package.
The NCP3218 is available in a 48-lead QFN 6x6mm 0.4 mm
pitch package. Except for the packages, the ADP3212 and
NCP3218 are identical. ADP3212 and NCP3218 are Halogen­Free, Pb-Free and RoHS compliant.

Rev. SpA | Page 1 of 43

ADP3212/NCP3218

FUNCTIONAL BLOCK DIAGRAM

ENGND

VCC

RPM RT RAMP

VARFREQ

TRDETTRDET

COMP

FB

LLINE

SWFB1

SWFB2

SWFB3

PH0

PH1

PWRGD

CLKENCLKEN

FBRTN

TRDET

TRDET

Generator

Generator

+

ΣΣ

REF

DAC + 200mV

DAC - 300mV

+

CSREF

PWRGD

Open
Drain

CLKEN

CLKEN

Open

Open
Drain

Drain

Precision

Precision

Reference

Reference

+

ΣΣ

_

1.55V

VID

DAC

Shutdown

Shutdown

VEA

-

+-+

CSREF

-

+-+

-

+-+

UVLO

UVLO

and Bias

and Bias

OVP

+-+

-

Number of

Phases

PWRGD
Start Up

Delay

CLKEN

CLKEN

Start Up

Start Up

Delay

Delay

Oscillator

Current

Current

Balancing

Balancing

Circuit

Circuit

OCP

Shutdown

Delay

Soft

Transient

Delay

Delay

Disable

DAC

Current

Limit

Circuit

REF

Driver

Logic

PSI and

PSI and

DPRSLP

DPRSLP

Logic

Logic

Current

Current
Monitor

Monitor

Thermal

Thermal
Throttle

Throttle

Control

Control

Soft Start

PVCC

PGND

+

-+-

BST1

DRVH1

SW1

PVCC

DRVL1

PGND

BST2

DRVH2

SW2

DRVL2

OD3OD3

PWM3

PSIPSI

DPRSLP

IMON

CSREF

CSSUM

CSCOMP

ILIM

TTSENSE

VRTT

VID6

VID5

VID4

VID3

VID2

VID1

VID0

IREF

Figure 1.

Rev. SpA | Page 2 of 43

ADP3212/NCP3218

TABLE OF CONTENTS

Features...............................................................................................1

Applications .......................................................................................1

General Description..........................................................................1

Functional Block Diagram...............................................................2

Revision History................................................................................3

Specifications .....................................................................................4

Timing Diagram................................................................................9

Absolute Maximum Ratings ..........................................................10

ESD Caution ................................................................................10

Pin Configuration and Function Descriptions ...........................11

Test Circuits .....................................................................................13

Typical Performance Characteristics............................................14

Theory of Operation.......................................................................15

Number of Phases .......................................................................15

Operation Modes ........................................................................15

Differential Sensing of Output Voltage....................................19

Output Current Sensing .............................................................19

Active Impedance Control Mode..............................................19

Current Control Mode and Thermal Balance.........................20

Voltage Control Mode................................................................20

Power-Good Monitoring............................................................20

Power-Up Sequence and Soft Start ...........................................21

Current Limit...............................................................................21

Output Crowbar..........................................................................24

Reverse Voltage Protection........................................................24

Output Enable and UVLO.........................................................24

Thermal Throttling Control......................................................24

Application Information ................................................................28

Setting the Clock Frequency for PWM....................................28

Setting the Switching Frequency for RPM Operation of Phase

1 .....................................................................................................28

Soft Start and Current Limit Latch-Off Delay Times ............28

Inductor Selection.......................................................................28

C

Selection..............................................................................31

OUT

Power MOSFETs.........................................................................32

Ramp Resistor Selection.............................................................33

Current Limit Setpoint...............................................................33

Current Monitor..........................................................................33

Feedback Loop Compensation Design ....................................33

CIN Selection and Input Current di/dt Reduction ..................35

RC Snubber..................................................................................35

Selecting Thermal Monitor Components................................35

Tuning Procedure for ADP3212/NCP3218.............................36

Layout and Component Placement ..........................................37

Outline Dimension .........................................................................39

Ordering Guide...........................................................................41

Changing VID on the Fly...........................................................21

REVISION HISTORY

4/08—Revision Sp0: Initial Version

Rev. SpA | Page 3 of 43

ADP3212/NCP3218

SPECIFICATIONS

VCC = PVCC = 5V, FBRTN = PGND = GND = 0 V, H = 5V, L = 0 V, EN = VARFREQ = H, DPRSLP = L,

1.2000 V, T

= −40°C to 100°C, unless otherwise noted.1 Current entering a pin (sink current) has a positive sign.

A

PSI

= 1.05 V, V

= VDAC =

VID

Table 1.

Parameter Symbol Conditions Min Typ Max Units

VOLTAGE CONTROL

VOLTAGE ERROR AMPLIFIER
(VEAMP)

FB, LLINE Voltage Range2 V
FB, LLINE Offset Voltage2 V
LLINE Bias Current I
FB Bias Current IFB −1 +1
LLINE Positioning Accuracy VFB − V

, V

Relative to CSREF = VDAC −200 +200 mV

FB

LLINE

Relative to CSREF = VDAC −0.5 +0.5 mV

OSVEA

−100 +100 nA

LLINE

Measured on FB relative to V

VID

, LLINE forced 80 mV

VID

−77.5 −80 −82.5 mV

μA

below CSREF
COMP Voltage Range2 V
COMP Current

COMP Slew Rate SR

Gain Bandwidth2 GBW Non-inverting unit gain configuration, RFB = 1

0.85 4.0 V

COMP

I

COMP

C

COMP

COMP = 2 V, CSREF = VDAC

FB forced 200 mV below CSREF

FB forced 200 mV above CSREF

= 10 pF, CSREF = VDAC, Open loop

COMP

configuration

FB forced 200 mV below CSREF

FB forced 200 mV above CSREF

−0.75
6

15

-20

20 MHz

mA
mA

V/μs
V/μs

kOhm

VID DAC VOLTAGE REFERENCE

VDAC Voltage Range2 See VID table 0 1.5 V
VDAC Accuracy VFB − V

VDAC Differential

−1 +1 LSB

VID

Measured on FB (includes offset), relative to V

= 1.2000 V to 1.5000 V, T = −40C to 100C

V

VID

V

= 0.3000 V to 1.1875 V, T = −40C to 100C

VID

VID

−8.5

−7.5

+8.5
+7.5

mV
mV

Nonlinearity2
VDAC Line Regulation
VDAC Boot Voltage V
Soft-start Delay

2

ΔV

FB

BOOTFB

t

Measured from EN pos edge to FB = 50 mV 200

DSS

Soft-start Time tSS Measured from FB = 50 mV to FB settles to 1.1 V

VCC = 4.75 V to 5.25 V 0.02 %

Measured during boot delay period 1.100 V

μs

1.4 ms

within 5 %
Boot Delay t

Measured from FB settling to 1.1 V within 5% to

BOOT

60

μs

CLKEN# neg edge
VDAC Slew Rate2 Soft-start

Non-LSB VID step, DPRSLP = H, Slow C4 Entry/Exit

Non-LSB VID step, DPRSLP = L, Fast C4 Exit

LSB VID step, DVID transition

FBRTN Current I

VOLTAGE MONITORING

−90 −200

FBRTN

0.0625

0.25
1

0.4

LSB/μs
LSB/μs
LSB/μs
LSB/μs
μA

and PROTECTION

POWER GOOD

CSREF Under-voltage
Threshold

CSREF Over-voltage
Threshold

V

Relative to nominal VDAC voltage −240 −300 −360 mV

UVCSREF

V

Relative to nominal VDAC voltage 150 200

OVCSREF

250 mV

Rev. SpA | Page 4 of 43

ADP3212/NCP3218

Parameter Symbol Conditions Min Typ Max Units

CSREF Crowbar Voltage
Threshold

CSREF Reverse Voltage
Threshold

PWRGD Low Voltage V
PWRGD High, Leakage

Current
PWRGD Start-up Delay T

PWRGD Latch-off Delay T

PWRGD Propagation Delay3 T

Crowbar Latch-off Delay2 T

PWRGD Masking Time Triggered by any VID change or OCP event 100 s
CSREF Soft-stop Resistance EN = L or Latch-off condition 70

CURRENT CONTROL

CURRENT-SENSE AMPLIFIER
(CSAMP)

CSSUM, CSREF Common-

Mode Range2
CSSUM, CSREF Offset Voltage V
CSSUM Bias Current I
CSREF Bias Current I
CSCOMP Voltage Range2 Voltage range of interest 0.05 2 V
CSCOMP Current

CSCOMP Slew Rate2 C

Gain Bandwidth2 GBW

CURRENT MONITORING
and PROTECTION

CURRENT REFERENCE

IREF Voltage V

CURRENT LIMITER (OCP)

Current Limit (OCP)
Threshold

Current Limit Latch-off Delay Measured from OCP event to PWRGD de-assertion 120 s

CURRENT MONITOR

Current Gain Accuracy I

V

Relative to FBRTN, V

CBCSREF

Relative to FBRTN, V

V

RVCSREF

Relative to FBRTN, Latch-off mode
CSREF is falling
CSREF is rising

I

PWRGD

I

V

PWRGD

SSPWRGD

PWRGD(SINK)

PWRDG

Measured from CLKEN# neg edge to PWRGD pos

= 4 mA 85 250 mV

= 5 V 1 A

> 1.1 V

VID

≤ 1.1 V

VID

1.5

1.3

−370 −300

1.55

1.35

−75

1.6

1.4 V V

−10

mV
mV

8 ms

edge

Measured from Out-off-Good-Window event to

LOFFPWRGD

120 s

Latch-off (switching stops)

PDPWRGD

Measured from Out-off-Good-Window event to

200 ns

PWRGD neg edge

LOFFCB

Measured from Crowbar event to Latch-off

200 ns

(switching stops)

Ω

Voltage range of interest 0 2 V

CSREF – CSSUM , TA = −40C to 85C −1.2 +1.2 mV

OSCSA

−20 +20 nA

BCSSUM

−3 +3

BCSREF

I

CSCOMPsource

I

CSCOMPsink

CSCOMP = 2 V,
CSSUM forced 200 mV below CSREF

CSSUM forced 200 mV above CSREF

= 10 pF, CSREF = VDAC, Open loop

CSCOMP

configuration
CSSUM forced 200 mV below CSREF

−750
1

20

−20

μA

μA

mA

V/μs
V/μs

CSSUM forced 200 mV above CSREF

Non-inverting unit gain configuration

CSA

= 1 kOhm

R

FB

20 MHz

REF

R

= 80 kΩ to set I

REF

= 20 uA

REF

1.55 1.6 1.65 V

V

Measured from CSCOMP to CSREF, R

LIMTH

3-ph configuration,
3-ph configuration,

2-ph configuration,
2-ph configuration,

1-ph configuration −75 −90 −106 mV

PSI
PSI

PSI
PSI

= H
= L

= H
= L

= 1.5 kΩ,

LIM

−75

−22

−75

−36

−90

−30

−90

−45

−106

−38

−106

−54

mV
mV

mV

Measured from ILIM to IMON

MON/ILIM

I

= −20 μA

LIM

I

= −10 μA

LIM

Rev. SpA | Page 5 of 43

3.7

3.6

4
4

4.3

4.4

-

-

ADP3212/NCP3218

Parameter Symbol Conditions Min Typ Max Units

I

= −5 μA

LIM

IMON Clamp Voltage V

PULSE WIDTH

Relative to FBRTN, ILIMP = −30 uA 1.0 1.15 V

MAXMON

MODULATOR

CLOCK OSCILLATOR

RT Voltage VRT

PWM Clock Frequency

f

Operation of interest 0.3 3 MHz

CLK

Range2
PWM Clock Frequency f

RAMP GENERATOR

RAMP Voltage V

RAMP Current Range2 I

T

CLK

EN = high, I

RAMP

EN = high 1 100

RAMP

EN = low, RAMP = 19 V −1 +1 µA

PWM COMPARATOR

PWM Comparator Offset2 V

RPM COMPARATOR

RPM Current I

RPM Comparator Offset2 V

EPWM CLOCK SYNC

V

OSRPM

RPM

V

OSRPM

Trigger Threshold2 Relative to COMP sampled T

TRDET#

Trigger Threshold2 Relative to COMP sampled T

TRDET# Low Voltage2 V
TRDET# Leakage Current I

SWITCH AMPLIFIER

SW Common Mode Range2 V
SWFB Input Resistance R

ZERO CURRENT SWITCHING

Logic low, I

LTR D E T

Logic high, V

HTRDET

SW(X)CM

SW(X)

COMPARATOR

SW ZCS Threshold V
Masked Off-Time t

SYSTEM I/O BUFFERS

DCM(SW1)

OFFMSKD

VID[6:0], DPRSLP, PSI# INPUTS

Input Voltage Refers to driving signal level

VARFREQ = high, R

= 125 kΩ, V

T

= 1.5000 V

VID

VARFREQ = low
See also V

= +25°C, V

A

RT(VVID

VID

) formula

= 1.2000 V
RT = 72 kΩ
R

= 120 kΩ

T

RT = 180 kΩ

= 60 µA

RAMP

EN = low

− V

RAMP

V

= 1.2 V, RT = 215 kΩ

VID

See also I

COMP

±3 mV

COMP

) formula

RPM(RT

− (1 + V

) ±3 mV

RPMTH

time earlier

CLK

3-phase configuration
2-phase configuration
1-phase configuration

time earlier

CLK

3-phase configuration
2-phase configuration
1-phase configuration

= 4mA 30 300 mV

TRDET#sink

= VCC 5 µA

TRDET#

Operation of interest for current sensing −600 +200 mV
SWX = 0 V, SWFB = 0 V 20 35 50 kΩ

DCM mode, DPRSLP = 3.3 V −3 mV
Measured from DRVH1 neg edge to DRVH1 pos

edge at max frequency of operation

Logic low
Logic high

Rev. SpA | Page 6 of 43

3.5 4 4.5 -

1.125

0.9

1100
700
500

0.9 1

1.25
1

1257
800
550

VIN

1.375

1.1 V V

1400
900
600

kHz
kHz
kHz

1.1 V
V
μA

−9

350
400
450

-450

-500

-600

μA

mV
mV
mV

mV
mV
mV

600 ns

0.7

0.3 V
V

ADP3212/NCP3218

Parameter Symbol Conditions Min Typ Max Units

Input Current V = 0.2 V

VID[6:0], DPRSLP (active pull down to GND)
PSI# (active pull-up to VCC)

VID Delay Time2 Any VID edge to FB change 10% 200 ns

VARFREQ

Input Voltage Refers to driving signal level

Logic low
Logic high

Input Current 1

EN INPUT

Input Voltage Refers to driving signal level

Logic low
Logic high

Input Current EN = L or EN = H (static)

0.8 V < EN < 1.6 V (during transition)

PH1, PH0 INPUTS

Input Voltage Refers to driving signal level

Logic low
Logic high

Input Current 1

OUTPUT

CLKEN

Output Low Voltage Logic low, I
Output High, Leakage

= 4 mA 60 200 mV

sink

Logic high, V

= VCC 1 µA

CLKEN

Current

PWM3, OD3 OUTPUTS

Output Voltage Logic low, I

THERMAL MONITORING
and PROTECTION

= 400 µA

SINK

Logic high, I

SOURCE

= −400 µA

TTSNS Voltage Range2 0 5 V
TTSNS Threshold VCC = 5 V, TTSNS is falling 2.45 2.5 2.55 V
TTSNS Hysteresis 95 mV
TTSNS Bias Current TTSNS = 2.6 V −2 2 µA
VRTT Output Voltage V

SUPPLY

Supply Voltage Range V

Logic low, I

VRTT

Logic high, I

VRTT(SINK)

VRTT(SOURCE)

= 400 µA

= −400 µA

CC

4.5 5.5 V
Supply Current EN = high 7 10 mA
EN = 0 V 10 150 µA
VCC OK Threshold V
VCC UVLO Threshold V

VCC is rising 4.4 4.5 V

CCOK

VCC is falling 4.0 4.15 V

CCUVLO

VCC Hysteresis2 150 mV

HIGH-SIDE MOSFET DRIVER

Pull-up Resistance, Sourcing

Pull-down Resistance,

3

Current

Sinking Current

3

Transition Times tr
tf
Dead Delay Times tpdh

DRVH,

BST = PVCC, CL = 3 nF, Figure 2 13 25 ns

DRVH

DRVH

BST = PVCC 1.8 3.3 Ω

BST = PVCC 1.0 2.0 Ω

BST = PVCC, CL = 3 nF, Figure 2 15 30 ns

BST = PVCC, Figure 2 15 30 40 ns

Rev. SpA | Page 7 of 43

−1
1

4

1.9
10

−70

4

4

4.5

10
5

10
5

μA
μA

0.7 V
V
μA

0.4 V
V

nA

μA

V

0.5

μA

100 mV

V

100 mV

V

ADP3212/NCP3218

Parameter Symbol Conditions Min Typ Max Units

BST Quiescent Current EN = L (Shutdown) 1 10 µA
EN = H, no switching 200 µA

LOW-SIDE MOSFET DRIVER

Pull-up Resistance, Sourcing

Pull-down Resistance,

3

Current

Sinking Current

3

Transition Times tr
tf
Propagation Delay Times tpdh
SW Transition Timeout t
SW Off Threshold V
PVCC Quiescent Current EN = L (Shutdown) 1 10 µA
EN = H, no switching 170 µA

BOOTSTRAP RECTIFIER
SWITCH

On Resistance

1

All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

2

Guaranteed by design or bench characterization, not production tested.

3

Based on bench characterization data.

3

DRVL

C

DRVL

DRVL

TOSW

OFFSW

1.7 2.8 Ω

0.8 1.7 Ω

CL = 3 nF, Figure 2 15 35 ns

= 3 nF, Figure 2 14 35 ns

L

CL = 3 nF, Figure 2 11 30 ns
DRVH = L, SW = 2.5 V 100 250 350 ns

2.5 V

EN = L or EN = H and DRVL = H 4 6 8 Ω

Rev. SpA | Page 8 of 43

ADP3212/NCP3218

TIMING DIAGRAM

Timing is referenced to the 90% and 10% points, unless otherwise noted.

IN

DRVL

tf

DRVL

tpdh

DRVHtrDRVH

tpdl

DRVH

tf

DRVH

tr

DRVL

tpdl

DRVL

(WITH RESPECT

DRVH

TO SW)

SW

V

TH

Figure 2. Timing Diagram

V

TH

tpdh

DRVL

1V

06374-006

Rev. SpA | Page 9 of 43

ADP3212/NCP3218

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

VCC, PVCC1, PVCC2 −0.3 V to +6 V
FBRTN, PGND1, PGND2 −0.3 V to +0.3 V
BST1, BST2, DRVH1, DRVH2

DC −0.3 V to +28 V
t < 200 ns −0.3 V to +33 V

BST1 to PVCC, BST2 to PVCC

DC −0.3 V to +22 V

t < 200 ns −0.3 V to +28 V
BST1 to SW1, BST2 to SW2 −0.3 V to +6 V
SW1, SW2

DC −1 V to +22 V

t < 200 ns −6 V to +28 V
DRVH1 to SW1, DRVH2 to SW2, −0.3 V to +6 V
DRVL1 to PGND1, DRVL2 to PGND2

DC −0.3 V to +6 V

t < 200 ns −5 V to +6 V
RAMP (in Shutdown) −0.3 V to +22 V
All Other Inputs and Outputs −0.3 V to +6 V
Storage Temperature −65°C to +150°C
Operating Ambient Temperature Range −40°C to 100°C
Operating Junction Temperature 125°C
Thermal Impedance (θJA) 2-Layer Board
Lead Temperature

Soldering (10 sec) 300°C

Infrared (15 sec) 260°C

30.5°C/W

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. SpA | Page 10 of 43

ADP3212/NCP3218

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DPRSLP

ILIM

VCC

PH0

PH1

OD3

PWM3

SWFB3

VID0

RT

RPM

IREF

Figure 3. QFN Pin Configuration

LLINE

RAMP

VID6

CSREF

CSSUM

CSCOMP

PSI

VID5

VID4

VID3

VID2

VID1

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1 EN Enable Input. Driving this pin low shuts down the chip, disables the driver outputs, pulls PWRGD

and VRTT low, and pulls

CLKEN

high.

2 PWRGD Power-Good Output. Open-drain output. A low logic state means that the output voltage is outside

of the VID DAC defined range.

3 IMON Current Monitor Output. This pin sources a current proportional to the output load current. A

resistor to FBRTN sets the current monitor gain.

4

CLKEN

Clock Enable Output. Open-drain output. A low logic state enables the CPU internal PLL clock to
lock to the external clock.

5 FBRTN Feedback Return Input/Output. This pin remotely senses the CPU core voltage. It is also used as the

ground return for the VID DAC and the voltage error amplifier blocks.
6 FB Voltage Error Amplifier Feedback Input. The inverting input of the voltage error amplifier.
7 COMP Voltage Error Amplifier Output and Frequency Compensation Point.
8

TRDET

Transient Detect Output. This pin is pulled low when a load release transient is detected. During

repetitive load transients at high frequencies, this circuit optimally positions the maximum and

minimum output voltage into a specified loadline window.
9 VARFREQ Variable Frequency Enable Input. A high logic state enables the PWM clock frequency to vary with

VID code.
10 VRTT Voltage Regulator Thermal Throttling Output. Logic high state indicates that the voltage regulator

temperature at the remote sensing point exceeded a set alarm threshold level.
11 TTSNS Thermal Throttling Sense and Crowbar Disable Input. A resistor divider where the upper resistor is

connected to VCC, the lower resistor (NTC thermistor) is connected to GND, and the center point is

connected to this pin and acts as a temperature sensor half bridge. Connecting TTSNS to GND disables

the thermal throttling function and disables the crowbar, or overvoltage protection (OVP), feature

of the chip.
12 GND Analog and Digital Signal Ground.
13 IREF This pin sets the internal bias currents. A 80kohm resistor is connected from this pin to ground.
14 RPM RPM Mode Timing Control Input. A resistor between this pin to ground sets the RPM mode turn-on

threshold voltage.
15 RT Multiphase Frequency Setting Input. An external resistor connected between this pin and GND sets

the oscillator frequency of the device when operating in multiphase PWM mode.threshold of the

converter.

Rev. SpA | Page 11 of 43

ADP3212/NCP3218

Pin No. Mnemonic Description

16 RAMP PWM Ramp Slope Setting Input. An external resistor from the converter input voltage node to this

pin sets the slope of the internal PWM stabilizing ramp used for phase-current balancing.

17 LLINE Output Load Line Programming Input. The center point of a resistor divider between CSREF and

CSCOMP is connected to this pin to set the load line slope.

18 CSREF Current Sense Reference Input. This pin must be connected to the common point of the output

inductors. The node is shorted to GND through an internal switch when the chip is disabled to
provide soft stop transient control of the converter output voltage.

19 CSSUM Current Sense Summing Input. External resistors from each switch node to this pin sum the

inductor currents to provide total current information.

20 CSCOMP Current-Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determine the

gain of the current-sense amplifier and the positioning loop response time.

21 ILIM Current-Limit Setpoint. An external resistor from this pin to CSCOMP sets the current-limit threshold of

the converter.

22

23 PWM3 Logic-Level PWM Output for phase 3. Connect to the input of an external MOSFET driver such as the

24 SWFB3 Current Balance Input for phase 3. Input for measuring the current level in phase 3. SWFB3 should

25 BST2 High-Side Bootstrap Supply for Phase 2. A capacitor from this pin to SW2 holds the bootstrapped

26 DRVH2 High-Side Gate Drive Output for Phase 2.
27 SW2 Current Return for High-Side Gate Drive for phase 2.
28 SWFB2 Current Balance Input for phase 2. Input for measuring the current level in phase 2. SWFB2 should

29 DRVL2 Low-Side Gate Drive Output for Phase 2.
30 PGND Low-Side Driver Power Ground
31 DRVL1 Low-Side Gate Drive Output for Phase 1..
32 PVCC Power Supply Input/Output of Low-Side Gate Drivers.
33 SWFB1 Current Balance Input for phase 1. Input for measuring the current level in phase 1.
34 SW1 Current Return For High-Side Gate Drive for phase 1.
35 DRVH1 High-Side Gate Drive Output for Phase 1.
36 BST1 High-Side Bootstrap Supply for Phase 1. A capacitor from this pin to SW1 holds the bootstrapped

37 VCC Power Supply Input/Output of the Controller.
38 PH1 Phase Number Configuration Input. Connect to VCC for 3 phase configuration.
39 PH0 Phase Number Configuration Input. Connect to GND for 1 phase configuration. Connect to VCC for

40 DPRSLP Deeper Sleep Control Input.
41

42 to 48 VID6 to VID0 Voltage Identification DAC Inputs. When in normal operation mode, the DAC output programs the

OD3

PSI

Multiphase Output Disable Logic Output. This pin is actively pulled low when the ADP3212/NCP3218
enters single-phase mode or during shutdown. Connect this pin to the SD inputs of the Phase-3
MOSFET drivers.

ADP3611.

be left open for 1 or 2 phase configuration.

voltage while the high-side MOSFET is on.

be left open for 1 phase configuration.

voltage while the high-side MOSFET is on.

multiphase configuration.

Power State Indicator Input. Pulling this pin to GND forces the ADP3212/NCP3218 to operate in
single-phase mode.

FB regulation voltage from 0.3 V to 1.5 V (see Table 6).

Rev. SpA | Page 12 of 43

ADP3212/NCP3218

TEST CIRCUITS

PH1

PH2

PSI#

VID6

VID5

VID3

VID2

VID1

VID0

IREF

RPMRTRAMP

VID4

LLINE

CSREF

CSSUM

CSCOMP

VCC

DPRSLP

ILIM

OD3#

PWM3

SWFB3

Figure 6. Positioning Accuracy

Figure 4. Closed-Loop Output Voltage Accuracy

5V

37

ADP3212

VCC

CSCOMP

20

39kΩ

1kΩ

1.0V

100nF

CSSUM

19

-

CSREF

18

+

GND

12

Figure 5. Current Sense Amplifier, V

CSCOMP – 1V

=

V

os

40V

OS

Rev. SpA | Page 13 of 43

ADP3212/NCP3218

)

V

V

V

V

TYPICAL PERFORMANCE CHARACTERISTICS

V

= 1.5 V, TA = 20°C to 100°C, unless otherwise noted.

VID

400

350

300

250

VARFREQ = 0V

1000

ID = 1.4125V

200

150

100

50

0

PE R PHAS E SWI TCHI NG FREQUENCY (kHz

0.25 0.5 0.75 1 1.25 1.5

VARFREQ = 5V

RT = 187kΩ

2 Phase Mode

VI D OUTP UT V OLTAGE (V)

Figure 7. Switching Frequency vs. VID Output Voltage in PWM Mode

ID = 1.2125V

VID = 1.1V

Switching Frequency (kHz)

100

10 100 1000

ID = 0.8125

ID = 0.6125

Rt RESISTANCE (kΩ)

Figure 8. Per Phase Switching Frequency vs. RT Resistance

Rev. SpA | Page 14 of 43

ADP3212/NCP3218

THEORY OF OPERATION

The ADP3212/NCP3218 combines multimode pulse-width­modulated (PWM) control and ramp-pulse-modulated (RPM)
control with multiphase logic outputs for use in single-, dual­phase, or triple-phase synchronous buck CPU core supply
power converters. The internal 7-bit VID DAC conforms to the
Intel IMVP-6.5 specifications.

Multiphase operation is important for producing the high
currents and low voltages demanded by today’s microprocessors.
Handling high currents in a single-phase converter would put
too high of a thermal stress on system components such as the
inductors and MOSFETs.

The multimode control of the ADP3212/NCP3218 is a stable,
high performance architecture that includes

• Current and thermal balance between phases

• High speed response at the lowest possible switching

frequency and minimal count of output decoupling capacitors

• Minimized thermal switching losses due to lower frequency

operation

• High accuracy load line regulation

• High current output by supporting 2-phase or 3-phase

operation

• Reduced output ripple due to multiphase ripple cancellation

• High power conversion efficiency with heavy and light loads

• Increased immunity from noise introduced by PC board

layout constraints

• Ease of use due to independent component selection

• Flexibility in design by allowing optimization for either low

cost or high performance

NUMBER OF PHASES

The number of operational phases can be set by the user. Tying
the PH1 pin to the GND pin forces the chip into single-phase
operation. Tying PH0 to GND and PH1 to VCC forces the chip
into 2-phase operation. Tying PH0 and PH1 to VCC forces the
chip in 3-phase operation. PH0 and PH1 should be hard wired
to VCC or GND. The ADP3212/NCP3218 switches between
single phase and multiphase operation with PSI and DPRSLP to
optimize power conversion efficiency. Table 4 summarizes PH0
and PH1.

Table 4. Phase Number Configuration

PH0 PH1 Number of Phases Configured

0 0 1

1 0 1 (GPU Mode)

0 1 2

1 1 3

In mulit-phase configuration, the timing relationship between
the phases is determined by internal circuitry that monitors the
PWM outputs. Because each phase is monitored independently,
operation approaching 100% duty cycle is possible. In addition,
more than one output can be active at a time, permitting
overlapping phases.

OPERATION MODES

The number of phases can be static (see the Number of Phases
section) or dynamically controlled by system signals to
optimize the power conversion efficiency with heavy and light
loads.

If ADP3212/NCP3218 is configured for mulit-phase
configuration, during a VID transient or with a heavy load
condition (indicated by DPRSLP being low and

the ADP3212/NCP3218 runs in multi-phase, interleaved PWM
mode to achieve minimal V
transient performance possible. If the load becomes light
(indicated by

ADP3212/NCP3218 switches to single-phase mode to
maximize the power conversion efficiency.

In addition to changing the number of phases, the
ADP3212/NCP3218 is also capable of dynamically changing the
control method. In dual-phase operation, the
ADP3212/NCP3218 runs in PWM mode, where the switching
frequency is controlled by the master clock. In single-phase
operation (commanded by the DPRSLP high state), the
ADP3212/NCP3218 runs in RPM mode, where the switching
frequency is controlled by the ripple voltage appearing on the
COMP pin. In RPM mode, the DRVH1 pin is driven high each
time the COMP pin voltage rises to a voltage limit set by the
VID voltage and an external resistor connected between the
RPM pin and GND. In RPM mode, the ADP3212/NCP3218
turns off the low-side (synchronous rectifier) MOSFET when
the inductor current drops to 0. Turning off the low-side
MOSFETs at the zero current crossing prevents reversed
inductor current build up and breaks synchronous operation of

PSI

being low or DPRSLP being high),

output voltage ripple and the best

CORE

PSI

being high),

Rev. SpA | Page 15 of 43

ADP3212/NCP3218

high- and low-side switches. Due to the asynchronous
operation, the switching frequency becomes slower as the load
current decreases, resulting in good power conversion
efficiency with very light loads.

Table 5 summarizes how the ADP3212/NCP3218 dynamically
changes the number of active phases and transitions the
operation mode based on system signals and operating
conditions.

GPU MODE

The ADP3212/NCP3218 can be used to power IMVP-6.5
GMCH. To configure the ADP3212/NCP3218 in GPU, connect
PH1 to VCC and connect PH0 to GND. In GPU mode, the
ADP3212/NCP3218 operates in single phase only. In GPU
mode, the boot voltage is disabled. During start up, the output
voltage ramps up to the programmed VID voltage. There is no
other difference between GPU mode and normal CPU mode.

Rev. SpA | Page 16 of 43

ADP3212/NCP3218

Table 5. Phase Number and Operation Modes1

No. of Phases

PSI

No.

DPRSLP VID Transition

2

Current Limit

the User

* * Yes * N [3,2 or 1] N PWM, CCM only
1 0 No * N [3,2 or 1] N PWM, CCM only
0 0 No No * 1 PWM, CCM only
0 0 No Yes N [3,2 or 1] N PWM, CCM only
* 1 No No * 1 RPM, automatic CCM/DCM
* 1 No Yes * 1 PWM, CCM only

Selected by

1

* = don’t care.

2

VID transient period is the time following any VID change, including entry into and exit from deeper sleep mode. The duration of VID transient period is the same as

that of PWRGD masking time.

3

CCM stands for continuous current mode, and DCM stands for discontinuous current mode.

No. of Phases
in Operation

Operation Modes3

Figure 9. Single-Phase RPM Mode Operation

ADP3212/NCP3218

I = A x I

RRRAMP

Clock

Oscillator

C

R

Gate Driver

Flip-Flop

QS

+

-

RD

IN

BST

DRVH

SW

DRVL

BST1

DRVH1

SW1

DRVL1

VCC

LR

L

VCC

A

I = A x I

RRRAMP

C

R

A

I = A x I

RRRAMP

C

R

A

RAMP

D

D

D

COMP

-

+

Clock

Oscillator

-

+

Clock

Oscillator

-

+

R

A

C

0.2V

0.2V

0.2V

FB

SWFB1

Gate Driver

Flip-Flop

+

-

+

-

+

+

Σ

­FBRTNFB

C

A

C

B

RD

Flip-Flop

RD

+

DAC

_

+

Σ

LLINE

QS

QS

_

+

CSCOMP

IN

BST

DRVH

SW

DRVL

BST2

DRVH2

SW2

DRVL2

SWFB2

PWM3

SWFB3

CSREF

+

-

CSSUM

R

CS

C

CS

1 kΩ

VCC

1 kΩ

Gate Driver

DRVH

IN

DRVL

R

R

PH

R

PH

PH

BST

SW

1 kΩ

LR

L

VCC

LR

L

LOAD

R

B

Figure 10. 3-Phase PWM Mode Operation

Rev. SpA | Page 18 of 43

ADP3212/NCP3218

Setting Switch Frequency

Master Clock Frequency in PWM Mode

When the ADP3212/NCP3218 runs in PWM, the clock
frequency is set by an external resistor connected from the RT
pin to GND. The frequency is constant at a given VID code but
varies with the VID voltage: the lower the VID voltage, the
lower the clock frequency. The variation of clock frequency
with VID voltage maintains constant V
power conversion efficiency at lower VID voltages. Figure 8
shows the relationship between clock frequency and VID
voltage, parameterized by RT resistance.

To determine the switching frequency per phase, divide the
clock by the number of phases in use.

ripple and improves

CORE

Switching Frequency in RPM Mode—
Single-Phase Operation

In single-phase RPM mode, the switching frequency is
controlled by the ripple voltage on the COMP pin, rather than
by the master clock. Each time the COMP pin voltage exceeds
the RPM pin voltage threshold level determined by the VID
voltage and the external resistor RPM resistor, an internal ramp
signal is started and DRVH1 is driven high. The slew rate of the
internal ramp is programmed by the current entering the
RAMP pin. One-third of the RAMP current charges an internal
ramp capacitor (5 pF typical) and creates a ramp. When the
internal ramp signal intercepts the COMP voltage, the DRVH1
pin is reset low.

DIFFERENTIAL SENSING OF OUTPUT VOLTAGE

The ADP3212/NCP3218 combines differential sensing with a high
accuracy VID DAC, referenced by a precision band gap source
and a low offset error amplifier, to meet the rigorous accuracy
requirement of the Intel IMVP-6.5 specification. In steady-state
mode, the combination of the VID DAC and error amplifier
maintain the output voltage for a worst-case scenario within ±8
mV of the full operating output voltage and temperature range.

The CPU core output voltage is sensed between the FB and
FBRTN pins. FB should be connected through a resistor to the
positive regulation point—the VCC remote sensing pin of the
microprocessor. FBRTN should be connected directly to the
negative remote sensing point—the V
CPU. The internal VID DAC and precision voltage reference
are referenced to FBRTN and have a maximum current of
200 µA for guaranteed accurate remote sensing.

sensing point of the

SS

OUTPUT CURRENT SENSING

The ADP3212/NCP3218 includes a dedicated current sense
amplifier (CSA) to monitor the total output current of the
converter for proper voltage positioning vs. load current and for
over current detection. Sensing the current delivered to the load

Rev. SpA | Page 19 of 43

is an inherently more accurate method than detecting peak
current or sampling the current across a sense element, such as
the low-side MOSFET. The current sense amplifier can be
configured several ways, depending on system optimization
objectives, and the current information can be obtained by

• Output inductor ESR sensing without the use of a

thermistor for the lowest cost

• Output inductor ESR sensing with the use of a thermistor

that tracks inductor temperature to improve accuracy

• Discrete resistor sensing for the highest accuracy

At the positive input of the CSA, the CSREF pin is connected to
the output voltage. At the negative input (that is, the CSSUM pin
of the CSA), signals from the sensing element (in the case of
inductor DCR sensing, signals from the switch node side of the
output inductors) are summed together by series summing
resistors. The feedback resistor between the CSCOMP and
CSSUM pins sets the gain of the current sense amplifier, and a
filter capacitor is placed in parallel with this resistor. The
current information is then given as the voltage difference
between the CSCOMP and CSREF pins. This signal is used
internally as a differential input for the current limit
comparator.

An additional resistor divider connected between the CSCOMP
and CSREF pins with the midpoint connected to the LLINE pin
can be used to set the load line required by the microprocessor
specification. The current information to set the load line is
then given as the voltage difference between the LLINE and
CSREF pins. This configuration allows the load line slope to be
set independent from the current limit threshold. If the current
limit threshold and load line do not have to be set independently,
the resistor divider between the CSCOMP and CSREF pins can
be omitted and the CSCOMP pin can be connected directly to
LLINE. To disable voltage positioning entirely (that is, to set no
load line), LLINE should be tied to CSREF.

To provide the best accuracy for current sensing, the CSA has a
low offset input voltage and the sensing gain is set by an external
resistor ratio.

ACTIVE IMPEDANCE CONTROL MODE

To control the dynamic output voltage droop as a function of
the output current, the signal that is proportional to the total
output current, converted from the voltage difference between
LLINE and CSREF, can be scaled to be equal to the required
droop voltage. This droop voltage is calculated by multiplying
the droop impedance of the regulator by the output current.
This value is used as the control voltage of the PWM regulator.
The droop voltage is subtracted from the DAC reference output
voltage, and the resulting voltage is used as the voltage

ADP3212/NCP3218

positioning setpoint. The arrangement results in an enhanced
feedforward response.

CURRENT CONTROL MODE AND
THERMAL BALANCE

The ADP3212/NCP3218 has individual inputs for monitoring
the current of each phase. The phase current information is
combined with an internal ramp to create a current-balancing
feedback system that is optimized for initial current accuracy and
dynamic thermal balance. The current balance information is
independent from the total inductor current information used for
voltage positioning described in the Active Impedance Control
Mode section.

The magnitude of the internal ramp can be set so that the transient
response of the system is optimal. The ADP3212/NCP3218
monitors the supply voltage to achieve feedforward control
whenever the supply voltage changes. A resistor connected from
the power input voltage rail to the RAMP pin determines the
slope of the internal PWM ramp. More detail about
programming the ramp is provided in the Application
Information section.

External resistors are placed in series with the SWFB1, SWFB2,
and SWFB3 pins to create an intentional current imbalance.
Such a condition can exist when one phase has better cooling
and supports higher currents the other phases. Resistors
RSWSB1, RSWFB2, and RSWFB3 (see figure 26) can be used to
adjust thermal balance. It is recommended to add these resistors
during the initial design to make sure placeholders are provided
in the layout.

To increase the current in any given phase, users should make
RSWFB for that phase larger (that is, RSWFB = 1 k Ω for the
hottest phase and do not change it during balance
optimization). Increasing RSWFB to 1.5 kΩ makes a substantial
increase in phase current. Increase each RSWFB value by small
amounts to achieve thermal balance starting with the coolest
phase.

If adjusting current balance between phases is not needed,
RSWFB should be 1 k Ω for all phases.

VDC

R

VDC

SWFB2

Phase 1
Inductor

VDC

Phase 2
Inductor

Phase 3
Inductor

ADP3212

SWFB1

SWFB2

SWFB3

R

SWFB1

33

28

R

SWFB3

24

Figure 11. Current Balance Resistors

VOLTAGE CONTROL MODE

A high-gain bandwidth error amplifier is used for the voltage
mode control loop. The noninverting input voltage is set via the
7-bit VID DAC. The VID codes are listed in Table 6. The
noninverting input voltage is offset by the droop voltage as a
function of current, commonly known as active voltage
positioning. The output of the error amplifier is the COMP pin,
which sets the termination voltage of the internal PWM ramps.

At the negative input, the FB pin is tied to the output sense
location using R

, a resistor for sensing and controlling the

B

output voltage at the remote sensing point. The main loop
compensation is incorporated in the feedback network
connected between the FB and COMP pins.

POWER-GOOD MONITORING

The power-good comparator monitors the output voltage via
the CSREF pin. The PWRGD pin is an open-drain output that
can be pulled up through an external resistor to a voltage rail—
not necessarily the same VCC voltage rail that is running the
controller. A logic high level indicates that the output voltage is
within the voltage limits defined by a range around the VID
voltage setting. PWRGD goes low when the output voltage is
outside of this range.

Following the IMVP-6.5 specification, the PWRGD range is
defined to be 300 mV less than and 200 mV greater than the
actual VID DAC output voltage. For any DAC voltage less than
300 mV, only the upper limit of the PWRGD range is
monitored. To prevent a false alarm, the power-good circuit is
masked during various system transitions, including a VID
change and entrance into or exit out of deeper sleep. The
duration of the PWRGD mask is set to approximately 130 µs by
an internal timer. If the voltage drop is greater than 200 mV

Rev. SpA | Page 20 of 43

ADP3212/NCP3218

during deeper sleep entry or slow deeper sleep exit, the
duration of PWRGD masking is extended by the internal logic
circuit.

POWER-UP SEQUENCE AND SOFT START

The power-on ramp-up time of the output voltage is set
internally. The ADP3212/NCP3218 steps sequentially through
each VID code until it reaches the boot voltage. The power-up
sequence, including the soft start is illustrated in Figure 12.

After EN is asserted high, the soft start sequence starts. The
core voltage ramps up linearly to the boot voltage. The
ADP3212/NCP3218 regulates at the boot voltage for
approximately 90s. After the boot time is over, CLKEN# is
asserted low. Before CLKEN# is asserted low, the VID pins are
ignored. 9ms after CLKEN# is asserted low, PWRGD is asserted
high.

When a VID input changes, the ADP3212/NCP3218 detects the
change but ignores new code for a minimum of 400 ns. This
delay is required to prevent the device from reacting to digital
signal skew while the 7-bit VID input code is in transition.
Additionally, the VID change triggers a PWRGD masking timer
to prevent
a PWRGD failure. Each VID change resets and retriggers the
internal PWRGD masking timer.

As listed in Table 6, during a VID transient, the
ADP3212/NCP3218 forces PWM mode regardless of the state
of the system input signals. For example, this means that if the
chip is configured as a dual-phase controller but is running in
single-phase mode due to a light load condition, a current
overload event causes the chip to switch to dual-phase mode to
share the excessive load until the delayed current limit latch-off
cycle terminates.

VCC = 5V

EN

V

= 1.1V

BOOT

V

CORE

t

BOOT

CLKEN

t

CPU_PWRGD

PWRGD

Figure 12. Power-Up Sequence of ADP3212/NCP3218

CURRENT LIMIT

The ADP3212/NCP3218 compares the differential output of a
current sense amplifier to a programmable current limit
setpoint to provide the current-limiting function. The current
limit threshold is set by the user with a resistor connected from
the ILIM pin to CSCOMP.

CHANGING VID ON THE FLY

The ADP3212/NCP3218 is designed to track dynamically
changing VID code. As a consequence, the CPU VCC voltage can
change without the need to reset the controller or the CPU. This
concept is commonly referred to as VID on-the-fly (VID OTF)
transient. A VID OTF can occur with either light or heavy load
conditions. The processor alerts the controller that a VID change
is occurring by changing the VID inputs in LSB incremental
steps from the start code to the finish code. The change can be
either upwards or downwards steps.

Rev. SpA | Page 21 of 43

In user-set single-phase mode, the ADP3212/NCP3218 usually
runs in RPM mode. When a VID transition occurs, however,
the ADP3212/NCP3218 switches to dual-phase PWM mode.

Light Load RPM DCM Operation

In single-phase normal mode, DPRSLP is pulled low and the
APD3208 operates in continuous conduction mode (CCM)
over the entire load range. The upper and lower MOSFETs run
synchronously and in complementary phase. See Figure 13 for
the typical waveforms of the ADP3212/NCP3218 running in
CCM with a 7 A load current.

4

2

3

1

OUTPUT VOLTAGE 20mV/DIV

INDUCTOR CURRENT 5A/DIV

SWITCH NODE 5V/DIV

LOW-SIDE GATE DRIVE 5V/DIV

400ns/DIV

Figure 13. Single-Phase Waveforms in CCM

06374-030

If DPRSLP is pulled high, the ADP3212/NCP3218 operates in
RPM mode. If the load condition is light, the chip enters
discontinuous conduction mode (DCM). Figure 14 shows a
typical single-phase buck with one upper FET, one lower FET,
an output inductor, an output capacitor, and a load resistor.
Figure 15 shows the path of the inductor current with the upper
FET on and the lower FET off. In Figure 16 the high-side FET is
off and the low-side FET is on. In CCM, if one FET is on, its
complementary FET must be off; however, in DCM, both high-

ADP3212/NCP3218

V

and low-side FETs are off and no current flows into the inductor
(see Figure 17). Figure 18 shows the inductor current and switch
node voltage in DCM.

OFF

L

In DCM with a light load, the ADP3212/NCP3218 monitors the
switch node voltage to determine when to turn off the low-side
FET. Figure 19 shows a typical waveform in DCM with a 1 A load
current. Between t

and t2, the inductor current ramps down. The

1

current flows through the source drain of the low-side FET and
creates a voltage drop across the FET with a slightly negative
switch node. As the inductor current ramps down to 0 A, the
switch voltage approaches 0 V, as seen just before t

. When the

2

switch voltage is approximately −6 mV, the low-side FET is
turned off.

Figure 18 shows a small, dampened ringing at t

. This is caused by

2

the LC created from capacitance on the switch node, including
the C

of the FETs and the output inductor. This ringing is normal.

DS

The ADP3212/NCP3218 automatically goes into DCM with a
light load. Figure 19 shows the typical DCM waveform of the
ADP3212/NCP3218. As the load increases, the
ADP3212/NCP3218 enters into CCM. In DCM, frequency
decreases with load current. Figure 20 shows switching frequency
vs. load current for a typical design. In DCM, switching frequency
is a function of the inductor, load current, input voltage, and
output voltage.

Q1

INPUT

OLTAGE

DRVH

DRVL

Q2

SWITCH

NODE

L

Figure 14. Buck Topology

ON

L

OFF

Figure 15. Buck Topology Inductor Current During t

C

OUTPUT

VOLTAGE

C

LOAD

LOAD

and t1

0

06374-031

06374-032

C

OFF

Figure 17. Buck Topology Inductor Current During t

INDUCTOR

CURRENT

SWITCH

NODE

VOLTAGE

t0t

1

t

2

t3t

LOAD

and t3

2

4

Figure 18. Inductor Current and Switch Node in DCM

4

OUTPUT VO LTAGE

20mV/DIV

SWITCH NODE 5V/DIV

2

INDUCTOR CURRENT

3

1

LOW-SIDE GATE DRIVE 5V/DIV

5A/DIV

2µs/DIV

Figure 19. Single-Phase Waveforms in DCM with 1 A Load Current

06374-034

06374-035

06374-036

OFF

L

C

ON

Figure 16. Buck Topology Inductor Current During t1 and t

LOAD

06374-033

2

Rev. SpA | Page 22 of 43

ADP3212/NCP3218

400

350

300

250

200

150

FREQUENCY (kHz)

100

50

Figure 20. Single-Phase CCM/DCM Frequency vs. Load Current

9V INPUT

19V INPUT

0

2 4 6 8 10 12

014

LOAD CURRENT (A)

06374-037

Rev. SpA | Page 23 of 43

ADP3212/NCP3218

OUTPUT CROWBAR

To prevent the CPU and other external components from
damage due to overvoltage, the ADP3212/NCP3218 turns off
the DRVH1 and DRVH2 outputs and turns on the DRVL1 and
DRVL2 outputs when the output voltage exceeds the OVP
threshold (1.55 V typical).

Turning on the low-side MOSFETs forces the output capacitor
to discharge and the current to reverse due to current build up
in the inductors. If the output overvoltage is due to a drain­source short of the high-side MOSFET, turning on the low-side
MOSFET results in a crowbar across the input voltage rail. The
crowbar action blows the fuse of the input rail, breaking the
circuit and thus protecting the microprocessor from
destruction.

When the OVP feature is triggered, the ADP3212/NCP3218 is
latched off. The latch-off function can be reset by removing and
reapplying VCC to the ADP3212/NCP3218 or by briefly pulling
the EN pin low.

Pulling TTSNS to less than 1 V disables the overvoltage
protection function. In this configuration, VRTT should be tied
to ground.

REVERSE VOLTAGE PROTECTION

Very large reverse current in inductors can cause negative V
voltage, which is harmful to the CPU and other output
components. The ADP3212/NCP3218 provides a reverse
voltage protection (RVP) function without additional system
cost. The V

voltage is monitored through the CSREF pin.

CORE

When the CSREF pin voltage drops to less than −300 mV, the
ADP3212/NCP3218 triggers the RVP function by disabling all
PWM outputs and driving DRVL1 and DRVL2 low, thus
turning off all MOSFETs. The reverse inductor currents can be
quickly reset to 0 by discharging the built-up energy in the
inductor into the input dc voltage source via the forward-biased
body diode of the high-side MOSFETs. The RVP function is
terminated when the CSREF pin voltage returns to greater than

−100 mV.

Sometimes the crowbar feature inadvertently causes output
reverse voltage because turning on the low-side MOSFETs
results in a very large reverse inductor current. To prevent
damage to the CPU caused from negative voltage, the
ADP3212/NCP3218 maintains its RVP monitoring function
even after OVP latch-off. During OVP latch-off, if the CSREF

CORE

pin voltage drops to less than −300 mV, the low-side MOSFETs
is turned off. DRVL outputs are allowed to turn back on when
the CSREF voltage recovers to greater than −100 mV.

OUTPUT ENABLE AND UVLO

For the ADP3212/NCP3218 to begin switching, the VCC supply
voltage to the controller must be greater than the V

CCOK

threshold and the EN pin must be driven high. If the VCC
voltage is less than the V

threshold or the EN pin is a logic

CCUVLO

low, the ADP3212/NCP3218 shuts off. In shutdown mode, the
controller holds the PWM outputs low, shorts the capacitors of
the SS and PGDELAY pins to ground, and drives the DRVH
and DRVL outputs low.

The user must adhere to proper power-supply sequencing during
startup and shutdown of the ADP3212/NCP3218. All input pins
must be at ground prior to removing or applying VCC, and all
output pins should be left in high impedance state while VCC is
off.

THERMAL THROTTLING CONTROL

The ADP3212/NCP3218 includes a thermal monitoring circuit
to detect whether the temperature of the VR has exceeded a
user-defined thermal throttling threshold. The thermal
monitoring circuit requires an external resistor divider
connected between the VCC pin and GND. The divider consists
of an NTC thermistor and a resistor. To generate a voltage that
is proportional to temperature, the midpoint of the divider is
connected to the TTSNS pin. An internal comparator circuit
compares the TTSNS voltage to half the VCC threshold and
outputs a logic level signal at the VRTT output when the
temperature trips the user-set alarm threshold. The VRTT
output is designed to drive an external transistor that in turn
provides the high current, open-drain VRTT signal required by
the IMVP-6.5 specification. The internal VRTT comparator has a
hysteresis of approximately 100 mV to prevent high frequency
oscillation of VRTT when the temperature approaches the set
alarm point.

OUTPUT CURRENT MONITOR

The ADP3212/NCP3218 has an output current monitor. The
IMON pin sources a current proportional to the inductor
current. A resistor from IMON pin to FBRTN sets the gain. A

0.1 µF is added in parallel with R
ripple. The IMON pin is clamped to prevent it from going
above 1.15V.

to filter the inductor

MON

Rev. SpA | Page 24 of 43

ADP3212/NCP3218

Table 6. VID Codes

VID6 VID5 VID4 VID3 VID2 VID1 VID0 Output

0 0 0 0 0 0 0 1.5000 V
0 0 0 0 0 0 1 1.4875 V
0 0 0 0 0 1 0 1.4750 V
0 0 0 0 0 1 1 1.4625 V
0 0 0 0 1 0 0 1.4500 V
0 0 0 0 1 0 1 1.4375 V
0 0 0 0 1 1 0 1.4250 V
0 0 0 0 1 1 1 1.4125 V
0 0 0 1 0 0 0 1.4000 V
0 0 0 1 0 0 1 1.3875 V
0 0 0 1 0 1 0 1.3750 V
0 0 0 1 0 1 1 1.3625 V
0 0 0 1 1 0 0 1.3500 V
0 0 0 1 1 0 1 1.3375 V
0 0 0 1 1 1 0 1.3250 V
0 0 0 1 1 1 1 1.3125 V
0 0 1 0 0 0 0 1.3000 V
0 0 1 0 0 0 1 1.2875 V
0 0 1 0 0 1 0 1.2750 V
0 0 1 0 0 1 1 1.2625 V
0 0 1 0 1 0 0 1.2500 V
0 0 1 0 1 0 1 1.2375 V
0 0 1 0 1 1 0 1.2250 V
0 0 1 0 1 1 1 1.2125 V
0 0 1 1 0 0 0 1.2000 V
0 0 1 1 0 0 1 1.1875 V
0 0 1 1 0 1 0 1.1750 V
0 0 1 1 0 1 1 1.1625 V
0 0 1 1 1 0 0 1.1500 V
0 0 1 1 1 0 1 1.1375 V
0 0 1 1 1 1 0 1.1250 V
0 0 1 1 1 1 1 1.1125 V
0 1 0 0 0 0 0 1.1000 V
0 1 0 0 0 0 1 1.0875 V
0 1 0 0 0 1 0 1.0750 V
0 1 0 0 0 1 1 1.0625 V
0 1 0 0 1 0 0 1.0500 V
0 1 0 0 1 0 1 1.0375 V
0 1 0 0 1 1 0 1.0250 V
0 1 0 0 1 1 1 1.0125 V
0 1 0 1 0 0 0 1.0000 V
0 1 0 1 0 0 1 0.9875 V
0 1 0 1 0 1 0 0.9750 V
0 1 0 1 0 1 1 0.9625 V
0 1 0 1 1 0 0 0.9500 V
0 1 0 1 1 0 1 0.9375 V
0 1 0 1 1 1 0 0.9250 V
0 1 0 1 1 1 1 0.9125 V
0 1 1 0 0 0 0 0.9000 V
0 1 1 0 0 0 1 0.8875 V
0 1 1 0 0 1 0 0.8750 V
0 1 1 0 0 1 1 0.8625 V
0 1 1 0 1 0 0 0.8500 V
0 1 1 0 1 0 1 0.8375 V
0 1 1 0 1 1 0 0.8250 V
0 1 1 0 1 1 1 0.8125 V
0 1 1 1 0 0 0 0.8000 V

VID6 VID5 VID4 VID3 VID2 VID1 VID0 Output

0 1 1 1 0 0 1 0.7875 V
0 1 1 1 0 1 0 0.7750 V
0 1 1 1 0 1 1 0.7625 V
0 1 1 1 1 0 0 0.7500 V
0 1 1 1 1 0 1 0.7375 V
0 1 1 1 1 1 0 0.7250 V
0 1 1 1 1 1 1 0.7125 V
1 0 0 0 0 0 0 0.7000 V
1 0 0 0 0 0 1 0.6875 V
1 0 0 0 0 1 0 0.6750 V
1 0 0 0 0 1 1 0.6625 V
1 0 0 0 1 0 0 0.6500 V
1 0 0 0 1 0 1 0.6375 V
1 0 0 0 1 1 0 0.6250 V
1 0 0 0 1 1 1 0.6125 V
1 0 0 1 0 0 0 0.6000 V
1 0 0 1 0 0 1 0.5875 V
1 0 0 1 0 1 0 0.5750 V
1 0 0 1 0 1 1 0.5625 V
1 0 0 1 1 0 0 0.5500 V
1 0 0 1 1 0 1 0.5375 V
1 0 0 1 1 1 0 0.5250 V
1 0 0 1 1 1 1 0.5125 V
1 0 1 0 0 0 0 0.5000 V
1 0 1 0 0 0 1 0.4875 V
1 0 1 0 0 1 0 0.4750 V
1 0 1 0 0 1 1 0.4625 V
1 0 1 0 1 0 0 0.4500 V
1 0 1 0 1 0 1 0.4375 V
1 0 1 0 1 1 0 0.4250 V
1 0 1 0 1 1 1 0.4125 V
1 0 1 1 0 0 0 0.4000 V
1 0 1 1 0 0 1 0.3875 V
1 0 1 1 0 1 0 0.3750 V
1 0 1 1 0 1 1 0.3625 V
1 0 1 1 1 0 0 0.3500 V
1 0 1 1 1 0 1 0.3375 V
1 0 1 1 1 1 0 0.3250 V
1 0 1 1 1 1 1 0.3125 V
1 1 0 0 0 0 0 0.3000 V
1 1 0 0 0 0 1 0.2875 V
1 1 0 0 0 1 0 0.2750 V
1 1 0 0 0 1 1 0.2625 V
1 1 0 0 1 0 0 0.2500 V
1 1 0 0 1 0 1 0.2375 V
1 1 0 0 1 1 0 0.2250 V
1 1 0 0 1 1 1 0.2125 V
1 1 0 1 0 0 0 0.2000 V
1 1 0 1 0 0 1 0.1875 V
1 1 0 1 0 1 0 0.1750 V
1 1 0 1 0 1 1 0.1625 V
1 1 0 1 1 0 0 0.1500 V
1 1 0 1 1 0 1 0.1375 V
1 1 0 1 1 1 0 0.1250 V
1 1 0 1 1 1 1 0.1125 V
1 1 1 0 0 0 0 0.1000 V
1 1 1 0 0 0 1 0.0875 V

ADP3212/NCP3218

VID6 VID5 VID4 VID3 VID2 VID1 VID0 Output

1 1 1 0 0 1 0 0.0750 V
1 1 1 0 0 1 1 0.0625 V
1 1 1 0 1 0 0 0.0500 V
1 1 1 0 1 0 1 0.0375 V
1 1 1 0 1 1 0 0.0250 V
1 1 1 0 1 1 1 0.0125 V
1 1 1 1 0 0 0 0.0000 V

VID6 VID5 VID4 VID3 VID2 VID1 VID0 Output

1 1 1 1 0 0 1 0.0000 V
1 1 1 1 0 1 0 0.0000 V
1 1 1 1 0 1 1 0.0000 V
1 1 1 1 1 0 0 0.0000 V
1 1 1 1 1 0 1 0.0000 V
1 1 1 1 1 1 0 0.0000 V
1 1 1 1 1 1 1 0.0000 V

Rev. SpA | Page 26 of 43

ADP3212/NCP3218

Figure 21. Typical Dual-Phase Application Circuit

Rev. SpA | Page 27 of 43

ADP3212/NCP3218

×

−

×

APPLICATION INFORMATION

The design parameters for a typical IMVP-6.5-compliant CPU
core VR application are as follows:

• Maximum input voltage (V

• Minimum input voltage (V

• Output voltage by VID setting (V

• Maximum output current (I

• Droop resistance (R

) = 1.9 mΩ

O

• Nominal output voltage at 40 A load (V

INMAX

) = 8 V

INMIN

) = 52 A

O

) = 19 V

) = 1.05 V

VID

) = 0.9512 V

OFL

• Static output voltage drop from no load to full load

(∆V) = V

• Maximum output current step (∆I

ONL

− V

= 1.05 V − 0.9512 V = 98 mV

OFL

) = 52 A

O

• Number of phases (n) = 2

• Switching frequency per phase (f

• Duty cycle at maximum input voltage (D

• Duty cycle at minimum input voltage (D

) = 300 kHz

SW

MIN

) = 0.13 V

MAX

) = 0.055 V

SETTING THE CLOCK FREQUENCY FOR PWM

In PWM operation, the ADP3212/NCP3218 uses a fixed­frequency control architecture. The frequency is set by an
external timing resistor (RT). The clock frequency and the
number of phases determine the switching frequency per phase,
which relates directly to the switching losses and the sizes of the
inductors and input and output capacitors. For a dual-phase
design, a clock frequency
of 600 kHz sets the switching frequency to 300 kHz per phase.
This selection represents the trade-off between the switching
losses and the minimum sizes of the output filter components.
To achieve a 600 kHz oscillator frequency at a VID voltage of

1.2 V, RT must be 181 kΩ. Alternatively, the value for RT can
be calculated by using the following equation:

+

VV

1

= k

R

T

VID

SW

×××

pFfn

92

where:
9 pF and 16 kΩ are internal IC component values.

is the VID voltage in volts.

V

VID

n is the number of phases.

is the switching frequency in hertz for each phase.

f

SW

For good initial accuracy and frequency stability, it is
recommended to use a 1% resistor.

When VARFREQ pin is connected to ground, the switching
frequency does not change with VID. The value for RT can be
calculated by using the following equation.

V

R

= k

T

1

×××

pFfn

92

SW

Ω−

16

(1)

Ω−

16

(2)

Rev. SpA | Page 28 of 43

SETTING THE SWITCHING FREQUENCY FOR
RPM OPERATION OF PHASE 1

During the RPM operation of Phase 1, the ADP3212/NCP3218
runs in pseudoconstant frequency if the load current is high
enough for continuous current mode. While in DCM, the
switching frequency is reduced with the load current in a linear
manner.

To save power with light loads, lower switching frequency is
usually preferred during RPM operation. However, the V

CORE

ripple specification of IMVP-6.5 sets a limitation for the lowest
switching frequency. Therefore, depending on the inductor and
output capacitors, the switching frequency in RPM can be equal
to, greater than, or less than its counterpart in PWM.

A resistor from RPM to GND sets the pseudo constant
frequency as following:

VDA

×−×

R

2

R

= k5.0

RPM

T

V

VID

×

+

V0.1

)1(

VIDR

fCR

××

SWRR

(3

Ω−

)where:

is the internal ramp amplifier gain.

A

R

is the internal ramp capacitor value.

C

R

is an external resistor on the RAMPADJ pin to set the

R

R

internal ramp magnitude.

SOFT START AND CURRENT LIMIT
LATCH-OFF DELAY TIMES

INDUCTOR SELECTION

The choice of inductance determines the ripple current of the
inductor. Less inductance results in more ripple current, which
increases the output ripple voltage and the conduction losses in the
MOSFETs. However, this allows the use of smaller-size inductors,
and for a specified peak-to-peak transient deviation, it allows
less total output capacitance. Conversely, a higher inductance
results in lower ripple current and reduced conduction losses,
but it requires larger-size inductors and more output capacitance
for the same peak-to-peak transient deviation. For a multiphase
converter, the practical value for peak-to-peak inductor ripple
current is less than 50% of the maximum dc current of that
inductor. Equation 4 shows the relationship between the
inductance, oscillator frequency, and peak-to-peak ripple
current. Equation 5 can be used to determine the minimum
inductance based on a given output ripple voltage.

)1(

DV

MINVID

=

I

R

SW

×

(4)

Lf

ADP3212/NCP3218

DnRV

×−××

))(1(

MINOVID

L

≥

Vf

×

RIPPLESW

(5)

Solving Equation 5 for a 16 mV peak-to-peak output ripple
voltage yields

≥L

()

×

055.021mΩ9.1V051.

×−××

=

nH528

mV16kHz003

If the resultant ripple voltage is less than the initially selected
value, the inductor can be changed to a smaller value until the
ripple value is met. This iteration allows optimal transient
response and minimum output decoupling.

The smallest possible inductor should be used to minimize the
number of output capacitors. Choosing a 490 nH inductor is a
good choice for a starting point, and it provides a calculated
ripple current of 9.0 A. The inductor should not saturate at the
peak current of 24.5 A, and it should be able to handle the sum
of the power dissipation caused by the winding’s average current
(20 A) plus the ac core loss. In this example, 330 nH is used.

The output current is measured by summing the currents of the
resistors monitoring the voltage across each inductor and by
passing the signal through a low-pass filter. The summing is
implemented by the CS amplifier that is configured with resistor
R

(summer) and resistors RCS and CCS (filters). The output

PH(x)

resistance of the regulator is set by the following equations:

R

R ×=

C×=

where R

Either R

CS

O

R

)(

xPH

L

CS

is the DCR of the output inductors.

SENSE

or R

CS

PH(x)

the current drive ability of the CSCOMP pin, the R
should be greater than 100 kΩ. For example, initially select R
to be equal to 200 kΩ, and then use Equation 7 to solve for C

=

C

CS

(6)

R

SENSE

(7)

RR

CSSENSE

can be chosen for added flexibility. Due to

resistance

CS

CS

CS

nH330

×

=

k200m8.0

nF1.2

:

Another important factor in the inductor design is the DCR,
which is used for measuring the phase currents. Too large of a
DCR causes excessive power losses, whereas too small of a value
leads to increased measurement error. For this example, an
inductor with a DCR of 0.8 mΩ is used.

Selecting a Standard Inductor

After the inductance and DCR are known, select a standard
inductor that best meets the overall design goals. It is also
important to specify the inductance and DCR tolerance to
maintain the accuracy of the system. Using 20% tolerance for
the inductance and 15% for the DCR at room temperature are
reasonable values that most manufacturers can meet.

Power Inductor Manufacturers

The following companies provide surface-mount power inductors
optimized for high power applications upon request:

Vishay Dale Electronics, Inc.

•

[phone]

Panasonic

•

[phone]

Sumida Electric Company

•

[phone]

NEC Tokin Corporation

•

[phone]

is not a standard capacitance, RCS can be tuned. For

If C

CS

example, if the optimal C
280 kΩ. For best accuracy, C
In this example, a 220 kΩ is used for R

capacitance is 1.5 nF, adjust RCS to

CS

should be a 5% NPO capacitor.

CS

to achieve optimal results.

CS

Next, solve for R

R

)(

xPH

The standard 1% resistor for R

by rearranging Equation 6 as follows:

PH(x)

m8.0

m1.2

=×≥

PH(x)

k8.83k220

is 86.6 kΩ.

Inductor DCR Temperature Correction

If the DCR of the inductor is used as a sense element and
copper wire is the source of the DCR, the temperature changes
associated with the inductor’s winding must be compensated
for. Fortunately, copper has a well-known temperature
coefficient (TC) of 0.39%/°C.

If R

is designed to have an opposite but equal percentage of

CS

change in resistance, it cancels the temperature variation of the
inductor’s DCR. Due to the nonlinear nature of NTC thermistors,
series resistors R

CS1

and R

(see Figure 22) are needed to linearize

CS2

the NTC and produce the desired temperature coefficient tracking.

Output Droop Resistance

The design requires that the regulator output voltage measured
at the CPU pins decreases when the output current increases. The
specified voltage drop corresponds to the droop resistance (R

O

Rev. SpA | Page 29 of 43

).

ADP3212/NCP3218

−

××=

r

+−×

=

Figure 22. Temperature-Compensation Circuit Values

The following procedure and expressions yield values for
R

, R

, and RTH (the thermistor value at 25°C) for a given

CS1

CS2

value.

R

CS

1.

Select an NTC to be used based on its type and value.

Because the value needed is not yet determined, start with
a thermistor with a value close to R
initial tolerance of better than 5%.

2.

Find the relative resistance value of the NTC at two

temperatures. The appropriate temperatures will depend
on the type of NTC, but 50°C and 90°C have been shown
to work well for most types of NTCs. The resistance values
are called A (A is R

(90°C)/RTH(25°C)). Note that the relative value of the

R

TH

(50°C)/RTH(25°C)) and B (B is

TH

NTC is always 1 at 25°C.

and an NTC with an

CS

3.

Find the relative value of R

temperatures. The relative value of R

required for each of the two

CS

is based on the

CS

percentage of change needed, which is initially assumed to
be 0.39%/°C in this example.
The relative values are called r
and r

(r2 is 1/(1 + TC × (T2 − 25))), where TC is 0.0039,

2

T

is 50°C, and T2 is 90°C.

1

4.

Compute the relative values for r

the following equations:

r

= (8)

CS2

)1(

=

r

CS1

r

=

TH

Calculate R

5.

1

−

1

−

A

1

r

CS2

A

−

rr

−

1

CS2

1

1

1

−

rr

CS1CS2

= rTH × RCS, and then select a thermistor of

TH

(r1 is 1/(1+ TC × (T1 − 25)))

1

, r

, and rTH by using

CS1

CS2

21

)1()1()(

rABrBArrBA

×−×+×−×−××−

1221

)()1()1(

BArABrBA

−−×−×−×−×

the closest value available. In addition, compute a scaling
factor k based on the ratio of the actual thermistor value
used relative to the computed one:

R

k =

ACTUALTH

R

(9)

)()(CALCULATEDTH

6.

Calculate values for R

CS1

and R

by using the following

CS2

equations:

rkRR

(10)

CS1CSCS1

))()1((

kkRR ×

CS2CSCS2

For example, if a thermistor value of 100 kΩ is selected in Step 1,
an available 0603-size thermistor with a value close to R

is the

CS

Vishay NTHS0603N04 NTC thermistor, which has resistance
values of A = 0.3359 and B = 0.0771. Using the equations in
Step 4, r

is 0.359, r

CS1

is 0.729, and rTH is 1.094. Solving for rTH

CS2

yields 241 kΩ, so a thermistor of 220 kΩ would be a reasonable
selection, making k equal to 0.913. Finally, R

CS1

and R

are found

CS2

to be 72.1 kΩ and 166 kΩ. Choosing the closest 1% resistor for

yields 165 kΩ. To correct for this approximation, 73.3 kΩ

R

CS2

is used for R

CS1

.

Rev. SpA | Page 30 of 43

ADP3212/NCP3218

(

C

SELECTION

OUT

The required output decoupling for processors and platforms is
typically recommended by Intel. For systems containing both
bulk and ceramic capacitors, however, the following guidelines
can be a helpful supplement.

Select the number of ceramics and determine the total ceramic
capacitance (C

). This is based on the number and type of

Z

capacitors used. Keep in mind that the best location to place
ceramic capacitors is inside the socket; however, the physical
limit is twenty 0805-size pieces inside the socket. Additional
ceramic capacitors can be placed along the outer edge of the
socket. A combined ceramic capacitor value of 200 µF to 300 µF
is recommended and is usually composed of multiple 10 µF or
22 µF capacitors.

Ensure that the total amount of bulk capacitance (C

) is within

X

its limits. The upper limit is dependent on the VID on-the-fly
output voltage stepping (voltage step, V

); the lower limit is based on meeting the critical capacitance

of V

ERR

for load release at a given maximum load step, ∆I
version of the IMVP-6.5 specification allows a maximum V
overshoot (V

) of 10 mV more than the VID voltage for a

OSMAX

, in time, tV, with error

V

. The current

O

CORE

step-off load current.

⎛
⎜

⎜

C

C −

where

≥

⎜

()

MINX

MAXX

)(

k ln

⎛

⎜

⎜

Rn

⎜

⎜
⎝

⎝

L

≤ 11

Rkn

××

⎛

V

⎜

−=
⎜

V

⎝

Δ×

IL

O

⎞

OSMAX

⎟

×

V

VID

⎟

Δ

I

O

⎠

⎛

⎛

⎜

V

VID

⎜

t

v

⎜

⎜

⎜

⎝

⎝

(12)

22

O

ERR

V

+×

O

V

V

⎞
⎟
⎟

V

⎠

⎞
⎟

⎟

−

C

(11)

⎟

Z

⎟
⎟
⎠

2

⎞

⎞

Rkn

V

VID

V

V

××

×+××

L

⎟

O

⎟
⎟
⎠

C

−

Z

⎟
⎟
⎠

To meet the conditions of these expressions and the transient
response, the ESR of the bulk capacitor bank (R
than two times the droop resistance, R
than C

, the system does not meet the VID on-the-fly

X(MAX)

. If the C

O

) should be less

X

is greater

X(MIN)

and/or the deeper sleep exit specifications and may require less
inductance or more phases. In addition, the switching frequency
may have to be increased to maintain the output ripple.

For example, if 30 pieces of 10 µF, 0805-size MLC capacitors

= 300 µF) are used, the fastest VID voltage change is when

(C

Z

the device exits deeper sleep, during which the V

change is

CORE

220 mV in 22 µs with a setting error of 10 mV. If k = 3.1, solving
for the bulk capacitance yields

C

()

MINX

C

()

MAXX

⎛
⎜

+

1

⎜
⎜

⎝

⎛
⎜

⎜
⎜

≥

⎛

⎜

⎜

⎜
⎜

⎝

m1.22

⎜
⎝

≤

⎛
⎜
⎜
⎝

×

A9.27nH330

⎞

mV10

⎟

+×

×

×

⎟

A9.27

⎠

mV220nH330

22

×××

××××

×

nH049mV022

−

V4375.1

×

V4375.1)m1.2(1.32

2

⎞

m1.21.32V75341.s22

⎟

−

⎟
⎠

⎞
⎟

⎟
⎟

=

mF0.1F300

⎟
⎟

⎟
⎠

⎞
⎟

−

⎟
⎟

⎠

F3001

= 21 mF

Using six 330 µF Panasonic SP capacitors with a typical ESR of
7 mΩ each yields C

Ensure that the ESL of the bulk capacitors (L

= 1.98 mF and RX = 1.2 mΩ.

X

) is low enough to

X

limit the high frequency ringing during a load change. This is
tested using

2

2

QRCL

××≤

X

O

Z

(13)

2

)

nH22m1.2F300

=××≤XL

where:

Q is limited to the square root of 2 to ensure a critically damped

system.

L

is about 150 pH for the six SP capacitors, which is low

X

enough to avoid ringing during a load change. If the L

of the

X

chosen bulk capacitor bank is too large, the number of ceramic
capacitors may need to be increased to prevent excessive
ringing.

For this multimode control technique, an all ceramic capacitor
design can be used if the conditions of Equations 11, 12, and 13
are satisfied.

Rev. SpA | Page 31 of 43

ADP3212/NCP3218

V

F

V

×

POWER MOSFETS

For typical 20 A per phase applications, the N-channel power
MOSFETs are selected for two high-side switches and two or
three low-side switches per phase. The main selection
parameters for the power MOSFETs are V
and R

. Because the voltage of the gate driver is 5 V, logic-

DS(ON)

GS(TH)

, QG, C

level threshold MOSFETs must be used.

The maximum output current, I

, determines the R

O

requirement for the low-side (synchronous) MOSFETs. In the
ADP3212/NCP3218, currents are balanced between phases; the
current in each low-side MOSFET is the output current divided
by the total number of MOSFETs (n

). With conduction losses

SF

being dominant, the following expression shows the total power
that is dissipated in each synchronous MOSFET in terms of the
ripple current per phase (I
current (I

):

O

×−= (14)

)1(

SF

DP ×

) and the average total output

R

⎡

⎛

⎞

I

O

⎜

⎟

⎢

⎜

⎟

n

⎢

SF

⎝

⎠

⎣

12

⎛

×

1

⎜

×+

⎜

n

SF

⎝

22

⎤

⎞

In

R

⎟

⎥

⎟

⎥

⎠

⎦

where:
D is the duty cycle and is approximately the output voltage
divided by the input voltage.

I

is the inductor peak-to-peak ripple current and is

R

approximately

D

×−=)1(

I

R

OUT

fL

×

SW

Knowing the maximum output current and the maximum
allowed power dissipation, the user can calculate the required
R

for the MOSFET. For 8-lead SOIC or 8-lead SOIC-

DS(ON)

compatible MOSFETs, the junction-to-ambient (PCB) thermal
impedance is 50°C/W. In the worst case, the PCB temperature is
70°C to 80°C during heavy load operation of the notebook, and
a safe limit for P

is about 0.8 W to 1.0 W at 120°C junction tem-

SF

perature. Therefore, for this example (40 A maximum), the R
per MOSFET is less than 8.5 mΩ for two pieces of low-side
MOSFETs. This R
120°C; therefore, the R

is also at a junction temperature of about

DS(SF)

per MOSFET should be less than

DS(SF)

6 mΩ at room temperature, or 8.5 mΩ at high temperature.

Another important factor for the synchronous MOSFET is the
input capacitance and feedback capacitance. The ratio of the
feedback to input must be small (less than 10% is recommended)
to prevent accidentally turning on the synchronous MOSFETs
when the switch node goes high.

The high-side (main) MOSFET must be able to handle two
main power dissipation components: conduction losses and
switching losses. Switching loss is related to the time for the
main MOSFET to turn on and off and to the current and

, C

,

ISS

RSS

DS(ON)

R

)(

SFDS

DS(SF)

voltage that are being switched. Basing the switching speed on
the rise and fall times of the gate driver impedance and
MOSFET input capacitance, the following expression provides
an approximate value for the switching loss per main MOSFET:

I

fP ×××

××= 2

)(

MFS

SW

ODC

n

M

n

MF

R

G

C

(15)

ISS

n

where:

n

is the total number of main MOSFETs.

MF

R

is the total gate resistance.

G

C

is the input capacitance of the main MOSFET.

ISS

The most effective way to reduce switching loss is to use lower
gate capacitance devices.

The conduction loss of the main MOSFET is given by the
following equation:

⎡

where R

MFC

DS(MF)

⎜

⎟

n

⎢

MF

⎝

⎠

⎣

is the on resistance of the MOSFET.

⎛

⎞

I

O

⎜

⎟

⎢

×= (16)

DP ×

)(

12

⎛

1

⎜

×+

⎜
⎝

Typically, a user wants the highest speed (low C

22

⎤

⎞

×

In

R

⎟

⎥

R

)(

⎥
⎦

MFDS

) device

ISS

⎟

n

MF

⎠

for a main MOSFET, but such a device usually has higher on
resistance. Therefore, the user must select a device that meets
the total power dissipation (about 0.8 W to 1.0 W for an 8-lead
SOIC) when combining the switching and conduction losses.

For example, an IRF7821 device can be selected as the main
MOSFET (four in total; that is, n
C

= 1010 pF (maximum) and R

ISS

= 120°C), and an IR7832 device can be selected as the

T

J

synchronous MOSFET (four in total; that is, n

= 6.7 mΩ (maximum at TJ = 120°C). Solving for the

R

DS(SF)

power dissipation per MOSFET at I

= 4), with approximately

MF

= 18 mΩ (maximum at

DS(MF)

= 4), with

SF

= 40 A and IR = 9.0 A

O

yields 630 mW for each synchronous MOSFET and 590 mW
for each main MOSFET. A third synchronous MOSFET is an
option to further increase the conversion efficiency and reduce
thermal stress.

Finally, consider the power dissipation in the driver for each
phase. This is best described in terms of the Q

for the

G

MOSFETs and is given by the following equation:

f

⎡

SW

P

DRV

where Q

is the total gate charge for each synchronous MOSFET.

Q

GSF

()

⎢
⎣

GMF

MF

n

×=2

is the total gate charge for each main MOSFET, and

The previous equation also shows the standby dissipation (I

⎤

VCCIQnQn

×

+×+××

CCGSFSFGMF

⎥
⎦

(17)

CC

times the VCC) of the driver.

Rev. SpA | Page 32 of 43

ADP3212/NCP3218

×

RAMP RESISTOR SELECTION

The ramp resistor (RR) is used to set the size of the internal PWM
ramp. The value of this resistor is chosen to provide the best
combination of thermal balance, stability, and transient response.
Use the following expression to determine a starting value:

×

LA

=

R

R

=

R

R

where:

is the internal ramp amplifier gain.

A

R

is the current balancing amplifier gain.

A

D

is the total low-side MOSFET on resistance.

R

DS

is the internal ramp capacitor value.

C

R

Another consideration in the selection of R
internal ramp voltage (see Equation 19). For stability and noise
immunity, keep the ramp size larger than 0.5 V. Taking this into
consideration, the value of R

The internal ramp voltage magnitude can be calculated as follows:

=

V

R

=

V

R

The size of the internal ramp can be increased or decreased. If it
is increased, stability and transient response improves but
thermal balance degrades. Conversely, if the ramp size is
decreased, thermal balance improves but stability and transient
response degrade. In the denominator of Equation 18, the factor
of 3 sets the minimum ramp size that produces an optimal
combination of good stability, transient response, and thermal
balance.

R

×××

3

CRA

RDSD

(18)

×

nH3605.0

×Ω××

pF5m2.553

in this example is selected as 280 kΩ.

R

)1(

×−×

VDA

VIDR

××

fCR

SWRR

Ω=

k462

is the size of the

R

(19)

×−×

××Ω

V150.1)061.01(5.0

V83.0

=

kHz280pF5k462

where:
R

is the current limit resistor.

LIM

is the output load line.

R

O

is the current limit setpoint.

I

LIM

When the ADP3212/NCP3218 is configured for 3 phase
operation, the equation above is used to set the current limit.
When the ADP3212/NCP3218 switches from 3 phase to 1 phase
operation by PSI or DPRSLP signal, the current is single phase
is one third of the current limit in 3 phase.

When the ADP3212/NCP3218 is configured for 2 phase
operation, the equation above is used to set the current limit.
When the ADP3212/NCP3218 switches from 2 phase to 1 phase
operation by PSI or DPRSLP signal, the current is single phase
is one half of the current limit in 2 phase.

When the ADP3212/NCP3218 is configured for 1 phase
operation, the equation above is used to set the current limit.

CURRENT MONITOR

The ADP3212/NCP3218 has output current monitor. The
IMON pin sources a current proportional to the total inductor
current. A resistor, R
of the output current monitor. A 0.1 µF is placed in parallel with

to filter the inductor current ripple and high frequency

R

MON

load transients. Since the IMON pin is connected directly to the
CPU, it is clamped to prevent it from going above 1.15V.

The IMON pin current is equal to the R

can be found using the following equation:

4. R

MON

15.1

=

R

MON

4

where:
R

is the current monitor resistor. R

MON

IMON pin to FBRTN.

is the current limit resistor.

R

LIM

R

is the output load line resistance.

O

is the output current when the voltage on IMON is at full

I

FS

scale.

, from IMON to FBRTN sets the gain

MON

times a fixed gain of

LIM

RV

LIM

(28)

IR

××

FSO

is connected from

MON

CURRENT LIMIT SETPOINT

To select the current limit setpoint, the resistor value for R
be determined. The current limit threshold for the

. R

ADP3212/NCP3218 is set with R
the following equation:

RI

×

OLIM

R

=

LIM

60

(20)

A

μ

CLIM

can be found using

CLIM

CLIM

must

FEEDBACK LOOP COMPENSATION DESIGN

Optimized compensation of the ADP3212/NCP3218 allows the
best possible response of the regulator’s output to a load change.
The basis for determining the optimum compensation is to
make the regulator and output decoupling appear as an output
impedance that is entirely resistive over the widest possible
frequency range, including dc, and that is equal to the droop
resistance (R

). With the resistive output impedance, the output

O

voltage droops in proportion with the load current at any load

Rev. SpA | Page 33 of 43

ADP3212/NCP3218

+

××−××

(

)

T

×−+

=

current slew rate, ensuring the optimal position and allowing
the minimization of the output decoupling.

With the multimode feedback structure of the
ADP3212/NCP3218, it is necessary to set the feedback
compensation so that the converter’s output impedance works
in parallel with the output decoupling. In addition, it is
necessary to compensate for the several poles and zeros created
by the output inductor and decoupling capacitors (output
filter).

A Type III compensator on the voltage feedback is adequate
for proper compensation of the output filter. Figure 23 shows the
Type III amplifier used in the ADP3212/NCP3218. Figure 24
shows the locations of the two poles and two zeros created by this
amplifier.

f×+=

0

P

f

1

P

1

)(π2

=

CC

π2

(23)

RCC

FBBA

BA

(24)

CCR

×××

ABA

The expressions that follow compute the time constants for
the poles and zeros in the system and are intended to yield an
optimal starting point for the design; some adjustments may be
necessary to account for PCB and component parasitic effects
(see the Tuning Procedure for 12 section):

×

VR

L

RT

(25)

+×+×=

RARnR

E

X

A

XB

D

O

X

()

O

'

DS

))(1(2

VDnL

RT

VRCn

×××

VID

O

L

X

RRCT

O

×+−×=

R

O

(27)

CRRR

X

+

V

VID

RR

''−

O

(26)

R

X

Figure 23. Voltage Error Amplifier

Figure 24. Poles and Zeros of Voltage Error Amplifier

The following equations give the locations of the poles and
zeros shown in Figure 24:

⎛
⎜

LV

−×

RT

⎜

2

T

C

T

D

⎝

=

=

X

×

X

()

O

⎞

RA

×

D

DS

⎟
⎟

f

×

SW

⎠

RV

EVID

Z

'

(28)

2

RCC

××

O

(29)

RCRRC

×+−×

O

Z

where:
R' is the PCB resistance from the bulk capacitors to the ceramics
and is approximately 0.4 mΩ (assuming an 8-layer motherboard).

is the total low-side MOSFET for on resistance per phase.

R

DS

is 5.

A

D

is 1.25 V.

V

RT

is 150 pH for the six Panasonic SP capacitors.

L

X

=

Z1

Z2

1

π2

1

RCf××=π2

(21)

RCf××

AA

(22)

FBFB

Rev. SpA | Page 34 of 43

ADP3212/NCP3218

E

The compensation values can be calculated as follows:

TRn

××

C

A

R =

A

C =

B

C =

FB

=

T

C

C

A

T

B

R

B

T

R

AO

(30)

RR

×

B

(31)

(32)

D

(33)

A

The standard values for these components are subject to the
tuning procedure described in the Tuning Procedure for 12
section.

CIN SELECTION AND INPUT CURRENT
di/dt REDUCTION

In continuous inductor-current mode, the source current of the
high-side MOSFET is approximately a square wave with a duty
ratio equal to
the maximum output current. To prevent large voltage
transients, use a low ESR input capacitor sized for the
maximum rms current. The maximum rms capacitor current
occurs at the lowest input voltage and is given by

n × V

OUT/VIN

××=DnIDI

OCRMS

and an amplitude that is one-nth of

11−

×

(34)

R

C

Where R
C

Snubber

f

is the frequency of the ringing on the switch node when

Rininging

=

Snubber

Snubber

Snubber

2

=

π

is the snubber resistor.

is the snubber capacitor.

the high side MOSFET turns on.
C

is the low side MOSFET output capacitance at V

OSS

taken from the low side MOSFET data sheet.
V

is the input voltage.

input

f

is the switching frequency.

Switching

P

is the power dissipated in R

Snubber

SELECTING THERMAL MONITOR COMPONENTS

To monitor the temperature of a single-point hot spot, set
R

equal to the NTC thermistor’s resistance at the alarm

TTSET1

temperature. For example, if the alarm temperature for VRTT is
100°C and a Vishey thermistor (NTHS-0603N011003J) with a
resistance of 100 kΩ at 25°C, or 6.8 kΩ at 100°C, is used, the
user can set R

equal to 6.8 kΩ (the R

TTSET1

1

π

×××

1

Rf

××

SnubberRinging

2

Snubber

(35)

Cf

OSSRinging

(36)

fVCP ××=

(37)

SwithingInputSnubberSnubber

. This is

Input

.

at 100°C).

TH1

1

I

CRMS

I

where

is the output current.

O

××=

A4018.0

0.182

×

A6.91

=−

In a typical notebook system, the battery rail decoupling is
achieved by using MLC capacitors or a mixture of MLC
capacitors and bulk capacitors. In this example, the input
capacitor bank is formed by eight pieces of 10 µF, 25 V MLC
capacitors, with a ripple current rating of about 1.5 A each.

RC SNUBBER

It is important in any buck topology to use a resistor-capacitor
snubber across the low side power MOSFET. The RC snubber
dampens ringing on the switch node when the high side
MOSFET turns on. The switch node ringing could cause EMI
system failures and increased stress on the power components
and controller. The RC snubber should be placed as close as
possible to the low side MOSFET. Typical values for the resistor
range from 1 Ω to 10 Ω. Typical values for the capacitor range
from 330 pF to 4.7 nF. The exact value of the RC snubber
depends on the PCB layout and MOSFET selection. Some fine
tuning must be done to find the best values. The equation below
is used to find the starting values for the RC subber.

Rev. SpA | Page 35 of 43

Figure 25. Single-Point Thermal Monitoring

To monitor the temperature of multiple-point hot spots, use the
configuration shown in Figure 26. If any of the monitored hot
spots reaches the alarm temperature, the VRTT signal is
asserted. The following calculation sets the alarm temperature:

V

FD

2/1

+

V

=

R ×

TTSET1

where V

is the forward drop voltage of the parallel diode.

FD

REF

R

V

FD

2/1

−

V

REF

(38)

mperatureTH1AlarmTe

Because the forward current is very small, the forward drop
voltage is very low, that is, less than 100 mV. Assuming the same

ADP3212/NCP3218

conditions used for the single-point thermal monitoring
example—that is, an alarm temperature of 100°C and use of an
NTHS-0603N011003J Vishay thermistor—solving Equation 42
gives a R

7.32 kΩ (1%).

The number of hot spots monitored is not limited. The alarm
temperature of each hot spot can be individually set by using
different values for R

TUNING PROCEDURE FOR ADP3212/NCP3218

Set Up and Test the Circuit

1. Build a circuit based on the compensation values

computed from the design spreadsheet.

2.

Connect a dc load to the circuit.

3.

Turn on the ADP3212/NCP3218 and verify that it operates

properly.

4.

Check for jitter with no load and full load conditions.

of 7.37 kΩ, and the closest standard resistor is

TTSET

Figure 26. Multiple-Point Thermal Monitoring

, R

TTSET1

TTSET2

, … R

TTSETn

.

Repeat Steps 4 and 5 until no adjustment of R

6.
Once this is achieved, do not change R

PH

, R

is needed.

PH

, R

CS1

, or RTH

CS2

for the rest of the procedure.

7.

Measure the output ripple with no load and with a full load

with scope, making sure both are within the specifications.

Set the AC Load Line

1. Remove the dc load from the circuit and connect a
dynamic load.

2.

Connect the scope to the output voltage and set it to dc

coupling mode with a time scale of 100 µs/div.

3.

Set the dynamic load for a transient step of about 40 A at

1 kHz with 50% duty cycle.

4.

Measure the output waveform (note that use of a dc offset

on the scope may be necessary to see the waveform). Try to
use a vertical scale of 100 mV/div or finer.

5.

The resulting waveform will be similar to that shown in

Figure 27. Use the horizontal cursors to measure V
V

, as shown in Figure 27. Do not measure the under-

DCDRP

ACDRP

and

shoot or overshoot that occurs immediately after the step.

V

ACDRP

V

DCDRP

Set the DC Load Line

1. Measure the output voltage with no load (VNL) and verify

that this voltage is within the specified tolerance range.

2.

Measure the output voltage with a full load when the

device is cold (V

). Allow the board to run for ~10

FLCOLD

minutes with a full load and then measure the output when
the device is hot (V

). If the difference between the two

FLHOT

measured voltages is more than a few millivolts, adjust R
using Equation 39.

VV

−

NL

FLCOLD

RR

Repeat Step 2 until no adjustment of R

3.

4.

Compare the output voltage with no load to that with a full

×=

CS2(OLD)CS2(NEW)

VV

−

NL

(39)

FLHOT

is needed.

CS2

load using 5 A steps. Compute the load line slope for each
change and then find the average to determine the overall
load line slope (R

5.

If the difference between R

use the following equation to adjust the R

OMEAS

RR ×=

).

and RO is more than 0.05 mΩ,

OMEAS

values:

PH

R

OMEAS

)()(

OLDPHNEWPH

(40)

R

O

Rev. SpA | Page 36 of 43

CS2

06374-046

Figure 27. AC Load Line Waveform

6. If the difference between V
couple of millivolts, use Equation 46 to adjust C
be necessary to try several parallel values to obtain an

ACDRP

and V

is more than a

DCDRP

. It may

CS

adequate one because there are limited standard capacitor
values available (it is a good idea to have locations for two
capacitors in the layout for this reason).

V

CC ×=

Repeat Steps 5 and 6 until no adjustment of C

7.
Once this is achieved, do not change C

ACDRP

)()(

OLDCSNEWCS

V

(41)

DCDRP

is needed.

CS

for the rest of the

CS

procedure.

8.

Set the dynamic load step to its maximum step size (but do

not use a step size that is larger than needed) and verify
that the output waveform is square, meaning V
V

are equal.

DCDRP

9.

Ensure that the load step slew rate and the power-up slew

ACDRP

and

rate are set to ~150 A/µs to 250 A/µs (for example, a load

ADP3212/NCP3218

step of 50 A should take 200 ns to 300 ns) with no
overshoot. Some dynamic loads have an excessive
overshoot at power-up if a minimum current is incorrectly
set (this is an issue if a VTT tool is in use).

Set the Initial Transient

1. With the dynamic load set at its maximum step size,

expand the scope time scale to 2 µs/div to 5 µs/div. This
results in a waveform that may have two overshoots and
one minor undershoot before achieving the final desired
value after V

V

TRAN1

Figure 28. Transient Setting Waveform, Load Step

(see Figure 28).

DROOP

V

TRAN2

V

DROOP

06374-047

2. If both overshoots are larger than desired, try the following

adjustments in the order shown.
a.

Increase the resistance of the ramp resistor

(R

) by 25%.

RAMP

b.

For V

, increase CB or increase the switching

TRAN1

frequency.

c.

For V

, increase RA by 25% and decrease CA by 25%.

TRAN2

If these adjustments do not change the response, it is
because the system is limited by the output decoupling.
Check the output response and the switching nodes each
time a change is made to ensure that the output decoupling
is stable.

3.

For load release (see Figure 29), if V

TRANREL

is larger than
the value specified by IMVP-6.5, a greater percentage of
output capacitance is needed. Either increase the
capacitance directly or decrease the inductor values. (If
inductors are changed, however, it will be necessary to
redesign the circuit using the information from the
spreadsheet and to repeat all tuning guide procedures).

LAYOUT AND COMPONENT PLACEMENT

The following guidelines are recommended for optimal
performance of a switching regulator in a PC system.

General Recommendations

1. For best results, use a PCB of four or more layers. This

should provide the needed versatility for control circuitry
interconnections with optimal placement; power planes for
ground, input, and output; and wide interconnection traces
in the rest of the power delivery current paths. Keep in
mind that each square unit of 1 oz copper trace has a
resistance of ~0.53 mΩ at room temperature.

2.

When high currents must be routed between PCB layers,

vias should be used liberally to create several parallel
current paths so that the resistance and inductance
introduced by these current paths is minimized and the via
current rating is not exceeded.

3.

If critical signal lines (including the output voltage sense

lines of the ADP3212/NCP3218) must cross through
power circuitry, it is best if a signal ground plane can be
interposed between those signal lines and the traces of the
power circuitry. This serves as a shield to minimize noise
injection into the signals at the expense of increasing signal
ground noise.

4.

An analog ground plane should be used around and under

the ADP3212/NCP3218 for referencing the components
associated with the controller. This plane should be tied to
the nearest ground of the output decoupling capacitor, but
should not be tied to any other power circuitry to prevent
power currents from flowing into the plane.

5.

The components around the ADP3212/NCP3218 should

be located close to the controller with short traces. The most
important traces to keep short and away from other traces
are those to the FB and CSSUM pins. Refer to Figure 22 for
more details on the layout for the CSSUM node.

6.

The output capacitors should be connected as close as

possible to the load (or connector) that receives the power
(for example, a microprocessor core). If the load is distributed,

V

TRANREL

Figure 29. Transient Setting Waveform, Load Release

V

DROOP

06374-048

Rev. SpA | Page 37 of 43

ADP3212/NCP3218

the capacitors should also be distributed and generally placed
in greater proportion where the load is more dynamic.

7.

Avoid crossing signal lines over the switching power path

loop, as described in the Power Circuitry section.

8.

Connect a 1 F decoupling ceramic capacitor from VCC to

GND. Place this capacitor as close as possible to the
controller. Connect a 4.7 µF decoupling ceramic capacitor
from PVCC to PGND. Place capacitor as close as possible
to the controller.

Power Circuitry

1. The switching power path on the PCB should be routed to

encompass the shortest possible length to minimize
radiated switching noise energy (that is, EMI) and
conduction losses in the board. Failure to take proper
precautions often results in EMI problems for the entire PC
system as well as noise-related operational problems in the
power-converter control circuitry. The switching power
path is the loop formed by the current path through the
input capacitors and the power MOSFETs, including all
interconnecting PCB traces and planes. The use of short,
wide interconnection traces is especially critical in this
path for two reasons: it minimizes the inductance in the
switching loop, which can cause high energy ringing, and it
accommodates the high current demand with minimal
voltage loss.

2.

When a power-dissipating component (for example, a

power MOSFET) is soldered to a PCB, the liberal use of
vias, both directly on the mounting pad and immediately
surrounding it, is recommended. Two important reasons
for this are improved current rating through the vias and
improved thermal performance from vias extended to the

opposite side of the PCB, where a plane can more readily
transfer heat to the surrounding air. To achieve optimal
thermal dissipation, mirror the pad configurations used to
heat sink the MOSFETs on the opposite side of the PCB. In
addition, improvements in thermal performance can be
obtained using the largest possible pad area.

3.

The output power path should also be routed to encompass

a short distance. The output power path is formed by the
current path through the inductor, the output capacitors,
and the load.

4.

For best EMI containment, a solid power ground plane

should be used as one of the inner layers and extended
under all power components.

Signal Circuitry

1. The output voltage is sensed and regulated between the FB

and FBRTN pins, and the traces of these pins should be
connected to the signal ground of the load. To avoid
differential mode noise pickup in the sensed signal, the
loop area should be as small as possible. Therefore, the FB
and FBRTN traces should be routed adjacent to each other,
atop the power ground plane, and back to the controller.

2.

The feedback traces from the switch nodes should be

connected as close as possible to the inductor. The CSREF
signal should be Kelvin connected to the center point of
the copper bar, which is the V
inductors of all the phases.

3.

On the back of the ADP3212/NCP3218 package, there is a

metal pad that can be used to heat sink the device.
Therefore, running vias under the ADP3212/NCP3218 is
not recommended because the metal pad may cause
shorting between vias.

common node for the

CORE

Rev. SpA | Page 38 of 43

ADP3212/NCP3218

OUTLINE DIMENSION

Figure 30. NCP3218 48-Lead Lead Frame Chip Scale Package [QFN_VQ]

6 mm × 6 mm Body, Very Thin Quad

(CP-48-1)

Dimensions shown in millimeters

Rev. SpA | Page 39 of 43

ADP3212/NCP3218

Figure 31. ADP3212 48-Lead Lead Frame Chip Scale Package [QFN_VQ]

7 mm × 7 mm Body, Very Thin Quad

(CP-48-1)

Dimensions shown in millimeters

Rev. SpA | Page 40 of 43

ADP3212/NCP3218

ORDERING GUIDE

Te mp e ra tu r e

Model

ADP3212MNR2G1 -40°C to 100°C 48-Lead Lead Frame Chip Scale Package [QFN_VQ]

NCP3218MNR2G1 -40°C to 100°C 48-Lead Lead Frame Chip Scale Package [QFN_VQ]

1

G = RoHS Compliant Part.S

Range

Package Description

7x7 mm, 0.5 mm pitch

6x6 mm, 0.4 mm pitch

Package
Option

CP-48-1 Line 1: ADP3212

CP-48-1 Line 1: NCP3218

Package Marking Ordering

Line 2: AWLYYWWG

Line 2: AWLYYWWG

Quantity

2,500

2,500

Rev. SpA | Page 41 of 43

ADP3212/NCP3218

NOTES

Rev. SpA | Page 42 of 43

ADP3212/NCP3218

NOTES

Rev. SpA | Page 43 of 43