Datasheet ADP3188 Datasheet (Analog Devices)

6-Bit Programmable 2-/3-/4-Phase

FEATURES

Selectable 2-, 3- or 4-phase operation at up to

1 MHz per phase

±9.5 mV worst-case differential sensing error over

temperature

Logic-level PWM outputs for interface to external

high power drivers
Active current balancing between all output phases
Built-in power good/crowbar blanking supports on-the-fly

VID code changes
6-bit digitally programmable 0.8375 V to 1.6 V output
Programmable short-circuit protection with

programmable latch-off delay

APPLICATIONS

Desktop PC power supplies for

Next-generation Intel processors

VRM modules

GENERAL DESCRIPTION

The ADP3188 is a highly efficient multiphase synchronous buck
switching regulator controller optimized for converting a 12 V
main supply into the core supply voltage required by high per­formance Intel® processors. It uses an internal 6-bit DAC to read
a voltage identification (VID) code directly from the processor,
which is used to set the output voltage between 0.8375 V and

1.6 V. It uses a multimode PWM architecture to drive the logic­level outputs at a programmable switching frequency that can
be optimized for VR size and efficiency. The phase relationship
of the output signals can be programmed to provide 2-, 3-, or
4-phase operation, allowing the construction of up to four
complementary buck switching stages.

Synchronous Buck Controller

ADP3188

FUNCTIONAL BLOCK DIAGRAM

GND

PWRGD

ILIMIT

DELAY

COMP

EN

ADP3188

11

19

DAC+150mV

CSREF

DAC-250mV

10

15

EN

12

9

VCC

28

UVLO

SHUTDOWN

AND BIAS

DELAY

START

PRECISION

REFERENCE

7

FBRTN

SOFT

VID41VID32VID23VID1

RAMPADJ

14

OSCILLATOR

CURRENT

BALANCING

CIRCUIT

RT

13

CURRENT

LIMIT

CIRCUIT

VID

DAC

4

Figure 1.

RESET

CMP

RESET

CMP

2-/3-/4-PHASE

DRIVER LOGIC

RESET

CMP

RESET

CMP

CROWBAR CURRENT

6

5

VID5

VID0

LIMIT

ENSET

27

26

25

24

23

22

21

20

17

16

18

8

PWM1

PWM2

PWM3

PWM4

SW1

SW2

SW3

SW4

CSSUM

CSREF

CSCOMP

FB

04835-0-001

The ADP3188 also includes programmable no-load offset and
slope functions to adjust the output voltage as a function of the
load current so that it is always optimally positioned for a system
transient. The ADP3188 also provides accurate and reliable
short-circuit protection, adjustable current limiting, and a delayed
power good output that accommodates on-the-fly output voltage
changes requested by the CPU.

The ADP3188 is specified over the commercial temperature
range of 0°C to 85°C and is available in a 28-lead TSSOP package.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

ADP3188

TABLE OF CONTENTS

Specifications..................................................................................... 3

Inductor Selection...................................................................... 15

Test Circuits....................................................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Description .............................. 7

Typical Performance Characteristics ............................................. 8

Theory of Operation ........................................................................ 9

Start-Up Sequence........................................................................ 9

Master Clock Frequency.............................................................. 9

Output Voltage Differential Sensing .......................................... 9

Output Current Sensing .............................................................. 9

Active Impedance Control Mode............................................. 10

Current Control Mode and Thermal Balance ........................10

Voltage Control Mode................................................................ 10

Soft Start ...................................................................................... 10

Current Limit, Short-Circuit, and Latch-Off Protection....... 11

Designing an Inductor............................................................... 16

Selecting a Standard Inductor .............................................. 16

Output Droop Resistance.......................................................... 16

Inductor DCR Temperature Correction ................................. 17

Output Offset.............................................................................. 17

C

Selection ............................................................................. 18

OUT

Power MOSFETs......................................................................... 18

Ramp Resistor Selection............................................................ 20

COMP Pin Ramp ....................................................................... 20

Current Limit Setpoint.............................................................. 20

Feedback Loop Compensation Design.................................... 20

C

Selection and Input Current di/dt Reduction.................. 22

IN

Tuning the ADP3188 ................................................................. 22

DC Loadline Setting .............................................................. 22

AC Loadline Setting............................................................... 23

Dynamic VID.............................................................................. 11

Power Good Monitoring ...........................................................12

Output Crowbar ......................................................................... 13

Output Enable and UVLO ........................................................ 13

Application Information................................................................ 15

Setting the Clock Frequency ..................................................... 15

Soft Start and Current Limit Latch-Off Delay Times........... 15

REVISION HISTORY

Revision 0: Initial Version

Initial Transient Setting......................................................... 23

Layout and Component Placement ......................................... 24

General Recommendations .................................................. 24

Power Circuitry Recommendations.................................... 24

Signal Circuitry Recommendations .................................... 24

Outline Dimensions....................................................................... 25

Ordering Guide .......................................................................... 25

Rev. 0 | Page 2 of 28

ADP3188

SPECIFICATIONS

VCC = 12 V, FBRTN = GND, TA = 0°C to 85°C, unless otherwise noted.1

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

ERROR AMPLIFIER

Output Voltage Range2 V
Accuracy VFB

Line Regulation
Input Bias Current IFB 14 15.5 17
FBRTN Current I
Output Current I
Gain Bandwidth Product GBW

Slew Rate C

VID INPUTS

Input Low Voltage V
Input High Voltage V
Input Current, Input Voltage Low I

Input Current, Input Voltage High I
Pull-Up Resistance R
Internal Pull-Up Voltage 0.9 1.1 V

VID Transition Delay Time2 VID code change to FB change 400 ns
No CPU Detection Turn-Off Delay

Time

2

OSCILLATOR

Frequency Range2 f
Frequency Variation f

Output Voltage VRT
RAMPADJ Output Voltage V

RAMPADJ Input Current Range I

CURRENT SENSE AMPLIFIER

Offset Voltage V

Input Bias Current I
Gain Bandwidth Product GBW
Slew Rate C

Input Common-Mode Range CSSUM and CSREF 0 2.7 V
Positioning Accuracy

Output Voltage Range 0.05 2.7 V
Output Current I

CURRENT BALANCE CIRCUIT

Common-Mode Range V
Input Resistance R

Input Current I
Input Current Matching

0.7 3.1 V

COMP

Relative to nominal DAC output,

−9.5 +9.5 mV
referenced to FBRTN,
CSSUM = CSCOMP, Figure 2

∆V

FB

VCC = 10 V to 14 V 0.05 %

µA

100 140

FBRTN

O(ERR)

(ERR)

IL(VID)

IH(VID)

VID(X) = 0 V −25 −35

IL(VID)

VID(X) = 1.25 V 5 15

IH(VID)

35 60 85

VID

FB forced to V

COMP = FB 20 MHz

= 10 pF 25

COMP

0.4 V

0.8 V

VID code change to 11111 to PWM

– 3% 500

OUT

400 ns

µA
µA

V/µs

µA
µA

kΩ

going low

0.25 4 MHz

OSC

PHASE

RAMPADJ

0 100

RAMPADJ

CSSUM – CSREF, Figure 3 −1.75 +1.75 mV

OS(CSA)

= 25°C, RT = 250 kΩ, 4-phase

T

A

= 25°C, RT = 115 kΩ, 4-phase

T

A

= 25°C, RT = 75 kΩ, 4-phase

T

A

= 100 kΩ to GND

R

T

RAMPADJ – FB −50 +50 mV

= 25°C to 85°C, CSSUM – CSREF,

T

A

155 200 245 kHz
400 kHz
600 kHz

1.9 2.0 2.1 V

µA

−1.5 +1.5 mV
Figure 3

BIAS(CSSUM)

∆V

CSCOMP

SW(X)

∆I

−50 +50 nA

10 MHz

(CSA)

= 10 pF 10

CSCOMP

FB

Figure 4 −77 −80 −83 mV

500

SW(X)CM

SW(X)

−600 +200 mV
SW(X) = 0 V 20 30 40

SW(X) = 0 V 4 7 10

SW(X)

SW(X) = 0 V −5 +5 %

V/µs

µA

kΩ
µA

Rev. 0 | Page 3 of 28

ADP3188

Parameter Symbol Conditions Min Typ Max Units

CURRENT LIMIT COMPARATOR

Output Voltage
Normal Mode V

Shutdown Mode V
Output Current, Normal Mode I

ILIMIT(NM)

ILIMIT(SD)

ILIMIT(NM)

Maximum Output Current2 60
Current Limit Threshold Voltage VCL
Current Limite Setting Ratio VCL/I
DELAY Normal Mode Voltage V
DELAY Overcurrent Threshold V
Latch-Off Delay Time t

DELAY(NM)

DELAY(OC)

DELAY

SOFT START

Output Current, Soft-Start Mode I
Soft-Start Delay Time t

DELAY(SS)

DELAY(SS)

ENABLE INPUT

Input Low Voltage V
Input High Voltage V
Input Current, Input Voltage Low I

Input Current, Input Voltage High I

0.4 V

IL(EN)

0.8 V

IH(EN)

EN = 0 V −1 +1

IL(EN)

EN = 1.25 V 10 25

IH(EN)

POWER GOOD COMPARATOR

Undervoltage Threshold V
Overvoltage Threshold V
Output Low Voltage V

PWRGD(UV)

PWRGD(OV)

OL(PWRGD)

Power Good Delay Time
During Soft Start

2

VID Code Changing 100 250
VID Code Static 200 ns

Crowbar Trip Point V

CROWBAR

Crowbar Reset Point Relative to FBRTN 450 550 650 mV
Crowbar Delay Time t

CROWBAR

VID Code Changing 100 250
VID Code Static 400 ns

PWM OUTPUTS

Output Low Voltage V
Output High Voltage V

OL(PWM)

OH(PWM)

SUPPLY

DC Supply Current 5 10 mA
UVLO Threshold Voltage V

VCC rising 6.5 6.9 7.3 V

UVLO

UVLO Hysteresis 0.7 0.9 1.1 V

1

All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

2

Guaranteed by design or bench characterization, not tested in production.

2.9 3 3.1 V
400 mV
12

µA

EN > 0.8 V, R
EN < 0.4 V, I
EN > 0.8 V, R

= 250 kΩ

ILIMIT

= -100 µA

ILIMIT

= 250 kΩ

ILIMIT

µA

– V

V

CSREF

ILIMIT

R

= 250 kΩ

DELAY

R
R

DELAY

DELAY

= 250 kΩ
= 250 kΩ, C

, R

CSCOMP

= 250 kΩ

ILIMIT

10.4

= 12 nF

DELAY

During startup, DELAY < 2.4 V 15 20 25

R

DELAY

= 250 kΩ, C

DELAY

= 12 nF,

105 125 145 mV

mV/µA

2.9 3 3.1 V

1.7 1.8 1.9 V

1.5 ms

µA

1 ms

VID code = 011111

µA
µA

Relative to nominal DAC output −180 −250 −300 mV
Relative to nominal DAC output 90 150 200 mV
I

PWRGD(SINK)

R

= 4 mA 225 400 mV

= 250 kΩ, C

DELAY

DELAY

= 12 nF,

1 ms

VID code = 011111

µs

Relative to nominal DAC output 90 150 200 mV

Overvoltage to PWM going low

µs

I

PWM(SINK)

I

PWM(SOURCE)

= −400 µA

= 400 µA

160 500 mV

4.0 5 V

Rev. 0 | Page 4 of 28

ADP3188

TEST CIRCUITS

6-BIT CODE

12nF

ADP3188

1.25V

250kΩ

1kΩ

1

VID4

2

VID3

3

VID2

4

VID1

5

VID0

6

VID5

7

FBRTN

8

FB

9

COMP

10

PWRGD

11

EN

12

DELAY

13

RT

14

RAMPADJ

VCC

PWM1

PWM2

PWM3

PWM4

SW1

SW2

SW3

SW4

GND

CSCOMP

CSSUM

CSREF

ILIMIT

28

27

26

25

24

23

22

21

20

19

18

17

16

15

250kΩ

+

1µF 100n F

20kΩ

Figure 2. Closed-Loop Output Voltage Accuracy

100nF

12V

04835-0-005

12V

39kΩ

1kΩ

1.0V

Figure 3. Current Sense Amplifier V

12V

10kΩ

200kΩ

200kΩ

∆V

1.0V

100nF

100nF

ADP3188

VCC

28

CSCOMP

18

CSSUM

17

CSREF

16

GND

19

VCC

28

8

9

CSCOMP

18

CSSUM

17

CSREF

16

GND

19

VOS =

ADP3188

FB

COMP

CSCOMP – 1V

40

OS

04835-0-006

∆VFB= FB

∆V = 80mV

– FB

∆V = 0mV

04835-0-007

Figure 4. Positioning Voltage

Rev. 0 | Page 5 of 28

ADP3188

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

VCC −0.3 V to +15 V
FBRTN −0.3 V to +0.3 V
VID0 – VID5, EN, DELAY, ILIMIT, CSCOMP,

RT, PWM1 – PWM4, COMP
SW1 – SW4 −5 V to +25 V
All Other Inputs and Outputs −0.3 V to VCC + 0.3 V
Storage Temperature −65°C to +150°C
Operating Ambient Temperature Range 0°C to 85°C
Operating Junction Temperature 125°C

Thermal Impedance (θJA)
Lead Temperature

Soldering (10 sec) 300°C
Infrared (15 sec) 260°C

−0.3 V to 5.5 V

100°C/W

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Absolute maximum ratings apply individually
only, not in combination. Unless otherwise specified all other
voltages re referenced to GND.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 6 of 28

ADP3188

PIN CONFIGURATION AND FUNCTION DESCRIPTION

1

VID4

2

VID3

3

VID2

4

VID1

5

VID0

ADP3188

6

VID5

FBRTN

FB

COMP

PWRGD

EN

DELAY

RT

RAMPADJ

7

8

9

10

11

12

13

14

TOP VIEW

(Not to Scale)

Figure 5. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1 to 6 VID4 to VID0,

VID5

Voltage Identification DAC Inputs. These six pins are pulled up to an internal reference, providing a Logic 1 if left
open. When in normal operation mode, the DAC output programs the FB regulation voltage from 0.8375 V to

1.6 V (see Table 4). Leaving all of the VID pins open results in the ADP3188 going into No CPU mode, shutting off

its PWM outputs and pulling the PWRGD output low.
7 FBRTN Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage.
8 FB Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor between this

pin and the output voltage sets the no-load offset point.
9 COMP Error Amplifier Output and Compensation Point.
10 PWRGD Power Good Output. Open-drain output that signals when the output voltage is outside the proper operating

range.
11 EN Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low.
12 DELAY Soft-Start Delay and Current Limit Latch-Off Delay Setting Input. An external resistor and capacitor connected

between this pin and GND sets the soft-start ramp-up time and the overcurrent latch-off delay time.
13 RT Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator

frequency of the device.
14 RAMPADJ PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal

PWM ramp.
15 ILIMIT Current Limit Setpoint/Enable Output. An external resistor from this pin to GND sets the current limit threshold

of the converter. This pin is actively pulled low when the ADP3188 EN input is low, or when VCC is below its

UVLO threshold, to signal to the driver IC that the driver high-side and low-side outputs should go low.
16 CSREF Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense

amplifier and the power good and crowbar functions. This pin should be connected to the common point of the

output inductors.
17 CSSUM Current Sense Summing Node. External resistors from each switch node to this pin sum the average inductor

currents together to measure the total output current.
18 CSCOMP Current Sense Compensation Point. A resistor and a capacitor from this pin to CSSUM determine the slope of the

load line and the positioning loop response time.
19 GND Ground. All internal biasing and the logic output signals of the device are referenced to this ground.
20 to 23 SW4 to SW1 Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases

should be left open.
24 to 27 PWM4 to

PMW1

Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the

ADP3418. Connecting the PWM3 and/or PWM4 outputs to GND causes that phase to turn off, allowing the

ADP3188 to operate as a 2-, 3-, or 4-phase controller.
28 VCC Supply Voltage for the Device.

28

27

26

25

24

23

22

21

20

19

18

17

16

15

VCC

PWM1

PWM2

PWM3

PWM4

SW1

SW2

SW3

SW4

GND

CSCOMP

CSSUM

CSREF

ILIMIT

04835-0-002

Rev. 0 | Page 7 of 28

ADP3188

TYPICAL PERFORMANCE CHARACTERISTICS

4

3

2

1

MASTER CLOCK FREQUENCY (MHz)

5.3
TA = 25°C
4-PHASE OPERATION

5.2

5.1

5.0

4.9

4.8

SUPPLY CURRENT (mA)

4.7

0

0 50 100 150 200 250 300

Figure 6. Master Clock Frequency vs. R

RT VALUE (kΩ)

T

04835-0-003

4.6

0 0.5 1 1.5 2 2.5 3 3.5 4

OSCILLATOR FREQUENCY (MHz)

Figure 7. Supply Current vs. Oscillator Frequency

04835-0-004

Rev. 0 | Page 8 of 28

ADP3188

THEORY OF OPERATION

The ADP3188 combines a mulitmode, fixed frequency PWM
control with mulitphase logic outputs for use in 2-, 3- and
4-phase synchronous buck CPU core supply power converters.
The internal VID DAC is designed to interface with the Intel
6-bit VRD/VRM 10 and 10.1 compatible CPUs. Multiphase
operation is important for producing the high currents and low
voltages demanded by today’s microprocessors. Handling the
high currents in a single-phase converter would place high
thermal demands on the components in the system such as the
inductors and MOSFETs.

The multimode control of the ADP3188 ensures a stable, high
performance topology for

• Balancing currents and thermals between phases

• High speed response at the lowest possible switching

frequency and output decoupling

• Minimizing thermal switching losses due to lower

frequency operation

• Tight load line regulation and accuracy

• High current output for up to 4-phase operation

• Reduced output ripple due to multiphase cancellation

• PC board layout noise immunity

• Ease of use and design due to independent component

selection

• Flexibility in operation for tailoring design to low cost or

high performance

START-UP SEQUENCE

During start-up, the number of operational phases and their
phase relationship is determined by the internal circuitry that
monitors the PWM outputs. Normally, the ADP3188 operates as
a 4-phase PWM controller. Grounding the PWM4 pin programs
3-phase operation, and grounding the PWM3 and PWM4 pins
programs 2-phase operation.

When the ADP3188 is enabled, the controller outputs a voltage
on PWM3 and PWM4, which is approximately 675 mV. An
internal comparator checks each pin’s voltage versus a threshold
of 300 mV. If the pin is grounded, it is below the threshold and
the phase is disabled. The output resistance of the PWM pin is
approximately 5 kΩ during this detection time. Any external
pull-down resistance connected to the PWM pin should not be
less than 25 kΩ to ensure proper operation. PWM1 and PWM2
are disabled during the phase detection interval, which occurs
during the first two clock cycles of the internal oscillator. After
this time, if the PWM output is not grounded, the 5 kΩ
resistance is removed. and it switches between 0 V and 5 V. If
the PWM output was grounded, it remains off.

The PWM outputs are logic-level devices intended for driving
external gate drivers such as the ADP3418. Since each phase is
monitored independently, operation approaching 100% duty
cycle is possible. Also, more than one output can be on at the
same time for overlapping phases.

MASTER CLOCK FREQUENCY

The clock frequency of the ADP3188 is set with an external
resistor connected from the RT pin to ground. The frequency
follows the graph in Figure 6. To determine the frequency per
phase, the clock is divided by the number of phases in use. If
PWM4 is grounded, then divide the master clock by 3 for the
frequency of the remaining phases. If PWM3 and 4 are grounded,
then divide by 2. If all phases are in use, divide by 4.

OUTPUT VOLTAGE DIFFERENTIAL SENSING

The ADP3188 combines differential sensing with a high accuracy
VID DAC and reference and a low offset error amplifier. This
maintains a worst-case specification of ±9.5 mV differential
sensing error over its full operating output voltage and tempera­ture range. The output voltage is sensed between the FB and
FBRTN pins. FB should be connected through a resistor to the
regulation point, usually the remote sense pin of the micro­processor. FBRTN should be connected directly to the remote
sense ground point. The internal VID DAC and precision
reference are referenced to FBRTN, which has a minimal
current of 100 µA to allow accurate remote sensing. The internal
error amplifier compares the output of the DAC to the FB pin to
regulate the output voltage.

OUTPUT CURRENT SENSING

The ADP3188 provides a dedicated current sense amplifier
(CSA) to monitor the total output current for proper voltage
positioning versus load current and for current limit detection.
Sensing the load current at the output gives the total average
current being delivered to the load, which is an inherently more
accurate method than peak current detection or sampling the
current across a sense element such as the low-side MOSFET.
This amplifier can be configured several ways depending on the
objectives of the system:

• Output inductor DCR sensing without a thermistor for

lowest cost

• Output inductor DCR sensing with a thermistor for

improved accuracy with tracking of inductor temperature

• Sense resistors for highest accuracy measurements

Rev. 0 | Page 9 of 28

ADP3188

The positive input of the CSA is connected to the CSREF pin,
which is connected to the output voltage. The inputs to the
amplifier are summed together through resistors from the
sensing element (such as the switch node side of the output
inductors) to the inverting input, CSSUM. The feedback resistor
between CSCOMP and CSSUM sets the gain of the amplifier,
and a filter capacitor is placed in parallel with this resistor. The
gain of the amplifier is programmable by adjusting the feedback
resistor to set the load line required by the microprocessor. The
current information is then given as the difference of CSREF –
CSCOMP. This difference signal is used internally to offset the
VID DAC for voltage positioning and as a differential input for
the current limit comparator.

To provide the best accuracy for sensing current, the CSA is
designed to have a low offset input voltage. Also, the sensing
gain is determined by external resistors so that it can be made
extremely accurate.

ACTIVE IMPEDANCE CONTROL MODE

For controlling the dynamic output voltage droop as a function
of output current, a signal proportional to the total output current
at the CSCOMP pin can be scaled to equal the droop impedance
of the regulator times the output current. This droop voltage is
then used to set the input control voltage to the system. The
droop voltage is subtracted from the DAC reference input
voltage directly to tell the error amplifier where the output voltage
should be. This differs from previous implementations and allows
enhanced feed-forward response.

CURRENT CONTROL MODE AND THERMAL BALANCE

The ADP3188 has individual inputs for each phase, which are
used for monitoring the current in each phase. This information
is combined with an internal ramp to create a current balancing
feedback system, which has been optimized for initial current
balance accuracy and dynamic thermal balancing during
operation. This current balance information is independent of
the average output current information used for positioning
described previously.

The magnitude of the internal ramp can be set to optimize the
transient response of the system. It also monitors the supply
voltage for feed-forward control for changes in the supply. A
resistor connected from the power input voltage to the RAMPADJ
pin determines the slope of the internal PWM ramp. Detailed
information about programming the ramp is given in the
Application Information section.

External resistors can be placed in series with individual phases
to create, if desired, an intentional current imbalance such as
when one phase may have better cooling and can support higher
currents. Resistors R

through R

SW1

(see the typical application

SW4

circuit in Figure 10) can be used for adjusting thermal balance.
It is best to have the ability to add these resistors during the initial
design, so make sure that placeholders are provided in the layout.

To increase the current in any given phase, make R
phase larger (make R
change during balancing). Increasing R

= 0 for the hottest phase and do not

SW

to only 500 Ω makes a

SW

substantial increase in phase current. Increase each R

for that

SW

SW

value by
small amounts to achieve balance, starting with the coolest
phase first.

VOLTAGE CONTROL MODE

A high gain bandwidth voltage mode error amplifier is used for
the voltage mode control loop. The control input voltage to the
positive input is set via the VID logic according to the voltages
listed in Table 4. This voltage is also offset by the droop voltage
for active positioning of the output voltage as a function of
current, commonly known as active voltage positioning. The
output of the amplifier is the COMP pin, which sets the termi­nation voltage for the internal PWM ramps.

The negative input (FB) is tied to the output sense location with
a resistor (R

) and is used for sensing and controlling the output

B

voltage at this point. A current source from the FB pin flowing
through R

is used for setting the no-load offset voltage from

B

the VID voltage. The no-load voltage is negative with respect to
the VID DAC. The main loop compensation is incorporated
into the feedback network between FB and COMP.

SOFT START

The power-on ramp-up time of the output voltage is set with a
capacitor and resistor in parallel from the DELAY pin to ground.
The RC time constant also determines the current limit latch off
time as explained in the following section. In UVLO or when
EN is a logic low, the DELAY pin is held at ground. After the
UVLO threshold is reached and EN is a logic high, the DELAY
capacitor is charged with an internal 20 µA current source. The
output voltage follows the ramping voltage on the DELAY pin,
limiting the inrush current. The soft-start time depends on the
value of VID DAC and C

, with a secondary effect from R

DLY

Refer to the Application Information section for detailed infor­mation on setting C

DLY

.

If either EN is taken low or VCC drops below UVLO, the
DELAY capacitor is reset to ground to be ready for another soft­start cycle. Figure 8 shows a typical soft-start sequence for the
ADP3188.

DLY

.

Rev. 0 | Page 10 of 28

ADP3188

VCC. This prevents the DELAY capacitor from discharging, so
the 1.8 V threshold is never reached. The resistor has an impact
on the soft-start time because the current through it adds to the
internal 20 µA current source.

During start-up when the output voltage is below 200 mV, a
secondary current limit is active. This is necessary because the
voltage swing of CSCOMP cannot go below ground. This
secondary current limit controls the internal COMP voltage to
the PWM comparators to 2 V. This limits the voltage drop
across the low-side MOSFETs through the current balance
circuitry.

An inherent per phase current limit protects individual phases
if one or more phases stops functioning because of a faulty

Figure 8. Typical S tart-Up Waveforms

Channel 1: PWRGD, Channel 2: CSREF,

Channel 3: DELAY, Channel 4: COMP

CURRENT LIMIT, SHORT-CIRCUIT, AND LATCH-OFF PROTECTION

The ADP3188 compares a programmable current limit setpoint
to the voltage from the output of the current sense amplifier.
The level of current limit is set with the resistor from the ILIMIT
pin to ground. During normal operation, the voltage on ILIMIT
is 3 V. The current through the external resistor is internally
scaled to give a current limit threshold of 10.4 mV/µA. If the
difference in voltage between CSREF and CSCOMP rises above
the current limit threshold, the internal current limit amplifier
controls the internal COMP voltage to maintain the average
output current at the limit.

component. This limit is based on the maximum normal mode
COMP voltage.

After the limit is reached, the 3 V pull-up on the DELAY pin is
disconnected, and the external delay capacitor is discharged
through the external resistor. A comparator monitors the DELAY
voltage and shuts off the controller when the voltage drops
below 1.8 V. The current limit latch-off delay time is therefore
set by the RC time constant discharging from 3 V to 1.8 V. The
Application Information section discusses the selection of C

DLY

.

and R

DLY

Because the controller continues to cycle the phases during the
latch-off delay time, if the short is removed before the 1.8 V
threshold is reached, the controller returns to normal operation.
The recovery characteristic depends on the state of PWRGD. If
the output voltage is within the PWRGD window, the controller
resumes normal operation. However, if short circuit has caused
the output voltage to drop below the PWRGD threshold, a soft­start cycle is initiated.

The latch-off function can be reset by either removing and
reapplying VCC to the ADP3188, or by pulling the EN pin low
for a short time. To disable the short-circuit latch-off function,
the external resistor to ground should be left open, and a high
value (>1 MΩ) resistor should be connected from DELAY to

Rev. 0 | Page 11 of 28

Figure 9. Overcurrent Latch-Off Waveforms

Channel 1: CSREF, Channel 2: DELAY,

Channel 3: COMP, Channel 4: Phase 1 Switch Node

DYNAMIC VID

The ADP3188 has the ability to dynamically change the VID
input while the controller is running. This allows the output
voltage to change while the supply is running and supplying
current to the load. This is commonly referred to as VID on­the-fly (OTF). A VID OTF can occur under either light or heavy
load conditions. The processor signals the controller by changing
the VID inputs in multiple steps from the start code to the finish
code. This change can be positive or negative.

When a VID input changes state, the ADP3188 detects the
change and ignores the DAC inputs for a minimum of 400 ns.
This time prevents a false code due to logic skew while the six
VID inputs are changing. Additionally, the first VID change
initiates the PWRGD and CROWBAR blanking functions for a
minimum of 100 µs to prevent a false PWRGD or CROWBAR
event. Each VID change resets the internal timer.

ADP3188

Table 4. VID Codes for the ADP3188

VID4 VID3 VID2 VID1 VID0 VID5 Output

1 1 1 1 1 1 No CPU
1 1 1 1 1 0 No CPU
0 1 0 1 0 0 0.8375 V
0 1 0 0 1 1 0.8500 V
0 1 0 0 1 0 0.8625 V
0 1 0 0 0 1 0.8750 V
0 1 0 0 0 0 0.8875 V
0 0 1 1 1 1 0.9000 V
0 0 1 1 1 0 0.9125 V
0 0 1 1 0 1 0.9250 V
0 0 1 1 0 0 0.9375 V
0 0 1 0 1 1 0.9500 V
0 0 1 0 1 0 0.9625 V
0 0 1 0 0 1 0.9750 V
0 0 1 0 0 0 0.9875 V
0 0 0 1 1 1 1.0000 V
0 0 0 1 1 0 1.0125 V
0 0 0 1 0 1 1.0250 V
0 0 0 1 0 0 1.0375 V
0 0 0 0 1 1 1.0500 V
0 0 0 0 1 0 1.0625 V
0 0 0 0 0 1 1.0750 V
0 0 0 0 0 0 1.0875 V
1 1 1 1 0 1 1.1000 V
1 1 1 1 0 0 1.1125 V
1 1 1 0 1 1 1.1250 V
1 1 1 0 1 0 1.1375 V
1 1 1 0 0 1 1.1500 V
1 1 1 0 0 0 1.1625 V
1 1 0 1 1 1 1.1750 V
1 1 0 1 1 0 1.1875 V
1 1 0 1 0 1 1.2000 V

VID4 VID3 VID2 VID1 VID0 VID5 Output

1 1 0 1 0 0 1.2125 V
1 1 0 0 1 1 1.2250 V
1 1 0 0 1 0 1.2375 V
1 1 0 0 0 1 1.2500 V
1 1 0 0 0 0 1.2625 V
1 0 1 1 1 1 1.2750 V
1 0 1 1 1 0 1.2875 V
1 0 1 1 0 1 1.3000 V
1 0 1 1 0 0 1.3125 V
1 0 1 0 1 1 1.3250 V
1 0 1 0 1 0 1.3375 V
1 0 1 0 0 1 1.3500 V
1 0 1 0 0 0 1.3625 V
1 0 0 1 1 1 1.3750 V
1 0 0 1 1 0 1.3875 V
1 0 0 1 0 1 1.4000 V
1 0 0 1 0 0 1.4125 V
1 0 0 0 1 1 1.4250 V
1 0 0 0 1 0 1.4375 V
1 0 0 0 0 1 1.4500 V
1 0 0 0 0 0 1.4625 V
0 1 1 1 1 1 1.4750 V
0 1 1 1 1 0 1.4875 V
0 1 1 1 0 1 1.5000 V
0 1 1 1 0 0 1.5125 V
0 1 1 0 1 1 1.5250 V
0 1 1 0 1 0 1.5375 V
0 1 1 0 0 1 1.5500 V
0 1 1 0 0 0 1.5625 V
0 1 0 1 1 1 1.5750 V
0 1 0 1 1 0 1.5875 V
0 1 0 1 0 1 1.6000 V

POWER GOOD MONITORING

The power good comparator monitors the output voltage via
the CSREF pin. The PWRGD pin is an open-drain output whose
high level (when connected to a pull-up resistor) indicates that
the output voltage is within the nominal limits specified in the
specifications above based on the VID voltage setting. PWRGD
goes low if the output voltage is outside of this specified range,
if all of the VID DAC inputs are high, or whenever the EN pin is
pulled low. PWRGD is blanked during a VID OTF event for a
period of 250 µs to prevent false signals during the time the
output is changing.

Rev. 0 | Page 12 of 28

The PWRGD circuitry also incorporates an initial turn-on delay
time based on the DELAY ramp. The PWRGD pin is held low
until the DELAY pin reaches 2.6 V. The time between when the
PWRGD undervoltage threshold is reached and when the
DELAY pin reaches 2.6 V provides the turn-on delay time. This
time is incorporated into the soft-start ramp. To ensure a 1 ms
delay time on PWRGD, the soft-start ramp must also be >1 ms.
Refer to the Application Information section for detailed
information on setting C

DLY

.

ADP3188

OUTPUT CROWBAR

As part of the protection for the load and output components of
the supply, the PWM outputs are driven low (turning on the
low-side MOSFETs) when the output voltage exceeds the upper
crowbar threshold. This crowbar action stops once the output
voltage falls below the release threshold of approximately 550 mV.

Turning on the low-side MOSFETs pulls down the output as the
reverse current builds up in the inductors. If the output over­voltage is due to a short in the high-side MOSFET, this action
current-limits the input supply or blows its fuse, protecting the
microprocessor from being destroyed.

OUTPUT ENABLE AND UVLO

For the ADP3188 to begin switching, the input supply (VCC) to
the controller must be higher than the UVLO threshold, and the
EN pin must be higher than its logic threshold. If UVLO is less
than the threshold or the EN pin is a logic low, the ADP3188 is
disabled. This holds the PWM outputs at ground, shorts the
DELAY capacitor to ground, and holds the ILIMIT pin at ground.

In the application circuit, the ILIMIT pin should be connected

OD

to the
grounded disables the drivers such that both DRVH and DRVL
are grounded. This feature is important in preventing the
discharge of the output capacitors when the controller is shut
off. If the driver outputs were not disabled, a negative voltage
could be generated during output due to the high current
discharge of the output capacitors through the inductors.

pins of the ADP3418 drivers. The ILIMIT being

Rev. 0 | Page 13 of 28

ADP3188

CC(CORE)

V

0.8375V – 1.6V

95A TDC, 119A PK

CC(CORE) RTN

V

C8

15nF

R3

2.2Ω

+ +

2700µF/16V/3.3 A × 2

SANYO MV-WX SERIES

L1

18A

370nH

IN
V

12V

C7

D2

C6

U2

RTN

IN

V

4.7µF

10nF

ADP3418

1N4148

C2

5mΩ EACH

560µF/4V × 8

SANYO SEPC SERIES

L2

320nH/1.4mΩ

Q2

NTD40N03

Q1

876

SW

DRVH

BSTINOD
123

C1

+

+

NTD40N03

DRVL

PGND

VCC

4 5

C5

C31

C22

Q4

Q3

C12

4.7µF

NTD110N02

NTD110N02

15nF

R4

IN

MLCC

0µF × 18

SOCKET

1

L3

F

µ

C11

4.7

320nH/1.4mΩ

Q6

NTD40N03

Q8

NTD110N02

NTD40N03

DRVL

PGND

VCC
4 5

R1

10Ω

Q7

NTD110N02

C16

15nF

R5

2.2Ω

C9

4.7µF

C4

+

C3

100µF

Q5

876

C10

10nF

SW

DRVH

U3

ADP3418

2.2Ω

BSTINOD

123

D3

1N4148

D1

1N4148

*FOR A DESCRIPTION OF OPTIONAL RSW RESISTORS, SEE THE THEORY OF OPERATION SECTION.

Figure 10. Typical VR 10.1 Application Circuit

RTH1

100kΩ, 5%

NTC

L4

F

µ

C15

4.7

320nH/1.4mΩ

Q10

28

VCC

D4

C14

10nF

U4

ADP3418

1N4148

27

PWM1

NTD40N03

Q9

876

SW

DRVH

BSTINOD
123

262524

PWM2

PWM3

NTD40N03

DRVL

PGND

VCC
4 5

*

SW1

R

23

PWM4

C13

*

R

SW1

Q12

NTD110N02

Q11

NTD110N02

C20

R6

4.7µF

SW2

*
SW3

R

222120

SW2

15nF

2.2Ω

SW3

PH2

R

PH4

R

*

SW4

R

SW4

U1

ADP3188

VID4

VID3

VID2

VID1

VID0

VID5

FBRTN

314

2

R2

357kΩ

1%

5

1µF

6

FBCOMP

789

CFB22pF

B

C

470pF

A

R

A

C

B

R

L5

C19

4.7µF

320nH/1.4mΩ

Q14

NTD40N03

Q13

NTD40N03

876

C18

10nF

SW

DRVL

DRVH

ADP3418

BSTINOD
123

PGND

VCC
4 5

U5

D5

1N4148

1%

PH1

R

158kΩ

1%

158kΩ

1%

PH3

R

158kΩ

1%

CS2

R

158kΩ

CS1

R

35.7kΩ

CS2

C

1.5nF

19

181716

GND

CSCOMP

PWRGDENDELAYRTRAMPADJ

10

111213

12.1kΩ

470pF

1.21kΩ

4.5kΩ

8

C

CSSUM

CS1

560pF

DLY

R

DLY

C

CSREF

T

R

470kΩ

39nF

15

ILIMIT

14

137kΩ

R7

1%

C17

220kΩ

Q16

NTD110N02

Q15

NTD110N02

4.7µF

C21

22pF

LIM

R

150kΩ

1%

FROM CPU

GOOD

POWER

ENABLE

04835-0-009

Rev. 0 | Page 14 of 28

ADP3188

t

(

()(

)

(

APPLICATION INFORMATION

The design parameters for a typical Intel VRD 10.1 compliant
CPU application are as follows:

• Input voltage (V

• VID setting voltage (V

) = 12 V

IN

) = 1.300 V

VID

• Duty cycle (D) = 0.108

• Nominal output voltage at no load (V

• Nominal output voltage at 101 A load (V

) = 1.281 V

ONL

) = 1.180 V

OFL

• Static output voltage drop based on a 1.0 mΩ load line (R

from no load to full load (V

) = V

D

ONL

− V

= 1.281 V −

OFL

)

O

as long as R
The value for C

where t
390 kΩ and a desired soft-start time of 3 ms, C
closest standard value for C
can be calculated for the current limit latch-off time using

1.180 V = 101 mV

• Maximum output current (I

• Maximum output current step (∆I

• Number of phases (n) = 4

• Switching frequency per phase (f

SETTING THE CLOCK FREQUENCY

The ADP3188 uses a fixed-frequency control architecture. The
frequency is set by an external timing resistor (R
frequency and the number of phases determine the switching
frequency per phase, which relates directly to switching losses
and the sizes of the inductors and of the input and output
capacitors. With n = 4 for four phases, a clock frequency of

1.32 MHz sets the switching frequency (f
330 kHz, which represents a practical trade-off between the
switching losses and the sizes of the output filter components.
Equation 1 shows that to achieve an 1.32 MHz oscillator
frequency, the correct value for R
value for R

where 4.7 pF and 27 kΩ are internal IC component values. For

can be calculated using

T

= kpF27

R (1)

T

1

××

7.4

fn

SW

) = 119 A

O

) = 95 A

O

) = 330 kHz

SW

). The clock

T

) of each phase to

SW

is 137 kΩ. Alternatively, the

T

Ω−

If the result for R
should be considered by recalculating the equation for C
longer latch-off time should be used. R
than 200 kΩ. In this example, a delay time of 9 ms results in R
= 452 kΩ. The closest standard 5% value is 470 kΩ.

INDUCTOR SELECTION

The choice of inductance for the inductor determines the ripple
current in the inductor. Less inductance leads to more ripple
current, which increases the output ripple voltage and conduction
losses in the MOSFETs but allows using smaller inductors and,
for a specified peak-to-peak transient deviation, less total output
capacitance. Conversely, a higher inductance means lower ripple
current and reduced conduction losses but requires larger
inductors and more output capacitance for the same peak-to­peak transient deviation. In any multiphase converter, a practical
value for the peak-to-peak inductor ripple current is less than
50% of the maximum dc current in the same inductor. Equation 4
shows the relationship between the inductance, oscillator
frequency, and peak-to-peak ripple current in the inductor.

Equation 5 can be used to determine the minimum inductance
based on a given output ripple voltage.

good initial accuracy and frequency stability, a 1% resistor is
recommended.

SOFT START AND CURRENT LIMIT LATCH-OFF DELAY TIMES

Because the soft start and current limit latch-off delay functions
share the DELAY pin, these two parameters must be considered
together. The first step is to set C

for the soft-start ramp. This

DLY

ramp is generated with a 20 µA internal current source. The
value of R

has a second-order impact on the soft-start time

DLY

because it sinks part of the current source to ground. However,

Solving Equation 5 for a 10 mV p-p output ripple voltage yields

If the resulting ripple voltage is less than that for which it was
designed, the inductor can be made smaller until the ripple
value is met. This allows optimal transient response and
minimum output decoupling.

C ×

R×=

I

R

L

is kept greater than 200 kΩ, this effect is minor.

DLY

can be approximated using

DLY

⎛
⎜

−µ=

DLY

is the desired soft-start time. Assuming an R

SS

DLY

VID

≥

≥L

A20 (2)

VID

⎜
⎝

96.1

SW

SW

×

2

DELAY

C

DLY

is less than 200 kΩ, a smaller soft-start time

DLY

DV

−×=1

)

(4)

Lf

×

1

O

Vf

×

RIPPLE

×

⎞

V

VID

R

DLY

DLY

t

SS

⎟
⎟

V

VID

⎠

is 39 nF. Once C

DLY

DLY

(3)

should never be less

DLY

DnRV

×−××

(5)

0.4321m1.0V1.3

−××

)

nH224

mV10kHz330

=

of

DLY

is 36 nF. The
is chosen, R

, or a

DLY

DLY

DLY

Rev. 0 | Page 15 of 28

ADP3188

The smallest possible inductor should be used to minimize the
number of output capacitors. For this example, choosing a
320 nH inductor is a good starting point and gives a calculated
ripple current of 11 A. The inductor should not saturate at the
peak current of 35.5 A and should be able to handle the sum of
the power dissipation caused by the average current of 30 A in
the winding and core loss.

Another important factor in the inductor design is the DCR,
which is used for measuring the phase currents. A large DCR
can cause excessive power losses, while too small a value can
lead to increased measurement error. A good rule is to have the
DCR be about 1 to 1½ times the droop resistance (R
example uses an inductor with a DCR of 1.4 mΩ.

DESIGNING AN INDUCTOR

Once the inductance and DCR are known, the next step is to
either design an inductor or to find a standard inductor that
comes as close as possible to meeting the overall design goals. It
is also important to have the inductance and DCR tolerance
specified to control the accuracy of the system. 15% inductance
and 8% DCR (at room temperature) are reasonable tolerances
that most manufacturers can meet.

The first decision in designing the inductor is to choose the
core material. Several possibilities for providing low core loss at
high frequencies include the powder cores (for example, Kool­Mµ® from Magnetics, Inc. or from Micrometals) and the gapped
soft ferrite cores (for example, 3F3 or 3F4 from Philips). Low
frequency powdered iron cores should be avoided due to their
high core loss, especially when the inductor value is relatively
low and the ripple current is high.

). The

O

• Coiltronics

[phone]
www.coiltronics.com

• Sumida Electric Company

[phone]
www.sumida.com

• Vishay Intertechnolog y

[phone]
www.vishay.com

OUTPUT DROOP RESISTANCE

The design requires that the regulator output voltage measured
at the CPU pins drops when the output current increases. The
specified voltage drop corresponds to a dc output resistance (R

The output current is measured by summing the voltage across
each inductor and passing the signal through a low-pass filter.
This summer filter is the CS amplifier configured with resistors

(summers), and RCS and CCS (filter). The output resistance

R

PH(X)

of the regulator is set by the following equations, where R
DCR of the output inductors:

R

CS

R ×= (6)

O

R

C×=

CS

One has the flexibility of choosing either R
to select R

CS

R

L

()

xPH

L

(7)

RR

L

CS

or R

CS

equal to 100 kΩ, and then solve for R

. It is best

PH(X)

by

PH(X)

rearranging Equation 6.

O

is the

L

).

The best choice for a core geometry is a closed-loop type such
as a potentiometer core, PQ, U, or E core or toroid. A good
compromise between price and performance is a core with a
toroidal shape.

Many useful magnetics design references are available for
quickly designing a power inductor, such as

• Magnetic Designer Software

Intusoft (www.intusoft.com)

• Designing Magnetic Components for High-Frequency DC-

DC Converters, by William T. McLyman, Kg Magnetics,

Inc., ISBN 1883107008

Selecting a Standard Inductor

The following power inductor manufacturers can provide design
consultation and deliver power inductors optimized for high
power applications upon request.

• Coilcraft

[phone]
www.coilcraft.com

Rev. 0 | Page 16 of 28

R

L

×=

R

PH

()

x

R

CS

R

O

R

()

xPH

m4.1

m0.1

Next, use Equation 6 to solve for C

=

C

CS

nH320

×

=

k100m4.1

It is best to have a dual location for C

k140k100

=×=

.

CS

nF82.2

in the layout so that

CS

standard values can be used in parallel to get as close to the
value desired. For best accuracy, C

should be a 5% or 10%

CS

NPO capacitor. This example uses a 5% combination for C

1.5 nF and 560 pF in parallel. Recalculating R

and R

CS

PH(X)

using

this capacitor combination yields 110 kΩ and 154 kΩ. The
closest standard 1% value for R

is 158 kΩ.

PH(X)

of

CS

ADP3188

(

(

(

−

, R

INDUCTOR DCR TEMPERATURE CORRECTION

With the inductor’s DCR being used as the sense element and
copper wire being the source of the DCR, one needs to
compensate for temperature changes of the inductor’s winding.
Fortunately, copper has a well known temperature coefficient
(TC) of 0.39%/°C.

is designed to have an opposite and equal percentage

If R

CS

change in resistance to that of the wire, it cancels the tempera­ture variation of the inductor’s DCR. Due to the nonlinear
nature of NTC thermistors, resistors R
See Figure 11 to linearize the NTC and produce the desired
temperature tracking.

PLACE AS CLOSE AS POSSIBLE

TO NEAREST INDUCTOR

OR LOW-SIDE MOSFET

R

TH

ADP3188

CSCOMP

18

C

CSREF

CS1

17

16

CSSUM

Figure 11. Temperature Compensation Circuit Values

R

CS1

C

CS2

The following procedure and expressions yield values to use for

, R

R

, and RTH (the thermistor value at 25°C) for a given RCS

CS1

CS2

value.

1. Select an NTC based on type and value. Since we do not

have a value yet, start with a thermistor with a value close

. The NTC should also have an initial tolerance of

to R

CS

better than 5%.

2. Based on the type of NTC, find its relative resistance value

at two temperatures. The temperatures that work well are
50°C and 90°C. These resistance values are called A
(R

TH(50°C

)/R

TH(25°C)

) and B (R

TH(90°C

NTC’s relative value is always 1 at 25°C.

3. Find the relative value of R

CS

temperatures. This is based on the percentage change
needed, which in this example is initially 0.39%/°C. These
are called r
(T

− 25))), where TC = 0.0039 for copper. T1 = 50°C and T2

2

(1/(1 + TC × (T1 − 25))) and r2 (1/(1 + TC ×

1

= 90°C are chosen. From this, one can calculate that r

0.9112 and r

= 0.7978.

2

CS1

R

)/R

and R

R

PH1

CS2

TH(25°C)

are needed.

CS2

TO

SWITCH

NODES

R

R

PH3

PH2

KEEP THIS PATH

AS SHORT AS POSSIBLE

AND WELL AWAY FROM

SWITCH NODE LINES

). Note that the

required for each of these

SENSE

=

1

TO

V

OUT

04835-0-009

4. Compute the relative values for R

r

CS2

=

)()()

() () ( )

11

)

A

−

r

CS1

=

1

1

−

r

−

1

A

rr

−

CS21CS2

=

r

TH

5. Calculate R

1

1

−

1

= rTH × RCS, then select the closest value of

TH

(8)

1

−

rr

CS1CS2

thermistor available. Also compute a scaling factor k based
on the ratio of the actual thermistor value used relative to
the computed one:

R

()

k =

ACTUALTH

R

CALCULATEDTH

()

6. Calculate values for R

(9)

and R

rkRR ××=

CS1CSCS1

CS1

CS2

)( )()

rkkRR ×+−×= 1 (10)

CS2CSCS2

For this example, R

has been calculated to be 110 kΩ ; it

CS

starts with a thermistor value of 100 kΩ. Looking through
available 0603 size thermistors, we find a Vishay
NTHS0603N01N1003JR NTC thermistor with A = 0.3602
and B = 0.09174. From these, one can compute r

0.3795, r

= 0.7195, and r

CS2

= 1.075. Solving for RTH yields

TH

118.28 kΩ, so 100 kΩ is chosen, making k = 0.8455. Finally,
we find R

CS1

and R

to be 35.3 kΩ and 83.9 kΩ. Choosing

CS2

the closest 1% resistor values yields a choice of 35.7 kΩ or

84.5 kΩ.

OUTPUT OFFSET

The Intel specification requires that at no load the nominal
output voltage of the regulator be offset to a value lower than
the nominal voltage corresponding to the VID code. The offset
is set by a constant current source flowing out of the FB pin (I
and flowing through R
Equation 11:

VID

=

R

B

I

FB

=BR (11)

. The value of RB can be found using

B

VV

ONL

V281.1V3.1=−

µA5.15

k22.1

, and RTH using

CS1

CS2

×−×+×−×−××−

11

BArABrBA

−−×−×−×−×

21

using Equation 10:

=

CS1

rABrBArrBA

1221

FB

)

The closest standard 1% resistor value is 1.21 kΩ.

Rev. 0 | Page 17 of 28

ADP3188

C

SELECTION

OUT

The required output decoupling for the regulator is typically
recommended by Intel for various processors and platforms.
One can also use some simple design guidelines to determine
what is required. These guidelines are based on having both
bulk and ceramic capacitors in the system.

The first thing is to select the total amount of ceramic capaci­tance. This is based on the number and type of capacitor to be
used. The best location for ceramics is inside the socket, with 12
to 18 of size 1206 being the physical limit. Others can be placed
along the outer edge of the socket as well.

Combined ceramic values of 200 µF to 300 µF are recom­mended, usually made up of multiple 10 µF or 22 µF capacitors.
Select the number of ceramics and find the total ceramic
capacitance (C

Next, there is an upper limit imposed on the total amount of
bulk capacitance (C
voltage stepping of the output (voltage step V
error of V
for load release for a given maximum load step I
maximum allowable overshoot. The total amount of load release
voltage is given as ∆V
maximum allowable overshoot voltage.

).

Z

) when one considers the VID on-the-fly

X

in time tV with

V

). A lower limit is based on meeting the capacitance

ERR

and a

O

= ∆IO × RO + ∆Vrl, where ∆Vrl is the

O

This example uses 18 10 µF 1206 MLC capacitors (C

= 180 µF).

Z

The VID on-the-fly step change is 450 mV in 230 µs with a
setting error of 2.5 mV. The maximum allowable load release
overshoot for this example is 50 mV, so solving for the bulk
capacitance yields

⎞
⎟

⎟

=

⎟
⎟
⎟

⎠

C

()

MINx

⎛
⎜

⎜

≤

⎜

⎛

⎜

⎜

m0.14

⎜

⎜

⎝

⎝

A95nH320

×

⎞

mV50

+×

⎟
⎟

A95

⎠

−

V3.1

×

mV450nH320

C

⎛
⎜

⎜
⎜

⎝

=

≤

()

MAXx

⎛
⎜

1

+

⎜
⎝

mF48.5

×

2

()

2

×××

××××

nH320mV450

×

×

V3.1m0.16.44

⎞

2

⎟

⎞

m1.04.64V1.3µs230

⎟

−

⎟

⎟
⎠

⎟
⎠

F1801

µ−

where k = 4.6.

Using eight 560 µF Al-Poly capacitors with a typical ESR of
5 mΩ each yields C

= 4.48 mF with an RX = 0.63 mΩ.

X

mF65.3µF180

×+×× 11

⎞
⎟

⎟

C

(12)

−

⎟

z

⎟
⎟

⎠

⎞

2

⎟

⎞

nKR

O

⎟

−

⎟

L

⎠

⎟
⎟

⎠

−

(13)

C

z

C

()

MINx

C

()

MAXx

L

2O2

RnK

nK 1where

=

⎛
⎜

⎜

≥

⎜

⎛

⎜

⎜

Rn

⎜

⎜

⎝

⎝

≤

V

V

V

VID

⎞

⎛

V

ERR

⎟

⎜

⎟

⎜

V

V

⎠

⎝

IL



×

O

⎞

V

∆

rl

⎟

+×

O

⎛
⎜

⎜
⎜

⎝

V

×

VID

⎟

I

∆

O

⎠

⎛

V

VID

⎜

t

v

⎜

V

V

⎝

To meet the conditions of these expressions and transient
response, the ESR of the bulk capacitor bank (R
than two times the droop resistance (R
than C

, the system cannot meet the VID on-the-fly

X(MAX)

). If the C

O

) should be less

X

is larger

X(MIN)

specification and may require the use of a smaller inductor or
more phases (and may have to increase the switching frequency
to keep the output ripple the same).

One last check should be made to ensure that the ESL of the
bulk capacitors (L

) is low enough to limit the high frequency

X

ringing during a load change. This is tested using

2

2

××≤

QRCL

O

zx

L

x

2

()

=××≤

(14)

pH3602m1µF180

where Q is limited to the square root of 2 to ensure a critically
damped system. In this example, L

is approximately 350 pH for

X

the eight A1-Polys capacitors, which satisfies this limitation. If

of the chosen bulk capacitor bank is too large, the number

the L

X

of ceramic capacitors may need to be increased if there is
excessive ringing.

One should note that for this multimode control technique,
all ceramic designs can be used as long as the conditions of
Equations 11, 12, and 13 are satisfied.

POWER MOSFETS

For this example, the N-channel power MOSFETs have been
selected for one high-side switch and two low-side switches per
phase. The main selection parameters for the power MOSFETs

GS(TH)

, QG, C

are V
voltage (the supply voltage to the ADP3418) dictates whether
standard threshold or logic-level threshold MOSFETs must be
used. With V
< 2.5 V) are recommended.

, C

, and R

ISS

RSS

~10 V, logic-level threshold MOSFETs (V

GATE

. The minimum gate drive

DS(ON)

GS(TH)

Rev. 0 | Page 18 of 28

ADP3188

M

The maximum output current (IO) determines the R
requirement for the low-side (synchronous) MOSFETs. With
the ADP3188, currents are balanced between phases, thus the
current in each low-side MOSFET is the output current divided
by the total number of MOSFETs (n

). With conduction losses

SF

being dominant, the following expression shows the total power
being dissipated in each synchronous MOSFET in terms of the
ripple current per phase (I

⎡
⎢

()

DP ×

1

SF

×−=

⎢
⎣

) and average total output current (IO):

R

22

⎤

⎞

12

⎛

In

1

R

⎟

⎜

⎥

×+

⎜

n

⎝

R

()

⎟

SF

⎠

SFDS

⎥
⎦

⎞

⎛

I

O

⎟

⎜

⎟

⎜

n

SF

⎠

⎝

Knowing the maximum output current being designed for and
the maximum allowed power dissipation, one can find the
required R

for the MOSFET. For D-PAK MOSFETs up to

DS(ON)

an ambient temperature of 50°C, a safe limit for P

1.5 W at 120°C junction temperature. Thus, for this example
(119 A maximum), R

(per MOSFET) < 7.5 mΩ. This R

DS(SF)

is also at a junction temperature of about 120°C, so one needs to
make sure to account for this when making this selection. This
example uses two lower-side MOSFETs at 4.8 mΩ each at 120°C.

Another important factor for the synchronous MOSFET is the
input capacitance and feedback capacitance. The ratio of the
feedback to input needs to be small (less than 10% is recom­mended) to prevent accidental turn-on of the synchronous
MOSFETs when the switch node goes high.

Also, the time to switch the synchronous MOSFETs off should
not exceed the nonoverlap dead time of the MOSFET driver
(40 ns typical for the ADP3418). The output impedance of the
driver is approximately 2 Ω, and the typical MOSFET input gate
resistances are about 1 Ω to 2 Ω, so a total gate capacitance of
less than 6000 pF should be adhered to. Since there are two
MOSFETs in parallel, the input capacitance for each synchronous
MOSFET should be limited to 3000 pF.

The high-side (main) MOSFET has to be able to handle two
main power dissipation components: conduction and switching
losses. The switching loss is related to the amount of time it
takes for the main MOSFET to turn on and off, and to the
current and voltage that are being switched. Basing the switching
speed on the rise and fall time of the gate driver impedance and
MOSFET input capacitance, the following expression provides
an approximate value for the switching loss per main MOSFET,
where n

is the total number of main MOSFETs:

MF

DS(ON)

(15)

is 1 W to

SF

DS(SF)

It is interesting to note that adding more main MOSFETs (n

)

MF

does not really help the switching loss per MOSFET since the
additional gate capacitance slows switching. The best thing to
reduce switching loss is to use lower gate capacitance devices.

The conduction loss of the main MOSFET is given by the
following, where R

DP ×

() ()

MFC

Typically, for main MOSFETs, the highest speed (low C

is the on resistance of the MOSFET:

DS(MF)

⎡

⎛

⎞

I

O

⎜

⎟

⎢

×=

⎜

⎟

n

⎢

MF

⎝

⎠

⎣

12

⎛

1

⎜

×+

⎜
⎝

22

⎤

×

In

⎞

R

⎟

⎥

⎟

n

⎥

MF

⎠

⎦

R

(17)

MFDS

)

ISS

device is preferred, but these usually have higher on resistance.
Select a device that meets the total power dissipation (about

1.5 W for a single D-PAK) when combining the switching and
conduction losses.

For this example, an NTD40N03L was selected as the main
MOSFET (eight total; n
R

= 19 mΩ (max at TJ = 120°C), and an NTD110N02L was

DS(MF)

= 8), with a C

MF

selected as the synchronous MOSFET (eight total; n

= 2710 pF (max) and R

C

ISS

The synchronous MOSFET C

= 4.8 mΩ (max at TJ = 120°C).

DS(SF)

is less than 3000 pF, satisfying

ISS

= 584 pF (max) and

ISS

= 8), with

SF

that requirement. Solving for the power dissipation per MOSFET
at IO = 119 A and IR = 11 A yields 958 mW for each synchronous
MOSFET and 872 mW for each main MOSFET. These numbers
comply with a good guideline which is to limit the power
dissipation to 1 W per MOSFET.

One last thing to consider is the power dissipation in the driver

GSF

for the

G

is the

GMF

is

for each phase. This is best described in terms of the Q
MOSFETs and is given by the following equation, where Q
the total gate charge for each main MOSFET and Q
total gate charge for each synchronous MOSFET:

⎡

f

SW

P ×

⎢

DRV

⎢

⎣

()

MF

n

×=2

Also shown is the standby dissipation factor (I

⎤

VIQnQn

+×+××

⎥
⎥

⎦

× VCC) for the

CC

(18)

CCCCGSFSFGMF

driver. For the ADP3418, the maximum dissipation should be
less than 400 mW. In this example, with I

5.8 nC, and Q

= 48 nC, one finds 297 mW in each driver,

GSF

= 7 mA, Q

CC

GMF

=

which is below the 400 mW dissipation limit. See the ADP3418
data sheet for more details.

IV

where R

×

fP ×××

××= 2

()

MFS

G

SW

is the total gate resistance (2 Ω for the ADP3418 and

OCC

n

F

n

MF

C

R

G

n

(16)

ISS

about 1 Ω for typical high speed switching MOSFETs, making

= 3 Ω), and C

R

G

is the input capacitance of the main MOSFET.

ISS

Rev. 0 | Page 19 of 28

ADP3188

A

−

RAMP RESISTOR SELECTION

The ramp resistor (RR) is used for setting the size of the internal
PWM ramp. The value of this resistor is chosen to provide the
best combination of thermal balance, stability, and transient
response. The following expression is used for determining the
optimum value:

×

LA

=

R

R

=

R

R

where A

is the internal ramp amplifier gain, AD is the current

R

balancing amplifier gain, R
resistance, and C
closest standard 1% resistor value is 357 kΩ.

The internal ramp voltage magnitude can be calculated by using

V

=

R

V

=

R

The size of the internal ramp can be made larger or smaller. If it
is made larger, stability and transient response improve, but
thermal balance degrades. Li kewise, if the ramp is made smaller,
thermal balance improves at the sacrifice of transient response
and stability. The factor of three in the denominator of
Equation 19 sets a ramp size that gives an optimal balance for
good stability, transient response, and thermal balance.

COMP PIN RAMP

A ramp signal on the COMP pin is due to the droop voltage and
output voltage ramps. This ramp amplitude adds to the internal
ramp to produce the following overall ramp signal at the PWM
input:

V

=

RT

In this example, the overall ramp signal is 0.49 V.

CURRENT LIMIT SETPOINT

To select the current limit setpoint, first find the resistor value

. The current limit threshold for the ADP3188 is set with

for R

LIM

a 3 V source (V

can be found using

R

LIM

R

= (22)

LIM

R

3

D

×××

CRA

RDS

(19)

nH3200.2

×

pF5m2.453

×××

is the total low-side MOSFET on

DS

is the internal ramp capacitor value. The

R

()

VDA

1

×−×

VIDR

fCR

××

SWRR

()

×−×

××

V

R

⎛
⎜

1

⎜
⎝

()

×−×

Dn

12

−

LIM

LIM

) across R

V

×

×

SW

RI

×××

RCfn

X

LIM

LIMLIM

O

k356

=

V1.30.10810.2

=

kHz330pF5k357

(21)

⎞
⎟
⎟

O

⎠

Vm390

with a gain of 10.4 mV/µA (A

(20)

).

LIM

For values of R
lower than expected, so some adjustment of R
Here, I

is the average current limit for the output of the supply.

LIM

In this example, choosing a peak current limit of 200 A for I
results in R

greater than 500 kΩ, the current limit may be

LIM

may be needed.

LIM

= 156 kΩ, for which 150 kΩ is chosen as the

LIM

LIM

,

nearest 1% value.

The limit of the per-phase current limit described earlier is
determined by

VVV

I +

PHLIM

≅

()

×

−−

RA

MAXDSD

()

For the ADP3188, the maximum COMP voltage (V

3.3 V, the COMP pin bias voltage (V
balancing amplifier gain (A

) is 5. Using VR of 0.49 V and R

D

I

BIASRMAXCOMP

BIAS

R

(23)

2

COMP(MAX)

) is 1.2 V, and the current

) is

DS(MAX)

of 3 mΩ (low-side on resistance at 150°C), one finds a per­phase peak current limit of 100 A. Although this number may
seem high, this current level can be reached only with an
absolute short at the output, and the current limit latch-off
function shuts down the regulator before overheating can occur.

This limit can be adjusted by changing the ramp voltage (V

),

R

but make sure not to set the per-phase limit lower than the
average per-phase current (I

LIM

/n).

The per-phase initial duty cycle limit is determined by

MAX

V

RT

VV

BIAS

MAXCOMP

()

×= (24)

DD

In this example, the maximum duty cycle is 0.46.

FEEDBACK LOOP COMPENSATION DESIGN

Optimized compensation of the ADP3188 allows the best
possible response of the regulator’s output to a load change. The
basis for determining the optimum compensation is to make
the regulator and output decoupling appear as an output
impedance that is entirely resistive over the widest possible
frequency range, including dc, and equal to the droop resistance

). With the resistive output impedance, the output voltage

(R

O

droops in proportion to the load current at any load current
slew rate. This ensures the optimal positioning and allows the
minimization of the output decoupling.

With the multimode feedback structure of the ADP3188, the
feedback compensation must be set to make the converter’s
output impedance, working in parallel with the output
decoupling, to meet this goal. Several poles and zeros created by
the output inductor and decoupling capacitors (output filter)
need to be compensated for.

A type-three compensator on the voltage feedback is adequate
for proper compensation of the output filter. Equations 25 to 29
are intended to yield an optimal starting point for the design;
some adjustments may be necessary to account for PCB and
component parasitic effects (see the Tuning the ADP3188
section).

Rev. 0 | Page 20 of 28

ADP3188

(

(

=

×

(

The first step is to compute the time constants for all of the poles and zeros in the system:

×

VR

RTL

+×+×=

RARnR

DSDOE

+×+×=

R (25)

E

() ()

−×=

OXA

′

()( )

+=

⎛
⎜

−×

LV

RT

⎜

=

T

C

T

=

D

⎝

()

m2.45m14 =

L

X

′

RRCT

2

×

×+

R

O

CRRRT (27)

XOXB

⎞

×

RA

DSD

⎟
⎟

×

f

SW

⎠

RV

EVID

××

'

=

2

RCC

OZX

RCRRC

×+−×

+

V

VID

×

V1.3

′

RR

−

O

R

X

=

OZOX

12

V0.49m1.4

+

−+=×−

⎛
⎜

⎜
⎝

−×

nH320V0.49

×

()

where, for the ADP3188, R' is the PCB resistance from the bulk
capacitors to the ceramics and where R
MOSFET on resistance per phase. In this example, A

is the total low-side

DS

is 5, VRT

D

××−××

VDnL

)

RT

×××

VRCn

VIDOX

)

×−××

V0.490.4321nH3202

×××

V1.3m1mF4.454

m0.5m1mF4.45 =

pH350

×+−×=

m1

m24.2

m0.65m1

−

m10.63

µs2.50

(26)

ns580mF4.45m1m0.5m0.63

×

×

m24.2V1.3

⎞

m2.45

⎟
⎟

kHz3302

⎠

µs4.7

=

m1µF180mF4.45

××

(28)

2

)

m1µF180m0.5m1mF4.45

×+−×

Figure 12 and Figure 13

ns333

=

(29)

show the typical transient response

using these compensation values.

equals 0.49 V, R' is approximately 0.5 mΩ (assuming a 4-layer,
1 ounce motherboard), and L

is 350 pH for the eight Al-Poly

X

capacitors.

The compensation values can then be solved using

××

TRn

=

C

A

AO

×

RR

BE

(30)

CA

R

C

C

A

B

FB

=

T
C

T
R

××

k1.21m24.2

×

C

A

B
B

T

R

µs4.7

===

pF342

ns580

===

k1.21

D

A

ns333

===

k13.7

pF342

=

k13.7

(31)

nF479

(32)

Fp24.3

(33)

µs2.50m14

These are the starting values, prior to tuning the design, to
account for layout and other parasitic effects (see the Tuning the
ADP3188 section). The final values selected after tuning are

pF470

=

C

A

k1.12

=

R

A

=

C

B

=

C

FB

pF470
pF22

Figure 12. Typical Transient Response for Design Example

Load Step

Figure 13. Typical Transient Response for Design Example

Load Release

04835-0-017

04835-0-016

Rev. 0 | Page 21 of 28

ADP3188

CIN SELECTION AND INPUT CURRENT di/dt REDUCTION

In continuous inductor current mode, the source current of the
high-side MOSFET is approximately a square wave with a duty
ratio equal to n × V
maximum output current. To prevent large voltage transients, a
low ESR input capacitor, sized for the maximum rms current,
must be used. The maximum rms capacitor current is given by

IDI

I

CRMS

Note that the capacitor manufacturer’s ripple current ratings are
often based on only 2,000 hours of life. This makes it advisable
to further derate the capacitor or to choose a capacitor rated at a
higher temperature than required. Several capacitors may be
placed in parallel to meet size or height requirements in the
design. In this example, the input capacitor bank is formed by
two 2,700 µF, 16 V aluminum electrolytic capacitors and eight

4.7 µF ceramic capacitors.

and an amplitude of one-nth the

OUT/VIN

1

1

××=

OCRMS

−

×

DN

A191108.0

1

××=

0.1084

×

(34)

A14.71

=−

TUNING THE ADP3188

1. Build a circuit based on the compensation values

computed from the design spreadsheet.

2. Hook up the dc load to circuit, turn it on, and verify its

operation. Also check for jitter at no-load and full-load.

DC Loadline Setting

3. Measure the output voltage at no-load (V

is within tolerance.

4. Measure the output voltage at full-load cold (V

the board sit for ~10 minutes at full-load, and then measure
the output (V
millivolts, adjust R

() ()

). If there is a change of more than a few

FLHOT

and R

CS1

RR

OLDCS2NEWCS2

using Equations 35 and 36.

CS2

VV

−

×= (35)

FLCOLDNL

VV

−

FLHOTNL

5. Repeat Step 4 until the cold and hot voltage measurements

remain the same.

6. Measure the output voltage from no-load to full-load using

5 A steps. Compute the loadline slope for each change, and
then average to get overall loadline slope (R

). Verify that it

NL

FLCOLD

).

OMEAS

). Let

To reduce the input current di/dt to a level below the recom­mended maximum of 0.1 A/µs, an additional small inductor
(L > 370 nH @ 18 A) should be inserted between the converter
and the supply bus. That inductor also acts as a filter between
the converter and the primary power source.

100

80

60

40

EFFICIENCY (%)

20

0

0 20 40 60 80 100 120

Figure 14. Efficiency of the Circuit of Figure 10 vs. Output Current

OUTPUT CURRENT (A)

R

()

V

= 1.3 V

OUT

= 25°C

T

A

04835-0-011

=

NEWCS1

() ( ) () ( )

7. If R

following to adjust the R

is off from RO by more than 0.05 mΩ, use the

OMEAS

values:

PH

R

()

OLDPHNEWPH

OMEAS

(36)

R

O

RR ×=

()

8. Repeat Steps 6 and 7 to check the loadline, and repeat

adjustments if necessary.

9. Once dc loadline adjustment is complete, do not change

, R

, R

R

PH

, or RTH for remainder of procedure.

CS1

CS2

10. Measure the output ripple at no-load and full-load with a

scope, and make sure it is within specifications.

1

+

RR

() ( )

()

C25

°

THOLDCS1

()

−×−+×

() ( )

−

RRRRRRR

THTHOLDCS1NEWCS2OLDCS1THOLDCS1

1

()

C25C25C25

°°°

(37)

Rev. 0 | Page 22 of 28

ADP3188

AC Loadline Setting

11. Remove the dc load from the circuit and hook up the

dynamic load.

12. Hook up the scope to the output voltage and set it to dc

coupling with the time scale at 100 µs/div.

13. Set the dynamic load for a transient step of about 40 A at

1 kHz with 50% duty cycle.

14. Measure the output waveform (you may have to use dc

offset on scope to see the waveform). Try to use a vertical
scale of 100 mV/div or finer. This waveform should look
similar to Figure 15.

V

ACDRP

V

DCDRP

04835-0-012

Figure 15. AC Loadline Waveform

15. Use the horizontal cursors to measure V

ACDRP

and V

DCDRP

shown. Do not measure the undershoot or overshoot that
happens immediately after the step.

as

Initial Transient Setting

18. With the dynamic load still set at the maximum step size,

expand the scope time scale to see 2 µs/div to 5 µs/div. The
waveform may have two overshoots and one minor under­shoot (see Figure 16). Here, V

V

TRAN1

V

TRAN2

Figure 16. Transient Setting Waveform

is the final desired value.

DROOP

V

DROOP

04835-0-013

19. If both overshoots are larger than desired, try making the

adjustments described below. Note that if these adjustments
do not change the response, you are limited by the output
decoupling. Check the output response each time you make
a change as well as the switching nodes to make sure that
the response is still stable.

Make the ramp resistor larger by 25% (R

For V

For V

, increase CB or increase the switching frequency.

TRAN1

, increase RA and decrease CA by 25%.

TRAN2

RAMP

).

16. If V

ACDRP

and V

millivolts, use Equation 38 to adjust C

are different by more than a few

DCDRP

You may ne ed to

CS.

parallel different values to get the right one since there are
limited standard capacitor values available. It is a good idea
to have locations for two capacitors in the layout for this.

V

ACDRP

CC ×=

NEWCS

()

()

OLDCS

V

(38)

DCDRP

17. Repeat Steps 11 to 13 and repeat the adjustments if

necessary. Once complete, do not change C

for the

CS

remainder of the procedure.

Set the dynamic load step to maximum step size (do not
use a step size larger than needed) and verify that the
output waveform is square, which means that V

are equal.

V

DCDRP

ACDRP

and

Rev. 0 | Page 23 of 28

20. For load release (see Figure 17), if V

V

(see Figure 16), there is not enough output capaci-

TRAN1

TRANREL

is larger than

tance. You need more capacitance or you have to make the
inductor values smaller. (If you change inductors, you need
to start the design again using the spreadsheet and this
tuning procedure.)

V

TRANREL

Figure 17. Transient Setting Waveform

V

DROOP

04835-0-014

ADP3188

Since the ADP3188 turns off all of the phases (switches inductors
to ground), there is no ripple voltage present during load release.
Thus, you do not have to add headroom for ripple, allowing
your load release VTRANREL to be larger than VTRAN1 by the
amount of ripple, and still meet specifications.

TRAN1

and V

If V
implies that capacitors can be removed. When removing capaci­tors, check the output ripple voltage as well to make sure that it
is still within specifications.

LAYOUT AND COMPONENT PLACEMENT

The following guidelines are recommended for optimal
performance of a switching regulator in a PC system.

General Recommendations

For good results, a PCB with at least four layers is recommended.
This should allow the needed versatility for control circuitry
interconnections with optimal placement, power planes for
ground, input and output power, and wide interconnection
traces in the remainder of the power delivery current paths.
Keep in mind that each square unit of 1 ounce copper trace
has a resistance of ~0.53 mΩ at room temperature.

Whenever high currents must be routed between PCB layers,
vias should be used liberally to create several parallel current
paths so that the resistance and inductance introduced by these
current paths is minimized and the via current rating is not
exceeded.

If critical signal lines (including the output voltage sense lines of
the ADP3188) must cross through power circuitry, it is best if a
signal ground plane can be interposed between those signal lines
and the traces of the power circuitry. This serves as a shield to
minimize noise injection into the signals at the expense of
making signal ground a bit noisier.

An analog ground plane should be used around and under the
ADP3188 as a reference for the components associated with the
controller. This plane should be tied to the nearest output
decoupling capacitor ground and should not be tied to any other
power circuitry to prevent power currents from flowing in it.

The components around the ADP3188 should be located close
to the controller with short traces. The most important traces to
keep short and away from other traces are the FB and CSSUM
pins. The output capacitors should be connected as close as
possible to the load (or connector), for example, a micro­processor core, that receives the power. If the load is distributed,
the capacitors should also be distributed and generally be in
proportion to where the load tends to be more dynamic.

are less than the desired final droop, this

TRANREL

Power Circuitry Recommendations

The switching power path should be routed on the PCB to
encompass the shortest possible length in order to minimize
radiated switching noise energy (i.e., EMI) and conduction
losses in the board. Failure to take proper precautions often
results in EMI problems for the entire PC system as well as
noise-related operational problems in the power converter
control circuitry. The switching power path is the loop formed
by the current path through the input capacitors and the power
MOSFETs including all interconnecting PCB traces and planes.
Using short and wide interconnection traces is especially critical
in this path for two reasons: it minimizes the inductance in the
switching loop, which can cause high energy ringing, and it
accommodates the high current demand with minimal voltage
loss.

Whenever a power dissipating component, for example, a power
MOSFET, is soldered to a PCB, the liberal use of vias, both
directly on the mounting pad and immediately surrounding it,
is recommended. Two important reasons for this are improved
current rating through the vias and improved thermal perform­ance from vias extended to the opposite side of the PCB, where
a plane can more readily transfer the heat to the air. Make a
mirror image of any pad being used to heatsink the MOSFETs
on the opposite side of the PCB to achieve the best thermal
dissipation to the air around the board. To further improve
thermal performance, use the largest possible pad area.

The output power path should also be routed to encompass a
short distance. The output power path is formed by the current
path through the inductor, the output capacitors, and the load.

For best EMI containment, a solid power ground plane should
be used as one of the inner layers extending fully under all the
power components.

Signal Circuitry Recommendations

The output voltage is sensed and regulated between the FB pin
and the FBRTN pin, which connect to the signal ground at the
load. To avoid differential mode noise pickup in the sensed
signal, the loop area should be small. Thus, the FB and FBRTN
traces should be routed adjacent to each other on top of the
power ground plane back to the controller.

The feedback traces from the switch nodes should be connected
as close as possible to the inductor. The CSREF signal should be
connected to the output voltage at the nearest inductor to the
controller.

Avoid crossing any signal lines over the switching power path
loop, described in the following section.

Rev. 0 | Page 24 of 28

ADP3188

OUTLINE DIMENSIONS

9.80

9.70

9.60

28

PIN 1

0.15

0.05

COPLANARITY

0.10

0.65
BSC

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153AE

1.20 MAX

SEATING

PLANE

15

4.50

4.40

4.30

0.20

0.09

6.40 BSC

8°
0°

0.75

0.60

0.45

141

Figure 18. 28-Lead This Shrink Small Outline Package [TSSOP]

(RU-28)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option Quantity per Reel

ADP3188JRUZ-REEL1 0°C to 85°C Thin Shrink SOIC 13” Reel RU-28 2500

1

Z = Pb-free part.

Rev. 0 | Page 25 of 28

ADP3188

NOTES

Rev. 0 | Page 26 of 28

ADP3188

NOTES

Rev. 0 | Page 27 of 28

ADP3188

NOTES

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

D04835–0–4/04(0)

Rev. 0 | Page 28 of 28