Datasheet ADP3182 Datasheet (Analog Devices)

Adjustable Output 1-/2-/3-Phase

FEATURES

Selectable 1-, 2-, or 3-phase operation at up to 1 MHz per

phase
±2% worst-case differential sensing error over temperature
Externally adjustable 0.8 V to >5 V output from a 12 V supply
Logic-level PWM outputs for interface to external high

power drivers
Active current balancing between all output phases
Built-in power good/crowbar functions
Programmable short-circuit protection with programmable

latch-off delay

APPLICATIONS

Auxiliary supplies
DDR memory supplies
Point-of-load modules

FUNCTIONAL BLOCK DIAGRAM

RAMPADJ

9

OSCILLATOR

CURRENT

BALANCING

CIRCUIT

EN

GND

PWRGD

ILIMIT

DELAY

COMP

6

14

5

10

EN

7

4

SHUTDOWN

950mV

FB

650mV

VCC

1

UVLO

& BIAS

DELAY

SOFT

START

RT

8

CURRENT

LIMIT

CIRCUIT

Synchronous Buck Controller

ADP3182

GENERAL DESCRIPTION

The ADP3182 is a highly efficient multiphase, synchronous,
buck-switching regulator controller optimized for converting a
12 V main supply into a high current, low voltage supply for use
in point-of-load (POL) applications. It uses a multimode PWM
architecture to drive the logic-level outputs at a programmable
switching frequency that can be optimized for VR size and
efficiency. The phase relationship of the output signals can be
programmed to provide 1-, 2-, or 3-phase operation, allowing
for the construction of up to three complementary buck­switching stages. The ADP3182 also provides accurate and
reliable short-circuit protection and adjustable current limiting.

ADP3182 is specified over the commercial temperature range of
0°C to +85°C and is available in a 20-lead QSOP package.

ENSET

20

19

18

17
16
15

12

11

13

3

PWM1

PWM2

PWM3

SW1
SW2
SW3
CSSUM

CSREF
CSCOMP

FB

CMP

CMP

1.05V

FB

RESET

RESET

CMP

RESET

CROWBAR CURRENT

2 / 3-PHASE

DRIVER LOGIC

LIMIT

ADP3182

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

Figure 1.

800mV

REFERENCE

2

FBRTN

04938-001

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]

www.analog.com

Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

ADP3182

TABLE OF CONTENTS

Specifications..................................................................................... 3

Output Enable and UVLO ........................................................ 12

Test C ir c uit s ....................................................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Description .............................. 7

Typical Performance Characteristics ............................................. 8

Theory of Operation ........................................................................ 9

Start-Up Sequence ........................................................................ 9

Master Clock Frequency .............................................................. 9

Output Voltage Differential Sensing .......................................... 9

Output Current Sensing .............................................................. 9

Current Control Mode and Thermal Balance ........................ 10

Volt a ge C o ntro l Mod e ................................................................10

Soft Start ......................................................................................10

Current Limit, Short-Circuit, and Latch-off Protection ....... 10

Power Good Monitoring ........................................................... 11

Applications..................................................................................... 14

Setting the Clock Frequency..................................................... 14

Soft Start and Current Limit Latch-Off Delay Time ............. 14

Inductor Selection...................................................................... 14

Output Current Sense................................................................ 15

Output Voltage............................................................................ 16

Power MOSFETs......................................................................... 16

Ramp Resistor Selection............................................................ 17

Current Limit Setpoint .............................................................. 17

Feedback Loop Compensation Design.................................... 17

Input Capacitor Selection and Input Current di/dt............... 18

Inductor DCR Temperature Correction ................................. 18

Layout and Component Placement ......................................... 19

Outline Dimensions ....................................................................... 20

Ordering Guide .......................................................................... 20

Output Crowbar .........................................................................11

REVISION HISTORY

10/04—Revision 0: Initial Version

Rev. 0 | Page 2 of 20

ADP3182

SPECIFICATIONS

VCC = 12 V, FBRTN = GND, TA = 0°C to 85°C, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

OSCILLATOR

Frequency Range
Frequency Variation f

Output Voltage V
RAMPADJ Output Voltage V

RAMPADJ Input Current Range I

2

f

OSC

PHASE

RT

RAMPADJ

RAMPADJ

0.25 3 MHz
TA = 25°C, RT = 348 kΩ, 3-phase

= 25°C, RT = 174 kΩ, 3-phase

T

A

= 25°C, RT = 100 kΩ, 3-phase

T

A

RT = 100 kΩ to GND
RAMPADJ − FB −50 +50 mV
0 100

VOLTAGE ERROR AMPLIFIER

Output Voltage Range2 V
Accuracy V
Line Regulation

Input Bias Current I
FBRTN Current I
Output Current I
Gain Bandwidth Product GBW

COMP

FB

∆V

FB

FBRTN

O(ERR)

FB

(ERR)

Slew Rate C

0.7 3.1 V
Referenced to FBRTN 784 800 816 mV
VCC = 10 V to 14 V 0.05 %

FB = 800 mV −4 +4
100 140
FB forced to V
COMP = FB 20 MHz

= 10 pF 25

COMP

CURRENT SENSE AMPLIFIER

Offset Voltage V
Input Bias Current I
Gain Bandwidth Product GBW

OS(CSA)

BIAS(CSSUM)

(CSA)

Slew Rate C

CSSUM − CSREF, Figure 2 −5.5 +5.5 mV

−50 +50 nA
10 MHz

= 10 pF 10

CSCOMP

Input Common-Mode Range CSSUM and CSREF 0 VCC − 2.5 V
Output Voltage Range 0.05 VCC − 2.5 V
Output Current I

CSCOMP

500

CURRENT BALANCE CIRCUIT

Common-Mode Range V
Input Resistance R

Input Current I
Input Current Matching

SW(X)CM

SW(X)

SW(X)

∆I

SW(X)

−600 +200 mV
SW(X) = 0 V 20 30 40

SW(X) = 0 V 4 7 10
SW(X) = 0 V −7 +7 %

CURRENT LIMIT COMPARATOR

Output Voltage
Normal Mode V

In Shutdown Mode V
Output Current, Normal Mode I

ILIMIT(NM)

ILIMIT(SD)

ILIMIT(NM)

EN > 2 V, R
EN < 0.8 V, I
EN > 2 V, R

Maximum Output Current2 60
Current Limit Threshold Voltage V
Current Limit Setting Ratio VCL/I
DELAY Normal Mode Voltage V
DELAY Overcurrent Threshold V
Latch-Off Delay Time t

CL

DELAY(NM)

DELAY(OC)

DELAY

V

R
R
R

CSREF

ILIMIT

DELAY

DELAY

DELAY

− V

CSCOMP

= 250 kΩ
= 250 kΩ
= 250 kΩ, C

SOFT START

Output Current, Soft Start Mode I
Soft Start Delay Time t

DELAY(SS)

DELAY(SS)

During start-up, DELAY < 2.4 V 15 20 25

R

= 250 kΩ, C

DELAY

1

155 200 245 kHz
400 kHz
600 kHz

1.9 2.0 2.1 V

− 3% 500

OUT

= 250 kΩ

ILIMIT

ILIMIT

= 250 kΩ

ILIMIT

, R

= −100 µA

= 250 kΩ

ILIMIT

2.9 3 3.1 V
400 mV
12

105 125 145 mV

10.4

2.9 3 3.1 V

1.7 1.8 1.9 V

DELAY

DELAY

= 12 nF

= 12 nF

1.5 ms

500

µA

µA
µA
µA

V/µs

V/µs

µA

kΩ

µA

µA
µA

mV/µA

µA
µs

Rev. 0 | Page 3 of 20

ADP3182

Parameter Symbol Conditions Min Typ Max Unit

ENABLE INPUT

Input Low Voltage V

Input High Voltage V

Input Current I

IL(EN)

IH(EN)

IN(EN)

POWER GOOD COMPARATOR

Undervoltage Threshold V

Overvoltage Threshold V

Output Low Voltage V

PWRGD(UV)

PWRGD(OV)

OL(PWRGD)IPWRGD(SINK)

Power Good Delay Time 200 ns

Crowbar Trip Point V

CROWBAR

Crowbar Reset Point Relative to FBRTN 550 650 750 mV

Crowbar Delay Time t

CROWBAR

PWM OUTPUTS

Output Low Voltage V

Output High Voltage V

OL(PWM)

OH(PWM)

SUPPLY

DC Supply Current 5 10 mA

UVLO Threshold Voltage V

UVLO

UVLO Hysteresis 0.7 0.9 1.1 V

1

All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

2

Guaranteed by design or bench characterization, not tested in production.

0.8 V

2.0 V

−1 +1

µA

Relative to FBRTN 600 660 720 mV
Relative to FBRTN 880 940 1000 mV

= 4 mA 225 400 mV

Relative to FBRTN 0.975 1.05 1.1 V

Overvoltage to PWM going low 400 ns

I

PWM(SINK)

I

PWM(SOURCE)

= −400 µA

= 400 µA

160 500 mV

4.0 5 V

VCC rising 6.5 6.9 7.3 V

Rev. 0 | Page 4 of 20

ADP3182

TEST CIRCUITS

ADP3182

1

100nF

V

CSCOMP

13

CSSUM

12

CSREF

11

14

GND

CC

CSCOMP –0.8V

VOS =

40

04938-002

OS

12V

39kΩ

1kΩ

0.8V

Figure 2. Current Sense Amplifier V

Rev. 0 | Page 5 of 20

ADP3182

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

VCC −0.3 V to +15 V
FBRTN −0.3 V to +0.3 V
EN, DELAY, ILIMIT, RT,

PWM1 to PWM3, COMP
SW1 to SW3 −5 V to +25 V
All Other Inputs and Outputs −0.3 V to VCC + 0.3 V
Storage Temperature −65°C to +150°C
Operating Ambient Temperature Range 0°C to 85°C
Operating Junction Temperature 125°C

Thermal Impedance (θJA)
Lead Temperature

Soldering (10 s) 300°C

Infrared (15 s) 260°C

−0.3 V to 5.5 V

100°C/W

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Absolute maximum ratings apply individually
only, not in combination. Unless otherwise specified, all other
voltages are referenced to GND.

Rev. 0 | Page 6 of 20

ADP3182

PIN CONFIGURATION AND FUNCTION DESCRIPTION

1

VCC

2

FBRTN

3

FB

4

COMP

PWRGD

EN

DELAY

RT

RAMPADJ

ILIMIT

5

6

7

8

9

10

ADP3182

TOP VIEW

(Not to Scale)

Figure 3. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1 VCC Supply Voltage for the Device.
2 FBRTN Feedback Return. Voltage error amplifier reference for remote sensing of the output voltage.
3 FB Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor divider

between the output and FBRTN connected to this pin sets the output voltage point. This pin is also the reference

point for the power good and crowbar comparators.
4 COMP Error Amplifier Output and Compensation Point.
5 PWRGD Power Good Output. Open-drain output that signals when the output voltage is outside the proper operating

range.
6 EN Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low.
7 DELAY Soft Start Delay and Current Limit Latch-Off Delay Setting Input. An external resistor and capacitor connected

between this pin and GND sets the soft start, ramp-up time and the overcurrent latch-off delay time.
8 RT Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator

frequency of the device.
9 RAMPADJ PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal

PWM ramp.
10 ILIMIT Current Limit Setpoint/Enable Output. An external resistor from this pin to GND sets the current limit threshold

of the converter. This pin is actively pulled low when the ADP3182’s EN input is low, or when VCC is below its

UVLO threshold, to signal to the driver IC that the driver high-side and low-side outputs should go low.
11 CSREF Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense

amplifier. This pin should be connected to the common point of the output inductors.
12 CSSUM Current Sense Summing Node. External resistors from each switch node to this pin sum the average inductor

currents together to measure the total output current.
13 CSCOMP Current Sense Compensation Point. A resistor and a capacitor from this pin to CSSUM determines the gain of the

current sense amplifier.
14 GND Ground. All internal biasing and the logic output signals of the device are referenced to this ground.
15 to 17 SW3 to SW1 Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases

should be left open.
18 to 20 PWM3 to

PMW1

Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the

ADP3418. Connecting the PWM3 output to GND causes that phase to turn off, allowing the ADP3182 to operate

as a 1- or 2-phase controller.

20

PWM1

19

PWM2

18

PWM3

17

SW1

16

SW2

15

SW3

14

GND

13

CSCOMP

12

CSSUM

11

CSREF

04938-003

Rev. 0 | Page 7 of 20

ADP3182

TYPICAL PERFORMANCE CHARACTERISTICS

3

5.4

5.3

TA = 25ºC

3-PHASE OPERATION

2

1

MASTER CLOCK FREQUENCY (MHz)

0

0

RT VALUE (kΩ)

Figure 4. Master Clock Frequency vs. RT

25020015010050 300

04938-004

5.2

5.1

5.0

4.9

SUPPLY CURRENT (mA)

4.8

4.7
0 2.52.01.51.00.5 3.0

OSCILLATOR FREQUENCY (MHz)

Figure 5. Supply Current vs. Oscillator Frequency

04938-005

Rev. 0 | Page 8 of 20

ADP3182

THEORY OF OPERATION

The ADP3182 combines a multimode, fixed frequency PWM
control with multiphase logic outputs for use in 1-, 2-, and
3-phase, synchronous, buck, point-of-load supply power
converters. Multiphase operation is important for producing the
high currents and low voltages demanded by auxiliary supplies
in desktop computers, workstations, and servers. Handling the
high currents in a single-phase converter would place high
thermal demands on the components in the system, such as the
inductors and MOSFETs.

The multimode control of the ADP3182 ensures a stable, high
performance topology for

• Balancing currents and thermals between phases

• High speed response at the lowest possible switching

frequency and output decoupling

• Minimizing thermal switching losses due to lower

frequency operation

• Tight regulation and accuracy

• Reduced output ripple due to multiphase cancellation

• PC board layout noise immunity

• Ease of use and design due to independent component

selection

• Flexibility in operation for tailoring design to low cost or

high performance

START-UP SEQUENCE

During start-up, the number of operational phases and their
phase relationship is determined by the internal circuitry that
monitors the PWM outputs. Normally, the ADP3182 operates
as a 3-phase PWM controller. Grounding the PWM3 pin
programs 1/2-phase operation.

When the ADP3182 is enabled, the controller outputs a voltage
on PWM3 that is approximately 675 mV. An internal comparator
checks the pin’s voltage vs. a threshold of 300 mV. If the pin is
grounded, it is below the threshold and the phase is disabled.
The output resistance of the PWM pin is approximately 5 kΩ
during this detection time. Any external pull-down resistance
connected to the PWM pin should be more than 25 kΩ to
ensure proper operation. PWM1 and PWM2 are disabled
during the phase detection interval, which occurs during the
first two clock cycles of the internal oscillator. After this time, if
the PWM output is not grounded, the 5 kΩ resistance is
removed, and the PWM output switches between 0 V and 5 V. If
the PWM output is grounded, it remains off.

The PWM outputs are logic-level devices intended for driving
external gate drivers such as the ADP3418. Because each phase
is monitored independently, operation approaching 100% duty

cycle is possible. Also, more than one output can be on at the
same time for overlapping phases.

MASTER CLOCK FREQUENCY

The clock frequency of the ADP3182 is set with an external
resistor connected from the RT pin to ground. The frequency
follows the graph in Figure 4. To determine the frequency per
phase, the clock is divided by the number of phases in use. If
PWM3 is grounded, then divide the master clock by 2 for the
frequency of the remaining two phases.

It is important to note that if only one phase is used, the clock
will switch as if two phases were operating. This means that the
oscillator frequency must be set at twice the expected value to
program the desired PWM frequency.

OUTPUT VOLTAGE DIFFERENTIAL SENSING

The ADP3182 uses a differential-sensing, low offset voltage error
amplifier. This maintains a worst-case specification of ±2%
differential-sensing error over its full operating output voltage
and temperature range. The output voltage is sensed between
the FB and FBRTN pins. FB should be connected through a
resistor to the regulation point, usually the local bypass
capacitor for the load. FBRTN should be connected directly to
the remote sense ground point. The internal precision reference
is referenced to FBRTN, which has a minimal current of 100 µA
to allow accurate remote sensing. The internal error amplifier
compares the output of the reference to the FB pin to regulate
the output voltage.

OUTPUT CURRENT SENSING

The ADP3182 provides a dedicated current sense amplifier
(CSA) to monitor the total output current for current limit
detection. Sensing the load current at the output gives the total
average current being delivered to the load, which is an
inherently more accurate method than peak current detection
or sampling the current across a sense element such as the low­side MOSFET. This amplifier can be configured several ways
depending on the objectives of the system:

• Output inductor DCR sensing without a thermistor for

lowest cost

• Output inductor DCR sensing with a thermistor for

improved accuracy for tracking inductor temperature

• Sense resistors for highest accuracy measurements

The positive input of the CSA is connected to the CSREF pin,
which is connected to the output voltage. The inputs to the
amplifier are summed together through resistors from the
sensing element (such as the switch node side of the output
inductors) to the inverting input, CSSUM. The feedback resistor
between CSCOMP and CSSUM sets the gain of the amplifier,
and a filter capacitor is placed in parallel with this resistor. The

Rev. 0 | Page 9 of 20

ADP3182

gain of the amplifier is programmable by adjusting the feedback
resistor. The current information is then given as the difference
of CSREF − CSCOMP. This difference in signal is used as a
differential input for the current limit comparator.

To provide the best accuracy for sensing current, the CSA is
designed to have a low offset input voltage. In addition, the
sensing gain is determined by external resistors so that the gain
can be made extremely accurate.

CURRENT CONTROL MODE AND THERMAL BALANCE

The ADP3182 has individual inputs for each phase that are used
for monitoring the current in each phase. This information is
combined with an internal ramp to create a current balancing
feedback system, which has been optimized for initial current
balance accuracy and dynamic thermal balancing during
operation. This current balance information is independent of
the average output current information used for the current
limit described previously.

The magnitude of the internal ramp can be set to optimize the
transient response of the system. It also monitors the supply
voltage for feed-forward control to compensate for changes in
the supply voltage. A resistor connected from the power input
voltage to the RAMPADJ pin determines the slope of the
internal PWM ramp. External resistors can be placed in series
with individual phases to create, if desired, an intentional
current imbalance such as when one phase may have better
cooling and can support higher currents. Resistors R

(see the typical application circuit in Figure 9) can be used

R

SW3

for adjusting thermal balance. Add placeholders for these
resistors during the initial layout so that adjustments can be made
after completing thermal characterization of the design.

To increase the current in any given phase, increase R
phase (set R
during balancing). Increasing R
increases the phase current. Increase each R

= 0 for the hottest phase and do not change it

SW

to only 500 Ω substantially

SW

value by small

SW

amounts to achieve balance, starting with the coolest phase.

VOLTAGE CONTROL MODE

A high gain-bandwidth voltage mode error amplifier is used for
the voltage-mode control loop. The control input voltage to the
positive input is derived from the internal 800 mV reference.
The output of the amplifier is the COMP pin, which sets the
termination voltage for the internal PWM ramps.

The negative input (FB) is tied to the center point of a resistor
divider from the output sense location. The main loop
compensation is incorporated into the feedback network
between FB and COMP.

through

SW1

SW

for that

SOFT START

The power-on, ramp-up time of the output voltage is set with a
capacitor and resistor in parallel from the DELAY pin to ground.
The RC time constant also determines the current limit latch­off time as explained in the following section. In UVLO or
when EN is logic low, the DELAY pin is held at ground. After
the UVLO threshold is reached and EN is logic high, the
DELAY capacitor is charged with an internal 20 µA current
source. The output voltage follows the ramping voltage on the
DELAY pin, limiting the inrush. The soft start time depends on
the value of C

, with a secondary effect from R

DLY

DLY

.

If either EN is taken low or VCC drops below UVLO, the
DELAY capacitor is reset to ground to prepare for another soft
start cycle. Figure 6 shows a typical soft start sequence for the
ADP3182.

04938-006

Figure 6. Typical S tart-Up Wavef orms

Channel 1: CSREF, Channel 2: DELAY,

Channel 3: PWRGD, Channel 4: COMP

CURRENT LIMIT, SHORT-CIRCUIT, AND LATCH-OFF PROTECTION

The ADP3182 compares a programmable current limit setpoint
to the voltage from the output of the current sense amplifier.
The level of current limit is set with the resistor from the ILIMIT
pin to ground. During normal operation, the voltage on ILIMIT
is 3 V. The current through the external resistor is internally
scaled to produce a current limit threshold of 10.4 mV/µA. If
the difference in voltage between CSREF and CSCOMP rises
above the current limit threshold, the internal current limit
amplifier controls the internal COMP voltage to maintain the
average output current at the limit.

Rev. 0 | Page 10 of 20

ADP3182

After the limit is reached, the 3 V pull-up on the DELAY pin is
disconnected, and the external delay capacitor is discharged
through the external resistor. A comparator monitors the DELAY
voltage and shuts off the controller when the voltage drops
below 1.8 V. The current limit latch-off delay time is therefore
set by the RC time constant discharging from 3 V to 1.8 V.
Typical overcurrent latch-off waveforms are shown in Figure 7.

Because the controller continues to cycle the phases during the
latch-off delay time, the controller returns to normal operation
if the short is removed before the 1.8 V threshold is reached.
The recovery characteristic depends on the state of PWRGD. If
the output voltage is within the PWRGD window, the controller
resumes normal operation. However, if a short circuit has

04938-007

caused the output voltage to drop below the PWRGD threshold,
a soft start cycle is initiated.

The latch-off function can be reset by either removing and
reapplying VCC to the ADP3182, or by pulling the EN pin low
for a short time. To disable the short-circuit latch-off function,
the external resistor to ground should be left open, and a high­value (>1 MΩ) resistor should be connected from DELAY to
VCC. This prevents the DELAY capacitor from discharging, so
the 1.8 V threshold is never reached. The resistor has an impact
on the soft start time because the current through it adds to the
internal 20 µA current source.

Figure 7. Overcurrent Latch-Off Waveforms

Channel 1: CSREF, Channel 2: COMP,

Channel 3: Phase 1 Switch Node, Channel 4: DELAY

During start-up when the output voltage is below 200 mV, a
secondary current limit is active. This is necessary because the
voltage swing of CSCOMP cannot go below ground. This
secondary current limit controls the internal COMP voltage to
the PWM comparators to 2 V. This limits the voltage drop
across the low-side MOSFETs through the current balance
circuitry.

An inherent per phase current limit protects individual phases
if one or more phases stop functioning because of a faulty
component. This limit is based on the maximum normal mode
COMP voltage.

POWER GOOD MONITORING

The power good comparator monitors the output voltage via the
FB pin. The PWRGD pin is an open-drain output whose high
level (when connected to a pull-up resistor) indicates that the
output voltage is within the nominal limits specified in the
electrical table. PWRGD goes low if the output voltage is
outside this specified range or the EN pin is pulled low. Figure 8
shows the PWRGD output response when the input power is
removed from the regulator.

04938-008

Figure 8. Shutdown Waveform s

Channel 1: CSREF, Channel 2: DELAY,

Channel 3: PWRGD, Channel 4: COMP

OUTPUT CROWBAR

As part of the protection for the load and output components of
the supply, the PWM outputs are driven low (turning on the
low-side MOSFETs) when the output voltage exceeds the upper
crowbar threshold. This crowbar action stops once the output
voltage falls below the release threshold of approximately 650 mV.

Turning on the low-side MOSFETs pulls down the output as the
reverse current builds up in the inductors. If the output over­voltage is due to a short in the high-side MOSFET, this action
limits the current of the input supply or blows the fuse to
protect the microprocessor from being destroyed.

Rev. 0 | Page 11 of 20

ADP3182

OUTPUT ENABLE AND UVLO

For the ADP3182 to begin switching, the input supply (VCC) to
the controller must be higher than the UVLO threshold, and
the EN pin must be higher than its logic threshold. If UVLO is
less than the threshold or the EN pin is logic low, the ADP3182 is
disabled. This holds the PWM outputs at ground, shorts the
DELAY capacitor to ground, and holds the ILIMIT pin at ground.

In the application circuit, the ILIMIT pin should be connected
to the

grounded disables the drivers such that both DRVH and DRVL
are grounded. This feature is important in preventing the
discharge of the output capacitors when the controller is shut
off. If the driver outputs were not disabled, a negative voltage
could be generated during output due to the high current
discharge of the output capacitors through the inductors.

pins of the ADP3418 drivers. The ILIMIT being

OD

Rev. 0 | Page 12 of 20

ADP3182

L1

1µH

V

IN

12V

V

IN

RTN C4

C1
2700µF
16V

++

C2
2700µF
16V

D1

1N4148WS

D2

1N4148WS

C3
1µF

D3

1N4148WS

C7
1µF

D4

1N4148WS

C11
1µF

1

2

3

4

1

2

3

4

1

2

3

4

BST
IN
OD
V

CC

ADP3418

BST
IN
OD
V

CC

ADP3418

BST
IN
OD
V

CC

U2

ADP3418

DRVH

PGND
DRVL

U3

DRVH

PGND

DRVL

U4

DRVH

PGND

DRVL

100nF

SW

100nF

SW

100nF

SW

8

7

6

5

C8

8

7

6

5

C12

8

7

6

5

Q2

NTD110N02

Q4

NTD110N02

Q6

NTD110N02

C5

4.7µF

Q1
NTD40N02

C9

4.7µF

Q3
NTD40N02

C13

4.7µF

Q5
NTD40N02

L2

600nH/1.4mΩ

C6

4.7nF

R1

2.2Ω

L3

600nH/1.4mΩ

C10

4.7nF

R2

2.2Ω

L4

600nH/1.4mΩ

C14

4.7nF

R3

2.2Ω

1200µF/6.3V × 5

15mΩ ESR (EACH)

+

C17

C21

4.7µF × 10

+

6.3V

MLCC

V

OUT

1.8V
55A

V

OUT

RTN

POWER

GOOD

ENABLE

R

LIM

287kΩ

R4

10Ω

+

C15
1µF

1.00kΩ

R

B1

1.24kΩ

R

B2

C

DLY

39nF

R

DLY

470kΩ

6.04kΩ

C

A

1.2nF

C16
33µF

R

A

258kΩ

R

332kΩ

C
100pF

T

R

R

1

2

3

FB

4

5

6

7

8

9

10

U1

ADP3182

V

CC

FBRTN

FB PWM3

COMP

PWRGD

EN

DELAY

RT

RAMPADJ CSSUM

ILIMIT

PWM1

PWM2

SW1

SW2

SW3

GND

CSCOMP

CSREF

20

19

18

17

R

16

15

14

13

12

11

SW2

*

C

CS

5.6nF

R

SW3

*

R

CS

100kΩ

R

SW1

*

R

PH2

140kΩ

R

PH3

140kΩ

R

PH1

140kΩ

04938-009

Figure 9. 1.8 V, 55 A Application Circuit

Rev. 0 | Page 13 of 20

ADP3182

(

()(

)

×−×

×

APPLICATIONS

The design parameters for the typical high current point-of­load dc/dc buck converter shown in Figure 9 are as follows:

• Input voltage (V

• VID setting voltage (V

• Duty cycle (D) = 0.15

• Output current I

• Maximum output current (I

• Number of phases (n) = 3

) = 12 V

IN

= 55 A

O

) = 1.8 V

OUT

) = 110 A

LIM

The value for C

C ×

DLY

can be approximated using

DLY

⎛
⎜
⎜
⎝

V

μA20

OUT

R

×−=2

DLY

where:

t

is the desired soft start time.

SS

R

Assuming an

C

ms,

is 36 nF.

DLY

of 390 kΩ and a desired soft start time of 3

DLY

The closest standard value for

Once C

is chosen, R

DLY

can be calculated for the current limit

DLY

latch-off time using

⎞
⎟
⎟
⎠

C

t

SS

(2)

V

OUT

is 39 nF.

DLY

• Switching frequency per phase (f

) = 250 kHz

SW

SETTING THE CLOCK FREQUENCY

The ADP3182 uses a fixed-frequency control architecture. The
frequency is set by an external timing resistor (RT). The clock
frequency and the number of phases determine the switching
frequency per phase, which relates directly to switching losses
and the sizes of the inductors and the input and output
capacitors. With n = 3 for three phases, a clock frequency of
750 kHz sets the switching frequency (f

) of each phase to

SW

250 kHz, which represents a practical trade-off between the
switching losses and the sizes of the output filter components.
Equation 1 shows that to achieve a 750 kHz oscillator frequency,
the correct value for R

is 256 kΩ. Alternatively, the value for RT

T

can be calculated using

=

R

T

1

××

fn

SW

=TR

−

pF4.7

1

××

(1)

kΩ27

kΩ256kΩ27

pF4.7kHz2503

=−

where 4.7 pF and 27 kΩ are internal IC component values. For
good initial accuracy and frequency stability, a 1% resistor is
recommended. The closest standard 1% value for this design is
258 kΩ.

SOFT START AND CURRENT LIMIT LATCH-OFF DELAY TIME

Because the soft start and current limit latch-off delay functions
share the DELAY pin, these two parameters must be considered
together. The first step is to set C
ramp is generated with a 20 µA internal current source. The
value of R

has a second-order impact on the soft start time

DLY

because it sinks part of the current source to ground. However,
as long as R

is kept greater than 200 kΩ, this effect is minor.

DLY

for the soft start ramp. This

DLY

t

96.1

R×=

DLY

If the result for R
should be considered by recalculating the equation for C
longer latch-off time should be used. R

DELAY

C

DLY

DLY

(3)

is less than 200 kΩ, a smaller soft start time

should never be less

DLY

DLY

, or a

than 200 kΩ. In this example, a delay time of 9 ms results in
R

= 452 kΩ. The closest standard 5% value is 470 kΩ.

DLY

INDUCTOR SELECTION

The amount of inductance determines the ripple current in the
inductor. Less inductance leads to more ripple current, which
increases the output ripple voltage and conduction losses in the
MOSFETs, but allows using smaller inductors and, for a
specified peak- peak transient deviation, less total output
capacitance. Conversely, a higher inductance means lower
ripple current and reduced conduction losses, but requires
larger inductors and more output capacitance for the same
peak-peak transient deviation. In any multiphase converter, a
practical value for the peak-peak inductor ripple current is less
than 50% of the maximum dc current in the same inductor.
Equation 4 shows the relationship between the inductance,
oscillator frequency, and peak-peak ripple current in the
inductor.

Equation 5 can be used to determine the minimum inductance
based on a given output ripple voltage.

DV

−×=1

OUT

I

R

L

≥

SW

OUT

SW

where:

is ESR of output bulk capacitors.

R

X

)

(4)

Lf

×

DnRV

1

x

Vf

×

RIPPLE

(5)

Rev. 0 | Page 14 of 20

ADP3182

Solving Equation 5 for a 20 mV p-p output ripple and an RX of
3 mΩ voltage yields

≥L

()

×

150.31mΩ3V81.

×−××

mV02kHz025

nH594

=

If the resulting ripple voltage is too low, the level of inductance
can be decreased until the desired ripple value is met. This
allows optimal transient response and minimum output
decoupling.

The smallest possible inductor should be used to minimize the
number of output capacitors. For this example, choosing a
600 nH inductor is a good starting point that produces a
calculated ripple current of 6.6 A. The inductor should not
saturate at the peak current of 21.6 A and should be able to
handle the sum of the power dissipation caused by the average
current of 18.3 A in the winding and core loss.

Another important factor in the inductor design is the DCR,
which is used for measuring the phase currents. A large DCR
can cause excessive power losses, whereas too small a value can
lead to increased measurement error. For this design, a DCR of

1.4 mΩ was chosen.

Designing an Inductor

Once the inductance and DCR are known, the next step is to
either design an inductor or find a standard inductor that
comes as close as possible to meeting the overall design goals.
The first decision in designing the inductor is to choose the
core material. Several possibilities for providing low core loss at
high frequencies include the powder cores (e.g., Kool-Mµ® from
Magnetics, Inc., or from Micrometals) and the gapped soft
ferrite cores (e.g., 3F3 or 3F4 from Philips). Low frequency
powdered iron cores should be avoided, especially when the
inductor value is relatively low and the ripple current is high, due
to their high core loss.

Selecting a Standard Inductor

The following power inductor manufacturers can provide design
consultation and deliver power inductors optimized for high
power applications upon request.

•

Coilcraft

[phone]

www.coilcraft.com

•

Coiltronics

[phone]

www.coiltronics.com

Sumida Electric Company

•

[phone]

www.sumida.com

Vishay Intertechnology

•

[phone]

www.vishay.com

OUTPUT CURRENT SENSE

The output current can be measured by summing the voltage
across each inductor and passing the signal through a low-pass
filter. The CS amplifier is configured with resistors R
summing the voltage), and R
The output current I

R

I ×=

O

R

CS

C×≥ (7)

CS

L

is set by the following equations:

O

V

xPH

)(

DRP

R

L

L

RR

CS

and CCS (for the low-pass filter).

CS

(6)

where:

R

is the DCR of the output inductors.

L

V

is the voltage drop from CSCOMP to CSREF.

DRP

PH(X)

(for

The best choice for a core geometry is a closed-loop type such
as a potentiometer core, a PQ, U, or E core, or a toroid core. A
good compromise between price and performance is a core with
a toroidal shape.

Many useful references for magnetics design are available for
quickly designing a power inductor, such as

•

Magnetic Designer Software

Intusoft (www.intusoft.com)

Designing Magnetic Components for High-Frequency DC-

•

DC Converters, by William T. McLyman, Kg Magnetics,
Inc., ISBN 1883107008

Rev. 0 | Page 15 of 20

When load current reaches its limit, V
(V

DRPMAX

). V

can be in the range of 100 to 200 mV. In this

DRPMAX

DRP

example, it is 110 mV.

One has the flexibility of choosing either R
recommended to select R

by rearranging Equation 6.

R

PH(X)

()

x

()

xPH

L

PH

R

equal to 100 kΩ, and then solve for

CS

I

LIM

××=

RRR

CS

V

DRPMAX

110A

Ωk100Ωm4.1 =××=

mV110

is at its maximum

CS

or R

PH(X)

. It is

Ωk140

ADP3182

MF

×

The closest standard 1% value for R
Equation 7 to solve for CCS.

≥

C

CS

nH600

×

≥

Ωk100Ωm4.1

Choose the closest standard value that is greater than the result
given by Equation 7. This example uses a C

OUTPUT VOLTAGE

ADP3182 has an internal FBRTN voltage reference V
800 mV. The output voltage can be set up using a voltage
divider made up of resistors R

RR

+

21

V ×

=

OUT

BB

R

1

B

B1

(8)

V

REF

Rearranging Equation 8 to solve for R
with an internal FB voltage of 800 mV and assuming a 1%, 1 kΩ
resistor for R

R

yields

B1

⎛

V

⎜

B

⎜

V

⎝

⎞

OUT

⎟

−= k25.1k11

1

⎟

REF

⎠

⎛
⎜

R

12 B

⎜
⎝

The closest standard 1% resistor value for R

POWER MOSFETS

For this example, one high-side, N-channel power MOSFET
and two low-side, N-channel power MOSFETs per phase have
been selected. The main selection parameters for the power
MOSFETs are V
gate drive voltage (the supply voltage to the ADP3418) dictates
whether standard threshold or logic-level threshold MOSFETs
must be used. With V

< 2.5 V) are recommended.

(V

GS(TH)

The maximum output current (I
requirement for the low-side (synchronous) MOSFETs. With
the ADP3182, currents are balanced between phases, thus the
current in each low-side MOSFET is the output current divided
by the total number of MOSFETs (n
being dominant, the following expression shows the total power
being dissipated in each synchronous MOSFET in terms of the
ripple current per phase (I
(I

):

O

1

()

SF

Knowing the maximum output current and the maximum
allowed power dissipation, one can determine the required
R

for the MOSFET. For D-PAK MOSFETs up to an

DS(ON)

ambient temperature of 50°C, a safe limit for P
at 120°C junction temperature. Therefore, for this example,

, QG, C

GS(TH)

⎡

⎛
⎜

⎢

DP ×

×−=

⎜

⎢

⎝

⎣

, C

ISS

~10 V, logic-level threshold MOSFETs

GATE

) and the average total output current

R

⎞

I

O

⎟
⎟

n

12

SF

⎠

is 140 kΩ. Next, use

PH(X)

nF29.4

value of 5.6 nF.

CS

and RB2:

using the ADP3182

B2

⎞

V8.1

⎟

−=×
⎟

V8.0

⎠

is 1.24 kΩ.

B2

, and R

RSS

) determines the R

O

). With conduction losses

SF

⎛

1

⎜

×+

⎜

n

⎝

In

SF

DS(ON)

R

22

⎤

⎞
⎟

⎥

⎟

⎥

⎠

⎦

. The minimum

R

is 1 W to 1.5 W

SF

of

REF

Ω=Ω×

DS(ON)

(9)

()

SFDS

(per MOSFET) < 7.5 mΩ. This R

R

DS(SF)

is also at a junction

DS(SF)

temperature of about 120°C, so one must account for this when
making this selection. This example uses a lower-side MOSFET
with 4.8 mΩ at 120

°C.

Another important factor for the synchronous MOSFET is the
input capacitance and feedback capacitance. The ratio of
feedback to input must be small (less than 10% is recom­mended) to prevent accidentally turning on the synchronous
MOSFETs when the switch node goes high.

Also, the time to switch the synchronous MOSFETs off should
not exceed the nonoverlap dead time of the MOSFET driver
(40 ns typical for the ADP3418). The output impedance of the
driver is approximately 2 Ω, and the typical MOSFET input gate
resistances are about 1 Ω to 2 Ω; therefore, one should adhere to
a total gate capacitance of less than 6000 pF. Because there are
two MOSFETs in parallel, the input capacitance for each
synchronous MOSFET should be limited to 3000 pF.

The high-side (main) MOSFET must handle two main power
dissipation components: conduction and switching losses. The
switching loss is related to the amount of time for the main
MOSFET to turn on and off, and to the current and voltage that
are being switched. Basing the switching speed on the rise and
fall time of the gate driver impedance and MOSFET input
capacitance, the following expression provides an approximate
value for the switching loss per main MOSFET:

()

MFS

IV

××= 2 (10)

fP ×××

SW

OCC

n

n

MF

R

G

C

ISS

n

where:

nMF is the total number of main MOSFETs.
R

is the total gate resistance (2 Ω for the ADP3418 and about

G

1 Ω for typical high speed switching MOSFETs, making RG = 3 Ω).
C

is the input capacitance of the main MOSFET.

ISS

Note that adding more main MOSFETs (n

) does not help the

MF

switching loss per MOSFET because the additional gate
capacitance slows switching. The most efficient way to reduce
switching loss is to use lower gate capacitance devices.

The conduction loss of the main MOSFET is given by the
following equation:

22

⎡

⎞

⎛

I

O

⎟

⎜

⎢

DP ×

() ()

MFC

×=

⎟

⎜

n

⎢

MF

⎠

⎝

⎣

12

⎛

1

⎜

×+

⎜

n

⎝

⎤

In

×

⎞

R

⎟

⎥

MF

R

⎟

⎥

⎠

⎦

MFDS

(11)

where:

R

is the on resistance of the MOSFET.

DS(MF)

Typically, for main MOSFETs, the highest speed (low C

)

ISS

device is preferred, but faster devices usually have higher on
resistance. Select a device that meets the total power dissipation

Rev. 0 | Page 16 of 20

ADP3182

(

×−×

×

(about 1.5 W for a single D-PAK) when combining the
switching and conduction losses.

For this example, an NTD40N03L was selected as the main
MOSFET (three total; n
R

= 19 mΩ (max at TJ = 120°C), and an NTD110N02L was

DS(MF)

selected as the synchronous MOSFET (three total; n
C

= 2710 pF (max) and R

ISS

The synchronous MOSFET C

= 3), with a C

MF

= 4.8 mΩ (max at TJ = 120°C).

DS(SF)

is less than 3000 pF, satisfying

ISS

= 584 pF (max) and

ISS

= 3), with

SF

that requirement. Solving for the power dissipation per MOSFET
at I

= 55 A and IR = 6.6 A yields 894 mW for each synchronous

O

MOSFET and 1.16 W for each main MOSFET. These numbers
comply with the guideline to limit the power dissipation to
around 1 W per MOSFET.

One last thing to consider is the power dissipation in the driver
for each phase. This is best described in terms of the Q

for the

G

MOSFETs and is given by the following equation:

⎡

f

SW

P ×

⎢

DRV

⎢

⎣

()

MF

n

×=2

⎤

+×+××

VIQnQn

⎥

CCCCGSFSFGMF

⎥

⎦

(12)

where:

Q

is the total gate charge for each main MOSFET.

GMF

Q

is the total gate charge for each synchronous MOSFET.

GSF

Also shown is the standby dissipation factor (I

× VCC) for the

CC

driver. For the ADP3418, the maximum dissipation should be
less than 400 mW. In this example, with I
9 nC, and Q

= 46 nC, there is 165 mW in each driver, which

GSF

= 7 mA, Q

CC

GMF

=

is below the 400 mW dissipation limit. See the ADP3418 data
sheet for more details.

The internal ramp voltage magnitude can be calculated by using

)

1

R

=

V

R

VDA

OUT

××

fCR

RR

SW

(14)

=

V

R

()

V81.50.110.2

×−×

××

=

kHz025pF5Ωk332

Vm737

The size of the internal ramp can be made larger or smaller. If it
is made larger, stability and transient response improve, but
thermal balance degrades. Likewise, if the ramp is made
smaller, thermal balance improves but transient response and
stability degrade. The factor of three in the denominator of
Equation 13 sets a ramp size with optimal balance for good
stability, transient response, and thermal balance.

CURRENT LIMIT SETPOINT

To select the current limit setpoint, first find the resistor value

. The current limit threshold for the ADP3182 is set

for R

LIM

with a 3 V source (V
(A

). R

LIM

can be found using

LIM

R

=

LIM

V

For values of R
lower than expected and therefore necessitate some adjustment of
R

. Here, I

LIM

is the average current limit for the output of the

LIM

supply. In this example, using the V
Equations 6 and 7 and choosing a peak current limit of 110 A
for I

results in R

LIM

the nearest 1% value.

) across R

LIM

VA

LIMLIM

(15)

DRPMAX

greater than 500 kΩ, the current limit may be

LIM

= 284 kΩ, for which 287 kΩ is chosen as

LIM

with a gain of 10.4 mV/µA

LIM

value of 110 mV from

DRPMAX

RAMP RESISTOR SELECTION

The ramp resistor (RR) is used for setting the size of the internal
PWM ramp. The value of this resistor is chosen to provide the
best combination of thermal balance, stability, and transient
response. The following expression is used to determine the
optimum value:

×

LA

=

R

R

3

=

R

R

where:

A

is the internal ramp amplifier gain.

R

is the current balancing amplifier gain.

A

D

R
C

is the total low-side MOSFET on resistance.

DS(ON)(SF)

is the internal ramp capacitor value.

R

The closest standard 1% resistor value is 332 kΩ.

R

×××

CRA

D

R

))((

SFONDS

(13)

nH0600.2

×

pF5Ωm8.453

×××

kΩ333

=

Rev. 0 | Page 17 of 20

The limit of the per phase current limit described earlier is
determined by

VVV

−−

RA

×

R

()

MAXDS

MAXCOMP

I +

≅

PHLIM

()

D

BIAS

I

R

(16)

2

FEEDBACK LOOP COMPENSATION DESIGN

Optimized compensation of the ADP3182 allows the best
possible response of the regulator’s output to a load change. The
basis for determining the optimum compensation is to make
the regulator and output decoupling appear as an output
impedance that is entirely resistive over the widest possible
frequency range, including dc.

With the multimode feedback structure of the ADP3182, the
feedback compensation must be set so that the converter’s
output impedance, working in parallel with the output
decoupling, will meet this goal. One will need to compensate for
the several poles and zeros created by the output inductor and
decoupling capacitors (output filter).

ADP3182

(

(

×−×

−××

−

A type three compensator on the voltage feedback is adequate
for proper compensation of the output filter. Equations 20 to 22
are intended to yield an optimal starting point for the design;
some adjustments may be necessary to account for PCB and
component parasitic effects.

RC

×

C

=

A

R

=

A

C

FB

is 6000 µF (five 1200 µF capacitors in parallel) with an

If C

X

XX

×

R

4

×

4

×

V

R

2

B

V

OUT

R

⎛

B

2

⎜

×

⎜

RCn

××

XX

⎝

1

Rfn

×××=2

equivalent ESR of 3 mΩ, the equations above give the following
compensation values:

C

= 1.33 nF

A

= 6.05 kΩ

R

A

C

= 110 pF

FB

Using the nearest standard value for each of these components
yields C

= 1.2 nF, RA = 6.04 kΩ, and CFB = 100 pF.

A

INPUT CAPACITOR SELECTION AND INPUT CURRENT di/dt

In continuous inductor current mode, the source current of the
high-side MOSFET is approximately a square wave with a duty
ratio equal to n × V
maximum output current. To prevent large voltage transients, a
low ESR input capacitor, sized for the maximum rms current,
must be used. The maximum rms capacitor current is given by

I

CRMS

Note that manufacturers often base capacitor ripple current
rating on only 2,000 hours of life. Therefore, it advisable to
further derate the capacitor or to choose a capacitor rated at a
higher temperature than required. Several capacitors may be
placed in parallel to meet size or height requirements in the
design. In this example, the input capacitor bank is formed by
two 2,700 µF, 16 V aluminum electrolytic capacitors and three

4.7 µF ceramic capacitors.

To reduce the input current di/dt to a level below the recom­mended maximum of 0.1 A/µs, an additional small inductor
(L > 370 nH @ 10 A) can be inserted between the converter and
the supply bus. That inductor also acts as a filter between the
converter and the primary power source.

OUT/VIN

IDI

OCRMS

××=

A5515.0

××=

Rn

×

X

DL

VL

×

R

−

VR

×

X

OUT

(17)

RAR

×+×

DS

⎞

RA

×

D

DS

⎟

(18)

2

SW

⎟

Rf

××

X

⎠

(19)

ASW

and an amplitude of one-nth the

1

1

−

×

DN

(20)

1

×

=−

50.13

A1.91

INDUCTOR DCR TEMPERATURE CORRECTION

With the inductor’s DCR being used as the sense element and
copper wire being the source of the DCR, one needs to
compensate for temperature changes in the inductor’s winding
if a highly accurate safety current limit setpoint is desired.
Fortunately, copper has a well-known temperature coefficient
(TC) of 0.39%/°C.

If R

is designed to have an opposite and equal percentage of

CS

change in resistance to that of the wire, it cancels the tempera­ture variation of the inductor’s DCR. Due to the nonlinear
nature of NTC thermistors, resistors R
See Figure 10 for instructions on how to linearize the NTC and
produce the desired temperature tracking.

PLACE AS CLOSE AS POSSIBLE

TO NEAREST INDUCTOR

OR LOW-SIDE MOSFET

R

TH

ADP3182

CSCOMP

18

C

CSREF

CS1

17

16

CSSUM

Figure 10. Temperature Compensation Circuit Values

R

CS1

C

CS2

The following procedures and expressions yield values to use

, R

for R
R

value.

CS

1.

Select an NTC based on type and value. Because we do not

, and RTH (the thermistor value at 25°C) for a given

CS1

CS2

have a value yet, start with a thermistor with a value close
to R

. The NTC should also have an initial tolerance of

CS

better than 5%.

2.

Based on the type of NTC, find its relative resistance value

at two temperatures. The temperatures that work well are
50°C and 90°C. These resistance values are called A
(R

TH(50°C

)/R

TH(25°C)

) and B (R

TH(90°C

NTC’s relative value is always 1 at 25°C.

3.

Find the relative value of R

CS

temperatures. This is based on the percentage of change
needed, which in this example is initially 0.39%/°C. These
are called r
(T

− 25))), where TC = 0.0039 for copper. T1 = 50°C and

2

T

= 90°C are chosen. From this, one can calculate that r1 =

2

0.9112 and r

4.

Compute the relative values for R

r

CS2

(1/(1 + TC × (T1 − 25))) and r2 (1/(1 + TC ×

1

= 0.7978.

2

=

)

()

and R

CS1

R

PH1RPH2

R

CS2

)/R

TH(25°C)

are needed.

CS2

TO

SWITCH

NODES

R

PH3

KEEP THIS PATH

AS SHORT AS POSSIBLE

AND WELL AWAY FROM

SWITCH NODE LINES

). Note that the

required for each of these

, R

, and RTH using

CS1

CS2

()

() ( )

+×−×

11

21

)

11

BArABrBA

−−×−×−×−×

TO

V

SENSE

rABrBArrBA

1221

OUT

(21)

04938-010

Rev. 0 | Page 18 of 20

ADP3182

()(

)

()

1

A

r

=

CS1

r

=

TH

5.

Calculate R

1

−

1

−

r

−

1

CS2

1

1

1

−

1

−

rr

CS1CS2

= rTH × RCS, then select the closest value of

TH

(22)

A

rr

−

CS2

(23)

thermistor available. Also, compute a scaling factor k based
on the ratio of the actual thermistor value used relative to
the computed one:

R

ACTUALTH

k =

Calculate values for R

6.

()

R

CALCULATEDTH

()

(24)

and R

CS1

rkRR ××=

(25)

CS1CSCS1

()

using

CS2

rkkRR ×+−×= 1

(26)

CS2CSCS2

LAYOUT AND COMPONENT PLACEMENT

The following guidelines are recommended for optimal
performance of a switching regulator in a PC system.

General Recommendations

For good results, a PCB with at least four layers is recommended.
This should allow the needed versatility for control circuitry
interconnections with optimal placement, power planes for
ground, input and output power, and wide interconnection
traces in the remainder of the power delivery current paths.
Keep in mind that each square unit of 1 ounce copper trace
has a resistance of ~0.53 mΩ at room temperature.

When high currents must be routed between PCB layers, vias
should be used liberally to create several parallel current paths
so that the resistance and inductance introduced by these current
paths is minimized and the via current rating is not exceeded.

If critical signal lines (including the output voltage sense lines of
the ADP3182) must cross through power circuitry, a signal
ground plane should be interposed between those signal lines
and the traces of the power circuitry. This serves as a shield to
minimize noise injection into the signals at the expense of
making the signal ground a bit noisier.

An analog ground plane should be used around and under the
ADP3182 as a reference for the components associated with the
controller. This plane should be tied to the nearest output de­coupling capacitor ground, but it should not be tied to any other
power circuitry to prevent power currents from flowing in it.

The components around the ADP3182 should be located close
to the controller with short traces. The most important traces to

keep short and away from other traces are the FB and CSSUM
pins. The output capacitors should be connected as close as
possible to the load or connector. If the load is distributed, the
capacitors should also be distributed and generally be in pro­portion to where the load tends to be more dynamic. Avoid
crossing any signal lines over the switching power path loop,
described in the following section.

Power Circuitry Recommendations

To minimize radiated switching noise energy (i.e., EMI) and
conduction losses in the board, the switching power path should
be routed on the PCB to encompass the shortest possible length.
Failure to take proper precautions often results in EMI problems
for the entire PC system as well as noise-related operational
problems in the power-converter control circuitry. The switching
power path is the loop formed by the current path through the
input capacitors and the power MOSFETs, including all inter­connecting PCB traces and planes. Using short and wide
interconnection traces is especially critical in this path for two
reasons: it minimizes the inductance in the switching loop,
which can cause high energy ringing, and it accommodates the
high current demand with minimal voltage loss.

When a power-dissipating component, for example, a power
MOSFET, is soldered to a PCB, the liberal use of vias, both
directly on the mounting pad and immediately surrounding it,
is recommended. Two important reasons for this are improved
current rating through the vias and improved thermal
performance from vias that extend to the opposite side of the
PCB, where a plane can more readily transfer the heat to the air.
To optimize thermal dissipation, make a mirror image of the
pads in use to heat sink the MOSFETs on the opposite side of
the PCB. To further improve thermal performance, use the
largest possible pad area.

The output power path should also be routed to encompass a
short distance. The output power path is formed by the current
path through the inductor, the output capacitors, and the load.

For best EMI containment, a solid power ground plane should
be used as one of the inner layers, extending fully under all the
power components.

Signal Circuitry Recommendations

The output voltage is sensed and regulated between the FB pin
and the FBRTN pin, which connect to the signal ground at the
load. To avoid differential mode noise pickup in the sensed signal,
the loop area should be small. Therefore, the FB and FBRTN
traces should be routed adjacent to each other on top of the
power ground plane back to the controller. The feedback traces
from the switch nodes should be connected as close as possible
to the inductor. The CSREF signal should be connected to the
output voltage at the nearest inductor to the controller.

Rev. 0 | Page 19 of 20

ADP3182

C

Y

OUTLINE DIMENSIONS

0.341
BSC

PIN 1

0.010

0.004

OPLANARIT

0.004

20 11

1

0.065

0.049

BSC

0.012

0.008

0.025

COMPLIANT TO JEDEC STANDARDS MO-137AD

0.069

0.053

10

SEATING
PLANE

0.154
BSC

0.236
BSC

0.010

0.006

8°
0°

0.050

0.016

Figure 11. 20-Lead Shrink Small Outline Package [QSOP]

(RQ-20)

Dimensions shown in inches

ORDERING GUIDE

Model Temperature Range Package Description Package Option Quantity per Reel

ADP3182JRQZ-RL

1

Z = Pb-free part.

1

0°C to 85°C Shrink SOIC 13” Reel RQ-20 2500

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

D04938–0–10/04(0)

Rev. 0 | Page 20 of 20