Datasheet ADP3181 Datasheet (Analog Devices)

5-Bit or 6-Bit Programmable 2-,3-,4-Phase

V

FEATURES

Selectable 2-, 3- or 4-phase operation at up to 1 MHz per

phase

±14.5 mV worst-case mV differential sensing error over

temperature

Logic-level PWM outputs for interface to external high

power drivers
Active current balancing between all output phases
Built-in power good/crowbar blanking supports on-the-fly

VID code changes
Digitally programmable output can be switched between

VRM 9 (5-bit) and VRD 10 (6-bit) VID codes
Programmable short-circuit protection with programmable

latch-off delay

APPLICATIONS

Desktop PC power supplies for:

Next-generation Intel

VRM modules

GENERAL DESCRIPTION

The ADP3181 is a highly efficient multiphase synchronous
buck-switching regulator controller optimized for converting
a 12 V main supply into the core supply voltage required by
high performance Intel processors. It uses an internal 6-bit
DAC to read a voltage identification (VID) code directly from
the processor, which is used to set the output voltage. The
CPUID input selects whether the DAC codes match the
VRM 9 or VRD 10 specifications. It uses a multimode PWM
architecture to drive the logic-level outputs at a programmable
switching frequency that can be optimized for VR size and
efficiency. The phase relationship of the output signals can
be programmed to provide 2-, 3-, or 4-phase operation,
allowing for the construction of up to four complementary
buck-switching stages.

® processors

Synchronous Buck Controller

ADP3181

FUNCTIONAL BLOCK DIAGRAM

GND

PWRGD

ILIMIT

DELAY

COMP

11

EN

19

10

15

12

UVLO

SHUTDOWN

AND BIAS

DAC + 300mV

CSREF

DAC – 250mV

DELAY

EN

9

PRECISION

REFERENCE

CC

28 1314

SOFT

START

VID4 VID3 VID2 VID1 VID0FBRTN CPUID

OSCILLATOR

CURRENT-

BALANCING

CIRCUIT

VID

DAC

1234576

Figure 1.

RTRAMPADJ

CMP

CMP

CURRENT-

LIMITING

CIRCUIT

CMP

CMP

CROWBAR

ADP3181

ENSET

RESET

RESET

2-/3-/4-PHASE

DRIVER LOGIC
RESET

RESET

CURRENT
LIMIT

27

26

25

24

23

22

21

20

17

16

18

8

PWM1

PWM2

PWM3

PWM4

SW1
SW2
SW3
SW4

CSSUM
CSREF

CSCOMP

FB

04796-0-001

The ADP3181 also includes programmable no-load offset and
slope functions to adjust the output voltage as a function of the
load current so that it is always optimally positioned for a
system transient. The ADP3181 provides accurate and reliable
short-circuit protection, adjustable current limiting, and a
delayed power good output that accommodates on-the-fly
output voltage changes requested by the CPU.

The device is specified over the commercial temperature range
of 0°C to +85°C and is available in a 28-lead TSSOP package.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

ADP3181

TABLE OF CONTENTS

Specifications..................................................................................... 3

Tes t Ci rc ui t s ....................................................................................... 5

Absolute Maximum Ratings............................................................ 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics............................................. 8

Theory of Operation ........................................................................ 9

Start-up Sequence......................................................................... 9

Master Clock Frequency............................................................ 10

Output Voltage Differential Sensing ........................................10

Output Current Sensing ............................................................ 11

Active Impedance Control Mode............................................. 11

Current Control Mode and Thermal Balance .......................11

Volt a ge C ont r o l Mo d e................................................................ 11

Soft Start ......................................................................................12

Current Limit, Short-Circuit, and Latch-Off Protection....... 12

Application Information................................................................ 15

Setting the Clock Frequency..................................................... 15

Soft-Start and Current-Limit Latch-Off Delay Times........... 15

Inductor Selection...................................................................... 15

Designing an Inductor............................................................... 16

Output Droop Resistance.......................................................... 16

Inductor DCR Temperature Correction ................................. 17

Output Offset.............................................................................. 17

C

Selection ............................................................................... 17

out

Power MOSFETS ........................................................................ 18

Ramp Resistor Selection............................................................ 19

Current Limit Setpoint.............................................................. 20

Feedback Loop Compensation Design.................................... 20

C

Selection and Input Current di/dt Reduction.................. 21

IN

Building a Switchable VR9/VR10 Design ............................... 22

Dynamic VID.............................................................................. 13

Power Good Monitoring ...........................................................13

Output Crowbar .........................................................................13

Output Enable and UVLO ........................................................ 13

REVISION HISTORY

5/04—Revision 0: Initial Version

Layout and Component Placement ............................................. 23

General Recommendations....................................................... 23

Outline Dimensions....................................................................... 24

Ordering Guide .......................................................................... 24

Rev. 0 | Page 2 of 24

ADP3181

SPECIFICATIONS

VCC = 12 V, FBRTN = GND, TA = 0°C to +85°C, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

ERROR AMPLIFIER

Output Voltage Range
Accuracy V

2

V

COMP

FB

0.7 3.1 V
Relative to nominal DAC output, referenced to

FBRTN, CSSUM = CSCOMP. See Figure 2.

Line Regulation
Input Bias Current I
FBRTN Current I
Output Current I

∆V

FB

FBRTN

O(ERR)

FB

Gain Bandwidth Product GBW
Slew Rate C

VCC = 10 V to 14 V 0.05 %
14 15.5 17
100 140
FB forced to V
COMP = FB 20 MHz

(ERR)

= 10 pF 25

COMP

VID INPUTS

Input Low Voltage V

IL(VID)

CPUID > 4.5 V 0.8 V
CPUID < 4.0 V 0.4 V
Input High Voltage V

IH(VID)

CPUID > 4.5 V 2.0 V
CPUID < 4.0 V 0.8 V
Input Current I

VID

VID(x) = 0 V, CPUID > 4.5 V 40 70
VID(x) = 0 V, CPUID < 4.0 V 20 35
Pull-up Resistance R

VID

40 60
Internal Pull-up Voltage CPUID > 4.5 V 2.25 2.5 2.75 V

CPUID < 4.0 V 1.1 1.25 1.4 V
VID Transition Delay Time

2

VID code change to FB change 400 ns

No CPU Detection Turn-off Delay Time2 VID code change to 11111 to PWM going low 400 ns

CPUID INPUT

Input Low Voltage V
Input High Voltage V

IL(CPUID)

IH(CPUID)

0.4 V

0.8 4.0 V
VR 9 Detection Threshold Voltage 4.0 4.5 V
Input Current I

Pull-up Resistance R

CPUID

CPUID

CPUID = 0 V 20 3.5

4.0 60

OSCILLATOR

Frequency Range
Frequency Variation f

Output Voltage V
RAMPADJ Output Voltage V
RAMPADJ Input Current Range I

2

f

OSC

PHASE

RT

RAMPADJ

RAMPADJ

0.25 4 MHz

TA = 25°C, RT = 250 kΩ, 4-phase

= 25°C, RT = 115 kΩ, 4-phase

T

A

= 25°C, RT = 75 kΩ, 4-phase

T

A

RT = 100 kΩ to GND
RAMPADJ – FB
0 100

CURRENT SENSE AMPLIFIER

Offset Voltage V
Input Bias Current I

OS(CSA)

BIAS(CSSUM)

Gain Bandwidth Product GBW
Slew Rate C

CSSUM – CSREF. See Figure 3.

10 MHz

(CSA)

= 10 pF 10

CSCOMP

Input Common-Mode Range CSSUM and CSREF 0 2.7 V
Positioning Accuracy

∆V

FB

See Figure 4.

Output Voltage Range 0.05 2.7 V
Output Current I

CSCOMP

500

1

−14.5

– 3% 500

OUT

+14.5 mV

155 200 245 kHz
400 kHz
600 kHz

1.9 2.0 2.1 V

−50

−3

−50

+50 mV

+3 mV
+50 nA

−77 −80 −83

µA
µA
µA

V/µs

µA
µA
kΩ

µA
kΩ

µA

V/µs

mV

µA

Rev. 0 | Page 3 of 24

ADP3181

Parameter Symbol Conditions Min Typ Max Unit

CURRENT BALANCE CIRCUIT

Common-Mode Range V
Input Resistance R
Input Current I
Input Current Matching

SW(X)CM

SW(X)

SW(X)

∆I

SW(X)

CURRENT LIMIT COMPARATOR

Output Voltage

Normal Mode V

In Shutdown V
Output Current, Normal Mode I
Maximum Output Current

2

Current Limit Threshold Voltage V

ILIMIT(NM)

ILIMIT(SD)

ILIMIT(NM)

60

CL

Current Limit Setting Ratio VCL/I
DELAY Normal Mode Voltage V
DELAY Overcurrent Threshold V
Latch-off Delay Time t

DELAY(NM)

DELAY(OC)

DELAY

SOFT START

Output Current, Soft-start Mode I
Soft-start Delay Time t

DELAY(SS)

DELAY(SS)

ENABLE INPUT

Input Low Voltage V
Input High Voltage V
Input Current, Input Voltage Low I

Input Current, Input Voltage High I

IL(EN)

IH(EN)

IL(EN)

IH(EN)

POWER GOOD COMPARATOR

Undervoltage Threshold V
Overvoltage Threshold V
Output Low Voltage V

PWRGD(UV)

PWRGD(OV)

OL(PWRGD)IPWRGD(SINK)

Power Good Delay Time

During Soft Start2

VID Code Changing 100 250

VID Code Static 200 ns
Crowbar Trip Point V

CROWBAR

Crowbar Reset Point Relative to FBRTN 630 700 770 mV
Crowbar Delay Time t

CROWBAR

VID Code Changing 100 250

VID Code Static 400 ns

PWM OUTPUTS

Output Low Voltage V
Output High Voltage V

OL(PWM)

OH(PWM)

SUPPLY

DC Supply Current 5 10 mA
UVLO Threshold Voltage V

UVLO

UVLO Hysteresis 0.7 0.9 1.1 V

−600

SW(X) = 0 V 20 30 40
SW(X) = 0 V 4 7 10
SW(X) = 0 V

−5

+200 mV

kΩ
µA

+5 %

EN > 0.8 V, R
EN < 0.4 V, I
EN > 0.8 V, R

= 250 kΩ

ILIMIT

= −100 µA

ILIMIT

= 250 kΩ

ILIMIT

2.9 3 3.1 V
400 mV
12

µA
µA

V

R
R
R

CSREF

ILIMIT

DELAY

DELAY

DELAY

– V

= 250 kΩ
= 250 kΩ
= 250 kΩ, C

CSCOMP

, R

= 250 kΩ

ILIMIT

DELAY

= 12 nF

During start-up, DELAY < 2.4 V 15 20 25

R

= 250 kΩ, C

DELAY

= 12 nF, VID code = 011111

DELAY

105 125 145 mV

10.4

mV/µA

2.9 3 3.1 V

1.7 1.8 1.9 V

1.5 ms

µA

1 ms

0.4 V

0.8 V
EN = 0 V

−1

EN = 1.25 V 10 25

Relative to nominal DAC output

−180 −250 −320

1

µA
µA

mV

Relative to nominal DAC output 230 300 370 mV

= 4 mA 225 400 mV

R

DELAY

= 250 kΩ, C

= 12 nF, VID Code = 011111

DELAY

1 ms

µs

Relative to nominal DAC output 230 300 370 mV

Overvoltage to PWM going low

µs

I

PWM(SINK)

I

PWM(SOURCE)

= −400 µA

= 400 µA

160 500 mV

4.0 5 V

VCC rising 6.5 6.9 7.3 V

1

All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

2

Guaranteed by design or bench characterization, not tested in production.

Rev. 0 | Page 4 of 24

ADP3181

5

TEST CIRCUITS

ADP3181

VCC

PWM1

PWM2

PWM3

PWM4

SW1

SW2

SW3

SW4

GND

CSCOMP

CSSUM

CSREF

ILIMIT

-BIT CODE

12nF

1.25V

1kΩ

250kΩ

1

VID4

2

VID3

3

VID2

4

VID1

5

VID0

6

CPUID

7

FBRTN

8

FB

9

COMP

10

PWRGD

11

EN

12

DELAY

13

RT

14

RAMPADJ

Figure 2. Closed-Loop Output Voltage Accuracy

ADP3181

VCC

100nF

28

18

17

16

19

CSCOMP

CSSUM

CSREF

GND

VOS=

12V

39kΩ

1kΩ

1.0V

28

+

27

26

25

24

23

22

21

20

19

18

20kΩ

17

16

15

250kΩ

CSCOMP–1V

40

100nF1µF

100nF

04796-0-005

12V

04796-0-004

ADP3181

VCC

V = 80mV

∆

28

FB

8

COMP

9

CSCOMP

18

CSSUM

17

CSREF

16

GND

19

– FB

V = 0mV

∆

04796-0-006

200kΩ

∆

V

1.0V

12V

10kΩ

200kΩ

100nF

∆

VFB = FB

Figure 4. Positioning Voltage

Figure 3. Current Sense Amplifier V

OS

Rev. 0 | Page 5 of 24

ADP3181

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

VCC
FBRTN
VID0 to VID4, CPUID, EN, DELAY, ILIMIT,

CSCOMP, RT, PWM1 to PWM4, COMP
SW1 to SW4
All other inputs and outputs
Storage temperature
Operating ambient temperature range 0°C to 85°C
Operating junction temperature 125°C
Thermal impedance (θJA) 100°C/W
Lead temperature

Soldering (10 sec) 300°C
Infrared (15 sec) 260°C

−0.3 V to +15 V

−0.3 V to +0.3 V

−0.3 V to +5.5 V

−5 V to +25 V

−0.3 V to VCC +0.3 V

−65°C to +150°C

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified all other voltages are
referenced to GND.

Rev. 0 | Page 6 of 24

ADP3181

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VID4
VID3
VID2
VID1
VID0

CPUID

FBRTN

FB

COMP

PWRGD

EN

DELAY

RT

RAMPADJ

1
2
3
4
5
6

ADP3181

7

TOP VIEW

8

(Not to Scale)

9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

VCC
PWM1
PWM2
PWM3
PWM4
SW1
SW2
SW3
SW4
GND
CSCOMP
CSSUM
CSREF
ILIMIT

04796-0-011

Figure 5. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Name Description

1 to 5 VID4 to VID0 Voltage Identification DAC Inputs. These five pins are pulled up to an internal reference, providing a

Logic 1 if left open. When in normal mode, the DAC output programs the FB regulation voltage based
on the condition of the CPUID pin (see Table 4 and Table 5). Leaving VID4 through VID0 open results in the
ADP3181 going into a “no CPU” mode, shutting off its PWM outputs.

6 CPUID

CPU DAC Code Selection Input. When this pin is pulled > 4.5 V, the internal DAC reads its inputs based on
the VR 9 VID table (see Table 4). When this pin is < 4 V, the DAC reads its inputs based on the VR 10 VID

table (see Table 5) and treats CPUID as the VID5 input.
7 FBRTN Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage.
8 FB

Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor

between this pin and the output voltage sets the no-load offset point.
9 COMP Error Amplifier Output and Compensation Point.
10 PWRGD

Power Good Output. Open-drain output that signals when the output voltage is outside of the proper

operating range.
11 EN Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs.
12 DELAY

Soft-start Delay and Current Limit Latch-off Delay Setting Input. An external resistor and capacitor

connected between this pin and GND sets the soft-start ramp-up time and the overcurrent latch-off

delay time.
13 RT

Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the

oscillator frequency of the device.
14 RAMPADJ

PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal

PWM ramp.
15 ILIMIT

Current Limit Setpoint/Enable Output. An external resistor from this pin to GND sets the current limit

threshold of the converter. This pin is actively pulled low when the ADP3181 EN input is low, or when VCC

is below its UVLO threshold, to signal to the driver IC that the driver high-side and low-side outputs should

go low.
16 CSREF

Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current

sense amplifier and the power good and crowbar functions. This pin should be connected to the common

point of the output inductors.
17 CSSUM

Current Sense Summing Node. External resistors from each switch node to this pin sum the average

inductor currents together to measure the total output current.
18 CSCOMP

Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determine the slope of

the load line and the positioning loop response time.
19 GND Ground. All internal biasing and the logic output signals of the device are referenced to this ground.
20 to 23 SW4 to SW1

Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused

phases should be left open.
24 to 27 PWM4 to PMW1

Logic-level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the

ADP3413 or ADP3418. Connecting the PWM3 and/or PWM4 outputs to GND causes that phase to turn off,

allowing the ADP3181 to operate as a 2-, 3-, or 4-phase controller.
28 VCC Supply Voltage for the Device.

Rev. 0 | Page 7 of 24

ADP3181

TYPICAL PERFORMANCE CHARACTERISTICS

4

3

2

1

MASTER CLOCK FREQUENCY (MHz)

0

0 50 100 150 200 250 300

Figure 6. Master Clock Frequency vs. R

5.3
TA = 25°C
4-PHASE OPERATION

5.2

5.1

5.0

4.9

4.8

SUPPLY CURRENT (mA)

4.7

4.6

0 4.03.53.02.52.01.51.00.5

RT VALUE (kΩ)

T

OSCILLATOR FREQUENCY (MHz)

Figure 7. Supply Current vs. Oscillator Frequency

04796-0-002

04796-0-003

Rev. 0 | Page 8 of 24

ADP3181

THEORY OF OPERATION

The ADP3181 combines a multimode, fixed-frequency PWM
control with multiphase logic outputs for use in 2-, 3-, and
4-phase synchronous buck CPU core supply power converters.
The internal VID DAC can be used in the Intel 5-bit VRM 9 or
6-bit VRD/VRM 10 designs, depending on the setting of the
CPUID pin. Multiphase operation is important for producing
the high currents and low voltages demanded by today’s micro­processors. Handling the high currents in a single-phase
converter places high thermal demands on the components
in the system such as the inductors and MOSFETs. The
multimode control of the ADP3181 ensures a stable, high
performance topology for

• Balancing currents and thermals between phases.

• High speed response at the lowest possible switching

frequency and output decoupling.

• Minimizing thermal switching losses due to lower

frequency operation.

• Tight load line regulation and accuracy.

• High current output from 4-phase operational design.

• Reduced output ripple due to multiphase cancellation.

• PC board layout noise immunity.

• Ease of use and design due to independent component

selection.

• Flexibility in operation for tailoring design to low cost or

high performance.

START-UP SEQUENCE

Two functions are set during the start-up sequence: the number
of active phases and the VID DAC configuration. The number
of operational phases and their phase relationship is determined
by internal circuitry that monitors the PWM outputs. Normally,
the ADP3181 operates as a 4-phase PWM controller. Grounding
the PWM4 pin programs 3-phase operation, and grounding the
PWM3 and PWM4 pins programs 2-phase operation.

When the ADP3181 is enabled, the controller outputs a voltage
on PWM3 and PWM4 that is approximately 675 mV. An
internal comparator checks each pin’s voltage versus a threshold
of 300 mV. If the pin is grounded, it is below the threshold and
the phase is disabled. The output resistance of the PWM pin is
approximately 5 kΩ during this detection time. Any external
pull-down resistance connected to the PWM pin should not be
less than 25 kΩ to ensure proper operation.

PWM1 and PWM2 are disabled during the phase detection
interval, which occurs during the first two clock cycles of the
internal oscillator. After this time, if the PWM output was not
grounded, the 5 kΩ resistance is removed and it switches
between 0 V and 5 V. If the PWM output was grounded, it
remains off.

The PWM outputs are logic-level devices intended for driving
external gate drivers such as the ADP3418. Because each phase
is monitored independently, operation approaching 100% duty
cycle is possible. Also, more than one output can be on at a time
for overlapping phases.

The VID DAC configuration is determined by the voltage at the
CPUID pin. If this pin is pulled up to > 4.5 V, the VID DAC
operates with five inputs and generates the VR 9 output voltage
range as shown in Table 4. If CPUID is < 4 V, the VID DAC
treats CPUID as the VID5 input of VR 10, and operates as a 6­bit DAC using the output voltage range given in Table 5.

Table 4. VR 9 VID Codes for the ADP3181, CPUID > 4.25

VID4 VID3 VID2 VID1 VID0 Output

1 1 1 1 1 No CPU
1 1 1 1 0 1.100 V
1 1 1 0 1 1.125 V
1 1 1 0 0 1.150 V
1 1 0 1 1 1.175 V
1 1 0 1 0 1.200 V
1 1 0 0 1 1.225 V
1 1 0 0 0 1.250 V
1 0 1 1 1 1.275 V
1 0 1 1 0 1.300 V
1 0 1 0 1 1.325 V
1 0 1 0 0 1.350 V
1 0 0 1 1 1.375 V
1 0 0 1 0 1.400 V
1 0 0 0 1 1.425 V
1 0 0 0 0 1.450 V
0 1 1 1 1 1.475 V
0 1 1 1 0 1.500 V
0 1 1 0 1 1.525 V
0 1 1 0 0 1.550 V
0 1 0 1 1 1.575 V
0 1 0 1 0 1.600 V
0 1 0 0 1 1.625 V
0 1 0 0 0 1.650 V
0 0 1 1 1 1.675 V
0 0 1 1 0 1.700 V
0 0 1 0 1 1.725 V
0 0 1 0 0 1.750 V
0 0 0 1 1 1.775 V
0 0 0 1 0 1.800 V
0 0 0 0 1 1.825 V
0 0 0 0 0 1.850 V

Rev. 0 | Page 9 of 24

ADP3181

Table 5. VR 10 VID Codes for the ADP3181, CPUID Used as a VID5 Input

VID4 VID3 VID2 VID1 VID0 CPUID Output VID4 VID3 VID2 VID1 VID0 CPUID Output

1 1 1 1 1 1 No CPU 1 1 0 1 0 0 1.2125 V
1 1 1 1 1 0 No CPU 1 1 0 0 1 1 1.2250 V
0 1 0 1 0 0 0.8375 V 1 1 0 0 1 0 1.2375 V
0 1 0 0 1 1 0.8500 V 1 1 0 0 0 1 1.2500 V
0 1 0 0 1 0 0.8625 V 1 1 0 0 0 0 1.2625 V
0 1 0 0 0 1 0.8750 V 1 0 1 1 1 1 1.2750 V
0 1 0 0 0 0 0.8875 V 1 0 1 1 1 0 1.2875 V
0 0 1 1 1 1 0.9000 V 1 0 1 1 0 1 1.3000 V
0 0 1 1 1 0 0.9125 V 1 0 1 1 0 0 1.3125 V
0 0 1 1 0 1 0.9250 V 1 0 1 0 1 1 1.3250 V
0 0 1 1 0 0 0.9375 V 1 0 1 0 1 0 1.3375 V
0 0 1 0 1 1 0.9500 V 1 0 1 0 0 1 1.3500 V
0 0 1 0 1 0 0.9625 V 1 0 1 0 0 0 1.3625 V
0 0 1 0 0 1 0.9750 V 1 0 0 1 1 1 1.3750 V
0 0 1 0 0 0 0.9875 V 1 0 0 1 1 0 1.3875 V
0 0 0 1 1 1 1.0000 V 1 0 0 1 0 1 1.4000 V
0 0 0 1 1 0 1.0125 V 1 0 0 1 0 0 1.4125 V
0 0 0 1 0 1 1.0250 V 1 0 0 0 1 1 1.4250 V
0 0 0 1 0 0 1.0375 V 1 0 0 0 1 0 1.4375 V
0 0 0 0 1 1 1.0500 V 1 0 0 0 0 1 1.4500 V
0 0 0 0 1 0 1.0625 V 1 0 0 0 0 0 1.4625 V
0 0 0 0 0 1 1.0750 V 0 1 1 1 1 1 1.4750 V
0 0 0 0 0 0 1.0875 V 0 1 1 1 1 0 1.4875 V
1 1 1 1 0 1 1.1000 V 0 1 1 1 0 1 1.5000 V
1 1 1 1 0 0 1.1125 V 0 1 1 1 0 0 1.5125 V
1 1 1 0 1 1 1.1250 V 0 1 1 0 1 1 1.5250 V
1 1 1 0 1 0 1.1375 V 0 1 1 0 1 0 1.5375 V
1 1 1 0 0 1 1.1500 V 0 1 1 0 0 1 1.5500 V
1 1 1 0 0 0 1.1625 V 0 1 1 0 0 0 1.5625 V
1 1 0 1 1 1 1.1750 V 0 1 0 1 1 1 1.5750 V
1 1 0 1 1 0 1.1875 V 0 1 0 1 1 0 1.5875 V
1 1 0 1 0 1 1.2000 V 0 1 0 1 0 1 1.6000 V

MASTER CLOCK FREQUENCY

The clock frequency of the ADP3181 is set with an external
resistor connected from the RT pin to ground. The frequency
follows the graph in Figure 6. To determine the frequency per
phase, the clock is divided by the number of phases in use. If
PWM4 is grounded, then divide the master clock by 3 for the
frequency of the remaining phases. If PWM3 and 4 are
grounded, divide by 2. If all phases are in use, divide by 4.

OUTPUT VOLTAGE DIFFERENTIAL SENSING

The ADP3181 combines differential sensing with a high
accuracy VID DAC and reference and a low offset error
amplifier to maintain a worst-case specification of ±14.5 mV

differential sensing error over its full operating output voltage
and temperature ranges. The output voltage is sensed between
the FB and FBRTN pins. FB should be connected through a
resistor to the regulation point, usually the remote sense pin of
the microprocessor. FBRTN should be connected directly to the
remote sense ground point. The internal VID DAC and
precision reference are referenced to FBRTN, which has a
minimal current of 100 µA to allow accurate remote sensing.
The internal error amplifier compares the output of the DAC to
the FB pin to regulate the output voltage.

Rev. 0 | Page 10 of 24

ADP3181

OUTPUT CURRENT SENSING

The ADP3181 provides a dedicated current sense amplifier
(CSA) to monitor the total output current for proper voltage
positioning versus load current and for current limit detection.
Sensing the load current at the output gives the total average
current being delivered to the load, which is an inherently more
accurate method than peak current detection or sampling the
current across a sense element such as the low-side MOSFET.
This amplifier can be configured several ways depending on the
objectives of the system:

• Output inductor ESR sensing without a thermistor for

lowest cost.

• Output inductor ESR sensing with a thermistor for

improved accuracy with tracking of inductor temperature.

• Sense resistors for highest accuracy measurements.

The positive input of the CSA is connected to the CSREF pin,
which is connected to the output voltage. The inputs to the
amplifier are summed together through resistors from the
sensing element (such as the switch node side of the output
inductors) to the inverting input, CSSUM. The feedback resistor
between CSCOMP and CSSUM sets the gain of the amplifier,
and a filter capacitor is placed in parallel with this resistor. The
gain of the amplifier is programmable by adjusting the feedback
resistor to set the load line required by the microprocessor. The
current information is then given as the difference of CSREF –
CSCOMP. This difference signal is used internally to offset the
VID DAC for voltage positioning and as a differential input for
the current limit comparator.

To provide the best accuracy for the sensing of current, the CSA
has been designed to have a low offset input voltage. Also, the
sensing gain is determined by external resistors so that it can be
made extremely accurate.

ACTIVE IMPEDANCE CONTROL MODE

For controlling the dynamic output voltage droop as a function
of output current, a signal proportional to the total output
current at the CSCOMP pin can be scaled to equal the droop
impedance of the regulator times the output current. This droop
voltage is then used to set the input control voltage to the
system. The droop voltage is subtracted from the DAC reference
input voltage directly to tell the error amplifier where the output
voltage should be. This differs from previous implementations
and allows enhanced feed-forward response.

CURRENT CONTROL MODE AND THERMAL BALANCE

The ADP3181 has individual inputs for each phase, which are
used for monitoring the current in each phase. This information
is combined with an internal ramp to create a current balancing
feedback system that has been optimized for initial current
balance accuracy and dynamic thermal balancing during
operation. This current balance information is independent of
the average output current information used for the positioning
described previously.

The magnitude of the internal ramp can be set to optimize
the transient response of the system. It is also monitors the
supply voltage for feed-forward control for changes in the
supply. A resistor connected from the power input voltage to
the RAMPADJ pin determines the slope of the internal PWM
ramp. Detailed information about programming the ramp is
given in the Application Information section.

If desired, external resistors can be placed in series with
individual phases to create an intentional current imbalance if
desired, such as when one phase may have better cooling and
can support higher currents. Resistors RSW1 through RSW4
(see the typical application circuit in Figure 10) can be used for
adjusting thermal balance. It is best to have the ability to add
these resistors during the initial design, so make sure
placeholders are provided in the layout.

To increase the current in any phase, make R
larger (make R
balancing). Increasing R

= 0 for the hottest phase; do not change during

SW

to only 500 Ω makes a substantial

SW

increase in phase current. Increase each R

for that phase

SW

value by small

SW

amounts to achieve balance, starting with the coolest phase first.

VOLTAGE CONTROL MODE

A high gain bandwidth voltage mode error amplifier is used for
the voltage-mode control loop. The control input voltage to the
positive input is set via the VID logic. This voltage is also offset
by the droop voltage for active positioning of the output voltage
as a function of current, commonly known as active voltage
positioning. The output of the amplifier is the COMP pin,
which sets the termination voltage for the internal PWM ramps.

The negative input (FB) is tied to the output sense location with
a resistor, RB, and is used for sensing and controlling the output
voltage at this point. A current source from the FB pin flowing
through RB is used for setting the no-load offset voltage from
the VID voltage. The no-load voltage is negative with respect to
the VID DAC. The main loop compensation is incorporated in
the feedback network between FB and COMP.

Rev. 0 | Page 11 of 24

ADP3181

SOFT START

The power-on ramp-up time of the output voltage is set with
a capacitor and resistor in parallel from the DELAY pin to
ground. The RC time constant also determines the current limit
latch off time as explained in the following section. In UVLO or
when EN is a logic low, the DELAY pin is held at ground. After
the UVLO threshold is reached and EN is a logic high, the
DELAY capacitor is charged with an internal 20 µA current
source. The output voltage follows the ramping voltage on the
DELAY pin, limiting the in-rush current. The soft-start time
depends on the value of VID DAC and C
effect from R

. Refer to the Application Information section

DLY

for detailed information on setting C

If either EN is taken low or VCC drops below UVLO, the
DELAY capacitor is reset to ground to be ready for another
soft-start cycle. Figure 8 shows the typical start-up waveforms
for the ADP3181.

, with a secondary

DLY

.

DLY

drops below 1.8 V. The current-limit latch-off delay time is thus
set by the RC time constant discharging from 3 V to 1.8 V. The
Application Information section discusses the selection of C
and R

DLY

.

DLY

Because the controller continues to cycle the phases during the
latch-off delay time, if the short is removed before the 1.8 V
threshold is reached, the controller returns to normal operation.
The recovery characteristic depends on the state of PWRGD. If
the output voltage is within the PWRGD window, the controller
resumes normal operation. However, if short circuit has caused
the output voltage to drop below the PWRGD threshold, a soft­start cycle is initiated.

The latch-off function can be reset either by removing and
reapplying VCC to the ADP3181, or by pulling the EN pin low
for a short time. To disable the short-circuit latch-off function,
the external resistor to ground should be left open, and a high
value (>1 MΩ) resistor should be connected from DELAY to
VCC. This prevents the delay capacitor from discharging so the

1.8 V threshold is never reached. The resistor has an impact on
the soft-start time because the current through it adds to the
internal 20 µA current source.

Figure 8. Typical S tart-up Waveforms

Channel 1: PWRGD, Channel 2: CSREF,

Channel 3: DELAY, Channel 4: COMP

CURRENT LIMIT, SHORT-CIRCUIT, AND LATCH­OFF PROTECTION

The ADP3181 compares a programmable current-limit setpoint
to the voltage from the output of the current sense amplifier.
The level of current limit is set with the resistor from the
ILIMIT pin to ground. During normal operation, the voltage on
ILIMIT is 3 V. The current through the external resistor is inter­nally scaled to give a current-limit threshold of 10.4 mV/µA. If
the difference in voltage between CSREF and CSCOMP rises
above the current-limit threshold, the internal current-limit
amplifier controls the internal COMP voltage to maintain the
average output current at the limit.

After the limit is reached, the 3 V pull-up on the DELAY pin is
disconnected, and the external delay capacitor is discharged
through the external resistor. A comparator monitors the
DELAY voltage and shuts off the controller when the voltage

Figure 9. Overcurrent Latch-off Waveforms

Channel 1: CSREF, Channel 2: DELAY,

Channel 3: COMP, Channel 4: Phase 1 Switch Node

During start-up when the output voltage is below 200 mV, a
secondary current limit is active because the voltage swing of
CSCOMP cannot go below ground. This secondary current
limit controls the internal COMP voltage to the PWM
comparators to 2 V. This limits the voltage drop across the low­side MOSFETs through the current balance circuitry.

There is also an inherent per phase current limit that protects
individual phases if one or more phases stops functioning
because of a faulty component. This limit is based on the
maximum normal mode COMP voltage.

Rev. 0 | Page 12 of 24

ADP3181

DYNAMIC VID

The ADP3181 incorporates the ability to dynamically change
the VID input while the controller is running. This allows the
output voltage to change while the supply is running and
supplying current to the load. This is commonly referred to as
VID on-the-fly (OTF). A VID OTF event can occur under
either light load or heavy load conditions. The processor signals
the controller by changing the VID inputs in multiple steps
from the start code to the finish code. This change can be either
positive or negative.

When a VID input changes state, the ADP3181 detects the
change and ignores the DAC inputs for a minimum of 400 ns.
This time is to prevent a false code due to logic skew while the
five VID inputs are changing. Additionally, the first VID change
initiates the PWRGD and CROWBAR blanking functions for a
minimum of 250 µs to prevent a false PWRGD or CROWBAR
event. Each VID change resets the internal timer.

POWER GOOD MONITORING

The power good comparator monitors the output voltage via
the CSREF pin. The PWRGD pin is an open-drain output
whose high level (when connected to a pull-up resistor)
indicates that the output voltage is within the nominal limits
specified based on the VID voltage setting. PWRGD goes low
if the output voltage is outside of this specified range, if all of
the VID DAC inputs are high, or whenever the EN pin is
pulled low. PWRGD is blanked during a VIDOTF event for a
period of 250 µs to prevent false signals during the time the
output is changing.

OUTPUT CROWBAR

As part of the protection for the load and output components of
the supply, the PWM outputs are driven low (turning on the
low-side MOSFETs) when the output voltage exceeds the upper
crowbar threshold. This crowbar action stops once the output
voltage falls below the release threshold of about 700 mV.

Turning on the low-side MOSFETs pulls down the output as the
reverse current builds up in the inductors. If the output
overvoltage is due to a short of the high-side MOSFET, this
action current-limits the input supply or blows its fuse,
protecting the microprocessor from destruction.

OUTPUT ENABLE AND UVLO

The input supply (VCC) to the controller must be higher than
the UVLO threshold and the EN pin must be higher than its
logic threshold for the ADP3181 to begin switching. IF UVLO is
less than the threshold or the EN pin is a logic low, the device is
disabled. This holds the PWM outputs at ground, shorts the
DELAY capacitor to ground, and holds the ILIMIT pin at
ground.

In the application circuit, the ILIMIT pin should be connected
to the OD pins of the ADP3418 drivers. Because ILIMIT is
grounded, this disables the drivers such that both DRVH and
DRVL are grounded. This feature is important to prevent dis­charging of the output capacitors when the controller is shut off.
If the driver outputs were not disabled, a negative voltage could
be generated on the output due to the high current discharge of
the output capacitors through the inductors.

The PWRGD circuitry also incorporates an initial turn-on delay
time based on the DELAY ramp. The PWRGD pin is held low
until the DELAY pin reaches 2.8 V. The time between when the
PWRGD undervoltage threshold is reached and when the
DELAY pin reaches 2.8 V provides the turn-on delay time. This
time is incorporated into the soft-start ramp. To ensure a 1 ms
delay time on PWRGD, the soft-start ramp must also be > 1 ms.
Refer to the Application Information section for detailed
information on setting C

DLY

.

Rev. 0 | Page 13 of 24

ADP3181

K

VIN RTN

V

12V

L1

IN

1.6µH

1N4148WS

470µF/16V× 6

NICHICON PW SERIES

+

C1 C6

D1

+

D2

1N4148WS

C7

4.7µF

D3

1N4148WS

C11

4.7µF

D4

1N4148WS

C15

4.7µF

1

2

3

4

1

2

3

4

1

2

3

4

ADP3418

BST
IN
OD
VCC

ADP3418

BST
IN
OD
VCC

ADP3418

BST
IN
OD
VCC

C9

4.7µF

C8

U2

100nF

8

DRVH

7

SW

6

PGND

5

DRVL

Q2

IPD06N03L

C12

U3

100nF

8

DRVH

7

SW

6

PGND

5

DRVL

Q5

IPD06N03L

C16

U4

100nF

8

DRVH

7

SW

6

PGND

5

DRVL

Q8

IPD06N03L

Q1

IPD12N03L

Q3

IPD06N03L

C13

4.7µF

Q4

IPD12N03L

Q6

IPD06N03L

C17

4.7µF

Q7

IPD12N03L

Q9

IPD06N03L

L2

600nH/1.6mΩ

C10

4.7nF

R1

2.2Ω

L3

600nH/1.6mΩ

C14

4.7nF

R2

2.2Ω

L4

600nH/1.6mΩ

C18

4.7nF
R3

2.2Ω

100kΩ, 5%

FUJITSU RE SERIES

RTH

820µF/2.5V

8mΩ ESR (EACH)

+

C21

×

8

C28

10µF × 23

MLCC

SOCKET

V

CC(CORE)

+

IN

0.8375V – 1.6V
65A AVG, 74A P

V

CC(CORE) RTN

POWER

GOOD

ENABLE

*FOR A DESCRIPTION OF
OPTIONAL R
SEE THE THEORY OF
OPERATION SECTION.

RESISTORS,

SW

C

DLY

12nF

C

B

1.5nF

R

B

1.33kΩ

R4

10Ω

R

DLY

330kΩ

C

390pF

+

C19

C20

1µF

33µF

R

A

16.9kΩ

249kΩ

R

383kΩ

FROM CPU

C

FB

33pF

R

A

R

T

10

11

12

13

14

1

VID4

2

VID3

3

VID2

4

VID1

5

VID0

6

CPUID

7

FBRTN

8

FB

9

COMP

PWRGD

EN

DELAY

RT

RAMPADJ

U1

ADP3181

Figure 10. Typical VR 10 Application Circuit

Rev. 0 | Page 14 of 24

VCC

PWM1

PWM2

PWM3

PWM4

SW1

SW2

SW3

SW4

GND

CSCOMP

CSSUM

CSREF

ILIMIT

28

27

26

25

24

23

22

21

20

19

18

17

C

2.2nF

16

15

R

CS1

SW2

*

C

1.5nF

CS2

R

SW1

*

R

SW3

*

R

CS1

35.7kΩ

R

LIM

200kΩ

R

CS2

73.2kΩ

R

PH3

124kΩ

R

PH2

124kΩ

R

PH1

124kΩ

04796-0-008

ADP3181

×

t

−

−××

(

)

×Ω×

APPLICATION INFORMATION

The design parameters for a typical ADP3181 CPU application
are as follows:

• Input voltage (V

• VID setting voltage (V

) = 12 V

IN

) = 1.500 V

VID

• Duty cycle (D) = 0.125

• Nominal output voltage at no load (V

• Nominal output voltage at 65 A load (V

• Static output voltage drop based on a 1.5 mΩ load line (R

) = 1.480 V

ONL

) = 1.3825 V

OFL

O

from no load to full load:

– V

V∆ = V

ONL

• Maximum output current (I

= 1.480 V – 1.3825 V = 97.5 mV

OFL

) = 65 A

O

• Number of phases (n) = 3

• Switching frequency per phase (f

) = 330 kHz

SW

SETTING THE CLOCK FREQUENCY

The ADP3181 uses a fixed-frequency control architecture. The
frequency is set by an external timing resistor (R

). The clock

T

frequency and the number of phases determine the switching
frequency per phase, which relates directly to switching losses
and the sizes of the inductors and input and output capacitors.
With n = 3 for three phases, a clock frequency of 990 kHz sets
the switching frequency, f

, of each phase to 330 kHz, which

SW

represents a practical trade-off between the switching losses and
the sizes of the output filter components. Figure 6 shows that to
achieve a 990 kHz oscillator frequency, the correct value for R

T

is 200 kΩ. For good initial accuracy and frequency stability, it is
recommended to use a 1% resistor.

SOFT-START AND CURRENT-LIMIT LATCH-OFF DELAY TIMES

Because the soft-start, PWRGD delay, and current-limit latch­off delay functions all share the DELAY pin, these three
parameters must be considered together. The first step is to set

for the PWRGD delay ramp. This ramp is generated with a

C

DLY

×

V8.22

has a second-

DLY

is kept

DLY

t

PWRGD

VV

−−

VID

PWRGD(UV)

DLY

can

UVPWRGD

(1)

is

20 µA internal current source. The value of R
order impact on the soft-start time because it sinks part of the
current source to ground. However, as long as R
greater than 200 kΩ, this effect is minor. The value for C
be approximated using

C

DLY

where t

⎛
⎜
⎜
⎝

PWRGD

V8.2

−µ=

A20

is the desired PWRGD delay time and V

VID

VV

×

R

DLY

⎞

)(

UVPWRGD

⎟
⎟
⎠

−−

the undervoltage threshold for the PWRGD comparator.

Assuming an R
time of 1 µs, C
calculated using

t

=

ss

Once C

DLY

)

current limit latch off time using:

R×=

DLY

If the result for R
time should be considered by recalculating the equation for
C

or a longer latch-off time should be used. In no case should

DLY,

R

be less than 200 kΩ. In this example, a delay time of 2 ms

DLY

gives R

= 333 kΩ. The closest standard 5% value is 330 kΩ.

DLY

Substituting 330 kΩ back into Equations 1 and 2 shows that the
PWRGD delay and soft-start times do not change significantly.

INDUCTOR SELECTION

The choice of inductance for the inductor determines the ripple
current in the inductor. Less inductance leads to more ripple
current, which increases the output ripple voltage and conduc­tion losses in the MOSFETs, but allows using smaller size
inductors and, for a specified peak-to-peak transient deviation,
less total output capacitance. Conversely, a higher inductance
means lower ripple current and reduced conduction losses, but
requires larger-size inductors and more output capacitance for
the same peak-to-peak transient deviation. In any multiphase
converter, a practical value for the peak-to-peak inductor ripple
current is less than 80% of the maximum dc current in the same
inductor. Equation 4 shows the relationship between the
inductance, oscillator frequency, and peak-to-peak ripple
current in the inductor. Equation 4 determines the minimum
inductance based on a given output ripple voltage:

I

=

RIPPLE

VID

L

≥

)(

Intel recommends that the ripple voltage should not exceed
10 mV peak-to-peak at the socket. Solving Equation 4 for a
12 mV peak-to-peak output ripple voltage at the regulator’s
output to allow for drops through the PCB traces yields

≥L

of 250 kΩ and a desired a PWRGD delay

DLY

is 12 nF. The soft-start delay time can then be

DLY

VC

VIDDLY

(2)

V

VID

−µ

A20

R

×

2

DLY

has been chosen, R

2

DELAY

C

(3)

DLY

is less than 200 kΩ, a smaller soft-start

DLY

DV

SW

)1(

(4)

Lf

×

Vf

×

RIPPLE

SW

VID

O

can be calculated for the

DLY

DnDRV

×−×

))(1()1(

(5)

375.01875.0m5.1V5.1

−×

mV12kHz330

×

=

(6)

nH310

Rev. 0 | Page 15 of 24

ADP3181

If the ripple voltage is less than that designed for, the inductor
can be made smaller until the ripple value is met. This allows
optimal transient response and minimum output decoupling.

The smallest possible inductor should be used to minimize the
number of output capacitors. A 300 nH inductor is a good
choice to start, and it gives a calculated ripple current of 13.3 A,
which is 61% of the full load current of 21.7 A. The inductor
should not saturate at the peak current of 29 A, and should be
able to handle the sum of the power dissipation caused by the
average current of 22 A in the winding and the core loss.

Another important factor in the inductor design is the DCR,
which is used for measuring the phase currents. A large DCR
causes excessive power losses, while too small a value leads to
increased measurement error. A good rule is to have the DCR
be about 1 to 1½ times the droop resistance (R

DESIGNING AN INDUCTOR

Once the inductance and DCR are known, the next step is to
design an inductor or find a standard inductor that comes as
close as possible to meeting the overall design goals. It is also
important to have the inductance and DCR tolerance specified
to keep the accuracy of the system controlled. Using 15% for the
inductance and 8% for the DCR (at room temperature) are
reasonable tolerances that most manufacturers can meet.

The first decision in designing the inductor is to choose the
core material. Several possibilities for providing low core loss
at high frequencies include the powder cores (Kool-Mµ® from
Magnetics, Inc. or Micrometals) and the gapped soft ferrite
cores (3F3 or 3F4 from Philips). Low frequency powdered
iron cores should be avoided due to their high core loss,
especially when the inductor value is relatively low and the
ripple current is high.

The best choice for a core geometry is a closed-loop types, such
as potentiometer cores, PQ, U, and E cores, or toroids. A good
compromise between price and performance are cores with a
toroidal shape. There are many useful references for quickly
designing a power inductor, such as

Magnetic Designer Software Intusoft

•

(http://www.intusoft.com)

•

Designing Magnetic Components for High Frequency

DC-DC Converters, McLyman, Kg Magnetics,
ISBN 1-883107-00-08

Selecting a Standard Inductor

The companies listed in Table 6 can provide design consultation
and deliver power inductors optimized for high power
applications upon request.

).

O

Table 6. Power Inductor Manufacturers

Company Contact Website

Coilcraft [phone] http://www.coilcraft.com
Coiltronics [phone] http://www.coiltronics.com

Sumida Electric

[phone] http://www.sumida.com

Company

Vishay [phone] http://www.vishay.com

OUTPUT DROOP RESISTANCE

The design requires that the regulator output voltage measured
at the CPU pins drops when the output current increases. The
specified voltage drop corresponds to a dc output resistance

).

(R

O

The output current is measured by summing together the
voltage across each inductor and then passing the signal
through a low-pass filter. This summer-filter is the CS amplifier
configured with resistors R
(filter). The output resistance of the regulator is set by these
equations, where R

R

R ×=

C×=

CS

O

R

CS

L

is the DCR of the output inductors:

L

R

(7)

L

XPH

)(

L

(8)

RR

CS

One has the flexibility of choosing either R
to start with R
solve for R

R

R

CS

R

R

CS

in the range of 100 kΩ to 200 kΩ, and then

PH(X)

by rearranging Equation 7. Using 100 kΩ for R

CS

O

×=

R

)(

L

XPH

Ωm5.1

mΩ6.1

Next, use equation 8 to solve for C

=

C

CS

nH300

×

The closest standard value for C
value is not a standard value, recalculate for the closest 1%
resistor values for R

. This can be quickly calculated by multiplying the

for C

CS

original values of R

to the actual value used. For best accuracy, CCS should be a

C

CS

and R

CS

and R

CS

5% or 10% NPO capacitor. For this example, the actual values
used for R

and R

CS

are 104.2 kΩ and 111.1 kΩ. The closest

PH(X)

standard 1% value for R
should not be rounded yet.

(summers) and RCS and CCS

PH(X)

or R

CS

PH(X).

Ωk8.93Ωk100

=×=

:

CS

nF0.2

=

Ωk8.93Ωm6.1

is 1.8 nF. If the calculated

CS

using the final value selected

PH(X)

by the ratio of the calculated

PH(X)

is 110 kΩ. RCS is used later and

PH(X)

It is best

PH(X)

:

Rev. 0 | Page 16 of 24

ADP3181

×

××=

+−×

=

−

−

INDUCTOR DCR TEMPERATURE CORRECTION

With the inductor’s DCR being used as the sense element,
and copper wire being the source of the DCR, one needs to
compensate for temperature changes of the inductor’s winding.
Fortunately, copper has a well known temperature coefficient
(TC) of 0.39%/°C.

is designed to have an opposite and equal percentage

If R

CS

change in resistance to that of the wire, it cancels the temper­ature variation of the inductor’s DCR. Due to the nonlinear
nature of NTC thermistors, Resistors R

CS1

and R
(see Figure 11) to linearize the NTC and produce the desired
temperature tracking.

PLACE AS CLOSE AS POSSIBLE
TO NEAREST INDUCTOR
OR LOW-SIDE MOSFET

R

TH

R

ADP3181

CSCOMP

18

CSSUM

17

CSREF

16

Figure 11. Temperature Compensation Circuit Values

C

CS

1.8nF

R

CS1

PH1

R

CS2

The following procedure yields values to use for R

(the thermistor value at 25°C) for a given RCS value.

R

TH

Select an NTC to be used based on type and value. Because

1.

there is not a value yet, start with a thermistor with a value
close to R

. The NTC should also have an initial tolerance

CS

of better than 5%.

2.

Based on the type of NTC, find its relative resistance value

at two temperatures. The temperatures that work well
are 50°C and 90°C. We call these resistance values A
(A is R

(50°C)/RTH(25°C)) and B (B is RTH(90°C)/RTH(25°C)).

TH

The NTC’s relative value is always 1 at 25°C.

are needed

CS2

TO

SWITCH

NODES

R

R

PH2

KEEP THIS PATH
AS SHORT AS POSSIBLE
AND WELL AWAY FROM
SWITCH NODE LINES

, R

CS1

PH3

CS2

SENSE

, and

R

=

TH

Calculate R
thermistor available. Also compute a scaling factor k based on
the ratio of the actual thermistor value used relative to the
computed one:

k = (10)

R

Calculate values for R

TO

V

OUT

For this example, R
previous section to be 104.2 kΩ, so a thermistor value of
100 kΩ is started with. In available 0603 size thermistors,
there is a Vishay NTHS0603N01N1003JR NTC thermistor
with A = 0.3602 and B = 0.09174. From these, r

= 0.7195 and rTH = 1.0751 can be computed. Solving for RTH

r

CS2

yields 112.05 kΩ, so when 100 kΩ is chosen, k = 0.8925. Finally,

and R

R

04796-0-009

CS1

the closest 1% resistor values yields a choice of 35.7 kΩ or

78.7 kΩ.

OUTPUT OFFSET

The Intel specification requires that, at no load, the nominal
output voltage of the regulator be offset to a lower value than
the nominal voltage corresponding to the VID code. The offset
is set by a constant current source flowing out of the FB pin

) and flowing through RB. The value of RB can be found

(I

FB

using Equation 12. The closest standard 1% resistor value is 1.33
kΩ.

= (12)

R

B

1

1

1

−

1

R

()

CS2

VID

rr

−

TH

CALCULATEDTH

CS1CS2

= rTH × RCS, then select the closest value of

ACTUALTH

()

and R

CS1

rkRR

(11)

CS1CSCS1

has already been calculated in the

CS

using the following:

CS2

))()1((

rkkRR ×

CS2CSCS2

= 0.3796,

CS1

are found to be 35.30 kΩ and 78.11 kΩ. Selecting

VV

ONL

I

FB

Find the relative value of R

3.

temperatures. This is based on the percentage change

required for each of these

CS

V480.1V5.1

=BR

μA15

=

Ωk33.1

needed, which can be 0.39%/°C initially. These values are

(r1 is 1/(1+ TC × (T1 − 25))) and

r

1

(r2 is 1/(1 + TC × (T2 − 25)))

r

2

where TC = 0.0039, T1 = 50°C, and T2 = 90°C.

4.

Compute the relative values for R

CS1

, R

, and RTH:

CS2

C

SELECTION

OUT

The required output decoupling for the regulator is typically
recommended by Intel for various processors and platforms.
One can also use some simple design guidelines to determine
what is required. These guidelines are based on having both

()

R

=

CS2

R

=

CS1

1

()

()

A

−

1

1

−

r

−

CS2

A

rr

−

1

()

() ( )

11

CS2

()

−×+×−×−××−

11

−−×−×−×−×

21

rABrBArrBA

1221

(9)

BArABrBA

Rev. 0 | Page 17 of 24

bulk and ceramic capacitors in the system.

ADP3181

The first thing is to select the total amount of ceramic capaci­tance. This is based on the number and type of capacitor to be
used. The best location for ceramics is inside the socket, with
12 to 18 of size 1206 being the physical limit. Others can be
placed along the outer edge of the socket as well.

The combined ceramic values of 200 µF to 300 µF are recom­mended, made of multiple 10 µF or 22 µF capacitors. Select the
number of ceramics and find the total ceramic capacitance (C

Next, there is an upper limit imposed on the total amount of
bulk capacitance (C
voltage stepping of the output (voltage step V
lower limit based on meeting the critical capacitance for load
release for a given maximum load step I

) when one considers the VID on-the-fly

X

in time tV), and a

V

:

MAX

Using ten 560 µF OSCONs with an ESR of 12 mΩ each yields

= 5.6 mF with an RX = 1.2 mΩ (making the new limits on C

C

X

X

2.4 mF to 8.8 mF, which is still within the acceptable range).

One last check should be made to ensure that the ESL of the
bulk capacitors (L

) is low enough to limit the initial high

X

frequency transient spike. This can be tested using

2

×≤

).

Z

X

L

X

In this example, L
which satisfies this limitation. If the L

RCL

O

Z

2

=Ω×≤

is 400 pH for the ten OSCSON capacitors,

X

(15)

pH893m3.1μF230

of the chosen bulk

X

capacitor bank is too large, the number of MLC capacitors must
be increased.

C

C

≥

MINX

)(

≤

()

MAXX

L

22

RnK

O

⎛

×

IL

VID

STEP

××

VRn

VID

O

⎛
⎜

V

⎜
⎜
⎝

⎞

⎛

V

ERR

⎟

⎜

nK 1where

(14)

⎟

⎜

V

V

⎠

⎝

⎜
⎜
⎝

V

V

=

⎞
⎟

−

C

(13)

Z

⎟
⎠

Note that for this multimode control technique, all ceramic
designs can be used as long as the conditions of Equations 11,
12, and 13 are satisfied.

POWER MOSFETS

2

⎛
⎜

t

v

⎜
⎝

nKR

V

VID

V

V

O

×+×× 11

L

⎞

⎞

⎟
⎟
⎟

⎠

−

C

⎟

⎟

⎠

Z

−

For this example, the N-channel power MOSFETs have been
selected for one high-side switch and two low-side switches per
phase. The main selection parameters for the power MOSFETs
are V
voltage (the supply voltage to the ADP3418) dictates whether
standard threshold or logic-level threshold MOSFETs must
be used. With V

where R
transient specification, R
If the C
VID on-the-fly specification and may require the use of a
smaller inductor or more phases (and may have to increase the
switching frequency to keep the output ripple the same).

is the ESR of the bulk capacitor bank. To meet the

X

cannot be greater than 3 times RO.

X

is larger than C

X(MIN)

, the system does not meet the

X(MAX)

(V

The maximum output current, I
requirement for the low-side (synchronous) MOSFETs. In the
ADP3181, currents are balanced between phases, so the current
in each low-side MOSFET is the output current divided by the
total number of MOSFETs (n

In this example, there are twelve 22 µF 1206 MLC capacitors
(CZ = 264 µF). The VID-on-the-fly step change is 12.5 mV in
5 µs. Solving for the bulk capacitance, assuming that R

= RO,

X

dominant, the following expression shows the total power being
dissipated in each synchronous MOSFET in terms of the ripple
current per phase (I

and where k = 4.6, yields

⎛
⎜

C

C

⎛
⎜

⎜
⎜

⎝
=

≥

()

MINX

⎜
⎝

≤

()

MAXX

⎛
⎜

1

+

⎜
⎝

mF9.23

×

A60nH600

−

×Ω×

V5.1m3.13

mV250nH600

×

22

×Ω××

××××

nH320mV450

×

⎞
⎟

=
⎟
⎠

mF92.5μF230

Knowing the maximum output current being designed for and

×

V5.1m3.16.43

2

⎞

⎞

Ωm31.4.63V51.μs150

⎟

⎟

−

⎟

⎟

⎟

⎠

⎠

F2301

µ−

the maximum allowed power dissipation, one can find the
required R
an ambient temperature of 50°C, a safe limit for P
(assuming 2 D-paks) at 120°C junction temperature. Here, for
example (65 A maximum), R
This R
this must be accounted for this when making this selection.

, QG , C

GS(TH)

< 2.5 V) are recommended.

GS(TH)

1 (16)

()

SF

DS(ON)

is also at a junction temperature of about 120°C, so

DS(SF)

, C

, and R

ISS

RSS

~10 V, logic-level threshold MOSFETs

GATE

) and average total output current (IO).

R

⎡

⎛

⎞

I

O

⎜

⎟

⎢

×−=

DP ×

⎜

⎟

n

⎢

SF

⎝

⎠

⎣

. The minimum gate drive

DS(ON)

determines the R

O,

). With conduction losses being

SF

22

⎤

⎞

×

In

R

⎟

⎥

R

()

⎟

n

SF

⎠

SFDS

⎥
⎦

12

⎛

1

⎜

×+

⎜
⎝

for the MOSFET. For D-PAK MOSFETs up to

is 1 W

SF

(per MOSFET) < 8.7 mW.

DS(SF)

DS(ON)

Rev. 0 | Page 18 of 24

ADP3181

M

×

(

×−×

Another important factor for the synchronous MOSFET is
the input capacitance and feedback capacitance. The ratio
of the feedback to input needs to be small (less than 10%
is recommended) to prevent accidental turn-on of the
synchronous MOSFETs when the switch node goes high.

Also, the time to switch the synchronous MOSFETs off should
not exceed the non-overlap dead time of the MOSFET driver
(40 ns typical for the ADP3418). The output impedance of
the driver is about 2 Ω, and the typical MOSFET input gate
resistances are about 1 Ω – 2 Ω, so a total gate capacitance
of less than 6000 pF should be adhered to. Because there
are two MOSFETs in parallel, the input capacitance for each
synchronous MOSFET should be limited to 3000 pF.

The high-side (main) MOSFET has to be able to handle two
main power dissipation components: conduction and switching
losses. The switching loss is related to the amount of time it
takes for the main MOSFET to turn on and off, and to the
current and voltage that are being switched. Basing the switch­ing speed on the rise and fall time of the gate driver impedance
and MOSFET input capacitance, the following expression
provides an approximate value for the switching loss per main
MOSFET, where n

()

MFS

Here, R

is the total gate resistance (2 Ω for the ADP3418

G

is the total number of main MOSFETs:

MF

IV

×

fP ×××

××= 2 (17)

SW

OCC

n

F

n

MF

R

G

C

ISS

n

and about 1 Ω for typical high speed switching MOSFETs,
making R

= 3 Ω), and C

G

is the input capacitance of the

ISS

main MOSFET. It is interesting to note that adding more main
MOSFETs (n

) does not really help the switching loss per

MF

MOSFET because the additional gate capacitance slows down
switching. The best thing to reduce switching loss is to use
lower gate capacitance devices.

The conduction loss of the main MOSFET is given by the
following, where R

×=

DP ×

() ()

MFC

is the on resistance of the MOSFET:

DS(MF)

22

⎡

⎛

⎞

I

O

⎜

⎟

⎢

⎜

⎟

n

⎢

MF

⎝

⎠

⎣

12

⎛

1

⎜

×+

⎜
⎝

⎤

⎞

×

In

R

⎟

⎥

⎟

n

⎥

MF

⎠

⎦

R

(18)

MFDS

Typically, for main MOSFETs, one wants the highest speed
(low C

) device, but these usually have higher on resistance.

ISS

One must select a device that meets the total power dissipation
(about 1.5 W for a single D-PAK) when combining the
switching and conduction losses.

For this example, an Infineon IPD12N03L was selected as the
main MOSFET (three total; n
(max) and R

= 14 mΩ (max at TJ = 120ºC), and an

DS(MF)

= 3), with a C

MF

= 1460 pF

ISS

Infineon IPD06N03L as the synchronous MOSFET (six total;
n

= 6), with C

SF

(max at T

= 2370 pF (max) and R

ISS

= 120ºC). The synchronous MOSFET C

J

= 8.3 mΩ

DS(SF)

is less than

ISS

3000 pF, satisfying that requirement. Solving for the power
dissipation per MOSFET at I

= 65 A and IR = 13 A yields 900

O

mW for each synchronous MOSFET and 1.6 W for each main
MOSFET. These numbers work well considering that there is
usually more PCB area available for each main MOSFET versus
each synchronous MOSFET.

One last thing to consider is the power dissipation in the driver
for each phase. This is best described in terms of the Q
MOSFETs and is given by the following, where Q
gate charge for each main MOSFET and Q

is the total gate

GSF

G

is the total

GMF

for the

charge for each synchronous MOSFET:

⎡

f

SW

P ×

=

⎢

DRV

⎢

⎣

()

MF

n

2

×

Also shown is the standby dissipation factor (I

⎤

+×+××

VIQnQn

⎥
⎥

⎦

× VCC) for the

CC

(19)

CCCCGSFSFGMF

driver. For the ADP3418, the maximum dissipation should be
less than 400 mW. For example, with I
nC and Q

= 34.3 nC, 260 mW is found in each driver, which

GSF

= 7 mA, Q

CC

GMF

= 22.8

is below the 400 mW dissipation limit.

RAMP RESISTOR SELECTION

The ramp resistor (RR) is used for setting the size of the internal
PWM ramp. The value of this resistor is chosen to provide the
best combination of thermal balance, stability, and transient
response. The following expression is used for determining the
optimum value:

LA

R

=

R

R

=

R

where A
balancing amplifier gain, R
resistance, and C
closest standard 1% resistor value is 226 kΩ.

The internal ramp voltage magnitude can be calculated using

V

=

R

=

V

R

The size of the internal ramp can be made larger or smaller. If it
is made larger, stability and transient response improve, but
thermal balance degrades. Likewise, if the ramp is made smaller,
thermal balance improves at the sacrifice of transient response
and stability. The factor of 3 in the denominator of Equation 20
sets a ramp size that gives an optimal balance for good stability,
transient response, and thermal balance.

R

3

D

CRA

×××

R

DS

(20)

nH0600.2

×

pF5Ωm2.453

×××

is the internal ramp amplifier gain, AD is the current

R

is the total low-side MOSFET on

DS

is the internal ramp capacitor value. The

R

VDA

)

1

VIDR

××

fCR

RR

SW

kΩ813

=

(21)

()

V51.1250.10.2

×−×

××

=

kHz267pF5Ωk833

Vm51.0

Rev. 0 | Page 19 of 24

ADP3181

(

)

×

(

)

×−×

−

(

)

(

)

=

×

CURRENT LIMIT SETPOINT

To select the current limit setpoint, it is necessary to find the
resistor value for R
ADP3181 is set with a 3 V source (V
of 10 mV/µA (A

=

R

LIM

where I

LIM

is the average current limit for the output of the

LIM

supply. For example, using 90 A for I
which 221 kΩ can be chosen as the nearest 1% value.

The per phase current limit described earlier has its limit
determined by the following:

≅ (23)

I +

PHLIM

. The current limit threshold for the

LIM

) across R

LIM

). R

LIM

×

×

can be found using the following:

LIM

VA

LIMLIM

(22)

RI

O

, R

LIM

LIM

−−

()

MAXCOMP

×

RA

D

()

VVV

R

MAXDS

BIAS

I

R

2

with a gain

LIM

is 222.2 kΩ and for

FEEDBACK LOOP COMPENSATION DESIGN

Optimized compensation of the ADP3181 allows the best
possible response of the regulator’s output to a load change. The
basis for determining the optimum compensation is to make
the regulator and output decoupling appear as an output
impedance that is entirely resistive over the widest possible
frequency range, including dc, and equal to the droop resistance
(R

). With the resistive output impedance, the output voltage

O

droops in proportion to the load current at any load current
slew rate; this ensures optimal positioning and allows the
minimization of the output decoupling.

With the multimode feedback structure of the ADP3181, one
needs to set the feedback compensation to make the converter’s
output impedance working in parallel with the output
decoupling meet this goal. Several poles and zeros created by
the output inductor and decoupling capacitors (output filter)
need to be compensated for.

where the maximum COMP voltage (V
the COMP pin bias voltage (V
balancing amplifier gain (A
R

of 5.3 mΩ (low-side on resistance at 150°C), there

DS(MAX)

BIAS

) is 5. Using VR of 0.7 V, and

D

COMP(MAX)

) is 1.2 V, and the current

) is 3.3 V,

is a per-phase limit of 52 A.

This limit can be adjusted by changing the ramp voltage V

, but

R

make sure not to set the per-phase limit lower than the average
per-phase current (I

E

R

E

A

O

()

X

O

D

RRCT

LIM/n

'

).

VR

×

L

RARnR

+×+×=

DS

L

X

R

O

RT

+

V

VID

Ωm2.45Ωm31.3 =

+×+×=

−

RR

'

O

×+−×=

R

X

12

X

V630.Ωm61.

×

+

V51.

()

VDnL

×−××

×××

VRCn

VID

O

×

A type-three compensator on the voltage feedback is adequate
for proper compensation of the output filter. The following
equations are intended to yield an optimal starting point for the
design; some minor adjustments may be necessary to account
for PCB and component parasitic effects.

Using equations 24 to 28, the first step is to compute the time
constants for all of the poles and zeros in the system, where, for
the ADP3181, R is the PCB resistance from the bulk capacitors
to the ceramics and where R

is approximately the total low-

DS

side MOSFET on resistance per phase at 25°C. For this example,

A

is 5, VR equals 1 V, R´ is approximately 0.6 mΩ (assuming a

D

4-layer motherboard) and L

is 400 pH for the 10 OSCSON

X

capacitors.

RT

(24)

V630.3750.1nH6002

×××

V51.Ωm31.mF56.63

pH753

Ωm60.Ωm31.mF56.6

×+−×=

Ωm31.

Ωm9.37

Ωm0.6Ωm31.

=

Ωm01.

(25)

μs79.4

CRRRT (26)

XB

⎛
⎜

LV

RT

⎜

=

T (27)

C

=

T (28)

D

⎝

X

()

X

O

X

O

⎞

×

RA

D

DS

−×

2

×

RV

Z

'

⎟
⎟

×

f

SW

⎠

=

EVID

××

RCC

O

=

×+−×

RCRRC

O

Z

−+=×−+=

⎛
⎜

nH600V630.

⎜
⎝

−×
×

×

Ωm2.45

×

kHz2672

Ωm9.37V51.

()

Rev. 0 | Page 20 of 24

ns97.1mF56.6Ωm31.Ωm60.Ωm0.1'

⎞
⎟
⎟
⎠

=

μs2.6

22

m3.1μF230mF56.6

Ω××

Ωm31.μF230Ωm60.Ωm31.mF56.6

×+−×

ns521

=

ADP3181

The compensation values can be solved using the following:

××

TRn

=

C

A

AO

×

RR

BE

(29)

××

=

C

A

T

C

R

A

C

A

T

B

C

B

R

B

T

C

FB

R

×

==

D

A

μs79.4Ωm31.3

=

Ωk331.Ωm79.3

μs2.6

===

pF713

s97.1

µ

=

Ωk331.

ns521

===

Ωk.761

pF371

Ωk.761

(30)

nF48.1

(31)

pF2.31

(32)

Choosing the closest standard values for these components
yields C

= 820 pF, RA = 7.87 kΩ, CB = 1.2 nF, and CFB = 100 pF.

A

These make a good starting point.

Using the design spreadsheet yields more optimal compen­sation values; from the spreadsheet, C

= 1.2 nF, and CFB = 68 pF.

C

B

= 680 pF, RA = 5.49 kΩ,

A

CIN SELECTION AND INPUT CURRENT di/dt REDUCTION

In continuous inductor-current mode, the source current of the
high-side MOSFET is approximately a square wave with a duty
ratio equal to n × V
maximum output current. To prevent large voltage transients, a
low ESR input capacitor sized for the maximum rms current
must be used. The maximum rms capacitor current is given by

××=

IDI

OCRMS

I

CRMS

Note that the capacitor manufacturer’s ripple current ratings are
often based on only 2000 hours of life. This makes it advisable
to further derate the capacitor, or to choose a capacitor rated at
a higher temperature than required. Several capacitors may be
placed in parallel to meet size or height requirements in the
design. In this example, the input capacitor bank is formed by
three 2200 µF, 16 V Nichicon capacitors with a ripple current
rating of 3.5 A each.

and an amplitude of one-nth of the

OUT/VIN

1

×

DN

A65125.0

1

××=

×

=−

1250.3

(33)

A5.101

To reduce the input-current di/dt to below the recommended
maximum of 0.1 A/µs, note that an additional small inductor
(L > 1 µH @ 15 A) should be inserted between the converter
and the supply bus. This inductor also acts as a filter between
the converter and the primary power source.

Rev. 0 | Page 21 of 24

ADP3181

BUILDING A SWITCHABLE VR9/VR10 DESIGN

Some designs may require the ability to work with either a VR9­or a VR10-based CPU, because both processors are available in
the same package/pin count. To accomplish this, the voltage
regulator must detect which processor is present and set the
VID DAC and load line accordingly. This can accomplished
using the BOOTSELECT output from the CPU. Figure 12
shows how this signal is used to modify the load line and
set the CPUID pin of the ADP3181 appropriately.

To determine the values of x and y, start with the two load lines;
R

(smaller slope) and ROH (larger slope). First, follow the

OL

standard design procedure, which gives the values for R
and C

for ROL. Tune RPH and CCS. Next, compute the values for

CS

R

and C

CS3

R ×

CS3

C

CS3

where R

using the following:

CS3

⎛
⎜
⎜
⎝

⎛
⎜
⎜
⎝

is 1.5 mΩ and ROH is 3 mΩ.

OL

⎞

R

OH

⎟

−= 1 (34)

R

CS

⎟

R

OL

⎠

C

CS

(35)

⎞

R

OH

⎟

−=1
⎟

R

OL

⎠

CS1

, R

CS2

,

R

TH

100kΩ, 5%

23

SW1

22

SW2

21

SW3

R

51Ω

PH3

124kΩ

R

CS3

C

CS3

100nF

BOOTSELECT

ADP3181

2.7kΩ

10kΩ

10kΩ

2N3904

SW4

GND

CSCOMP

CSSUM

CSREF

ILIMIT

100nF

10kΩ

20

19

18

17

16

15

5VSB

C

1.5nF

C

CS1

2.2nF

2N3905

CS2

100nF

R

CS1

35.7kΩ

R

CS2

73.2kΩ

BSS84

2N7001

Figure 12. Connections to Allow Automatic Switching between VR9 and VR10 Operation

TO

PHASE INDUCTORS

R

PH1

124kΩ

R

PH2

124kΩ

CPU NWD HI

CPU PSC HI

TO APD3181
CPUID (PIN 6)

04796-0-010

Rev. 0 | Page 22 of 24

ADP3181

LAYOUT AND COMPONENT PLACEMENT

The following guidelines are recommended for optimal
performance of a switching regulator in a PC system.

GENERAL RECOMMENDATIONS

For good results, at least a 4-layer PCB is recommended.
This should allow the needed versatility for control circuitry
interconnections with optimal placement, power planes for
ground, input and output power, and wide interconnection
traces in the rest of the power delivery current paths. Keep in
mind that each square unit of 1 ounce copper trace has a
resistance of ~0.53 mW at room temperature.

Whenever high currents must be routed between PCB layers,
use vias liberally to create several parallel current paths so that
the resistance and inductance introduced by these current paths
is minimized and the via current rating is not exceeded.

If critical signal lines (including the output voltage sense lines
of the ADP3181) must cross through the power circuitry, it is
best if a signal ground plane is interposed between those signal
lines and the traces of the power circuitry. This serves as a
shield to minimize noise injection into the signals at the
expense of making the signal ground a bit noisier.

An analog ground plane should be used around and under the
ADP3181 for referencing the components associated with the
controller. This plane should be tied to the nearest output de­coupling capacitor ground and should not be tied to any other
power circuitry to prevent power currents from flowing in it.

The components around the ADP3181 should be located close
to the controller with short traces. The most important traces to
keep short and away from other traces are the FB and CSSUM
pins.

The output capacitors should be connected as closely as possible
to the load (or connector) that receives the power (for example,
a microprocessor core). If the load is distributed, the capacitors
should also be distributed, and generally in proportion to where
the load tends to be more dynamic.

Avoid crossing any signal lines over the switching power path
loop as described next.

Power Circuitry

The switching power path should be routed on the PCB to
encompass the shortest possible length to minimize radiated
switching noise energy (EMI) and conduction losses in the
board. Failure to take proper precautions often results in EMI
problems for the entire PC system as well as noise-related
operational problems in the power converter control circuitry.
The switching power path is the loop formed by the current
path through the input capacitors and the power MOSFETs
including all interconnecting PCB traces and planes. The use of
short and wide interconnection traces is especially critical in
this path because it minimizes the inductance in the switching
loop, which can cause high energy ringing, and because it
accommodates the high current demand with minimal
voltage loss.

Whenever a power-dissipating component (for example, a
power MOSFET) is soldered to a PCB, the liberal use of vias,
both directly on the mounting pad and immediately sur­rounding it, is recommended. Two important reasons for this
are improved current rating through the vias, and improved
thermal perform-ance from vias extended to the opposite side
of the PCB where a plane can more readily transfer the heat to
the air. Make a mirror image of any pad being used to heat sink
the MOSFETs on the opposite side of the PCB to achieve the
best thermal dissipation to the air around the board. To further
improve thermal performance, use the largest possible pad area.

The output power path should also be routed to encompass a
short distance. The output power path is formed by the current
path through the inductor, the output capacitors, and the load.

For best EMI containment, a solid power ground plane should
be used as one of the inner layers extending fully under all the
power components.

Signal Circuitry

The output voltage is sensed and regulated between the FB pin
and the FBRTN pin (which connects to the signal ground at the
load). To avoid differential mode noise pickup in the sensed
signal, the loop area should be small. Thus the FB and FBRTN
traces should be routed adjacent to each other atop the power
ground plane back to the controller.

Connect the feedback traces from the switch nodes as close as
possible to the inductor. The CSREF signal should be connected
to the output voltage at the nearest inductor to the controller.

Rev. 0 | Page 23 of 24

ADP3181

OUTLINE DIMENSIONS

9.80

9.70

9.60

28

PIN 1

0.15

0.05

COPLANARITY

0.10

0.65

BSC

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153AE

1.20 MAX

SEATING

PLANE

15

4.50

4.40

4.30

0.20

0.09

6.40 BSC

8°
0°

0.75

0.60

0.45

141

Figure 13. 28-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-28)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option Quantity per Reel

ADP3181JRUZ-REEL1 0°C to +85°C Thin Shrink SO—13” Reel RU-28 2500

1

Z = PB-free part.

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

D04796-0-5/04(0)

Rev. 0 | Page 24 of 24