Datasheet ADP3166 Datasheet (Analog Devices)

5-Bit Programmable 2-, 3-, 4-Phase

Synchronous Buck Controller

FEATURES
Selectable 2-, 3- or 4-Phase Operation at up to

1 MHz per Phase

Differential Sensing Error ±1% over Temperature
Logic-Level PWM Outputs for Interface to

External High Power Drivers
Active Current Balancing between All Output Phases
Built-in Power Good Blanking Supports On-the-Fly

VID Code Changes
5-Bit Digitally Programmable 0.8 V to 1.55 V Output
Short-Circuit Protection with Programmable

Latch-Off Delay
Overvoltage Protection Crowbar Logic Output

APPLICATIONS
Desktop PC Power Supplies

Next-Generation AMD Processors

VRM Modules

GENERAL DESCRIPTION

The ADP3166 is a highly efficient, multiphase, synchronous
buck switching regulator controller optimized for converting a
12 V main supply into the core supply voltage required by high
performance AMD processors. It uses an internal 5-bit DAC to
read a

voltage identification (VID) code directly from the pro­cessor, which is used to set the output voltage between 0.8 V
and 1.55 V. The ADP3166 also uses a multimode PWM
archi

tecture to drive the logic-level outputs at a programmable
switching frequency that can be optimized for VRM size and
efficiency. The phase relationship of the output signals can be
programmed to provide 2-, 3-, or 4-phase operation, allowing
for the construction of up to four complementary buck switch­ing stages.

The ADP3166 includes programmable no-load offset and slope
functions to adjust the output voltage as a function of the load
current so that it is always optimally positioned for a system
transient. The ADP3166 also provides accurate and reliable
short-circuit protection, adjustable current limiting, and a delayed
power good output that accommodates on-the-fly output volt­age changes requested by the CPU.

ADP3166 is specified over the commercial temperature range of
0°C to 85°C and is available in a 28-lead TSSOP package.

GND

CROWBAR

PWRGD

ILIMIT

DELAY

COMP

EN

ADP3166

FUNCTIONAL BLOCK DIAGRAM

ADP3166

11

19

6

CSREF

DAC + 300mV

CSREF

DAC – 300mV

10

15

EN

12

9

VCC

28

UVLO

SHUTDOWN

AND BIAS

+
–

2.1V

+

–

+

–

DELAY

SOFT

START

PRECISION

REFERENCE

7 1 2 3 4 5

VID4 VID3 VID2 VID1 VID0FBRTN

RTRAMPADJ

14

13

OSCILLATOR

CURRENT

BALANCING

CIRCUIT

CURRENT

CIRCUIT

VID

DAC

LIMIT

+

CMP

–

+

CMP

–

+

CMP

–

+

CMP

–

CROWBAR

–

+

+
–

ENSET

RESET

RESET
2-, 3- , 4-PHASE

DRIVER LOGIC
RESET

RESET

CURRENT
LIMIT

–
+

27

26

25

24

23

22

21

20

17

16

18

8

*

PWM1

PWM2

PWM3

PWM4

SW1

SW2

SW3

SW4

CSSUM

CSREF

CSCOMP

FB

*Patent pending

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

ADP3166–SPECIFICATIONS

Parameter Symbol Conditions Min Typ Max Unit

ERROR AMPLIFIER

Accuracy V

0.8 V Output

1.175 V Output

1.55 V Output

Line Regulation ∆V
Input Bias Current I
FBRTN Current I
Output Current I
Gain Bandwidth Product GBW
Slew Rate C

VID INPUTS

Input Low Voltage V
Input High Voltage V
Input Current I
Pull-Up Resistance R
Internal Pull-Up Voltage 2.0 2.4 2.65 V
VID Transition Delay Time
No CPU Detection Turn-Off VID code change to 11111 to 400 ns

Delay Time

OSCILLATOR

Frequency Range

2

2

2

Frequency Variation f

Output Voltage V
Timing Resistor Value 500 kΩ
RAMPADJ Voltage V
RAMPADJ Input Current Range I

CURRENT SENSE AMPLIFIER

Offset Voltage V
Input Bias Current I
Gain Bandwidth Product GBW
Slew Rate C
Input Common-Mode Range CSSUM and CSREF 0 3 V
Positioning Accuracy ∆V
Output Voltage Range I
Output Current I

CURRENT BALANCE CIRCUIT

Common-Mode Range V
Input Resistance R
Input Current I
Input Current Matching ∆I

CURRENT LIMIT COMPARATOR

Output Voltage

Normal Mode V
In Shutdown V

Output Current, Normal Mode I
Maximum Output Current EN > 2 V 60 µA
Current Limit Threshold Voltage V
Current Limit Setting Ratio V
Latch-Off Delay Threshold V
Latch-Off Delay Time t

FB

FB

FB

FBRTN

O(ERR)

(ERR)

IL(VID)

IH(VID)

VID

VID

f

OSC

PHASE

RT

RAMPADJ

RAMPADJ

OS(CSA)

BIAS(CSA)

CSA

FB

CSCOMP

SW(X)CM

SW(X)

SW(X)

SW(X)

ILIMIT(NM)

ILIMIT(SD)

ILIMIT(NM)

CL

SET(DLY)

SET(DLY)

(VCC = 12 V, FBRTN = GND, TA = 0ⴗC to 85ⴗC, unless otherwise noted.)

Referenced to FBRTN, CSSUM = CSCOMP,

0.792 0.800 0.808 V
See Test Circuit 1
Referenced to FBRTN, CSSUM = CSCOMP,

1.163 1.175 1.187 V
See Test Circuit 1
Referenced to FBRTN, CSSUM = CSCOMP,

1.535 1.55 1.566 V
See Test Circuit 1
VCC = 10 V to 14 V 0.05 %

–13 –15.5 –17 µA

100 200 µA

FB forced to V

– 3% 500 µA

OUT

COMP = FB 20 MHz

= 10 pF 50 V/µs

COMP

0.8 V

2V

VID(X) = 0 V 20 26 µA

100 120 kΩ

VID code change to FB change 400 ns

PWM going low

0.25 4 MHz
TA = 25°C, RT = 250 kΩ, 4-phase 160 200 240 kHz
T

= 25°C, RT = 115 kΩ, 4-phase

A

= 25°C, RT = 75 kΩ, 4-phase

T

A

2

2

400 kHz
600 kHz

RT = 100 kΩ to GND 1.9 2.0 2.1 V

RAMPADJ – FB –50 +50 mV

050µA

CSSUM – CSREF, see Test Circuit 2 –3 +3 mV

20 100 nA
20 MHz

= 10 pF 50 V/µs

CSCOMP

See Test Circuit 3 –76 –80 –84 mV

= ±100 µA 0.05 3.3 V

CSCOMP

500 µA

–600 +200 mV

SW(X) = 0 V 24 30 36 kΩ
SW(X) = 0 V 5 7 9 µA
SW(X) = 0 V –5 +5 %

EN > 2 V 2.9 3 3.1 V
EN < 0.8 V, I
EN > 2 V, R

V

– V

CSREF

CL/IILIMIT

CSCOMP

= –100 µA 400 mV

ILIMIT

= 250 kΩ 12 µA

ILIMIT

, R

= 250 kΩ 105 125 145 mV

ILIMIT

10.4 mV/µA

In current limit 1.7 1.8 1.9 V
R

= 250 kΩ, C

DELAY

= 4.7 nF 600 µs

DELAY

1

REV. 0–2–

ADP3166

Parameter Symbol Conditions Min Typ Max Unit

SOFT START

Output Current, Soft Start Mode I
Soft Start Delay Time t

DELAY(SS)

DELAY(SS)

ENABLE INPUT

Input Low Voltage V
Input High Voltage V

IL(EN)

IH(EN)

Input Current –1 +1 µA

POWER GOOD COMPARATOR

Undervoltage Threshold V
Overvoltage Threshold V
Output Low Voltage V

PWRGD(UV)

PWRGD(OV)

OL(PWRGD)IPWRGD(SINK)

Off-State Leakage Current V
Delay Time

VID Code Changing 100 250 µs
VID Code Static 400 ns

CROWBAR COMPARATOR

Crowbar Trip Point V

CROWBAR

Crowbar Reset Point 300 400 500 mV
Crowbar Response Time t

CROWBAR

Overvoltage to PWM Low 400 ns

Overvoltage to CRWBR High 400 ns
Output Voltage Low V
Output Voltage High V

OL(CROWBAR)ICROWBAR(SINK)

OH(CROWBAR)ICROWBAR(SOURCE)

PWM OUTPUTS

Output Voltage Low V
Output Voltage High V

OL(PWM)

OH(PWM)

SUPPLY

DC Supply Current I
UVLO Threshold Voltage V

CC

UVLO

UVLO Hysteresis 0.7 0.9 1.1 V

During start-up, DELAY < 2.8 V 15 20 25 µA
R

= 250 kΩ, C

DELAY

= 4.7 nF 350 µs

DELAY

VID Code = 01111

0.8 V

2V

Relative to nominal DAC output –200 –300 –400 mV
Relative to nominal DAC output 200 300 400 mV

= 4 mA 150 400 mV

CSREF

= V

DAC

50 µA

2.0 2.1 2.2 V

= 100 µA 100 500 mV

= 100 µA 4.0 5.0 V

I

PWM(SINK)

I

PWM(SOURCE)

= 400 µA 160 500 mV

= 400 µA 4.0 5.0 V

710 mA

VCC rising 6.5 6.9 7.3 V

NOTES

1

All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).

2

Guaranteed by design, not tested in production.

Specifications subject to change without notice.

REV. 0

–3–

ADP3166

ABSOLUTE MAXIMUM RATINGS*

VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +15 V

FBRTN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

VID0 to VID4, EN, DELAY, ILIMIT, CSCOMP, RT, COMP,

CROWBAR, PWM1 to PWM4 . . . . . . . . . –0.3 V to +5.5 V

SW1 to SW4 . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V to +25 V

All Other Inputs and Outputs . . . . . . .–0.3 V to VCC + 0.3 V

Operating Ambient Temperature Range . . . . . . . 0°C to 85°C

Operating Junction Temperature . . . . . . . . . . . . . . . . . . 125°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100°C/W

␪

JA

ORDERING GUIDE

Temperature Package Quantity

Model Range Options per Reel

ADP3166JRU-REEL7 0°C to 85°C RU-28 (TSSOP-28) 1000
ADP3166JRU-REEL 0°C to 85°C RU-28 (TSSOP-28) 2500

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only. Functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Absolute maximum
ratings apply individually only, not in combination. Unless otherwise specified, all
other voltages are referenced to GND.

5.3
TA = 25ⴗC
4-PHASE OPERATION

5.2

5.1

5.0

4.9

4.8

SUPPLY CURRENT – mA

4.7

4.6

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

MASTER CLOCK FREQUENCY – MHz

TPC 1. Supply Current vs. Master Clock Frequency

4

3

2

1

MASTER CLOCK FREQUENCY – MHz

0

050100 150 200 250 300

RT VALUE – kΩ

TPC 2. Master Clock Frequency vs. R

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADP3166 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

T

REV. 0–4–

ADP3166

ADP3166

VCC

PWM1

PWM2

PWM3

PWM4

SW1

SW2

SW3

SW4

GND

CSCOMP

CSSUM

CSREF

ILIMIT

28

27

26

25

24

23

22

21

20

19

18

17

16

15

250k⍀

+

1␮F

20k⍀

12V

100nF

100nF

5-BIT CODE

4.7nF

1.25V

1k⍀

250k⍀

1

VID4

2

VID3

3

VID2

4

VID1

5

VID0

6

CROWBAR

7

FBRTN

8

FB

9

COMP

10

PWRGD

11

EN

12

DELAY

13

RT

14

RAMPADJ

Test Circuit 1. Closed-Loop Output Voltage Accuracy

ADP3166

VCC

200k⍀

28

FB

8

COMP

9

CSCOMP

18

CSSUM

17

CSREF

16

GND

19

–

+

⌬VFB = FB – V

VID

200k⍀

80mV

1V

12V

10k⍀

+
–

+
–

Test Circuit 3. Positioning Voltage Test Circuit

ADP3166

VCC

100nF

28

CSCOMP

18

CSSUM

17

CSREF

16

GND

19

–

+

VOS =

CSCOMP – 1V

40

12V

39k⍀

1k⍀

1V

+
–

Test Circuit 2. Positioning Amplifier VOS Test Circuit

REV. 0

–5–

ADP3166

PIN CONFIGURATION

RU-28

1

VID4 VCC

2

VID3 PWM1

3

VID2 PWM2

VID1 PWM3

VID0 PWM4

CROWBAR SW1

FBRTN SW2

FB SW3

COMP SW4

PWRGD GND

EN CSCOMP

DELAY CSSUM

RT CSREF

RAMPADJ ILIMIT

4

5

6

7

8

9

10

11

12

13

14

ADP3166

TOP VIEW

(Not to Scale)

28

27

26

25

24

23

22

21

20

19

18

17

16

15

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1–5 VID4–VID0

Voltage Identification DAC Inputs. These five pins are pulled up to an internal reference, providing a
logic 1 if left open. When in normal operation mode, the DAC output programs the FB regulation voltage
from 0.8 V to 1.55 V. Leaving VID4 through VID0 open results in the ADP3166 going into a “No CPU”
mode, shutting off its PWM outputs.

6 CROWBAR Crowbar Output. This logic-level output can be used to control an external device to short the 12 V supply

to ground to protect the CPU from overvoltage if CSREF exceeds 2.1 V.

7 FBRTN Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage.

8FB Feedback Input. Error amplifier input for remote sensing of the output voltage. A resistor between this pin

and the output voltage sets the no-load offset point.

9 COMP Error Amplifier Output and Compensation Point.

10 PWRGD Power Good Output. Open-drain output that pulls to GND when the output voltage is outside of the

proper operating range.

11 EN Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs.

12 DELAY Soft Start Delay and Current Limit Latch-Off Delay Setting Input. A resistor and capacitor connected

between this pin and GND sets the soft start ramp-up time and the overcurrent latch-off delay time.

13 RT Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscil-

lator frequency of the device.

14 RAMPADJ

PWM Ramp Current Input. A resistor from the converter input voltage to this pin sets the internal PWM ramp.

15 ILIMIT Current Limit Set Point/Enable Output. A resistor from this pin to GND sets the current limit threshold of

the converter. This pin is actively pulled low when the ADP3166 EN input is low, or when VCC is below
its UVLO threshold to signal to the driver IC that the driver high-side and low-side outputs should go low.

16 CSREF Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current

sense amplifiers and the Power Good and Crowbar functions. This pin should be connected to the com­mon point of the output inductors.

17 CSSUM Current Sense Summing Node. Resistors from each switch node to this pin sum the average inductor cur-

rents together to measure the total output current.

18 CSCOMP Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determine the slope

of the load line and the positioning loop response time.

19 GND Ground. All internal biasing and the logic output signals of the device are referenced to this ground.

20–23 SW4–SW1 Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused

phases should be grounded.

24–27 PWM4–PWM1 Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such

as the ADP3413 or ADP3418. Connecting the PWM3 and/or PWM 4 outputs to GND will cause that
phase to turn off, allowing the ADP3166 to operate as a 2-, 3-, or 4-phase controller.

28 VCC Supply Voltage for the Device.

REV. 0–6–

ADP3166

THEORY OF OPERATION

The ADP3166 combines a multimode, fixed frequency PWM
control with multiphase logic outputs for use in 2-, 3-, and 4-phase
synchronous buck CPU core supply power converters. The
internal 5-bit VID DAC conforms to AMD’s Hammer family
power specifications. Multiphase operation is important for
producing the high currents and low voltages demanded by
today’s microprocessors. Handling the high currents in a single­phase converter would place high thermal demands on the
components in the system such as the inductors and MOSFETs.

The multimode control of the ADP3166 ensures a stable, high
performance topology for

•

Balancing currents and thermals between phases.

•

High speed response at the lowest possible switching frequency
and output decoupling.

•

Minimizing thermal switching losses due to lower frequency
operation.

•

Tight load line regulation and accuracy.

•

High current output from having up to 4-phase operation.

•

Reduced output ripple utilizing multiphase cancellation.

•

Immunity to board layout.

•

Ease of use and design due to independent component
selection.

•

Flexibility in operation for tailoring design to low cost or
high performance.

Number of Phases

The number of operational phases and their phase relationship
are determined by internal circuitry that monitors the PWM
outputs. Normally, the ADP3166 operates as a 4-phase PWM
controller. Grounding the PWM 4 pin programs 3-phase opera­tion, and grounding the PWM3 and PWM4 pins programs
2-phase operation.

When the ADP3166 is enabled, the controller outputs a voltage
on PWM3 and PWM4 that is approximately 550 mV. An inter­nal comparator checks each pin’s voltage versus a threshold of
400 mV. If the pin is grounded, it will be below the threshold
and the phase will be disabled. The output impedance of the
PWM pin is approximately 5 kΩ. Any external pull-down resis­tance connected to the PWM pin should not be less than 25 kΩ
to ensure proper operation. The phase detection is made during
the first two clock cycles of the internal oscillator. After this
time, if the PWM output was not grounded, it will switch between
0V and 5 V. If the PWM output was grounded, it will remain off.

The PWM outputs are logic-level devices intended for driving
external gate drivers such as the ADP3418. Since each phase is
monitored independently, operation approaching 100% duty
cycle is possible. Also, more than one output can be on at a time
for overlapping phases.

Master Clock Frequency

The clock frequency of the ADP3166 is set with an external
resistor connected from the RT pin to ground. The frequency
follows the graph in TPC 1. To determine the frequency per
phase, the clock is divided by the number of phases in use. If
PWM4 is grounded, divide the master clock by 3 for the frequency
of the remaining phases. If PWM3 and PWM4 are grounded,
divide by 2. If all phases are in use, divide by 4.

Table I. VID Code vs. Output Voltage

VID4 VID3 VID2 VID1 VID0 V

11111No CPU

111100.800

111010.825

111000.850

110110.875

110100.900

110010.925

110000.950

101110.975

101101.000

101011.025

101001.050

100111.075

100101.100

100011.125

100001.150

011111.175

011101.200

011011.225

011001.250

010111.275

010101.300

010011.325

010001.350

001111.375

001101.400

001011.425

001001.450

000111.475

000101.500

000011.525

000001.550

Output Voltage Differential Sensing

The ADP3166 combines differential sensing with a high accu­racy VID DAC and reference and a low offset error amplifier to
maintain a worst-case specification of ±1% differential sensing
error over its full operating output voltage and temperature
range. The output voltage is sensed between the FB and
FBRTN pins. FB should be connected through a resistor to the
regulation point, usually the remote sense pin of the micropro­cessor. FBRTN should be connected directly to the remote
sense ground point. The internal VID DAC and precision refer­ence are referenced to FBRTN, which has a minimal current of
100 µA to allow accurate remote sensing. The internal error
amplifier compares the output of the DAC to the FB pin to
regulate the output voltage.

Output Current Sensing

The ADP3166 provides a dedicated current sense amplifier
(CSA) to monitor the total output current for proper voltage
positioning versus load current, and for current limit detection.
Sensing the load current at the output gives the total average
current being delivered to the load, which is an inherently more
accurate method than peak current detection or sampling the
current across a sense element such as the low-side MOSFET.

OUT(NOM)

(V)

REV. 0

–7–

ADP3166

This amplifier can be configured several ways depending on the
objectives of the system:

•

Output inductor ESR sensing without thermistor for
lowest cost

•

Output inductor ESR sensing with thermistor for improved
accuracy with tracking of inductor temperature

•

Sense resistors for highest accuracy measurements

The positive input of the CSA is connected to the CSREF pin,
which is connected to the output voltage. The inputs to the
amplifier are summed together through resistors from the sensing
element (such as the switch node side of the output inductors) to
the inverting input, CSSUM. The feedback resistor between
CSCOMP and CSSUM sets the gain of the amplifier, and a filter
capacitor is placed in parallel with this resistor. The gain of the
amplifier is programmable by adjusting the feedback resistor to
set the load line required by the microprocessor. The current
information is then given as the difference of CSREF – CSCOMP.
This difference signal is used internally to offset the VID DAC
for voltage positioning, and as a differential input for the current
limit comparator.

To provide the best accuracy for the sensing of current, the
CSA has been designed to have a low offset input voltage. Also,
the sensing gain is determined by external resistors so that it can
be made extremely accurate.

Active Impedance Control Mode

For controlling the dynamic output voltage droop as a function
of output current, a signal proportional to the total output cur­rent at the CSCOMP pin can be scaled to be equal to the droop
impedance of the regulator times the output current. This droop
voltage is then used to set the input control voltage to the sys­tem. The droop voltage is subtracted from the DAC reference
input voltage directly to tell the error amplifier where the output
voltage should be. This differs from previous implementations
and allows enhanced feed-forward response.

Voltage Control Mode

A high gain-bandwidth voltage mode error amplifier is used for
the voltage mode control loop. The control input voltage to the
positive input is set via the VID 5-bit logic code according to
the voltages listed in Table I. This voltage is also offset by the
droop voltage for active positioning of the output voltage as a
function of current, commonly known as active voltage position­ing. The output of the amplifier is the COMP pin, which sets
the termination voltage for the internal PWM ramps.

The negative input (FB) is tied to the output sense location with
a resistor, R

, and is used for sensing and controlling the output

B

voltage at this point. A current source from the FB pin flowing
through R

is used for setting the no-load offset voltage from

B

the VID voltage. The no-load voltage will be positive with respect
to the VID DAC. The main loop compensation is incorporated
in the feedback network between FB and COMP.

Soft Start

The power-on ramp-up time of the output voltage is set with a
capacitor and resistor in parallel from the DELAY pin to ground.
The RC time constant also determines the current limit latch-off
time, as explained in the following section. In UVLO or when

EN is a logic low, the DELAY pin is held at ground. After the
UVLO threshold is reached and EN is a logic high, the DELAY
capacitor is charged up with an internal 20 µA current source.
The output voltage follows the ramping voltage on the DELAY
pin, limiting the inrush current. The soft start time depends on
the value of VID DAC and C

. Refer to the Applications section for detailed information

R

DLY

on setting C

DLY

.

, with a secondary effect from

DLY

When the PWRGD threshold is reached, the soft start cycle is
stopped and the DELAY pin is pulled up to 3 V. This ensures
that the output voltage is at the VID voltage when the PWRGD
signals to the system that the output voltage is good. If EN is
taken low or if VCC drops below UVLO, the DELAY capacitor
is reset to ground to be ready for another soft start cycle.

Current Limit and Short-Circuit Protection

The ADP3166 compares a programmable current limit set point
to the voltage on the output of the current sense amplifier at the
CSCOMP pin. The level of current limit is set with the resistor
from the ILIMIT pin to ground. During normal operation, the
voltage on ILIMIT is 3 V. The current through the external
resistor is internally scaled to give a current limit threshold of

10.4 mV/µA. If the difference in voltage between CSREF and
CSCOMP drops below the current limit threshold, the internal
current limit amplifier will control the internal COMP voltage
to maintain the average output current at the limit.

After the limit is reached, the 3 V pull-up on the DELAY pin is
disconnected, and the external delay capacitor is discharged
through the external resistor. A comparator monitors the DELAY
voltage and shuts off the controller when the voltage drops
below 1.8 V. The current limit latch-off delay time is therefore
set by the RC time constant discharging from 3 V to 1.8 V. The
Applications section discusses the selection of R
the C

that has been chosen.

DLY

based on

DLY

Because the controller continues to cycle the phases during the
latch-off delay time, if the short is removed before the 1.8 V
threshold is reached, the controller will return to normal operation.
The recovery characteristic depends on the state of PWRGD. If
the output voltage is within the PWRGD window, the controller
resumes normal operation. However, if short circuit has caused
the output voltage to drop below the PWRGD threshold, then a
soft start cycle is initiated.

The latch-off function can be reset by either removing and
reapplying VCC to the ADP3166, or by pulling the EN pin low
for a short time. To disable the short-circuit latch-off function,
the external resistor to ground should be left open, and a large
(greater than 1 MΩ) resistor should be connected from VCC to
DELAY. This prevents the DELAY capacitor from discharging
so the 1.8 V threshold is never reached. The resistor will have
an impact on the soft start time because the current through it
will add to the internal 20 µA current source.

During startup when the output voltage is below 200 mV, a
secondary current limit is active. This is necessary because the
voltage swing of CSCOMP cannot go below ground. This sec­ondary current limit controls the internal COMP voltage to the
PWM comparators to 2 V. This will limit the voltage drop across
the low-side MOSFETs through the current balance circuitry.

REV. 0–8–

ADP3166

Dynamic VID

The ADP3166 incorporates the ability to dynamically change
the VID input while the controller is running. This allows the
output voltage to change while the supply is running and sup­plying current to the load. This is commonly referred to as
VID on-the-fly (OTF). A VID-OTF can occur under either
light load or heavy load conditions. The processor signals the
controller by changing the VID inputs in multiple steps from
the start code to the finish code. This change can be either
positive or negative.

When a VID input changes state, the ADP3166 detects the
change and blanks the DAC for a minimum of 400 ns. This
time is to prevent a false code due to logic skew while the six
VID inputs are changing. Additionally, the first VID change
initiates the PWRGD blanking function for a minimum of
100 µs to prevent a false PWRGD event. Each VID change will
reset the internal timer.

Power Good Monitoring

The power good comparator monitors the output voltage via the
CSREF pin. The PWRGD pin is an open-drain output whose
high level (when connected to a pull-up resistor) indicates that
the output voltage is within the nominal limits specified previ­ously, based on the VID voltage setting. PWRGD will go low if
the output voltage is outside of this specified range. PWRGD is
blanked during a VID-OTF event for a period of 100 µs to
prevent false signals during the time the output is changing.

Output Crowbar

As part of the protection for the load and output components of
the supply, the PWM outputs are driven low (turning on the
low-side MOSFETs) and the CROWBAR logic output goes
high when the output voltage exceeds the upper power good
threshold. This crowbar action releases once the output volt­age has fallen back within specifications if no other faults are
present. The release threshold is approximately 400 mV.

Turning on the low-side MOSFETs pulls down the output as
the reverse current builds up in the inductors. If the output
overvoltage is due to a short of the high-side MOSFET, this
action current limits the input supply or blow its fuse, protect­ing the microprocessor from destruction.

The CROWBAR output can be used to signal an external input
crowbar or other protection circuit.

Output Enable and UVLO

The input VCC must be higher than the UVLO threshold and the
EN pin must be higher than its logic threshold for the ADP3166 to
begin switching. IF UVLO is less than the threshold or the EN pin
is a logic low, the ADP3166 is disabled. This holds the PWM
outputs at ground, shorts the DELAY capacitor to ground, and
holds the ILIMIT pin at ground.

In the application circuit, the ILIMIT pin should be connected
to the OD pins of the ADP3418 drivers. Because ILIMIT is
grounded, this disables the drivers such that both DRVH and
DRVL are grounded. This feature is important to prevent dis­charging of the output capacitors when the controller is shut off.
If the driver outputs were not disabled, a negative voltage could
be generated on the output due to the high current discharge of
the output capacitors through the inductors.

APPLICATION INFORMATION

The design parameters for a typical AMD K8 compliant CPU
application are as follows:

•

Input voltage (VIN) = 12 V

•

VID setting voltage (V

•

Duty cycle (D) = 0.125

•

Maximum static output voltage error (±V

•

Maximum dynamic output voltage error (±V

•

Error voltage allowed for controller and ripple (±V

) = 1.500 V

VID

) = ±50 mV

SERR

DERR

) = ±70 mV

) =

RERR

±20 mV

•

Maximum output current (IO) = 56 A

•

Maximum output current step (⌬IO) = 24 A

•

Static output droop resistance (RO) based on:

a) No load output voltage set at upper output
voltage limit.

V

= V

ONL

VID

+ V

SERR

– V

= 1.530 V

RERR

b) Full load output voltage set at lower output
voltage limit.

•

V

= V

OFL

• RO = (V

VID

ONL

– V

– V

+ V

SERR

)/ (IO) = (1.530 V – 1.470 V)/(56A) =

OFL

= 1.470 V

RERR

1.1 mΩ

•

Dynamic output droop resistance (ROD) based on:

a) Output current step to no load with output voltage
set at upper output dynamic voltage limit.

V

= V

ONLD

VID

+ V

DERR

– V

= 1.550 V

RERR

b) Output voltage prior to load change
(at I

•

VOL = V

• ROD = (V

= ⌬IO).

OUT

– (⌬IO ⴛ RO)= 1.504 V

ONL

– VOL)/ (⌬IO) = (1.550 V – 1.504 V)/(24A) =

ONLD

1.9 mΩ

•

Number of phases (n) = 3

•

Switching frequency per phase (fSW) = 330 kHz

Setting the Clock Frequency

The ADP3166 uses a fixed-frequency control architecture. The
frequency is set by an external timing resistor (R

). The clock

T

frequency and the number of phases determine the switching
frequency per phase, which relates directly to switching losses
and the sizes of the inductors and input and output capacitors.
With n = 3 for three phases, a clock frequency of 990 kHz sets
the switching frequency of each phase, f

, to 330 kHz, which

SW

represents a practical trade-off between the switching losses and
the sizes of the output filter components. Figure 1 shows that to
achieve a 990 kHz oscillator frequency, the correct value for R

T

is 200 kΩ. Alternatively, the value for RT can be calculated using

583

1

1

–

.

ΩpFM

15

(1)

R=

T

nf .

××

()

SW

where 5.83 pF and 1.5 MΩ are internal IC component values.

For good initial accuracy and frequency stability, it is recom­mended to use a 1% resistor.

REV. 0

–9–

ADP3166

12V

V

IN

V

RTN

IN

D1

1N4148WS

L1

1.6␮H

2200␮F/16V ⴛ 3

NICHICON PW SERIES

++

C1

1N4148WS

C6

D2

C7

4.7␮F

D3

1N4148WS

C11

4.7␮F

D4

1N4148WS

C15

4.7␮F

U2

C8

U3

U4

DRVH

SW

PGND

DRVL

DRVH

SW

PGND

DRVL

DRVH

SW

PGND

DRVL

100nF

C12

100nF

8

7

6

Q2

IPD06N03L

8

7

6

5

Q5

IPD06N03L

C16

100nF

8

7

6

Q8

IPD06N03L

ADP3418

BST

1

IN

2

OD

3

VCC

45

ADP3418

1

BST

2

IN

3

OD

VCC

4

ADP3418

BST

1

IN

2

OD

3

VCC

45

C9

4.7␮F

Q1

IPD12N03L

Q3

IPD06N03L

C13

4.7␮F

Q4

IPD12N03L

Q6

IPD06N03L

C17

4.7␮F

Q7

IPD12N03L

Q9

IPD06N03L

L2

600nH/1.6m⍀

C10

4.7nF
R1

2.2⍀

L3

600nH/1.6m⍀

C14

4.7nF

R2

2.2⍀

L4

600nH/1.6m⍀

C18

4.7nF
R3

2.2⍀

100k⍀, 5%

820␮F/2.5V ⴛ 8

OSCON SERIES

12m⍀ ESR (EACH)

++

C21

10␮F ⴛ 5MLCC

AROUND
SOCKET

R

TH

C28

V

CC(CORE)

0.8V–1.55V

56A

V

CC(CORE) RTN

POWER

GOOD

ENABLE

*SEE THEORY OF

OPERATION
SECTION FOR
DESCRIPTION
OF OPTIONAL

RESISTORS

R

SW

2.00k⍀

C

DLY

39nF

680pF

R

B

C19
1␮F

R

A

7.32k⍀

R

T

200k⍀

+

33␮F

C

18pF

C20

FB

R

R

383k⍀

1

2

3

4

5

6

7

8

9

10

11

12

13

14

U1

ADP3166

VID4

VID3

VID2

VID1

VID0

CROWBAR

FBRTN

FB

COMP

PWRGD

EN

DELAY

RT

RAMPADJ

VCC

PWM1

PWM2

PWM3

PWM4

SW1

SW2

SW3

SW4

GND

CSCOMP

CSSUM

CSREF

ILIMIT

28

27

26

25

24

23

R

SW2

22

21

20

19

C

1.5nF

18

17

C

CS1

2.2nF

16

15

CS2

*

R

SW1

R

R

35.7k⍀

R

LIM

200k⍀

SW3

CS1

*

*

R

CS2

73.2k⍀

R

PH3

147k⍀

R

PH2

147k⍀

R

PH1

147k⍀

R4

10⍀

FROM CPU

C

B

C

A

680pF

R

DLY

390k⍀

Figure 1. 56 AMD K8 CPU Supply Circuit

REV. 0–10–

ADP3166

Soft Start and Current Limit Latch-Off Delay Times

Because the soft start and current limit latch-off delay functions
share the DELAY pin, these two parameters must be considered
together. The first step is to set C

for the soft start ramp.

DLY

This ramp is generated with a 20 µA internal current source.
The value of R

will have a second order impact on the soft-

DLY

start time because it sinks part of the current source to ground.
However, as long as R
is minor. The value for C

DLY






202µ

C= A–

where tSS is the desired soft start time. Assuming an R
kΩ and a desired a soft start time of 3 ms, C

The closest standard value for C
been chosen, R

DLY

is kept greater than 200 kΩ, this effect

DLY

can be approximated using

DLY

V

×



VID

R

×




DLY

is 39 nF. Once C

CS

t

SS

V

VID

is 36 nF.

DLY

DLY

DLY

has

(2)

of 390

can be calculated for the current limit latch

off time using

196×

.t

R=

DLY

If the result for R
time should be considered by recalculating the equation for C
or a longer latch-off time should be used. In no case should R

DLY

C

DLY

is less than 200 kΩ , then a smaller soft start

DLY

(3)

DLY

DLY

be less than 200 kΩ. In this example, a delay time of 8 ms makes

R

= 402 kΩ. The closest standard 5% value is 390 kΩ.

DLY

Inductor Selection

The choice of inductance for the inductor determines the ripple
current in the inductor. Less inductance leads to more ripple
current, which increases the output ripple voltage and conduc­tion losses in the MOSFETs but allows using smaller-size
inductors and, for a specified peak-to-peak transient deviation,
less total output capacitance. Conversely, a higher inductance
means lower ripple current and reduced conduction losses, but
requires larger-size inductors and more output capacitance for
the same peak-to-peak transient deviation. In any multiphase
converter, a practical value for the peak-to-peak inductor ripple
current is less than 50% of the maximum dc current in the same
inductor. Equation 4 shows the relationship between the induc­tance, oscillator frequency, and peak-to-peak ripple current in
the inductor. Equation 5 can be used to determine the mini­mum inductance based on a given output ripple voltage:

I=

R

VR –nD

L ≥

×1L

f

SW

×× ×

VID OD

fV

SW RIPPLE

1

()

×

()

(4)

(5)

×

V–D

()

VID

Solving Equation 5 for a 10 mV p-p output ripple voltage yields

If the ripple voltage is less than that designed for, the inductor can
be made smaller until the ripple value is met. This will allow opti­mal transient response and minimum output decoupling.

The smallest possible inductor should be used to minimize the
number of output capacitors. A 600 nH inductor is a good
choice for a starting point, and it gives a calculated ripple cur­rent of 6.6 A. The inductor should not saturate at the peak
current of 22 A, and should be able to handle the sum of the
power dissipation caused by the average current of 18.7 A in the
winding and the core loss.

Another important factor in the inductor design is the DCR,
which is used for measuring the phase currents. A large DCR
will cause excessive power losses, while too small a value will
lead to increased measurement error. A good rule is to have the
DCR be about 1 to 1 1/2 times the static droop resistance (R

).

O

For our example, we are using an inductor with a DCR of 1.6 mΩ.

Designing an Inductor

Once the inductance and DCR are known, the next step is either
to design an inductor or to find a standard inductor that comes as
close as possible to meeting the overall design goals. It is also
important to have the inductance and DCR tolerance specified to
keep the accuracy of the system controlled. Using 20% for the
inductance and 8% for the DCR (at room temperature) are rea­sonable tolerances that most manufacturers can meet.

The first decision in designing the inductor is to choose the core
material. There are several possibilities for providing low core
loss at high frequencies. Two examples are the powder cores
(e.g., Kool-Mµ® from Magnetics, Inc. or Micrometals) and the
gapped soft ferrite cores (e.g., 3F3 or 3F4 from Philips). Low
frequency powdered iron cores should be avoided due to their
high core loss, especially when the inductor value is relatively
low and the ripple current is high.

The best choices for a core geometry are closed-loop types, such
as pot cores, PQ, U, and E cores, or toroids. A good compromise
between price and performance are cores with a toroidal shape.

There are many useful references for quickly designing a power
inductor, such as

•

Magnetic Designer Software
Intusoft (http://www.intusoft.com)

•

Designing Magnetic Components for High-Frequency
DC-DC Converters
McLyman, Kg Magnetics
ISBN 1-883107-00-8

REV. 0

15 19 1 0375

×Ω×

.V .m – .

L ≥

330 10

×

kHz mV

()

540

=nH

–11–

ADP3166

Selecting a Standard Inductor

The following companies can provide design consultation and
deliver power inductors optimized for high power applications
upon request.

•

Coilcraft
[phone]
http://www.coilcraft.com

•

Coiltronics
[phone]
http://www.coiltronics.com

•

Sumida Electric Company
[phone]
http://www.sumida.com

•

Vishay Intertechnology
[phone]
http://www.vishay.com

Output Droop Resistance

The design requires that the regulator output voltage measured
at the CPU pins drops when the output current increases. The
specified voltage drop corresponds to the static output droop
resistance (R

).

O

The output current is measured by summing together the voltage
across each inductor and then passing the signal through a low­pass filter. This summer-filter is the CS amplifier configured with
resistors R

(summers) and RCS, and CCS (filter). The output

PH(X)

resistance of the regulator is set by the following equations, where

R

is the DCR of the output inductors:

L

R

R=

C=

One has the flexibility of choosing either RCS or R
to select R

CS

R

PH(X)

×

L

O

R

L

CS

RR

×

LCS

equal to 100 kΩ, and then solve for R

CS

PH(X)

PH(X)

(6)

(7)

. It is best

by

rearranging Equation 6.

R

R=

PH(X)

.m

R=

PH(X)

16

.m

11

L

×

R

O

Ω

Ω

k= .k

100 145 5

R

CS

ΩΩ×

Next, use Equation 6 to solve for CCS:

nH

C=

CS

600

.m k

16 100

ΩΩ×

=. nF

375

It is best to have a dual location for CCS in the layout so stan­dard values can be used in parallel to get as close to the value
desired. For this example, choosing C

to be a 1.5 nF and 2.2 nF

CS

in parallel is a good choice. For best accuracy, CCS should be
a 10% capacitor. The closest standard 1% value for R

PH(X)

is

147 kΩ .

Inductor DCR Temperature Correction

With the inductor’s DCR being used as the sense element and
copper wire being the source of the DCR, one needs to com­pensate for temperature changes of the inductor’s winding.
Fortunately, copper has a well known temperature coefficient
(TC) of 0.39%/°C.

If RCS is designed to have an opposite and equal percentage
change in resistance to that of the wire, it will cancel the tem­perature variation of the inductor’s DCR. Due to the nonlinear
nature of NTC thermistors, resistors R

CS1

and R

(see Figure 2)

CS2

are needed to linearize the NTC and produce the desired tem­perature tracking.

PLACE AS CLOSE AS POSSIBLE

TO NEAREST INDUCTOR

OR LOW SIDE MOSFET

ADP3166

CSCOMP

18

CSSUM

17

CSREF

16

R

TH

R

R

CS1

CS2

C

CS

TO

SWITCH

NODES

R

R

R

PH1

KEEP THIS PATH

AS SHORT AS POSSIBLE

AND WELL AWAY FROM

SWITCH NODE LINES

PH2

PH3

TO

V

OUT

SENSE

Figure 2. Temperature Compensation Circuit Values

The following procedure and expressions will yield values to use
for R
given R

CS1

, R

, and RTH (the thermistor value at 25°C) for a

CS2

value.

CS

1. Select an NTC based on type and value. Since we do not
have a value yet, start with a thermistor with a value close to
R

. The NTC should also have an initial tolerance of better

CS

than 5%.

2. Based on the type of NTC, find its relative resistance value at
two temperatures. The temperatures to use that work well are
50°C and 90°C. We will call these resistance values A (A is
R

TH(50°C)/RTH(25°C))

and B (B is R

TH(90°C)/RTH(25°C))

. Note that

the NTC’s relative value is always 1 at 25°C.

3. Next, find the relative value of R

required for each of these

CS

temperatures. This is based on the percentage change needed,
which we will initially make 0.39%/°C. We will call these r
(r1 is 1/(1 + TC ⫻ (T1 – 25))) and r2 (r2 is 1/(1 + TC ⫻ (T2 – 25)))
where T

= 0.0039,

C

T1 = 50°C and T2 = 90°C.

1

,

REV. 0–12–

ADP3166









4. Compute the relative values for R

×× ×

A–B r r –A –Br+B –Ar

()

R=

CS

2

R=

CS

1

1

R=

TH

1

–R

–R–R

12 2 1

××

11

×

A–Br–B–Ar–A–B

()

1– A

()

1

–

S

CCS

21 2

12

A

r–R

1

1

1

CS CS

21

, R

CS1

11

()

, and RTH using

CS2

××

()

×

()×()

(8)

5. Calculate RTH = rTH ⫻ RCS, then select the closest value of
thermistor available. Also compute a scaling factor k based on
the ratio of the actual thermistor value used relative to the
computed one:

R

TH ACTUAL

k=

6. Finally, calculate values for R

R=R kR

CS CS CS

11

R=R -k+kR

CS CS CS

()

R

TH CALCULATED

()

CS1

and R

using the following:

CS2

××

1

×

()

22

()

×

()

(9)

(10)

For this example, RCS has been chosen to be 100 kΩ, so we start
with a thermistor value of 100 kΩ. Looking through available 0603
size thermistors, we find a Vishay NTHS0603N01N1003JR NTC
thermistor with A = 0.3602 and B = 0.09174. From these we
compute R
Solving for R

= 0.3796, R

CS1

yields 107.51 kΩ, so we choose 100 kΩ, mak-

TH

ing k = 0.9302. Finally, we find R

= 0.7195 and RTH = 1.0751.

CS2

CS1

and R

to be 35.3 kΩ

CS2

and 73.9 kΩ. Choosing the closest 1% resistor values yields a
choice of 35.7 kΩ and 73.2 kΩ.

Output Offset

AMD’s specification requires that at no load, the nominal output
voltage of the regulator be offset to a higher value than the nominal
voltage corresponding to the VID code. The offset is set by a con­stant current source flowing out of the FB pin (I
through R

. The value of RB can be found using Equation 11:

B

V–V

ONL VID

R=

B

R=

B

I

FB

.V–.V

153 15

A

15

=. k

200µΩ

) and flowing

FB

(11)

The closest standard 1% resistor value is 2.00 kΩ.

C

Selection

OUT

The required output decoupling for the regulator is typically
recommended by AMD for various processors and platforms.
One can also use some simple design guidelines to determine
what is required. These guidelines are based on having both
bulk and ceramic capacitors in the system.

The first thing is to select the total amount of ceramic capaci­tance, which is based on the number and type of capacitor to be
used. The best location for ceramics is inside the socket. Others
can be placed along the outer edge of the socket as well.

Combined ceramic values of 30 µF to 100 µF are recommended,
usually made up of multiple ceramic capacitors. Select the num­ber of ceramics and find the total ceramic capacitance (C

).

Z

Next, there is an upper limit imposed on the total amount of
bulk capacitance (C
voltage stepping of the output (voltage step V
error of V

) and a lower limit based on meeting the critical

ERR

capacitance for load release for a given maximum load step ∆I

C

X MIN

C

XMAX

()




V

V

1



V

VID




where K

–In

) when one considers the VID on-the-fly

X




nR V

××



≤

nK R

××



V

+t

××



V



V

ERR





V

V





LI

×

∆

O

OD VID

L

×

2

2

O

nKR

VID

V

V

C

–≥

××

L

Z()

O

in time tV with

V








2





–1 – C










:

O

(12)

(13)

Z

To meet the conditions of these expressions and transient
response, the ESR of the bulk capacitor bank (R
less than or equal to the dynamic droop resistance, R
C

is larger than C

X(MIN)

, the system will not meet the VID

X(MAX)

) should be

X

. If the

OD

on-the-fly specification and may require the use of a smaller
inductor or more phases (and may have to increase the switch­ing frequency to keep the output ripple the same).

For our example, a combination of MLCC capacitors (C

= 50 µF)

Z

was used. The VID on-the-fly step change is from 1.5 V to 0.8 V
(making V

= 700 mV) in 100 µs with a setting error of 3%.

V

Solving for the bulk capacitance yields

nH A

C

X MIN()

C







≤

XMAX

()



100 1 5 3 3 5 1 1

+

1







nH mV

600 700

..V

××

335 15

ms . V . . m

××××

mV nH

700 600

600 24

××

319 15

×

2

×

mV

..

Ω

×

Ω

×

FmF

–.≥

µ

=

50 1 63




2







––mF=.mF

150 204







where K = 3.5.
Using eight 820 µF OSCONs with a typical ESR of 12 mΩ each

yields C

= 6.56 mF with an RX = 1.5 mΩ.

X

One last check should be made to ensure that the ESL of the
bulk capacitors (L

) is low enough to limit the initial high fre-

X

quency transient spike. This is tested using

LCR

≥× ×

2

XZOD

LmF.mW=pH

≥× ×

250 19 361

X

2

2

(14)

REV. 0

–13–

ADP3166

In this example, LX is 375 pH for the eight OSCON capacitors,
which basically satisfies this limitation. If the L

of the chosen

X

bulk capacitor bank is too large, the number of capacitors must
be increased.

One should note for this multimode control technique, all­ceramic designs can be used as long as the conditions of
Equations 12, 13, and 14 are satisfied.

Power MOSFETs

For this example, the N-channel power MOSFETs have been
selected for one high-side switch and two low-side switches per
phase. The main selection parameters for the power MOSFETs
are V
d

rive voltage (the supply voltage to the ADP3418) dictates

GS(TH)

, QG, C

ISS

, C

, and R

RSS

. The minimum gate

DS(ON)

whether standard threshold or logic-level threshold MOSFETs
must be used. With V
(V

< 2.5 V) are recommended.

GS(TH)

The maximum output current, IO, determines the R

~10 V, logic-level threshold MOSFETs

GATE

DS(ON)

requirement for the low-side (synchronous) MOSFETs. With
the ADP3166, currents are balanced between phases, thus the
current in each low-side MOSFET is the output current divided
by the total number of MOSFETs (n

). With conduction losses

SF

being dominant, the following expression shows the total power
being dissipated in each synchronous MOSFET in terms of the
ripple current per phase (I

P=–D

1

()

SF

) and average total output current (IO):

R

22







I

O



×





n







SF





1

+

×



12



nI

×

R

n

SF









R

×

DS SF

()




(15)

Knowing the maximum output current being designed for and
the maximum allowed power dissipation, one can find the required

for the MOSFET. For D-PAK MOSFETs up to an

R

DS(ON)

ambient temperature of 50ºC, a safe limit for P

is 1 W to 1.5 W

SF

at 120ºC junction temperature. Thus, for our example (56 A
maximum), we find R
R

is also at a junction temperature of about 120ºC, so we

DS(SF)

(per MOSFET) < 10 mΩ. This

DS(SF)

need to make sure we account for this when making this selection.
For our example, we selected two lower-side MOSFETs at 7 mΩ
each at room temperature, which gives 8.4 mΩ at high temperature.

Another important factor for the synchronous MOSFET is the
input capacitance and the feedback capacitance. The ratio of
the feedback to input needs to be small (less than 10% is recom­mended) to prevent accidental turn-on of the synchronous
MOSFETs when the switch node goes high.

Also, the time to switch off the synchronous MOSFETs should
not exceed the nonoverlap dead time of the MOSFET driver
(40 ns typical for the ADP3418). The output impedance of the
driver is about 2 Ω and the typical MOSFET input gate resistances
are about 1 Ω to 2 Ω, so a total gate capacitance of less than
6000 pF should be adhered to. Since there are two MOSFETs in
parallel, we should limit the input capacitance for each synchro­nous MOSFET to 3000 pF.

The high-side (main) MOSFET must be able to handle two
main power dissipation components: conduction and switching
losses. The switching loss is related to the amount of time it

takes for the main MOSFET to turn on and off, and to the
current and voltage that are being switched. Basing the switch­ing speed on the rise and fall time of the gate driver impedance
and MOSFET input capacitance, the following expression pro­vides an approximate value for the switching loss per main
MOSFET, where n

P=2f

SMF

()

Here, R

is the total gate resistance (2 Ω for the ADP3418 and

G

is the total number of main MOSFETs:

MF

VI

ЧЧЧЧЧ Ч

SW

CC O

n

MF

n

MF

R

G

C

n

ISS

(16)

about 1 Ω for typical high speed switching MOSFETs, making

= 3 Ω) and C

R

G

is the input capacitance of the main

ISS

MOSFET. It is interesting to note that adding more main
MOSFETs (n

) does not really help the switching loss per

MF

MOSFET since the additional gate capacitance slows down
switching. The best thing to reduce switching loss is to use
lower gate capacitance devices.

The conduction loss of the main MOSFET is given by the fol­lowing, where RDS(MF) is the on resistance of the MOSFET:



P=D

CMF

() ()



×




22





I

O





n





MF



1

+

×



12



nI

×

R

n

MF









R

×

DS MF




(17)

Typically, for main MOSFETs, one wants the highest speed
(low C

) device, but these usually have higher on resistance.

ISS

One must select a device that meets the total power dissipation
(about 1.5 W for a single D-PAK) when combining the switch­ing and conduction losses.

For our example, we have selected an Infineon IPD12N03L as
main MOSFET (three total; nMF = 3), with a C
and R

= 14 mΩ (max at TJ = 120ºC) and an Infineon

DS(MF)

= 1460 pF (max)

ISS

IPD06N03L as the synchronous MOSFET (six total; n
with C

= 2370 pF (max) and R

ISS

= 8.4 mΩ (max at TJ = 120ºC).

DS(SF)

= 6),

SF

the

The synchronous MOSFET CISS is less than 3000 pF, satisfy­ing that requirement. Solving for the power dissipation per
MOSFET at I

= 56 A and IR = 6.6 A yields 647 mW for each

O

synchronous MOSFET and 1.26 W for each main MOSFET.
These numbers work well considering there is usually more
PCB area available for each main MOSFET versus each syn­chronous MOSFET.

One last thing to look at is the power dissipation in the driver
for each phase. This is best described in terms of the Q
MOSFETs and is given by the following, where Q
total gate charge for each main MOSFET and Q

GSF

for the

G

is the

GMF

is the total

gate charge for each synchronous MOSFET:

f



SW

P=

DRV

×× ×

nQ+nQ+I V

()



2 ×



MF GMF SF GSF CC CC

n

Also shown is the standby dissipation factor (I



×




⫻ VCC) for the

CC

(18)

driver. For the ADP3418, the maximum dissipation should be
less than 400 mW. For our example, with I

22.8 nC and Q

= 34.3 nC, we find 265 mW in each driver,

GSF

= 7 mA, Q

CC

GMF

=

which is below the 400 mW dissipation limit. See the ADP3418
data sheet for more details.

REV. 0–14–

ADP3166

Ramp Resistor Selection

The ramp resistor (RR) is used for setting the size of the internal
PWM ramp. The value of this resistor is chosen to provide the
best combination of thermal balance, stability, and transient
response. The following expression is used for determining the
optimum value:

×

AL

R=

R

3

R=

R

3542 5

where A

is the internal ramp amplifier gain, AD is the current

R

balancing amplifier gain, R
resistance, and C

R

×× ×

AR C

DDSR

×

02

. 600 nH

×× ×

.mW pF

is the internal ramp capacitor value. The

R

DS

381 Ω

=k

is the total low-side MOSFET on

(19)

closest standard 1% resistor value is 383 kΩ.

The internal ramp voltage magnitude can be calculated using

A–DV

×

V=

V=

R VID

R

RC f

RRSW

.–. .V

×

02 1 0125 15

R

kpF kHz

383 5 330

×

1

()

××

()

××

Ω

×

=. V

041

(20)

The size of the internal ramp can be made larger or smaller. If it
is made larger, stability and transient response will improve, but
thermal balance will degrade. Conversely, if the ramp is made
smaller, thermal balance will improve at the sacrifice of transient
response and stability. The factor of three in the denominator of
Equation 19 sets a ramp size that gives an optimal balance for
good stability, transient response, and thermal balance.

COMP Pin Ramp

There is a ramp signal on the COMP pin due to the droop
voltage and output voltage ramps. This ramp amplitude adds to
the internal ramp to produce the following overall ramp signal
at the PWM input.

V

V=

RT







R+R –nD

()

–

1

nf C R R

××××

R

1

×

OOD

SW X O OD

()







(21)

For this example, the overall ramp signal is found to be 0.48 V.

Current Limit Set Point

To select the current limit set point, we need to find the resistor
value for R
set with a 3 V source (V
(A

). R

LIM

R=

. The current limit threshold for the ADP3166 is

LIM

can be found using the following:

LIM

AV

LIM

LIM LIM

IR

LIM O

×

×

) across R

LIM

with a gain of 10.4 mV/µA

LIM

(22)

For values of R
lower than expected, so some adjustment of R
Here, I

is the average current limit for the output of the sup-

LIM

ply. For our example, choosing 75 A for I

greater than 500 kΩ, the current limit may be

LIM

may be needed.

LIM

, we find R

LIM

LIM

to be

378 kΩ, for which we choose 374 kΩ as the nearest 1% value.

The per phase current limit described earlier has its limit deter­mined by the following:

V–V–V

I

PHLIM

COMP(MAX) R BIAS

≅

AR

× 2

D DS(MAX)

For the ADP3166, the maximum COMP voltage (V
is 3.3 V, the COMP pin bias voltage (V
current balancing amplifier gain (A
and R

of 4.2 mΩ (low-side on resistance at 150°C), we

DS(MAX)

D

I

R

–

) is 1.2 V, and the

BIAS

(23)

COMP(MAX))

) is 5. Using VR of 0.48 V,

find a per phase limit of 74 A.

This limit can be adjusted by changing the ramp voltage V

. But

R

make sure not to set the per phase limit lower than the average
per phase current (I

LIM/n

).

There is also a per phase initial duty cycle limit determined by:

D=D

MAX

×

V–V

COMP MAX

()

V

RT

BIAS

(24)

For this example, the maximum duty cycle is found to be 0.55.

Feedback Loop Compensation Design

Optimized compensation of the ADP3166 allows the best pos­sible response of the regulator’s output to a load change. The
basis for determining the optimum compensation is to make the
regulator and output decoupling appear as an output impedance
that is optimized over the widest possible frequency range,
including dc, and equal to the droop resistances (R

). With the output impedance, the output voltage will respond

R

OD

and

O

in proportion with the load current; this ensures the optimal
output positioning and allows the minimization of the output
decoupling.

With the multimode feedback structure of the ADP3166, one
needs to set the feedback compensation to make the converter’s
output impedance work in parallel with the output decoupling to
meet this goal. There are several poles and zeros created by the
output inductor and decoupling capacitors (output filter) that
need to be compensated for.

REV. 0

–15–

ADP3166

The first step is to compute the time constants for all of the poles and zeros in the system:

1

RV

R=n R +A R +

××

eODDDS

319 5 42

R= . m + . m +

e

R= . m

36 0

e

ΩΩ

××

Ω

LR

V

×

VID

R+R L –n D V

()

OOD RT

T

+

Ω

16 048

×

.m . V

15

.V

×× ×

()

××× ×

nC R R V

XOODVID

11 19 600 10375 0

Ω

.m +.m nH – .

()

+

3656 11 19 15

×

Ω

××

.mF .m .m.V

××××ΩΩ

()

×

..V

48

(25)

L

X

R

OD






×

542

×

2 330

ΩV

2

×

R–R

×

.m

T=C R –R +

aX OD

T=6.56 mF 1.9 m – 0.6 m +

a

T=8.70 s

a

T=R +R–R C

T= . + . m – . m.mF=. s

T=

c

T=

c

T=

d

T=

d

×

()

µ

bX'OD X

()

ΩΩΩ

()

b



×

VL–



RT



VR

.V nH–

048 600

CCR

XZOD

×

CR–R+CR

()

XO ZOD

.mF .m–.m+ mF .m

656 19 06 50 19

'

×

()

×

×

AR

DDS

×

2f

SW

×

VID e



×




×

..m

15 360

××

.mF mF .m

656 50 19

×Ω Ω

××Ω

()

OD

R

×µ15 06 19 656 131m

Ω

kHz

'

X

375 pH

1.5 m






=. s

2

Ω

505

1.9 m – 0.6 m

ΩΩ

×ΩΩ

1.5 m

Ω

µ

=7ns

×Ω

13

(26)

(27)

(28)

(29)

where, for the ADP3166, R' is the PCB resistance from the bulk
capacitors to the ceramics and where R
MOSFET on resistance per phase. For this example, A
equals 0.48 V, R' is approximately 0.6 mΩ (assuming a 4-layer
motherboard), and L

is 375 pH for the eight OSCON capacitors.

X

A type-three compensator on the voltage feedback is adequate for
proper compensation of the output filter. The expressions that
follow are intended to yield an optimal starting point for the design;
some adjustments may be necessary to account for PCB and com­ponent parasitic effects (see the Tuning Procedure section).

The compensation values can then be solved using the following:

nR T

××

C=

A

C=

A

C=

B

OD a

RR

×

eB

.m . s

××µ

319 870

36 0 2 00

T

R

Ω

.m . k

×

ΩΩ

µ

.s

131

b

=

B

.k

200

Ω

=pF

=pF

655

is the total low-side

DS

689

is 5, V

D

RT

Choosing the closest standard values for these components yields:

C

Figure 3 shows the typical transient response using the compen­sation values.

CIN Selection and Input Current di/dt Reduction

In continuous inductor-current mode, the source current of the
high-side MOSFET is approximately a square wave with a duty
ratio equal to n ⫻ V
maximum output current. To prevent large voltage transients, a
low ESR input capacitor sized for the maximum rms current
must be used. The maximum rms capacitor current is given by

(30)

(31)

Note that the capacitor manufacturer’s ripple current ratings are

C=

B

T

b

R

B

.s

131

=

.k

200

µ

=pF

655

Ω

(32)

often based on only 2,000 hours of life. This makes it advisable

T

C=

= 680 pF, RA = 7.32 kΩ, CB = 680 pF, and CFB = 18 pF.

A

I=DI

I= A

d

FB

R

A

CRMS O

CRMS

××

0 125 56

ns

137

=

.k

733

OUT/VIN

nD

××

=.pF

18 7

Ω

and an amplitude one-nth of the

1

–

1

×

1

–=. A

1905.

.

3 125

×

(33)

(34)

REV. 0–16–

ADP3166

to further derate the capacitor, or to choose a capacitor rated at
a higher temperature than required. Several capacitors may be
placed in parallel to meet size or height requirements in the
design. In this example, the input capacitor bank is formed by
three 2200 µF, 16 V Nichicon capacitors with a ripple current
rating of 3.5 A each.

To reduce the input-current di/dt to below the recommended
maximum of 0.1 A/µs, an additional small inductor (L > 1 µH
@ 15 A) should be inserted between the converter and the sup­ply bus. That inductor also acts as a filter between the converter
and the primary power source.

V–V

()

R=R

CS2 NEW CS2 OLD

() ()

TUNING PROCEDURE FOR ADP3166

NL FLCOLD

×

V–V

()

NL FLHOT

(35)

1. Build a circuit based on compensation values computed

from the design spreadsheet.

2. Hook up the dc load to the circuit, turn it on, and verify its

operation. Also check for jitter at no load and full load.

DC Loadline Setting

3. Measure the output voltage at no load (VNL). Verify that

it is within tolerance.

4. Measure the output voltage at full load cold (V

FLCOLD

). Let
the board set for a ~10 minutes at full load and measure
output (V
millivolts, adjust R

). If there is a change of more than a few

FLHOT

CS1

and R

using Equations 35 and 37.

CS2

5. Repeat Step 4 until the cold and hot voltage measurements
remain the same.

6.

Measure the output voltage from no load to full load using 5
A steps. Compute the loadline slope for each change and
then average them to get the overall loadline slope (R

7. If R
tion 36 to adjust the R

R=R

PH NEW PH OLD

is off by more than 0.05 mΩ from RO, use Equa-

OMEAS

() ()

values:

PH

R

OMEAS

R

O

OMEAS

(36)

).

8. Repeat Steps 6 and 7 to check the loadline and repeat the
adjustments if necessary.

9. Once finished with dc loadline adjustment, do not change
R

, R

, R

PH

CS1

, or RTH for the rest of the procedure.

CS2

10. Measure the output ripple at no load and at full load with
a scope and make sure that it is within spec.

AC Loadline Setting

11. Remove the dc load from the circuit and hook up the
dynamic load.

12. Hook up the scope to the output voltage and set it to dc
coupling with the time scale at 100 µs/div.

13. Set the dynamic load for a transient step of about 24 A at 1
kHz with 50% duty cycle.

14. Measure the output waveform (it might be necessary to
use a dc offset on scope to see the waveform). Try to use a
vertical scale of 100 mV/div or finer.

15.

The waveform should look something like Figure 3. Use
the horizontal cursors to measure V
as shown. DO NOT MEASURE THE UNDER
OR OVERSHOOT THAT HAPPENS

ACDRP

and V

DCDRP

SHOOT

IMMEDI-

ATELY AFTER THE STEP.

V

ACDRP

V

DCDRP

Figure 3. AC Loadline Waveform

16. If the V
millivolts, use the following to adjust C

ACDRP

and V

are different by more than a few

DCDRP

. It might be

CS

necessary to parallel different values to get the right one
since there are limited standard capacitor values available.
(It is a good idea to have locations for two capacitors in
the layout for this.)

17. Repeat Steps 11 to 13 and repeat adjustments if neces­sary. Once complete, do not change C

for the rest of

CS

the procedure.

18. Set the dynamic load step to maximum step size (do not
use a step size larger than needed), and verify that the
output waveform is square (meaning V

ACDRP

and V

DCDRP

are equal).

R=

CS NEW

2

()

RR+R–R R–R

CS OLD

1

C=C

CS NEW CS OLD

() ()

()

REV. 0

×

TH C

()

V

ACDRP

V

DCDRP

1

R+R

CS OLD

1

()

o o

()

CS OLD CS2 NEW OLD

21

25

() ( ) ()

o

TH C

25

()



×



–17–

CS

–



TH C

25

()



1

R

o

TH C

25

()

(37)

(38)

12V CONNECTOR

INPUT POWER PLANE

THERMISTOR

OUTPUT

POWER

PLANE

CPU

SOCKET

KEEP-OUT

AREA

KEEP-OUT

AREA

SWITCH NODE

PLANES

KEEP-OUT

AREA

KEEP-OUT

AREA

ADP3166

Initial Transient Setting

19. With dynamic load still set at maximum step size, expand

scope time scale to see 2 µs/div to 5 µs/div. The waveform
may have two overshoots and one minor undershoot (see
Figure 5). Here, V

V

TRAN1

Figure 4. Transient Setting Waveform

20. If the overshoots are larger than desired, try making the
following adjustments in this order (Note: if these adjust­ments do not change the response, you are limited by the
output decoupling). Check the output response each time
a change is made as well as the switching nodes (to make
sure it is still stable).

a. Make the ramp resistor larger by 25% (R
b.

For V

c. For V

, increase CB or switching frequency.

TRAN1

, increase RA and decrease CA by 25%.

TRAN2

V

TRANREL

Figure 5. Transient Setting Waveform

21. For load release (see Figure 5), if VTRANREL is larger
than V

(refer to Figure 4), there is not enough

TRAN1

output capacitance. Either more capacitance is needed or
it is necessary to make the inductor values smaller (if
inductors are changed, it is necessary to start design over
using the spreadsheet and this tuning guide).

LAYOUT AND COMPONENT PLACEMENT

The following guidelines are recommended for optimal performance
of a switching regulator in a PC system. Key layout issues are
illustrated in Figure 6.

is the final desired static value.

DROOP

V

DROOP

V

TRAN2

V

DROOP

RAMP

).

Figure 6. Layout Recommendations

General Recommendations

•

For good results, at least a four-layer PCB is recommended.
This should allow the needed versatility for control circuitry
interconnections with optimal placement, power planes for
ground, input and output power, and wide interconnection
traces in the rest of the power delivery current paths. Keep
in mind that each square unit of 1 ounce copper trace has a
resistance of ~0.53 mΩ at room temperature.

•

Whenever high currents must be routed between PCB lay­ers, vias should be used liberally to create several parallel
current paths so that the resistance and inductance intro­duced by these current paths is minimized and the via current
rating is not exceeded.

•

If critical signal lines (including the output voltage sense
lines of the ADP3166) must cross through power circuitry,
it is best if a signal ground plane can be interposed between
those signal lines and the traces of the power circuitry. This
serves as a shield to minimize noise injection into the signals
at the expense of making signal ground a bit noisier.

•

An analog ground plane should be used around and under
the ADP3166 for referencing the components associated
with the controller. This plane should be tied to the nearest
output decoupling capacitor ground and should not be tied
to any other power circuitry to prevent power currents from
flowing in it.

•

The components around the ADP3166 should be located
close to the controller with short traces. The most important
traces to keep short and away from other traces are the FB
and CSSUM pins. Refer to Figure 6 for more details on
layout for the CSSUM node.

•

The output capacitors should be connected as close as
possible to the load (or connector) that receives the power
(e.g., a microprocessor core). If the load is distributed, the
capacitors should also be distributed, and generally in pro­portion to where the load tends to be more dynamic.

•

Avoid crossing any signal lines over the switching power
path loop, described below.

REV. 0–18–

Power Circuitry

•

The switching power path should be routed on the PCB to
encompass the shortest possible length to minimize radiated
switching noise energy (i.e., EMI) and conduction losses in
the board. Failure to take proper precautions often results in
EMI problems for the entire PC system as well as noise­related operational problems in the power converter control
circuitry. The switching power path is the loop formed by
the current path through the input capacitors and the power
MOSFETs including all interconnecting PCB traces and
planes. The use of short and wide interconnection traces is
especially critical in this path for two reasons: it minimizes
the inductance in the switching loop, which can cause high
energy ringing, and it accommodates the high current
demand with minimal voltage loss.

•

Whenever a power dissipating component (e.g., a power
MOSFET) is soldered to a PCB, the liberal use of vias, both
directly on the mounting pad and immediately surrounding
it, is recommended. Two important reasons for this are
improved current rating through the vias, and improved
thermal performance from vias extended to the opposite side
of the PCB where a plane can more readily transfer the heat
to the air. Make a mirror image of any pad being used to
heatsink the MOSFETs on the opposite side of the PCB to
achieve the best thermal dissipation to the air around the
board. To further improve thermal performance, the largest
possible pad area should be used.

•

The output power path should also be routed to encompass
a short distance. The output power path is formed by the
current path through the inductor, the output capacitors,
and the load.

•

For best EMI containment, a solid power ground plane
should be used as one of the inner layers extending fully
under all the power components.

Signal Circuitry

•

The output voltage is sensed and regulated between the
FB pin and the FBRTN pin, which connects to the signal
ground at the load. To avoid differential mode noise pickup
in the sensed signal, the loop area should be small. Therefore
the FB and FBRTN traces should be routed adjacent to each
other on top of the power ground plane back to the controller.

•

The feedback traces from the switch nodes should be con­nected as close as possible to the inductor. The CSREF
signal should be connected to the output voltage at the
inductor nearest to the controller.

ADP3166

REV. 0

–19–

ADP3166

OUTLINE DIMENSIONS

28-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-28)

Dimensions shown in millimeters

9.80

9.70

9.60

28

PIN 1

0.15

0.05

COPLANARITY

0.10

15

4.50

4.40

4.30

141

0.65

BSC

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153AE

SEATING
PLANE

1.20

MAX

6.40 BSC

0.20

0.09

C03589–0–4/03(0)

8ⴗ
0ⴗ

0.75

0.60

0.45

–20–

REV. 0