Datasheet ADP3157 Datasheet (Analog Devices)

5-Bit Programmable Synchronous

a

Controller for Pentium® III Processors

FEATURES
Active Voltage Positioning with Gain and Offset

Adjustment

Optimal Compensation for Superior Load Transient

Response
VRM 8.2, VRM 8.3 and VRM 8.4 Compliant
5-Bit Digitally Programmable 1.3 V to 3.5 V Output
Dual N-Channel Synchronous Driver
Total Output Accuracy ⴞ1% Over Temperature
High Efficiency, Current-Mode Operation
Short Circuit Protection
Overvoltage Protection Crowbar Protects Microprocessors

with No Additional External Components
Power Good Output
SO-16 Package

APPLICATIONS
Desktop PC Power Supplies for:

Pentium II and Pentium III Processor Families

AMD-K6 Processors

VRM Modules

GENERAL DESCRIPTION

The ADP3157 is a highly efficient synchronous buck switching
regulator controller optimized for converting the 5 V main sup­ply into the core supply voltage required by the Pentium III and
other high performance processors. The ADP3157 uses an
internal 5-bit DAC to read a voltage identification (VID) code
directly from the processor, which is used to set the output
voltage between 1.3 V and 3.5 V. The ADP3157 uses a current
mode, constant off-time architecture to drive two external N­channel MOSFETs at a programmable switching frequency that
can be optimized for size and efficiency. It also uses a unique
supplemental regulation technique called active voltage position­ing to enhance load transient performance.

Active voltage positioning results in a dc/dc converter that meets
the stringent output voltage specifications for Pentium II and
Pentium III processors, with the minimum number of output
capacitors and smallest footprint. Unlike voltage-mode and
standard current-mode architectures, active voltage positioning
adjusts the output voltage as a function of the load current so that
it is always optimally positioned for a system transient.

The ADP3157 provides accurate and reliable short circuit pro­tection and adjustable current limiting. It also includes an
integrated overvoltage crowbar function to protect the micro­processor from destruction in case the core supply exceeds the
nominal programmed voltage by more than 15%.

SD

ADP3157

FUNCTIONAL BLOCK DIAGRAM

V

CMPI

SENSE–

REF

AGND

+15%

DELAY

V

REF

V

T1

+5% V

g

m

PWRGD

DRIVE1 DRIVE2 PGND

V

CC

NONOVERLAP

DRIVE

CROWBAR

IN

S

Q

R

V

T2

C

T

CMPT

OFF-TIME
CONTROL

ADP3157

CMP

V

+12V

CC

22mF

1mF

R1

R2

C

COMP

150pF

V

CC

DRIVE1

SD

ADP3157

SENSE+

CMP

SENSE–

DRIVE2

C

T

AGND

VID0–VID4

5-BIT CODE

PGND

V

1nF

Figure 1. 5-Bit Code Typical Application

+5V

IN

SENSE+

–5%

REF

V

REF

REFERENCE

1.20V

DAC

C

IN

+

L

R

SENSE

SENSE–

2R

R

V

1.3V TO

3.5V

+

C

O

VID0

VID1

VID2

VID3

VID4

O

Pentium is a registered trademark of Intel Corporation.
All other trademarks are the property of their respective holders.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

ADP3157–SPECIFICATIONS

(0ⴗC ≤ TA ≤ +70ⴗC, V

= 12 V, VIN = 5 V, unless otherwise noted)

CC

1

Parameter Symbol Conditions Min Typ Max Units

OUTPUT ACCURACY

1.3 V Output Voltage V

O

(Figure 13) 1.283 1.3 1.317 V

2.0 V Output Voltage 1.980 2.0 2.020 V

3.5 V Output Voltage 3.465 3.5 3.535 V

I

OUTPUT VOLTAGE LINE ∆V

O

= 10 A (Figure 2)

LOAD

REGULATION VIN = 4.75 V to 5.25 V 0.05 %

INPUT DC SUPPLY CURRENT

Normal Mode I
Shutdown T

2

Q

VSD = 0.6 V 4.1 5.5 mA

= +25°C, VID Pins Floating 140 250 µA

A

CURRENT SENSE THRESHOLD

VOLTAGE V

SENSE(TH)VSENSE–

VID0–VID4 THRESHOLD VID

(TH)

Forced to V

– 3% 125 145 165 mV

OUT

Low 0.6 V
High 2.0 V

VID0–VID4 INPUT CURRENT I

VID0–VID4 PULL-UP RESISTANCE R

C

PIN DISCHARGE CURRENT I

T

OFF-TIME t

DRIVER OUTPUT TRANSITION t

VID

VID

12

OFF

, t

R

F

TIME T

POSITIVE POWER GOOD TRIP POINT3V

NEGATIVE POWER GOOD TRIP POINT3V

POWER GOOD RESPONSE TIME t

CROWBAR TRIP POINT V

PWRGD

PWRGD

PWRGD

CROWBAR

VID = 0 V 110 220 µA

20 30 kΩ

T

= +25°C

A

in Regulation 65 µA

V

OUT

V

= 0 V 2 10 µA

OUT

C

= 150 pF 1.8 2.45 3.2 µs

T

CL = 7000 pF (Drive 1, 2)

= +25°C 120 200 ns

A

% Above Output Voltage 5 8 %

% Below Output Voltage –8 –5 %

500 µs

% Above Output Voltage 9 15 24 %

ERROR AMPLIFIER

OUTPUT IMPEDANCE RO

ERR

275 kΩ

ERROR AMPLIFIER

TRANSCONDUCTANCE g

m(ERR)

2.2 mmho

ERROR AMPLIFIER MINIMUM

OUTPUT VOLTAGE V

CMPMIN

V

SENSE+

Forced to V

+ 3% 0.8 V

OUT

ERROR AMPLIFIER MAXIMUM

OUTPUT VOLTAGE V

CMPMAXVSENSE+

ERROR AMPLIFIER BANDWIDTH –3 dB BW

ERR

CMP = Open 500 kHz

Forced to V

– 3% 2.4 V

OUT

SHUTDOWN (SD) PIN

Low Threshold SD
High Threshold SD
Input Current SD

NOTES

1

All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.

2

Dynamic supply current is higher due to the gate change being delivered to the external MOSFETs.

3

The trip point is for the output voltage coming into regulation.

Specifications subject to change without notice.

L

H

IC

Part Active 0.6 V
Part in Shutdown 2.0 V

10 µA

–2–

REV. A

ADP3157

TOP VIEW

(Not to Scale)

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

ADP3157

SENSE–

VID2
VID3
VID4

SD

AGND

SENSE+

C

T

CMP

PGND
DRIVE1

PWRGD

V

CC

DRIVE2

VID1

VID0

WARNING!

ESD SENSITIVE DEVICE

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1–4, 16 VID1–VID4, Voltage Identification DAC Inputs. These pins are pulled up to an internal reference, providing a logic

VID0 one if left open. The DAC output programs the SENSE– regulation voltage from 1.3 V to 3.5 V. Leav-

ing all five DAC inputs open results in placing the ADP3157 into shutdown.
5 AGND Analog Ground. All internal signals of the ADP3157 are reference to this ground.
6 SD Shutdown. A logic high will place the ADP3157 in shutdown and disable both outputs. This pin is

internally pulled down.
7 SENSE– Connects to the internal resistor divider that senses the output voltage. This pin is also the (–) input

for the current comparator.
8 SENSE+ The (+) input for the current comparator. The output current is sensed as a voltage at this pin with

respect to SENSE–.
9C

T

10 CMP Error Amplifier output and compensation point. The voltage at this output programs the output cur-

11 PWRGD Power Good. An open drain signal indicates that the output voltage is within a ±5% regulation band.

12 V

CC

13 DRIVE2 Gate Drive for the (bottom) synchronous rectifier N-channel MOSFET. The voltage at DRIVE2

14 DRIVE1 Gate Drive for the buck switch N-channel MOSFET. The voltage at DRIVE1 swings from ground to

15 PGND Power Ground. The drivers turn off the buck and synchronous MOSFETs by discharging their gate

External capacitor CT connection to ground sets the off time of the device.

rent control level between the SENSE pins.

Supply Voltage to ADP3157.

swings from ground to V

V

.

CC

CC

.

capacitances to this pin. PGND should have a low impedance path to the source of the synchronous

MOSFET.

ABSOLUTE MAXIMUM RATINGS*

PIN CONFIGURATION

Input Supply Voltage (VCC) . . . . . . . . . . . . . . –0.3 V to +16 V

VID0–VID4, SD, PWRGD, CMP, C

DRIVE1, DRIVE2, SENSE+, SENSE– . . . . . . –0.3 V to V

. . . . . . . –0.3 V to V

T

CC

CC

Operating Ambient Temperature Range . . . . . . 0°C to +70°C

Junction Temperature Range . . . . . . . . . . . . . . 0°C to +150°C

θ

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110°C/W

JA

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+300°C

*This is a stress rating only; operation beyond these limits can cause the device to

be permanently damaged.

ORDERING GUIDE

Temperature Package Package

Model Range Description Options

ADP3157JR 0°C to +70°C 16-Lead SOIC R-16A/SO-16

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADP3157 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. A

–3–

ADP3157

mP

SYSTEM

100kV

22V

ESR = 25mV EACH

2200mF 33

(25V)

22mF

ADP3157

1

VID1

2

VID2

3

VID3

4

VID4

5

AGND

6

SD

7

SENSE–

8

SENSE+

1nF

VID0

PGND
DRIVE1
DRIVE2

V

PWRGD

CMP

16

15

14

13

12

CC

11

10

9

C

T

C

T

200pF

R1
105kV

R2

18.2kV

1mF

C

COMP

3600pF

220V

IRL3803

IRL3803

L1

1.7mH

10BQ015

R

5mV

SENSE

220V

Figure 2. Typical VRM8.2/8.3/8.4 Compliant Core DC/DC Converter Circuit

SD

V

DRIVE1 DRIVE2 PGND

CC

14

12

NONOVERLAP

6

13

DRIVE

CROWBAR

IN

AGND PWRGD

5

V

+15%

REF

V

REF

+5% V

CMPI

S

Q

R

V

T2

CMPT

C

T

OFF-TIME

CONTROL

SENSE–

11

V

REF

T1

DELAY

–5%

SENSE+

g

m

2R

V

REF

SENSE–

ADP3157

REFERENCE

1.20V

R

DAC

L2

1mH

1mF

ESR = 25mV EACH

2200mF 3 6

(25V)

VID0

1

VID1

2

VID2

3

VID3

4

VID4

VCC +12V

VIN +5V
+5V RTN

+12V RTN

V

O

1.3V TO

3.5V
0-19A

RTN

10

CMP

Figure 3. Functional Block Diagram

–4–

REV. A

Typical Performance Characteristics–

ADP3157

100

95

90

85

80

EFFICIENCY – %

75

70

65

1.4 2.8 144.2 5.6 7 9.8 11.2 12.68.4

V

= 3.5V

OUT

V

= 1.3V

OUT

OUTPUT CURRENT – Amps

V

OUT

V

= 2.0V

OUT

SEE FIGURE 2

= 2.8V

Figure 4. Efficiency vs. Output
Current

SEE FIGURE 2

PRIMARY

N-DRIVE

1

2

DRIVER OUTPUT

SECONDARY

N-DRIVE

DRIVER OUTPUT

450
400
350

300
250
200
150

FREQUENCY – kHz

100

50

0

50 100 800

200 300 400 500 600 700
TIMING CAPACITOR – pF

Figure 5. Frequency vs. Timing
Capacitor

SEE FIGURE 2

VCC = +12V

= +5V

V

IN

I

= 10A

OUT

45

40
35
30
25
20
15

SUPPLY CURRENT – mA

10

5
0

45 397

Q

GATE(TOTAL)

58 83 134

OPERATING FREQUENCY – kHz

= 100nC

Figure 6. Supply Current vs. Oper­ating Frequency

OUTPUT VOLTAGE
20mV/DIV

OUTPUT CURRENT
19A TO 1A

DRIVE 1 AND 2 = 5V/DIV

500ns/DIV

Figure 7. Gate Switching Waveforms

OUTPUT VOLTAGE
20mV/DIV

OUTPUT CURRENT
1A TO 19A

10ms/DIV

Figure 10. Load Transient Response,
1 A–19 A of Figure 2 Circuit

100ns/DIV

Figure 8. Driver Transition
Waveforms

VCC VOLTAGE

5V/DIV

3

REGULATOR

OUTPUT VOLTAGE

1V/DIV

4

10ms/DIV

Figure 11. Power-On Start-Up
Waveform

10ms/DIV

Figure 9. Load Transient Response,
19 A–1 A of Figure 2 Circuit

25

TA = +258C
SEE FIGURE 13

20

15

10

NUMBER OF PARTS

5

0

–0.4

–0.5

–0.3

–0.45

–0.55

–0.35

OUTPUT ACCURACY – %

–0.2

–0.25

–0.1

–0.15

0

–0.05

0.05

0.1

0.2

0.3

0.4

0.25

0.35

0.45

0.5

0.15

Figure 12. Output Accuracy
Distribution, V

OUT

= 2.0 V

REV. A

–5–

ADP3157

12V

SENSE+
SENSE–

PGNDAGND

OP27

0.1mF

V

DRIVE1
DRIVE2

CC

1mF

0.1mF

V

OUT

1kV

4700pF

1.2V

SD

CMP

C

T

100kV

ADP3157

Figure 13. Closed-Loop Test Circuit for Accuracy

THEORY OF OPERATION

The ADP3157 uses a current-mode, constant-off-time control
technique to switch a pair of external N-channel MOSFETs in a
synchronous buck topology. Constant off-time operation offers
several performance advantages, including that no slope com­pensation is required for stable operation. A unique feature of
the constant-off-time control technique is that since the off-time
is fixed, the converter’s switching frequency is a function of the
ratio of input voltage to output voltage. The fixed off-time is
programmed by the value of an external capacitor connected to

pin. The on-time varies in such a way that a regulated

the C

T

output voltage is maintained as described below in the cycle-by­cycle operation. Under fixed operating conditions the on-time
does not vary, and it only varies slightly as a function of load.
This means that switching frequency is fairly constant in stan­dard VRM applications. In order to maintain a ripple current in
the inductor that is independent of the output voltage (which
also helps control losses and simplify the inductor design), the
off-time is made proportional to the value of the output voltage.
Normally, the output voltage is constant and therefore the off­time is constant as well.

Active Voltage Positioning

The output voltage is sensed at the SENSE– pin. A voltage-error
amplifier, (g

), amplifies the difference between the output voltage

m

and a programmable reference voltage. The reference voltage is
programmed to between 1.3 V and 3.5 V by an internal 5-bit
DAC, which reads the code at the voltage identification (VID)
pins. Refer to Table I for output voltage vs. VID pin code infor­mation. A unique supplemental regulation technique called
active voltage positioning with optimal compensation adjusts
the output voltage as a function of the load current so that it
is always optimally positioned for a load transient. Standard
(passive) load voltage positioning, sometimes recommended for
use with other architectures, has poor dynamic performance
which renders it ineffective under the stringent repetitive tran­sient conditions specified in Intel VRM documents. Conse­quently, such techniques do not allow the minimum possible
number of output capacitors to be used. Optimally compensated
active voltage positioning as used in the ADP3157 provides a
bandwidth for transient response that is limited only by parasitic
output inductance. This yields optimal load transient response
with the minimum number of output capacitors.

Table I. Output Voltage vs. VID Code

VID4 VID3 VID2 VID1 VID0 V

OUT

011111.30

011101.35

011011.40

011001.45

010111.50

010101.55

010011.60

010001.65

001111.70

001101.75

001011.80

001001.85

000111.90

000101.95

000012.00

000002.05
11111No CPU—Shutdown

111102.10

111012.20

111002.30

110112.40

110102.50

110012.60

110002.70

101112.80

101102.90

101013.00

101003.10

100113.20

100103.30

100013.40

100003.50

Cycle-by-Cycle Operation

During normal operation (when the output voltage is regulated),
the voltage-error amplifier and the current comparator (CMPI)
are the main control elements. (See the block diagram of Figure

3.) During the on-time of the high side MOSFET, CMPI moni­tors the voltage between the SENSE+ and SENSE– pins. When
the voltage level between the two pins reaches the threshold level

, the high side drive output is switched to ground, which

V

T1

turns off the high side MOSFET. The timing capacitor C

is

T

then discharged at a rate determined by the off-time controller.
While the timing capacitor is discharging, the low side drive
output goes high, turning on the low side MOSFET. When the
voltage level on the timing capacitor has discharged to the thresh­old voltage level V

, comparator CMPT resets the SR flip-flop.

T2

The output of the flip-flop forces the low side drive output to go
low and the high side drive output to go high. As a result, the low
side switch is turned off and the high side switch is turned on.
The sequence is then repeated. As the load current increases, the
output voltage starts to decrease. This causes an increase in the
output of the voltage-error amplifier, which, in turn, leads to an
increase in the current comparator threshold V

, thus tracking

T1

the load current. To prevent cross conduction of the external
MOSFETs, feedback is incorporated to sense the state of the driver
output pins. Before the low side drive output can go high, the
high side drive output must be low. Likewise, the high side drive
output is unable to go high while the low side drive output is high.

–6–

REV. A

ADP3157

Power Good

The ADP3157 has an internal monitor that senses the output
voltage and drives the PWRGD pin of the device. This pin is an
open drain output whose high level (when connected to a pull­up resistor) indicates that the output voltage has been within a

±5% regulation band of the targeted value for more than 500 µs.

The PWRGD pin will go low if the output is outside the regula-

tion band for more than 500 µs.

Output Crowbar

An added feature of using an N-channel MOSFET as the syn­chronous switch is the ability to crowbar the output with the
same MOSFET. If the output voltage is 15% greater than the
targeted value, the ADP3157 will turn on the lower MOSFET,
which will current-limit the source power supply or blow its
fuse, pull down the output voltage, and thus save the micropro­cessor from destruction. The crowbar function releases at ap­proximately 50% of the nominal output voltage. For example, if
the output is programmed to 2.0 V, but is pulled up to 2.3 V or
above, the crowbar will turn on the lower MOSFET. If in this
case the output is pulled down to less than 1.0 V, the crowbar
will release, allowing the output voltage to recover to 2.0 V if
the fault condition has been removed.

Shutdown

The ADP3157 has a shutdown (SD) pin that is pulled down by
an internal resistor. In this condition the device functions nor­mally. This pin should be pulled high to disable the output drives.

APPLICATION INFORMATION
Specifications for a Design Example

The design parameters for a typical 550 MHz Pentium III appli­cation (Figure 2) are as follows:

Input voltage: V
Auxiliary input: V
Output voltage: V

= 5 V

IN

CC

= 2.0 V

O

= 12 V

Maximum output current:

I

= 17.0 A dc

OMAX

Minimum output current:

I

= 1.0 A dc

OMIN

Static tolerance of the supply voltage for the processor core:

∆V

= +70 mV

OST+

∆V

= –70 mV

OST–

Transient tolerance (for less than 2 µs) of the supply voltage for

the processor core when the load changes between the minimum

and maximum values with a di/dt of 30 A/µs:

∆V

= +140 mV

OTR+

∆V

= –140 mV

OTR–

Input current di/dt when the load changes between the mini-

mum and maximum values: less than 8 A/µs

The above requirements correspond to Intel’s published power
supply requirements based on Intel Pentium III specifications.

C

Selection for Operating Frequency

T

The ADP3157 uses a constant-off-time architecture with t

OFF

determined by an external timing capacitor CT. Each time the
high side N-channel MOSFET switch turns on, the voltage
across C

is reset to approximately 3.3 V. During the off time,

T

C

is discharged by a constant current of 65 µA. Once C

T

T

reaches 2.3 V, a new on-time cycle is initiated. The value of the
off-time is calculated using the continuous-mode operating
frequency. Assuming a nominal operating frequency of f

NOM

=
200 kHz at an output voltage of 2.0 V, the corresponding off
time is:





V

1



Vf



O




IN NOM

=1

30–.µ

s

t

OFF

=

The timing capacitor can be calculated from the equation:

tA

×

65

OFF

C

=

T

µ

V

1

pF

=

200

The converter operates at the nominal operating frequency only
at the above specified V

and at light load. At higher V

OUT

OUT

or
heavy load, the operating frequency decreases due to the para­sitic voltage drops across the power devices. The actual mini­mum frequency at V

= 2.0 V is calculated to be 180 kHz (see

OUT

Equation 1), where:

I

IN

R

IN

is the input dc current
(assuming an efficiency of 90%, I

IN

is the resistance of the input filter

= 7.5 A)

(estimated value: 7 mΩ)

R

DS(ON)HSF

is the resistance of the high side MOSFET

(estimated value: 10 mΩ)

R

DS(ON)LSF

is the resistance of the low side MOSFET

(estimated value: 10 mΩ)

R

SENSE

is the resistance of the sense resistor

(estimated value: 5 mΩ)

R

L

is the resistance of the inductor

(estimated value: 6 mΩ)

C

Selection–Determining the ESR

OUT

The required ESR and capacitance drive the selection of the
type and quantity of the output capacitors. The ESR must be
small enough that both the resistive voltage deviation due to a
step change in the load current and the output ripple voltage
stay below the values defined in the specification of the supplied
microprocessor. The capacitance must be large enough that the
output is held up while the inductor current ramps up or down
to the value corresponding to the new load current.

The total static tolerance of the Pentium III processor is 140 mV.

Taking into account the ±1% setpoint accuracy of the ADP3157,

and assuming a 0.5% (or 10 mV) peak-to-peak ripple, the al­lowed static voltage deviation of the output voltage when the
load changes between the minimum and maximum values is

90 mV. Assuming a step change of ∆I = I

OMAX–IOMIN

= 16 A,
and allocating all of the total allowed static deviation to the
contribution of the ESR sets the following limit:

mV

R ESR

E MAX MAX()

90

1

16

A

m

.===

56 Ω

The output filter capacitor must have an ESR of less than 5.6 mΩ.

One can use, for example, two SP-Type OS-CON capacitors

from Sanyo, with 2200 µF capacitance, 7 V voltage rating, and

REV. A

f

=×

MIN

VIRI R R RV

1

t

VIRI R R RR

OFF

––( )–

IN IN IN OMAX DS ON HSF SENSE L O

––( – )

IN IN IN OMAX DS ON HSF SENSE L DS ON LSF

() ()

++

()

++

–7–

=

180

kHz

(1)

ADP3157

10 mΩ ESR. The two capacitors have a total ESR of 5.0 mΩ when

connected in parallel, which gives adequate margin.

Inductor Selection

The minimum inductor value can be calculated from ESR, off­time, dc output voltage and allowed peak-to-peak ripple voltage
using the following equation:

Vt R

L

MIN

O OFF E MAX

1

V

()

,

RIPPLE p p

−

Vsm

20 3 53

××

..

10

µ

mV

Ω

32==

=

.

µ

H

The minimum inductance gives a peak-to-peak ripple current of

2.55 A, or 15% of the maximum dc output current I

OMAX

.

The inductor peak current in normal operation is:

I

LPEAK

= I

OMAX

+ I

/2 = 19.5 A

RPP

The inductor valley current is:

I

LVALLEY

= I

LPEAK

– I

= 14.5 A

RPP

The inductor for this application should have an inductance

of 3.3 µH at full load current and should not saturate at the

worst-case overload or short circuit current at the maximum
specified ambient temperature.

Tips for Selecting the Inductor Core

Ferrite designs have very low core loss, so the design should
focus on copper loss and on preventing saturation. Molypermalloy,
or MPP, is a low loss core material for toroids, and it yields the
smallest size inductor, but MPP cores are more expensive than

ferrite cores or the Kool Mµ

C

Selection–Determining the Capacitance

OUT

®

cores from Magnetics, Inc.

The minimum capacitance of the output capacitor is determined
from the requirement that the output be held up while the in­ductor current ramps up (or down) to the new value. The mini­mum capacitance should produce an initial dv/dt which is equal
(but opposite in sign) to the dv/dt obtained by multiplying the
di/dt in the inductor and the ESR of the capacitor:

(/)

×

0 8 17 1 0 8

=

AA

()

×

52030

Ωµ

mVH

–.

II

()

C

MIN

OMAX OMIN

=

Rdidt

E

×

–.

(. / . )

=µ

3840

F

In the above equation the value of di/dt is calculated as the
smaller voltage across the inductor (i.e., V
V

) divided by the maximum inductance inductor. The two

OUT

IN–VOUT

rather than

parallel-connected 2200 µF capacitors have a total capacitance
of 4400 µF, so the minimum capacitance requirement is met

with ample margin.

R

SENSE

The value of R

is based on the required output current.

SENSE

The current comparator of the ADP3157 has a threshold range
that extends from 0 mV to 125 mV (minimum). Note that the
full 125 mV range cannot be used for the maximum specified
nominal current, as headroom is needed for current ripple, and
transients.

The current comparator threshold sets the peak of the inductor
current yielding a maximum output current, I

, which equals

OMAX

the peak value less half of the peak-to-peak ripple current. Solv­ing for R

, allowing a 20% margin for overhead, and using

SENSE

the minimum current sense threshold of 125 mV, yields:

R

= (125 mV)/[1.2(I

SENSE

OMAX

+ I

RPP

/2)] = 5.0 mΩ

Once R
I

SC(PK)

I

has been chosen, the peak short-circuit current

SENSE

can be predicted from the following equation:

= (145 mV)/R

SC(PK)

= (145 mV)/(5.0 mΩ) = 29 A

SENSE

The actual short-circuit current is less than the above calculated
I

value because the off-time rapidly increases when the

SC(PK)

output voltage drops below 1 V. The relationship between the
off-time and the output voltage is:

CV

×

1

≈

360

T

V

O

k

A

+

2

µ

Ω

t

OFF

With a short circuit across the output, the off-time will be about

70 µs. During that time the inductor current gradually decays.

The amount of decay depends on the L/R time constant in the

output circuit. With an inductance of 3.3 µH and total resis-
tance of 22 mΩ, the time constant will be 73 µs. This yields an

average short-circuit current of about 20 A. To safely carry the
short-circuit current, the sense resistor must have a power rating
of at least 20 A

2

× 5.0 mΩ = 2.0 W.

Current Transformer Option

An alternative to using a low value and high power current sense
resistor is to reduce the sensed current by using a low cost cur­rent transformer and a diode. The current can then be sensed
with a small-size, low cost SMT resistor. Using a transformer
with one primary and 50 secondary turns reduces the worst-case
resistor dissipation to a few mW. Another advantage of using
this option is the separation of the current and voltage sensing,
which makes the voltage sensing more accurate.

Power MOSFETs

Two external N-channel power MOSFETs must be selected for
use with the ADP3157, one for the main switch, and an identi­cal one for the synchronous switch. The main selection param­eters for the power MOSFETs are the threshold voltage V
and the on resistance R

DS(ON)

.

GS(TH)

The minimum input voltage dictates whether standard threshold
or logic-level threshold MOSFETs must be used. For V
standard threshold MOSFETs (V
V

is expected to drop below 8 V, logic-level threshold MOSFETs

IN

(V
MOSFETs with V
of V

The maximum output current I

< 2.5 V) are strongly recommended. Only logic-level

GS(TH)

should be used.

CC

ratings higher than the absolute maximum

GS

OMAX

< 4 V) may be used. If

GS(TH)

determines the R

> 8 V,

IN

DS(ON)

requirement for the two power MOSFETs. When the ADP3157
is operating in continuous mode, the simplifying assumption can
be made that one of the two MOSFETs is always conducting
the average load current. For V

IN

= 5 V and V

= 2.8 V, the

OUT

maximum duty ratio of the high side FET is:

D

MAXHF

= (1–f

MIN

× t

) = (1 kHz–180 kHz × 3.0 µs) = 46%

OFF

The maximum duty ratio of the low side (synchronous rectifier)
FET is:

D

MAXLF

= 1 – D

MAXHF

= 54%

The maximum rms current of the high side FET is:

I

RMSHS

= [D

MAXHF

(I

LVALLEY

2 + I

LPEAK

2 + I

LVALLEYILPEAK

)/3]

0.5

= 11.6 A rms

–8–

REV. A

ADP3157

The maximum rms current of the low side FET is:

I

RMSLS

= [D

MAXLF

(I

LVALLEY

2 + I

LPEAK

2 + I

LVALLEYILPEAK

)/3]

0.5

= 12.5 A rms

The R

for each FET can be derived from the allowable

DS(ON)

dissipation. If 5% of the maximum output power is allowed for
FET dissipation, the total dissipation will be:

P

FETALL

= 0.05 VOI

OMAX

= 1.7 W

Allocating half of the total dissipation for the high side FET and
half for the low side FET, the required minimum FET resis­tances will be:

R

DS(ON)HSF(MIN)

R

DS(ON)LSF(MIN)

= 0.85 W/(11.6 A)2 = 6 m

= 0.85 W/(12.5 A)2 = 5.5 m

Ω

Ω

Note that there is a trade-off between converter efficiency and
cost. Larger FETs reduce the conduction losses and allow
higher efficiency, but increase the system cost. If efficiency is
not a major concern, the International Rectifier IRL3803 is an
economical choice for both the high side and low side positions.
Those devices have an R

of 6 mΩ at V

DS(ON)

= 10 V and at

GS

+25°C. The low side FET is turned on with at least 10 V. The

high side FET, however, is turned on with only 12 V – 5 V = 7 V.
The specified R

at the expected highest FET junction

DS(ON)

temperature of +140°C must be modified by:

R

DS(ON)MULT

Using this multiplier, the expected R

= 1.7

at +140°C is 1.7 ×

DS(ON)

6 mΩ = 10 mΩ.

The high side FET dissipation is:

P

DFETHS

= I

RMSHS

2

R

DS(ON)

+ 0.5 VINI

LPEAKQGfMIN/IG

~ 2.3 W

where the second term represents the turn-off loss of the FET.
(In the second term, Q
the gate for turn-off and I
sheet, Q

is a 41 nC and the peak gate drive current provided

GS

is the gate charge to be removed from

GS

is the gate current. From the data

G

by the ADP3157 is about 1 A.)

The low side FET dissipation is:

P

DFETLS

= I

RMSLS

2

R

DS(ON)

= 1.6 W

(Note that there are no switching losses in the low side FET.)

To maintain an acceptable MOSFET junction temperature,
proper heat sinks should be used. The Thermalloy 6030 heat

sink has a thermal impedance of 13°C/W with convection cool-

ing. With this heat sink, the junction-to-ambient thermal imped-

ance of the chosen high side FET θ

will be 13°C/W (heat

JAHS

sink-to-ambient) + 2°C/W (junction-to-case) + 0.5°C/W (case­to-heat sink) = 15.5°C/W.

At full load, and at +50°C ambient temperature, the junction

temperature of the high side FET is:

T

JHSMAX

= TA +

θ

JAHS PDFETHS

= +86°C

The same heat sink may be used for the low side FET, e.g., the

Thermalloy type 7141 (θ = 20.3°C/W). With this heat sink, the

junction temperature of the low side FET is:

T

JLSMAX

= TA +

θ

JALS PDFETLS

= +82.5°C

All of the above-calculated junction temperatures are safely

below the +175°C maximum specified junction temperature of

the selected FETs.

The maximum operating junction temperature of the ADP3157
is calculated as follows:

T

where

θ

is the junction-to-ambient thermal impedance of the

JA

ADP3157 and P

is equal to 110°C/W and I

= TA +

JICMAX

is the drive power. From the data sheet, θ

DR

θ

(IICVCC + PDR)

JA

= 2.7 mA. PDR can be calculated as

IC

JA

follows:

P

DR

= (C

RSS

+ C

ISS)VCC

2

f

MAX

= 307 mW

The result is:

T

= +86°C

JICMAX

CIN Selection and Input Current di/dt Reduction

In continuous inductor-current mode, the source current of the
high side MOSFET is a square wave with a duty ratio of V

. To keep the input ripple voltage at a low value, one or more

V

lN

OUT

/

capacitors with low equivalent series resistance (ESR) and ad­equate ripple-current rating must be connected across the input
terminals. The maximum rms current of the input bypass ca­pacitors is:

I

CINRMS

= 0.5 I

= 8.5 A rms

OMAX

For an FA-type capacitor with 2700 µF capacitance and
10 V voltage rating, the ESR is 34 mΩ and the allowed ripple
current at 100 kHz is 1.94 A. At +105°C, at least four such

capacitors must be connected in parallel to handle the calculated

ripple current. At +50°C ambient, however, a higher ripple

current can be tolerated, so three capacitors in parallel are
adequate.

The ripple voltage across the three paralleled capacitors is:

V

CINRPL

= I

[ESRIN/3 +D

OMAX

MAXHF

/(3 CIN f

MIN

)] =

100 mV p-p

To further reduce the effect of the ripple voltage on the system
supply voltage bus and to reduce the input-current di/dt to

below the recommended maximum of 0.1 A/µs, an additional
small inductor (L > 1.7 µH @ 10 A) should be inserted between

the converter and the supply bus (see Figure 2).

Feedback Loop Compensation Design for Active Voltage
Positioning

Optimized compensation of the ADP3157 allows the best pos­sible containment of the peak-to-peak output voltage deviation.
Any practical switching power converter is inherently limited by
the inductor in its output current slew rate to a value much less
than the slew rate of the load. Therefore, any sudden change of
load current will initially flow through the output capacitors,
and this will produce an output voltage deviation equal to the
ESR of the output capacitor array times the load current change.

REV. A

–9–

ADP3157

To correctly implement active voltage positioning, the low fre­quency output impedance (i.e., the output resistance) of the
converter should be made equal to the maximum ESR of the
output capacitor array. This can be achieved by having a single
pole roll-off of the voltage gain of the g

error amplifier, where

m

the pole frequency coincides with the ESR zero of the output
capacitor. A gain with single pole roll-off requires that the g

m

amplifier output pin be terminated by the parallel combination
of a resistor and capacitor. The required resistor value can be
calculated from the equation:

kRt

×275

Ω

R

=

C

kRt

275

Ω –

TOTAL

TOTAL

where

kR I

××16 4.–Ω

Rt

TOTAL

=

CS OMAX

VV

HI LO

and where the quantities 16.4 kΩ and 275 kΩ are characteristics

of the ADP3157 and the value of the current sense resistor, R

CS

,

has already been determined as above.

Although a single termination resistor equal to R

would yield

C

the proper voltage positioning gain, the dc biasing of that resis­tor would determine how the regulation band is centered (i.e.,
offset). Note that sometimes the specified regulation band is
asymmetrical with respect to the nominal VID voltage. With the
ADP3157, the offset is already considered as part of the design
procedure—no special provision is required. To accomplish the
dc biasing, it is simplest to use two resistors to terminate the g

m

amplifier output, with the lower resistor tied to ground and the
upper resistor to the 12 V supply of the IC. The values of these
resistors can be calculated using:

V

RR

=×

UPPER C

DIV

V

OS

and

V

RR

=×

LOWER C

where V
ommended 12 V), and V

is the resistor divider supply voltage (e.g., the rec-

DIV

is the offset voltage required on the

OS

amplifier to produce the desired offset at the output. V
calculated using Equation 2 below, where V

OS

VV

–

DIV OS

OUT(OS)

is

OS

is the offset
from the nominal VID-programmed value to the center of the
specified regulation window for the output voltage. (Note this
may be either positive or negative.) For clarification, that offset
is given by:

Finally, the compensating capacitance is determined from the
equality of the pole frequency of the error amplifier gain and the
zero frequency of the impedance of the output capacitor:

C ESR

×

C

COMP

O

=

Rt

TOTAL

Trade-Offs Between DC Load Regulation and AC Load
Regulation

Casual observation of the circuit operation—e.g., with a voltmeter
—would make it appear that the dc load regulation appears
to be rather poor compared to a conventional regulator. This
would be especially noticeable under very light or very heavy
loads where the voltage is “positioned” near one of the extremes
of the regulation window rather than near the nominal center
value. It must be noted and understood that this low gain char­acteristic (i.e., loose dc load regulation) is inherently required to
allow improved transient containment (i.e., to achieve tighter ac
load regulation). That is, the dc load regulation is intentionally
sacrificed (but kept within specification) in order to minimize
the number of capacitors required to contain the load transients
produced by the CPU.

LAYOUT AND COMPONENT PLACEMENT GUIDELINES

The following guidelines are recommended for optimal perfor­mance of a switching regulator in a PC system:

General Recommendations

1. For best results, a four-layer (minimum) PCB is recom­mended. This should allow the needed versatility for con­trol circuitry interconnections with optimal placement, a
signal ground plane, power planes for both power ground
and the input power (e.g., 5 V), and wide interconnection
traces in the rest of the power delivery current paths. Each
square unit of 1 ounce copper trace has a resistance of
~0.53 mW at room temperature.

2. Whenever high currents must be routed between PCB
layers, vias should be used liberally to create several parallel
current paths so that the resistance and inductance intro­duced by these current paths is minimized and the via cur­rent rating is not exceeded.

3. The power and ground planes should overlap each other as
little as possible. It is generally easiest (although not neces­sary) to have the power and signal ground planes on the
same PCB layer. The planes should be connected nearest
to the first input capacitor where the input ground current
flows from the converter back to the power source (e.g.,
5 V).

VVVVID

OUT OS HI LO()

1

()–=+

2

where VHI and VLO are the respective upper and lower limits
allowed for regulation.

V

OS

R

=×+

Rt

TOTAL



C



08

VV





OUT OS

()



Rt

TOTAL TOTAL



136

.

k





–.



ΩΩ



17



Rt

V



275





+

6.

RI

CS OMAX



k



–10–







(2)

REV. A

ADP3157

4. If critical signal lines (including the voltage and current
sense lines of the ADP3157) must cross through power
circuitry, it is best if a signal ground plane can be inter­posed between those signal lines and the traces of the
power circuitry. This serves as a shield to minimize noise
injection into the signals at the expense of making signal
ground a bit noisier.

5. The PGND pin of the ADP3157 should connect first to a
ceramic bypass capacitor (on the V
power ground plane using the shortest possible trace. How­ever, the power ground plane should not extend under
other signal components, including the ADP3157 itself. If
necessary, follow the preceding guideline to use the signal
plane as a shield between the power ground plane and the
signal circuitry.

6. The AGND pin of the ADP3157 should connect first to the
timing capacitor (on the C
ground plane. In cases where no signal ground plane can be
used, short interconnections to other signal ground cir­cuitry in the power converter should be used—the compen­sation capacitor being the next most critical.

7. The output capacitors of the power converter should be
connected to the signal ground plan even though power
current flows in the ground of these capacitors. For this
reason, it is advised to avoid critical ground connections (e.g.,
the signal circuitry of the power converter) in the signal
ground plane between the input and output capacitors. It
is also advised to keep the planar interconnection path short
(i.e., have input and output capacitors close together).

8. The output capacitors should also be connected as closely
as possible to the load (or connector) that receives the
power (e.g., a microprocessor core). If the load is distrib­uted, the capacitors also should be distributed, and gen­erally in proportion to where the load tends to be more
dynamic.

9. Absolutely avoid crossing any signal lines over the switching
power path loop, described below.

Power Circuitry

10. The switching power path should be routed on the PCB to
encompass the smallest possible area in order to minimize
radiated switching noise energy (i.e., EMI). Failure to take
proper precaution often results in EMI problems for the
entire PC system as well as noise related operational prob­lems in the power converter control circuitry. The switching
power path is the loop formed by the current path through
the input capacitors, the two FETs, and the power Schottky
diode if used, including all interconnecting PCB traces and
planes. The use of short and wide interconnection traces is
especially critical in this path for two reasons: it minimizes
the inductance in the switching loop, which can cause high­energy ringing, and it accommodates the high current de­mand with minimal voltage loss.

11. A power Schottky diode (1 ~ 2 A dc rating) placed from the
lower FET’s source (anode) to drain (cathode) will help to
minimize switching power dissipation in the upper FET. In
the absence of an effective Schottky diode, this dissipation
occurs through the following sequence of switching events.
The lower FET turns off in advance of the upper FET
turning on (necessary to prevent cross-conduction). The

pin), and then into the signal

T

pin) and then into the

CC

circulating current in the power converter, no longer find­ing a path for current through the channel of the lower
FET, draws current through the inherent body-drain diode
of the FET. The upper FET turns on, and the reverse
recovery characteristic of the lower FET’s body-drain diode
prevents the drain voltage from being pulled high quickly.
The upper FET then conducts very large current while it
momentarily has a high voltage forced across it, which
translates into added power dissipation in the upper FET.
The Schottky diode minimizes this problem by carrying a
majority of the circulating current when the lower FET is
turned off, and by virtue of its essentially nonexistent re­verse recovery time.

12. A small ferrite bead inductor placed in series with the drain
of the lower FET can also help to reduce this previously
described source of switching power loss.

13. Whenever a power dissipating component (e.g., a power
MOSFET) is soldered to a PCB, the liberal use of vias,
both directly on the mounting pad and immediately sur­rounding it, is recommended. Two important reasons for
this are: improved current rating through the vias (if it is a
current path), and improved thermal performance—espe­cially if the vias extended to the opposite side of the PCB
where a plane can more readily transfer the heat to the air.

14. The output power path, though not as critical as the switch­ing power path, should also be routed to encompass a small
area. The output power path is formed by the current path
through the inductor, the current sensing resistor, the out­put capacitors, and back to the input capacitors.

15. For best EMI containment, the power ground plane should
extend fully under all the power components except the
output capacitors. These are: the input capacitors, the
power MOSFETs and Schottky diode, the inductor, the
current sense resistor and any snubbing elements that
might be added to dampen ringing. Avoid extending the
power ground under any other circuitry or signal lines,
including the voltage and current sense lines.

Signal Circuitry

16. The output voltage is sensed and regulated between the
AGND pin (which connects to the signal ground plane)
and the SENSE– pin. The output current is sensed (as a
voltage) and regulated between the SENSE– pin and the
SENSE+ pin. In order to avoid differential mode noise
pickup in those sensed signals, their loop areas should be
small. Thus the SENSE– trace should be routed atop the
signal ground plane, and the SENSE+ and SENSE– traces
should be routed as a closely coupled pair (SENSE+ should
be over the signal ground plane as well).

17. The SENSE+ and SENSE– traces should be Kelvin con­nected to the current sense resistor so that the additional
voltage drop due to current flow on the PCB at the current
sense resistor connections does not affect the sensed volt­age. It is desirable to have the ADP3157 close to the output
capacitor bank and not in the output power path, so that
any voltage drop between the output capacitors and the
AGND pin is minimized, and voltage regulation is not
compromised.

REV. A

–11–

ADP3157

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

16-Lead SOIC

(R-16A/SO-16)

0.3937 (10.00)

0.3859 (9.80)

0.1574 (4.00)

0.1497 (3.80)

PIN 1

0.0098 (0.25)

0.0040 (0.10)

16 9

0.050 (1.27)
BSC

0.0688 (1.75)

0.0532 (1.35)

0.0192 (0.49)

0.0138 (0.35)

0.2440 (6.20)

0.2284 (5.80)

81

SEATING
PLANE

0.0099 (0.25)

0.0075 (0.19)

0.0196 (0.50)

0.0099 (0.25)

88
08

0.0500 (1.27)

0.0160 (0.41)

C3502a–2–9/99

3 458

–12–

PRINTED IN U.S.A.

REV. A