Datasheet ADP3118 Datasheet (ANALOG DEVICES)

查询ADP3118供应商

Dual Bootstrapped 12 V MOSFET

FEATURES

Optimized for low gate charge MOSFETs
All-in-one synchronous buck driver
Bootstrapped high-side drive
One PWM signal generates both drives
Anticross-conduction protection circuitry
Output disable control turns off both MOSFETs

to float output per Intel® VRM 10 specification

APPLICATIONS

Multiphase desktop CPU supplies
Single-supply synchronous buck converters

SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM

Driver with Output Disable

ADP3118

GENERAL DESCRIPTION

The ADP3118 is a dual high voltage MOSFET driver optimized
for driving two N-channel MOSFETs, which are the two switches
in a nonisolated synchronous buck power converter. Each of the
drivers is capable of driving a 3000 pF load with a 25 ns
propagation delay and a 25 ns transition time. One of the drivers
can be bootstrapped and is designed to handle the high voltage
slew rate associated with floating high-side gate drivers. The
ADP3118 includes overlapping drive protection to prevent
shoot-through current in the external MOSFETs.

OD

The
MOSFETs to prevent rapid output capacitor discharge during
system shutdown.

The ADP3118 is specified over the commercial temperature
range of 0°C to 85°C and is available in 8-lead SOIC package.

pin shuts off both the high-side and the low-side

VIN12V

ADP3118

2

IN

DELAY

CMP

1V

3

OD

Flex-Mode™ is Protected by U.S. Patent 6683441

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

DELAY

CONTROL

LOGIC

CMP

Figure 1.

BST1

D1

R

BST

C

BST2

R

G

Q1

TO

INDUCTOR

Q2

05452-001

VCC

4

BST

1

C

DRVH

8

SW

7

VCC

6

DRVL

5

PGND

6

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] ©2005 Analog Devices, Inc. All rights reserved.

www.analog.com

ADP3118

TABLE OF CONTENTS

Specifications..................................................................................... 3

Application Information................................................................ 10

Absolute Maximum Ratings............................................................ 4

ESD Caution.................................................................................. 4

Pin Configuration and Function Descriptions............................. 5

Timing Characteristics..................................................................... 6

Typical Performance Characteristics ............................................. 7

Theory of Operation ........................................................................ 9

Low-Side Driver............................................................................ 9

High-Side Driver .......................................................................... 9

Overlap Protection Circuit.......................................................... 9

REVISION HISTORY

4/05—Revision 0: Initial Version

Supply Capacitor Selection ....................................................... 10

Bootstrap Circuit........................................................................ 10

MOSFET Selection..................................................................... 10

High-Side (Control) MOSFETs................................................ 10

Low-Side (Synchronous) MOSFETs ........................................ 11

PC Board Layout Considerations............................................. 11

Outline Dimensions ....................................................................... 13

Ordering Guide .......................................................................... 13

Rev. 0 | Page 2 of 16

ADP3118

SPECIFICATIONS

VCC = 12 V, BST = 4 V to 26 V, TA = 0°C to 85°C, unless otherwise noted.

Table

1.

Parameter Symbol Conditions Min Typ Max Unit

PWM INPUT

Input Voltage High 2.0 V
Input Voltage Low 0.8 V
Input Current −1 +1 µA
Hysteresis 90 250 mV

OD INPUT

Input Voltage High 2.0 V
Input Voltage Low 0.8 V
Input Current −1 +1 µA
Hysteresis 90 250 mV
Propagation Delay Times
t

HIGH-SIDE DRIVER

Output Resistance, Sourcing Current BST − SW = 12 V 2.2 3.5 Ω
Output Resistance, Sinking Current BST − SW = 12 V 1.0 2.5 Ω
Output Resistance, Unbiased BST − SW = 0 V 10 kΩ
Transition Times
t
Propagation Delay Times2 t
t
SW Pull-Down Resistance SW to PGND 10 kΩ

LOW-SIDE DRIVER

Output Resistance, Sourcing Current 2.0 3.2 Ω
Output Resistance, Sinking Current 1.0 2.5 Ω
Output Resistance, Unbiased VCC = PGND 10 kΩ
Transition Times
t
Propagation Delay Times2 t
t
Timeout Delay SW = 5 V 110 190 ns
SW = PGND 95 150 ns

SUPPLY

Supply Voltage Range V
Supply Current I
UVLO Voltage VCC rising 1.5 3.0 V
Hysteresis 350 mV

1

All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods.

2

For propagation delays, t

1

2

refers to the specified signal going high, and t

pdh

t

pdlOD

pdhOD

t

rDRVH

fDRVH

pdhDRVH

pdlDRVH

t

rDRVL

fDRVL

pdhDRVL

pdlDRVL

CC

SYS

See Figure 3 20 35 ns
See Figure 3 40 55 ns

BST − SW = 12 V, C
BST − SW = 12 V, C
BST − SW = 12 V, C
BST − SW = 12 V, C

C

= 3 nF, see Figure 4 20 35 ns

LOAD

C

= 3 nF, see Figure 4 16 30 ns

LOAD

C

= 3 nF, see Figure 4 12 35 ns

LOAD

C

= 3 nF, see Figure 4 30 45 ns

LOAD

= 3 nF, see Figure 4 25 40 ns

LOAD

= 3 nF, see Figure 4 20 30 ns

LOAD

= 3 nF, see Figure 4 25 40 ns

LOAD

= 3 nF, see Figure 4 25 35 ns

LOAD

4.15 13.2 V
BST = 12 V, IN = 0 V 2 5 mA

refers to it going low.

pdl

Rev. 0 | Page 3 of 16

ADP3118

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

VCC −0.3 V to +15 V
BST −0.3 V to VCC +15 V
BST to SW −0.3 V to +15 V
SW

DC −5 V to +15 V
<200 ns −10 V to +25 V

DRVH

DC SW − 0.3 V to BST + 0.3 V
<200 ns SW − 2 V to BST + 0.3 V

DRVL

DC −0.3 V to VCC + 0.3 V
<200 ns −2 V to VCC + 0.3 V

OD

IN,
θJA, SOIC

2-Layer Board
4-Layer Board

Operating Ambient Temperature

Range
Junction Temperature Range 0°C to 150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature Range

Soldering (10 sec)

Vapor Phase (60 sec)

Infrared (15 sec)

−0.3 V to 6.5 V

123°C/W
90°C/W
0°C to 85°C

300°C
215°C
260°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Unless otherwise specified, all voltages are referenced to PGND.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degrada­tion or loss of functionality.

Rev. 0 | Page 4 of 16

ADP3118

V

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

BST

OD
CC

IN

1

ADP3118

2
3

TOP VIEW

(Not to Scale)

4

8
7
6
5

DRVH
SW
PGND
DRVL

05452-002

Figure 2. 8-Lead SOIC Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1 BST

Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this
bootstrapped voltage for the high-side MOSFET as it is switched.

2 IN

Logic Level PWM Input. This pin has primary control of the driver outputs. In normal operation, pulling this pin
low turns on the low-side driver; pulling it high turns on the high-side driver.

3

OD

Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low.
4 VCC Input Supply. This pin should be bypassed to PGND with ~1 µF ceramic capacitor.
5 DRVL Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.
6 PGND Power Ground. Should be closely connected to the source of the lower MOSFET.
7 SW

This pin is connected to the buck-switching node, close to the upper MOSFET’s source. It is the floating return

for the upper MOSFET drive signal. It is also used to monitor the switched voltage to prevent turn-on of the

lower MOSFET until the voltage is below ~1 V.
8 DRVH Buck Drive. Output drive for the upper (buck) MOSFET.

Rev. 0 | Page 5 of 16

ADP3118

TIMING CHARACTERISTICS

OD

tpdl

OD

tpdh

OD

DRVH
OR
DRVL

90%

10%

05452-004

Figure 3. Output Disable Timing Diagram

IN

DRVL

tf

DRVL

tpdh

DRVHtrDRVH

tpdl

DRVH

tf

DRVH

V

TH

V

TH

tr

DRVL

tpdl

DRVL

DRVH-SW

SW

tpdh

DRVL

1V

Figure 4. Timing Diagram—Timing Is Referenced to the 90% and 10% Points, Unless Otherwise Noted

Rev. 0 | Page 6 of 16

05452-005

ADP3118

TYPICAL PERFORMANCE CHARACTERISTICS

IN

24

22

20

VCC = 12V
C

= 3nF

LOAD

DRVH

DRVL

DRVH

Figure 5. DRVH Rise and DRVL Fall Times

C

= 6 nF for DRVL, C

LOAD

IN

DRVL

DRVH

Figure 6. DRVH Fall and DRVL Rise Times

= 6 nF for DRVL, C

C

LOAD

35

VCC = 12V

= 3nF

C

LOAD

30

= 2 nF for DRVH

LOAD

= 2 nF for DRVH

LOAD

DRVH

05452-006

05452-007

18

FALL TIME (ns)

16

14

0 125

25 50 75 100

JUNCTION TEMPERATURE (°C)

DRVL

Figure 8. DRVH and DRVL Fall Times vs. Temperature

40

TA = 25°C
VCC = 12V

35

30

25

20

RISE TIME (ns)

15

10

5

2.0

2.5 3.0 3.5 4.0 4.5
LOAD CAPACITANCE (nF)

DRVH

Figure 9. DRVH and DRVL Rise Times vs. Load Capacitance

35

VCC = 12V
T

= 25°C

A

30

25

DRVH

DRVL

5.0

05452-009

05452-010

25

RISE TIME (ns)

20

15

0 125

25 50 75 100

JUNCTION TEMPERATURE (°C)

DRVL

Figure 7. DRVH and DRVL Rise Times vs. Temperature

05452-008

Rev. 0 | Page 7 of 16

20

FALL TIME (ns)

15

10

5

2.0

2.5 3.0 3.5 4.0 4.5
LOAD CAPACITANCE (nF)

DRVL

Figure 10. DRVH and DRVL Fall Times vs. Load Capacitance

5.0

05452-011

ADP3118

60

TA= 25°C
VCC = 12V
C

LOAD

45

[mA])

CC

30

15

SUPPLY CURRENT (I

0

0

13

VCC = 12V
C

LOAD

f

IN

12

= 3nF

200 400 600 800 1000 1200 1400

FREQUENCY (kHz)

Figure 11. Supply Current vs. Frequency

= 3nF

= 250kHz

05452-012

12

TA = 25°C

11
10

DRVL OUTPUT VOLTAGE (V)

= 3nF

C

LOAD

9
8
7
6
5
4
3
2
1
0

0

1234567891011

VCC VOLTAGE (V)

Figure 13. DRVL Output Voltage vs. Supply Voltage

12

05452-014

11

SUPPLY CURRENT (mA)

10

9

0 125

25 50 75 100

JUNCTION TEMPERATURE (°C)

Figure 12. Supply Current vs. Temperature

05452-013

Rev. 0 | Page 8 of 16

ADP3118

THEORY OF OPERATION

The ADP3118 is a dual-MOSFET driver optimized for driving
two N-channel MOSFETs in a synchronous buck converter
topology. A single PWM input signal is all that is required to
properly drive the high-side and the low-side MOSFETs. Each
driver is capable of driving a 3 nF load at speeds up to 500 kHz.

A more detailed description of the ADP3118 and its features
follows. See Figure 1.

LOW-SIDE DRIVER

The low-side driver is designed to drive a ground-referenced
N-channel MOSFET. The bias to the low-side driver is
internally connected to the VCC supply and PGND.

When the driver is enabled, the driver’s output is 180° out of
phase with the PWM input. When the ADP3118 is disabled,
the low-side gate is held low.

To complete the cycle, Q1 is switched off by pulling the gate
down to the voltage at the SW pin. When the low-side
MOSFET, Q2, turns on, the SW pin is pulled to ground. This
allows the bootstrap capacitor to charge up to VCC again.

The high-side driver’s output is in phase with the PWM input.
When the driver is disabled, the high-side gate is held low.

OVERLAP PROTECTION CIRCUIT

The overlap protection circuit prevents both of the main power
switches, Q1 and Q2, from being on at the same time. This is
done to prevent shoot-through currents from flowing through
both power switches and the associated losses that can occur
during their on/off transitions. The overlap protection circuit
accomplishes this by adaptively controlling the delay from the
Q1 turn off to the Q2 turn on, and by internally setting the
delay from the Q2 turn off to the Q1 turn on.

HIGH-SIDE DRIVER

The high-side driver is designed to drive a floating N-channel
MOSFET. The bias voltage for the high-side driver is developed
by an external bootstrap supply circuit, which is connected
between the BST and SW pins.

The bootstrap circuit comprises a diode, D1, and bootstrap

. C

capacitor, C

BST1

BST2

and R
side gate drive voltage and to limit the switch node slew rate
(referred to as a Boot-Snap circuit, see the Application
Information section for more details). When the ADP3118 is
starting up, the SW pin is at ground, so the bootstrap capacitor
charges up to VCC through D1. When the PWM input goes
high, the high-side driver begins to turn on the high-side
MOSFET, Q1, by pulling charge out of C
turns on, the SW pin rises up to V
+ V

, which is enough gate-to-source voltage to hold Q1 on.

C (BST)

are included to reduce the high-

BST

and C

BST1

, forcing the BST pin to VIN

IN

BST2

. As Q1

To prevent the overlap of the gate drives during the Q1 turn off
and the Q2 turn on, the overlap circuit monitors the voltage at
the SW pin. When the PWM input signal goes low, Q1 begins
to turn off (after propagation delay). Before Q2 can turn on, the
overlap protection circuit makes sure that SW has first gone
high and then waits for the voltage at the SW pin to fall from

to 1 V. Once the voltage on the SW pin falls to 1 V, Q2

V

IN

begins turn on. If the SW pin has not gone high first, the Q2
turn on is delayed by a fixed 150 ns. By waiting for the voltage
on the SW pin to reach 1 V or for the fixed delay time, the
overlap protection circuit ensures that Q1 is off before Q2 turns
on, regardless of variations in temperature, supply voltage, input
pulse width, gate charge, and drive current. If SW does not go
below 1 V after 190 ns, DRVL turns on. This can occur if the
current flowing in the output inductor is negative and is flowing
through the high-side MOSFET body diode.

Rev. 0 | Page 9 of 16

ADP3118

C

C

×

=

−

APPLICATION INFORMATION

SUPPLY CAPACITOR SELECTION

For the supply input (VCC) of the ADP3118, a local bypass
capacitor is recommended to reduce the noise and to supply
some of the peak currents drawn. Use a 4.7 µF, low ESR
capacitor. Multilayer ceramic chip (MLCC) capacitors provide
the best combination of low ESR and small size. Keep the
ceramic capacitor as close as possible to the ADP3118.

BOOTSTRAP CIRCUIT

The bootstrap circuit uses a charge storage capacitor (C
and a diode, as shown in Figure 1. These components can be
selected after the high-side MOSFET is chosen. The bootstrap
capacitor must have a voltage rating that can handle twice the
maximum supply voltage. A minimum 50 V rating is
recommended. The capacitor values are determined by:

Q

GATE

CC ×=+ 10

C

BST1

CC

+

BST2BST1

V

=

BST2BST1

C

(1)

V

GATE

GATE

(2)

VV

−

D

where:

is the total gate charge of the high-side MOSFET at V

Q

GATE

V

is the desired gate drive voltage (usually in the range of 5 V

GATE

to 10 V, 7 V being typical).

is the voltage drop across D1.

V

D

BST

)

GATE.

A small-signal diode can be used for the bootstrap diode due
to the ample gate drive voltage supplied by V

. The bootstrap

CC

diode must have a minimum 15 V rating to withstand the
maximum supply voltage. The average forward current can
be estimated by

fQI

where

GATE

)(

is the maximum switching frequency of the

f

AVGF

MAX

(3)

MAX

controller. The peak surge current rating should be calculated
using

VV

D

I

PEAKF

CC

=

)(

R

(4)

BST

MOSFET SELECTION

When interfacing the ADP3118 to external MOSFETs, there are
a few considerations that the designer should be aware of. These
help to make a more robust design that minimizes stresses on
both the driver and the MOSFETs. These stresses include
exceeding the short-time duration voltage ratings on the driver
pins as well as the external MOSFET.

It is also highly recommended to use the Boot-Snap circuit to
improve the interaction of the driver with the characteristics of
the MOSFETs. If a simple bootstrap arrangement is used, make
sure to include a proper snubber network on the SW node.

Rearranging Equations 1 and 2 to solve for C

Q

C

BST1

C

can then be found by rearranging Equation 1

BST2

C −×=

BST2

GATE

×= 10

C

Q

GATE

V

GATE

VV

−

D

C

110BST

BST1

yields

For example, an NTD60N02 has a total gate charge of about
12 nC at V

= 12 nF and C

C

BST1

= 7 V. Using VCC = 12 V and VD = 1 V, one finds

GATE

= 6.8 nF. Good quality ceramic capacitors

BST2

should be used.

is used for slew-rate limiting to minimize the ringing at the

R

BST

switch node. It also provides peak current limiting through D1.

value of 1.5 Ω to 2.2 Ω is a good choice. The resistor

An R

BST

needs to be able to handle at least 250 mW due to the peak
currents that flow through it.

HIGH-SIDE (CONTROL) MOSFETS

The high-side MOSFET is usually selected to be high speed to
minimize switching losses (see the
sheet for Flex-Mode controller details). This usually implies a
low gate resistance and low input capacitance/charge device.
Yet, a significant source lead inductance can also exist. This
depends mainly on the MOSFET package; it is best to contact
the MOSFET vendor for this information.

The ADP3118 DRVH output impedance and the input resistance
of the MOSFETs determine the rate of charge delivery to the
gate’s internal capacitance. This determines the speed at which
the MOSFETs turn on and off. However, due to potentially large
currents flowing in the MOSFETs at the on and off times (this
current is usually larger at turn off due to ramping up of the out­put current in the output inductor), the source lead inductance
generates a significant voltage when the high-side MOSFETs
switch off. This creates a significant drain-source voltage spike
across the internal die of the MOSFETs and can lead to a
catastrophic avalanche. The mechanisms involved in this
avalanche condition can be referenced in literature from the
MOSFET suppliers.

ADP3186 or ADP3188 data

Rev. 0 | Page 10 of 16

ADP3118

X

The MOSFET vendor should provide a maximum voltage slew
rate at drain current rating such that this can be designed around.
Once you have this specification, determine the maximum
current you expect to see in the MOSFET. This can be done
with the following equation:

D

VVphaseperII

()

CCDCMAX

OUT

MAX

×−+= )(

MA

(5)

Lf

×

OUT

where:

D

is determined for the VR controller being used with

MAX

the driver. This current is divided roughly equally between
MOSFETs if more than one is used (assume a worst-case
mismatch of 30% for design margin).

L

is the output inductor value.

OUT

When producing your design, there is no exact method for
calculating the dV/dt due to the parasitic effects in the external
MOSFETs as well as the PCB. However, it can be measured to
determine if it is safe. If it appears that the dV/dt is too fast, an
optional gate resistor can be added between DRVH and the
high-side MOSFETs. This resistor slows down the dV/dt, but it
increases the switching losses in the high-side MOSFETs. The
ADP3118 has been optimally designed with an internal drive
impedance that works with most MOSFETs to switch them
efficiently yet minimizes dV/dt. However, some high speed
MOSFETs may require this external gate resistor depending on
the currents being switched in the MOSFET.

LOW-SIDE (SYNCHRONOUS) MOSFETS

The low-side MOSFETs are usually selected to have a low on
resistance to minimize conduction losses. This usually implies a
large input gate capacitance and gate charge. The first concern is
to make sure the power delivery from the ADP3118’s DRVL
does not exceed the thermal rating of the driver (see the

ADP3186 or ADP3188 data sheet for Flex-Mode controller

details).

The next concern for the low-side MOSFETs is based on
preventing them from inadvertently being switched on when
the high-side MOSFET turns on. This occurs due to the drain­gate (Miller, also specified as C
When the drain of the low-side MOSFET is switched to VCC by
the high-side turning on (at a rate dV/dt), the internal gate of
the low-side MOSFET is pulled up by an amount roughly equal
to V

CC

× (C

). It is important to make sure this does not put

rss/Ciss

the MOSFET into conduction.

) capacitance of the MOSFET.

rss

proper switching time, so the state of the DRVL pin is moni­tored to go below one sixth of V

. A delay is then added. Due

CC

to the Miller capacitance and internal delays of the low-side
MOSFET gate, one must ensure that the Miller to input capaci­tance ratio is low enough and that the low-side MOSFET internal
delays are not so large as to allow accidental turn on of the low­side when the high-side turns on.

Contact sales for an updated list of recommended low-side
MOSFETs.

PC BOARD LAYOUT CONSIDERATIONS

Use the following general guidelines when designing printed
circuit boards.

• Trace out the high current paths and use short, wide

(>20 mil) traces to make these connections.

• Minimize trace inductance between DRVH and DRVL

outputs and MOSFET gates.

• Connect the PGND pin of the ADP3118 as closely as

possible to the source of the lower MOSFET.

• Locate the V

VCC and PGND pins.

• Use vias to other layers when possible to maximize thermal

conduction away from the IC.

The circuit in Figure 15 shows how four drivers can be
combined with the ADP3188 to form a total power conversion
solution for generating V

10.x-compliant.

Figure 14 shows an example of the typical land patterns based
on the guidelines given previously. For more detailed layout
guidelines for a complete CPU voltage regulator subsystem,
refer to the PC Board Layout Considerations section of the

ADP3188 data sheet.

bypass capacitor as close as possible to the

CC

for an Intel CPU that is VRD

CC (CORE)

C

BST1

R

C

D1

BST2

BST

Another consideration is the nonoverlap circuitry of the
ADP3118, which attempts to minimize the nonoverlap period.
During the state of the high-side turning off to low-side turning
on, the SW pin is monitored (as well as the conditions of SW
prior to switching) to adequately prevent overlap.

However, during the low-side turn off to high-side turn on,
the SW pin does not contain information for determining the

Rev. 0 | Page 11 of 16

Figure 14. External Component Placement Example

C

VCC

05452-015

ADP3118

CC (CORE)

CC (CORE) RTN

V

0.8375V – 1.6V

95A TDC, 119A PK

V

MLCC IN

SOCKET

10µF × 18

5mΩ EACH

560µF/4V × 8

C24 C31

+ +

SANYO SEPC SERIES

RTH1

100kΩ, 5%

NTC

L1

C8

R3

12nF

2.2Ω

2700µF/16V/3.3A × 2

18A

370nH

C11

L3

320nH/1.4mΩ

F

µ

4.7

Q5

NTD60N02

C10

876

6.8nF

DRVH

U3

ADP3118

BST1IN

D3

1N4148

Q8

NTD110N02

Q7

NTD110N02

5

C16

SW

PGND

OD

2

3

12nF

DRVL

R5

2.2Ω

VCC

4

F

µ

C9

4.7

L2

320nH/1.4mΩ

F

µ

C7

4.7

Q1

NTD60N02

C6

876

6.8nF

DRVH

U2

ADP3118

BST1IN

D2

1N4148

Q4

NTD110N02

Q3

NTD110N02

5

C12

SW

PGND

OD

2

3

12nF

DRVL

R4

2.2Ω

VCC

4

C5

4.7µF

F

µ

C15

4.7

Q9

C14

6.8nF

U4

ADP3118

D4

1N4148

2827262524

VCC

PWM1

L4

320nH/1.4mΩ

Q12

NTD60N02

876

5

SW

DRVL

DRVH

PGND

BST1IN

VCC

OD

2

3

4

F

µ

C13

4.7

1

1

SW1

SW3

R

R

1

SW2

R

232221201918171615

SW1

PWM2

SW2

PWM3

PWM4

NTD110N02

Q11

NTD110N02

C20

12nF

R6

2.2Ω

PH2

R

158kΩ,

PH4

R

1

SW4

R

SW3

SW4

GND

PH1

R

1%

PH3

R

158kΩ, 1%

U1

ADP3188

VID4

VID3

VID2

VID1

VID0

VID5

FBRTNFBCOMP

B

C

470pF

1

C21

CFB22pF

1nF

PWRGDENDELAYRTRAMPADJ

10

A

R

12.1kΩ

A

C

470pF

B

R

1.21kΩ

GOOD

POWER

123456789

R2

357kΩ,

1%

R1

10Ω

++

C1 C2

SANYO MV-WX SERIES

IN

V

12V

RTN

IN

V

D1

1N4148

C4

1µF

+

C3

100µF

CPU

FROM

C19

U5

1%

158kΩ,

1%

158kΩ,

CS2

R

CS1

R

CS2

C

CS1

C

CSSUM

CSCOMP

111213

ENABLE

F

µ

4.7

C16

6.8nF

D5

84.5kΩ

35.7kΩ

1.5nF

560pF

CSREF

ADP3118

1N4148

C22

T

R

LDY

R

LDY

C

L5

Q13

NTD60N02

876

DRVH

BST1IN

1nF

ILIMIT

14

1%

137kΩ,

470kΩ

39nF

320nH/1.4mΩ

Q16

NTD110N02

Q15

NTD110N02

5

SW

DRVL

PGND

VCC

OD

2

3

4

F

µ

C17

4.7

LIM

R

150kΩ,

1%

1nF

C23

NOTE:

1. FOR A DESCRIPTION OF OPTIONAL COMPONENTS, SEE THE ADP3188 THEORY OF OPERATION SECTION.

05452-016

Figure 15. VRD 10-Compliant Power Supply Circuit

Rev. 0 | Page 12 of 16

ADP3118

OUTLINE DIMENSIONS

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

85

6.20 (0.2440)

5.80 (0.2284)

41

1.27 (0.0500)
BSC

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012-AA

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

8°

1.27 (0.0500)

0°

0.40 (0.0157)

× 45°

Figure 16. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body

(R-8)

Dimensions shown in millimeters (inches)

ORDERING GUIDE

Temperature

Model

ADP3118JRZ

1

Range Package Description

0°C to 85°C 8-Lead Standard Small Outline Package (SOIC_N) R-8 N/A

ADP3118JRZ-RL1 0°C to 85°C 8-Lead Standard Small Outline Package(SOIC_N) R-8 2500

1

Z = Pb-free part.

Package
Option

Quantity
per Reel

Rev. 0 | Page 13 of 16

ADP3118

NOTES

Rev. 0 | Page 14 of 16

ADP3118

NOTES

Rev. 0 | Page 15 of 16

ADP3118

NOTES

©2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

D05452–0–4/05(0)

Rev. 0 | Page 16 of 16