Datasheet ADP3110 Datasheet (ANALOG DEVICES)

查询ADP3110供应商

Dual Bootstrapped, 12 V MOSFET

FEATURES

All-in-one synchronous buck driver
Bootstrapped high-side drive
One PWM signal generates both drives
Anticross-conduction protection circuitry
Output disable control turns off both MOSFETs to float

output per Intel® VRM 10 specification

APPLICATIONS

Multiphase desktop CPU supplies
Single-supply synchronous buck converters

Driver with Output Disable

ADP3110

GENERAL DESCRIPTION

The ADP3110 is a dual, high voltage MOSFET driver optimized
for driving two N-channel MOSFETs, which are the two
switches in a nonisolated synchronous buck power converter.
Each of the drivers is capable of driving a 3000 pF load with a
25 ns propagation delay and a 30 ns transition time. One of the
drivers can be bootstrapped and is designed to handle the high
voltage slew rate associated with floating high-side gate drivers.
The ADP3110 includes overlapping drive protection to prevent
shoot-through current in the external MOSFETs.

OD

The
MOSFETs to prevent rapid output capacitor discharge during
system shutdown.

The ADP3110 is specified over the commercial temperature
range of 0°C to 85°C and is available in an 8-lead SOIC_N
package.

pin shuts off both the high-side and the low-side

OD

IN

2

3

ADP3110

SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM

12V

C

BST1

D1

C

BST2

R

G

R

BST

Q1

TO

INDUCTOR

Q2

05514-001

VCC

4

BST

1

DRVH

8

DELAY

SW

7

CMP

VCC

6

CMP

1V

DELAY

CONTROL

LOGIC

Figure 1.

5

6

DRVL

PGND

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2005 Analog Devices, Inc. All rights reserved.

ADP3110

TABLE OF CONTENTS

Specifications..................................................................................... 3

Overlap Protection Circuit...........................................................7

Absolute Maximum Ratings............................................................ 4

ESD Caution.................................................................................. 4

Pin Configuration and Function Descriptions............................. 5

Timing Characteristics..................................................................... 6

Theory of Operation ........................................................................ 7

Low-Side Driver............................................................................ 7

High-Side Driver .......................................................................... 7

REVISION HISTORY

6/05—Revision 0: Initial Version

Application Information...................................................................8

Supply Capacitor Selection ..........................................................8

Bootstrap Circuit...........................................................................8

MOSFET Selection........................................................................8

PC Board Layout Considerations................................................9

Outline Dimensions ....................................................................... 11

Ordering Guide .......................................................................... 11

Rev. 0 | Page 2 of 12

ADP3110

SPECIFICATIONS

VCC = 12 V, BST = 4 V to 26 V, TA = 25°C, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

PWM INPUT

OD INPUT

HIGH-SIDE DRIVER

LOW-SIDE DRIVER

SUPPLY

1

2

3

1

Input Voltage High
Input Voltage Low
Input Current
Hysteresis

2

2

2

2

2.0 V

0.8 V

−1 +1 μA
90 250 mV

Input Voltage High
Input Voltage Low
Input Current
Hysteresis

2

Propagation Delay Times

2

2

2

2.0 V

0.8 V

−1 +1 μA
90 250 mV

3

See Figure 3 20 35 ns

tpdl

OD

See

tpdh

OD

Figure 3 40 55 ns

Output Resistance, Sourcing Current BST to SW = 12 V 3.8 4.4 Ω
Output Resistance, Sinking Current R

DRV + SW

BST to SW = 12 V 1.4 1.8 Ω
Output Resistance, Unbiased BST to SW = 0 V 10 kΩ
Transition Times
tf
Propagation Delay Times
tpdl
SW Pull Down Resistance R

3

tr

DRVH

DRVH

tpdh

SW − PGND

DRVH

DRVH

BST to SW = 12 V, C

BST to SW = 12 V, C

BST to SW = 12 V, C

BST to SW = 12 V, C

= 3 nF, see Figure 4 40 55 ns

LOAD

= 3 nF, see Figure 4 30 45 ns

LOAD

= 3 nF,see Figure 4 45 65 ns

LOAD

= 3 nF, see Figure 4 25 35 ns

LOAD

SW to PGND 10 kΩ

Output Resistance, Sourcing Current 3.4 4.0 Ω
Output Resistance, Sinking Current R

DRVL − PGND

1.4 1.8 Ω
Output Resistance, Unbiased VCC = PGND 10 kΩ
Transition Times tr
tf
Propagation Delay Times

3

DRVL

DRVL

tpdh

tpdl

DRVL

DRVL

C

= 3 nF, see Figure 4 40 50 ns

LOAD

C

= 3 nF, see Figure 4 20 30 ns

LOAD

C

= 3 nF, see Figure 4 15 35 ns

LOAD

C

= 3 nF, see Figure 4 30 40 ns

LOAD

Time-out Delay SW = 5 V 110 190 ns
SW = PGND 95 150 ns

Supply Voltage Range
Supply Current
UVLO Voltage
Hysteresis

All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods.
Specifications apply over the full operating temperature range TA = 0°C to 85°C.
For propagation delays, tpdh refers to the specified signal going high, and tpdl refers to it going low.

2

2

2

2

V

CC

I

SYS

4.15 13.2 V

BST = 12 V, IN = 0 V 2 5 mA
VCC rising 1.5 3.0 V
350 mV

Rev. 0 | Page 3 of 12

ADP3110

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

VCC –0.3 V to +15 V
BST –0.3 V to VCC + 15 V
BST to SW –0.3 V to +15 V
SW

DC –5 V to +15 V
<200 ns –10 V to +25 V

DRVH

DC SW – 0.3 V to BST + 0.3 V
<200 ns SW – 2 V to BST + 0.3 V

DRVL

DC –0.3 V to VCC + 0.3 V
<200 ns –2 V to VCC + 0.3 V

OD

IN,
θJA, SOIC_N

2-Layer Board 123°C/W
4-Layer Board 90°C/W

Operating Ambient Temperature

Range
Junction Temperature Range 0°C to 150°C
Storage Temperature Range –65°C to +150°C
Lead Temperature Range

Soldering (10 sec) 300°C

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 260°C

–0.3 V to 6.5 V

0°C to 85°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Unless otherwise specified all other voltages
are referenced to PGND.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 4 of 12

ADP3110

V

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

BST

OD
CC

IN

1

ADP3110

2
3

TOP VIEW

(Not to Scale)

4

8
7
6
5

DRVH
SW
PGND
DRVL

05514-002

Figure 2. 8-Lead SOIC_N Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1 BST

Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this
bootstrapped voltage for the high-side MOSFET as it is switched.

2 IN

Logic Level PWM Input. This pin has primary control of the driver outputs. In normal operation, pulling this pin
low turns on the low-side driver; pulling it high turns on the high-side driver.

3

OD

Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low.
4 VCC Input Supply. This pin should be bypassed to PGND with ~1 μF ceramic capacitor.
5 DRVL Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.
6 PGND Power Ground. This pin should be closely connected to the source of the lower MOSFET.
7 SW

Switch Node Connection. This pin is connected to the buck-switching node, close to the upper MOSFET’s

source. It is the floating return for the upper MOSFET drive signal. It is also used to monitor the switched voltage

to prevent turn-on of the lower MOSFET until the voltage is below ~1 V.
8 DRVH Buck Drive. Output drive for the upper (buck) MOSFET.

Rev. 0 | Page 5 of 12

ADP3110

TIMING CHARACTERISTICS

OD

tpdl

OD

tpdh

OD

DRVH
OR
DRVL

DRVL

DRVH-SW

90%

10%

05514-003

Figure 3. Output Disable Timing Diagram

IN

DRVL

tf

DRVL

tpdh

DRVHtrDRVH

tpdl

DRVH

tf

DRVH

V

TH

V

TH

tr

DRVL

tpdl

tpdh

SW

1V

DRVL

05514-004

Figure 4. Timing Diagram

(Timing is Referenced to the 90% and 10% Points Unless Otherwise Noted)

Rev. 0 | Page 6 of 12

ADP3110

THEORY OF OPERATION

The ADP3110 is a dual MOSFET driver optimized for driving
two N-channel MOSFETs in a synchronous buck converter
topology. A single PWM input signal is all that is required to
properly drive the high-side and the low-side MOSFETs. Each
driver is capable of driving a 3 nF load at speeds up to 500 kHz.

A more detailed description of the ADP3110 and its features
follows. Refer to

Figure 1.

LOW-SIDE DRIVER

The low-side driver is designed to drive a ground-referenced
N-channel MOSFET. The bias to the low-side driver is
internally connected to the VCC supply and PGND.

When the ADP3110 is enabled, the driver’s output is
180 degrees out of phase with the PWM input. When the
ADP3110 is disabled, the low-side gate is held low.

on. To complete the cycle, Q1 is switched off by pulling the gate
down to the voltage at the SW pin. When the low-side
MOSFET, Q2, turns on, the SW pin is pulled to ground. This
allows the bootstrap capacitor to charge up to VCC again.

The high-side driver’s output is in phase with the PWM input.
When the driver is disabled, the high-side gate is held low.

OVERLAP PROTECTION CIRCUIT

The overlap protection circuit prevents both of the main power
switches, Q1 and Q2, from being on at the same time. This
prevents shoot-through currents from flowing through both
power switches, and the associated losses that can occur during
their on/off transitions. The overlap protection circuit
accomplishes this by adaptively controlling the delay from the
Q1 turn off to the Q2 turn on, and by internally setting the
delay from the Q2 turn off to the Q1 turn on.

HIGH-SIDE DRIVER

The high-side driver is designed to drive a floating N-channel
MOSFET. The bias voltage for the high-side driver is developed
by an external bootstrap supply circuit, which is connected
between the BST and SW pins.

The bootstrap circuit comprises a diode, D1, and bootstrap

. C

capacitor, C

BST1

BST2

and R
side gate drive voltage and limit the switch node slew rate
(referred to as a Boot-Snap™ circuit, see the
Information

section for more details). When the ADP3110 is
starting up the SW pin is at ground; therefore the bootstrap
capacitor charges up to VCC through D1. When the PWM
input goes high, the high-side driver begins to turn on the high­side MOSFET, Q1, by pulling charge out of C
Q1 turns on, the SW pin rises up to V
V

IN

+ V

, which is enough gate-to-source voltage to hold Q1

C(BST)

are included to reduce the high-

BST

Application

and C

BST1

, forcing the BST pin to

IN

BST2

. As

To prevent the overlap of the gate drives during the Q1 turn off
and the Q2 turn on, the overlap circuit monitors the voltage at
the SW pin. When the PWM input signal goes low, Q1 begins
to turn off (after propagation delay). Before Q2 can turn on, the
overlap protection circuit makes sure that SW has first gone
high and then waits for the voltage at the SW pin to fall from
V

to 1 V. Once the voltage on the SW pin has fallen to 1 V, Q2

IN

begins turn on. If the SW pin had not gone high first, then the
Q2 turn on is delayed by a fixed 150 ns. By waiting for the
voltage on the SW pin to reach 1 V or for the fixed delay time,
the overlap protection circuit ensures that Q1 is off before Q2
turns on, regardless of variations in temperature, supply voltage,
input pulse width, gate charge, and drive current. If SW does
not go below 1 V after 190 ns, DRVL turns on. This can occur if
the current flowing in the output inductor is negative and is
flowing through the high-side MOSFET body diode.

Rev. 0 | Page 7 of 12

ADP3110

×

=

−

APPLICATION INFORMATION

SUPPLY CAPACITOR SELECTION

For the supply input (VCC) of the ADP3110, a local bypass
capacitor is recommended to reduce the noise and to supply
some of the peak currents drawn. Use a 4.7 μF, low ESR
capacitor. Multilayer ceramic chip (MLCC) capacitors provide
the best combination of low ESR and small size. Keep the
ceramic capacitor as close as possible to the ADP3110.

BOOTSTRAP CIRCUIT

The bootstrap circuit uses a charge storage capacitor (C
a diode, as shown in Figure 1. These components can be
selected after the high-side MOSFET is chosen. The bootstrap
capacitor must have a voltage rating that is able to handle twice
the maximum supply voltage. A minimum 50 V rating is
recommended. The capacitor values are determined using the
following equations:

Q

CC ×=+ 10

C

1

BST

CC

+

BSTBST

21

21

BSTBST

GATE

(1)

V

GATE

V

GATE

=

(2)

VVCC

−

D

where:

Q

is the total gate charge of the high-side MOSFET at V

GATE

V

is the desired gate drive voltage (usually in the range of

GATE

5 V to 10 V, 7 V being typical).

V

is the voltage drop across D1.

D

Rearranging Equation 1 and Equation 2 to solve for C

Q

C

10

BST

1

C

can then be found by rearranging Equation 1

BST2

10

C −×= (4)

BST

GATE

×=

Q

GATE

V

GATE

(3)

VVCC

−

D

C

12

BST

For example, an NTD60N02 has a total gate charge of about
12 nC at V
C

= 12 nF and C

BST1

= 7 V. Using VCC = 12 V and VD = 1 V, we find

GATE

= 6.8 nF. Good quality ceramic

BST2

capacitors should be used.

R

is used for slew rate limiting to minimize the ringing at the

BST

switch node. It also provides peak current limiting through D1.
An R

value of 1.5 Ω to 2.2 Ω is a good choice. The resistor

BST

needs to be able to handle at least 250 mW due to the peak
currents that flow through it.

BST1

BST1

) and

GATE

yields

.

A small signal diode can be used for the bootstrap diode due to
the ample gate drive voltage supplied by V
diode must have a minimum 15 V rating to withstand the
maximum supply voltage. The average forward current can be
estimated by

where
controller.

The peak surge current rating should be calculated by

MOSFET SELECTION

When interfacing the ADP3110 to external MOSFETs, the
designer should be aware of a few considerations. These help to
make a more robust design that minimizes stresses on both the
driver and MOSFETs. These stresses include exceeding the
short-time duration voltage ratings on the driver pins as well as
the external MOSFET.

It is also highly recommended to use the Boot-Snap circuit to
improve the interaction of the driver with the characteristics of
the MOSFETs. If a simple bootstrap arrangement is used, make
sure to include a proper snubber network on the SW node.

High-Side (Control) MOSFETs

The high-side MOSFET is usually selected to be high speed to
minimize switching losses (see any ADI Flex-Mode™ controller
data sheet for more details on MOSFET losses). This usually
implies a low gate resistance and low input capacitance/charge
device. Yet, there is also a significant source lead inductance
that can exist (this depends mainly on the MOSFET package; it
is best to contact the MOSFET vendor for this information).

The ADP3110 DRVH output impedance and the external
MOSFETs’ input resistance determine the rate of charge
delivery to the MOSFETs’ gate capacitance which, in turn,
determines the switching times of the MOSFETs. A large
voltage spike can be generated across the source lead inductance
when the high-side MOSFETs switch off, due to large currents
flowing in the MOSFETs during switching (usually larger at
turn off due to ramping of the current in the output inductor).
This voltage spike occurs across the internal die of the
MOSFETs and can lead to catastrophic avalanche. The
mechanisms involved in this avalanche condition can be
referenced in literature from the MOSFET suppliers.

CC

fQI

(5)

MAX

GATE

)(

AVGF

f

is the maximum switching frequency of the

MAX

VVCC

D

I

=

)(

PEAKF

R

(6)

BST

. The bootstrap

Rev. 0 | Page 8 of 12

ADP3110

The MOSFET vendor should provide a maximum voltage slew
rate at drain current rating such that this can be designed
around. The next step is to determine the expected maximum
current in the MOSFET. This can be done by

D

()

DCMAX

D

is determined for the VR controller being used with the

MAX

)(

VVCCphaseperII

OUT

MAX

×−+=

MAX

(7)

Lf

×

OUT

driver. Note this current gets divided roughly equally between
MOSFETs if more than one is used (assume a worst-case
mismatch of 30% for design margin).

L

is the output

OUT

inductor value.

When producing the design, there is no exact method for
calculating the dV/dt due to the parasitic effects in the external
MOSFETs as well as the PCB. However, it can be measured to
determine if it is safe. If it appears the dV/dt is too fast, an
optional gate resistor can be added between DRVH and the
high-side MOSFET. This resistor slows down the dV/dt, but it
also increases the switching losses in the high-side MOSFET.
The ADP3110 is optimally designed with an internal drive
impedance that works with most MOSFETs to switch them
efficiently yet minimize dV/dt. However, some high speed
MOSFETs may require this external gate resistor, depending on
the currents being switched in the MOSFET.

Low-Side (Synchronous) MOSFETs

The low-side MOSFETs are usually selected to have a low on
resistance to minimize conduction losses. This usually implies a
large input gate capacitance and gate charge. The first concern is
to make sure the power delivery from the ADP3110’s DRVL
does not exceed the thermal rating of the driver.

ratio is low enough and the low-side MOSFET internal delays
are not large enough to allow accidental turn on of the low-side
MOSFET when the high-side MOSFET turns on.

Contact Sales for an updated list of recommended low-side
MOSFETs.

PC BOARD LAYOUT CONSIDERATIONS

Use the following general guidelines when designing printed
circuit boards.

1.

Trace out the high current paths and use short, wide

(>20 mil) traces to make these connections.

2.

Minimize trace inductance between the DRVH and DRVL

outputs and the MOSFET gates.

3.

Connect the PGND pin of the ADP3110 as closely as

possible to the source of the lower MOSFET.

4.

The V

possible to the VCC and PGND pins.

5.

Use vias to other layers when possible to maximize thermal

conduction away from the IC.

The circuit in
with the ADP3181 to form a total power conversion solution for
generating V
compliant.

Figure 5 shows an example of the typical land patterns based on
the guidelines given previously. For more detailed layout
guidelines for a complete CPU voltage regulator subsystem,
refer to the Layout and Component Placement section in the
ADP3181 data sheet.

bypass capacitor should be located as closely as

CC

Figure 6 shows how four drivers can be combined

for an Intel CPU that is VRD 10.x

CC(CORE)

C

BST1

The next concern for the low-side MOSFETs is to prevent them
from inadvertently being switched on when the high-side
MOSFET turns on. This occurs due to the drain-gate (Miller,
also specified as C

) capacitance of the MOSFET. When the

rss

drain of the low-side MOSFET is switched to VCC by the high­side turning on (at a rate dV/dt), the internal gate of the low­side MOSFET is pulled up by an amount roughly equal to
VCC

× (C

). It is important to make sure this does not put

rss/Ciss

the MOSFET into conduction.

Another consideration is the nonoverlap circuitry of the
ADP3110, which attempts to minimize the nonoverlap period.
During the state of the high-side turning off to low-side turning
on, the SW pin and the conditions of SW prior to switching are
monitored to adequately prevent overlap.

However, during the low-side turn off to high-side turn on, the
SW pin does not contain information for determining the
proper switching time, so the state of the DRVL pin is monitored
to go below one sixth of V

and then a delay is added. Due to

CC

the Miller capacitance and internal delays of the low-side
MOSFET gate, one must ensure the Miller-to-input capacitance

Rev. 0 | Page 9 of 12

R

C

D1

C

VCC

Figure 5. External Component Placement Example

BST2

BST

05514-005

ADP3110

CC (CORE)

CC (CORE) RTN

V

0.8375V – 1.6V

95A TDC, 119A PK

V

MLCC IN

SOCKET

10μF × 18

5mΩ EACH

560μF/4V × 8

C24 C31

+ +

SANYO SEPC SERIES

RTH1

100kΩ, 5%

NTC

C8

R3

L1

12nF

2.2Ω

2700μF/16V/3.3A × 2

18A

370nH

C11

C10

U3

F

μ

4.7

6.8nF

ADP3110

D3

L3

Q5

NTD60N02

876

DRVH

BST1IN

1N4148

320nH/1.4mΩ

Q8

NTD110N02

Q7

NTD110N02

5

C16

SW

PGND

OD

2

3

12nF

DRVL

R5

2.2Ω

VCC

4

F

μ

C9

4.7

L2

320nH/1.4mΩ

F

μ

C7

4.7

Q1

NTD60N02

C6

876

6.8nF

DRVH

U2

ADP3110

BST1IN

D2

1N4148

Q4

NTD110N02

Q3

NTD110N02

5

C12

SW

PGND

OD

2

3

12nF

DRVL

R4

2.2Ω

VCC

4

C5

4.7μF

F

μ

C15

4.7

Q9

C14

876

6.8nF

DRVH

U4

ADP3110

BST1IN

D4

1N4148

2827262524

VCC

PWM1

PWM2

L4

320nH/1.4mΩ

Q12

NTD60N02

5

SW

DRVL

PGND

VCC

OD

2

3

4

F

μ

C13

4.7

1

1

SW1

SW3

R

R

1

SW2

R

232221201918171615

SW1

SW2

PWM3

PWM4

NTD110N02

Q11

NTD110N02

C20

12nF

R6

2.2Ω

PH2

R

158kΩ,

PH4

R

1

SW4

R

SW3

SW4

GND

PH1

R

1%

PH3

R

158kΩ, 1%

U1

ADP3181

VID4

VID3

VID2

VID1

VID0

CPUID

FBRTNFBCOMP

B

C

470pF

1

C21

CFB22pF

1nF

PWRGDENDELAYRTRAMPADJ

10

A

R

12.1kΩ

A

C

470pF

B

R

1.21kΩ

GOOD

POWER

123456789

R2

357kΩ,

1%

R1

10Ω

++

C1 C2

SANYO MV-WX SERIES

IN

V

12V

RTN

IN

V

D1

1N4148

C4

1μF

+

C3

100μF

CPU

FROM

F

μ

C19

4.7

C16

U5

1%

158kΩ,

1%

158kΩ,

CS2

R

84.5kΩ

CS1

R

35.7kΩ

CS2

C

1.5nF

CS1

C

560pF

CSSUM

CSCOMP

111213

ENABLE

6.8nF

ADP3110

D5

C22

CSREF

R

C

L5

Q13

NTD60N02

876

DRVH

BST1IN

1N4148

1nF

ILIMIT

14

T

137kΩ,

R

LDY

470kΩ

LDY

39nF

320nH/1.4mΩ

Q16

NTD110N02

Q15

NTD110N02

5

SW

DRVL

PGND

VCC

OD

2

3

4

F

μ

C17

4.7

LIM

R

150kΩ,

1%

1nF

C23

1%

FOR A DESCRIPTION OF OPTIONAL COMPONENTS, SEE THE ADP3181 THEORY OF OPERATION SECTION.

1

05514-006

Figure 6. VRD 10.x Compliant Power Supply Circuit

Rev. 0 | Page 10 of 12

ADP3110

OUTLINE DIMENSIONS

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

85

6.20 (0.2440)

5.80 (0.2284)

41

1.27 (0.0500)
BSC

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012-AA

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

8°

1.27 (0.0500)

0°

0.40 (0.0157)

× 45°

Figure 7. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body

(R-8)

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Model Temperature Range Package Description Package Option Quantity per Reel

ADP3110KRZ
ADP3110KRZ-RL

1

Z = Pb-free part.

1

0°C to 85°C Standard Small Outline Package [SOIC_N] R-8 N/A

1

0°C to 85°C Standard Small Outline Package [SOIC_N] R-8 2500

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ADP3110

NOTES

©2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

D05514–0–6/05(0)

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