Datasheet ADP2323 Datasheet (ANALOG DEVICES)

Dual 3 A, 20 V Synchronous Step-Down

Regulator with Integrated High-Side

FEATURES

Input voltage: 4.5 V to 20 V
±1% output accuracy
Integrated 90 mΩ typical high-side MOSFET
Flexible output configuration

Dual output: 3 A/3 A

Parallel single output: 6 A
Programmable switching frequency: 250 kHz to 1.2 MHz
External synchronization input with programmable phase

shift, or internal clock output
Selectable PWM or PFM mode operation
Adjustable current limit for small inductor
External compensation and soft start
Startup into precharged output

APPLICATIONS

Communications infrastructure
Networking and servers
Industrial and instrumentation
Healthcare and medical
Intermediate power rail conversion
DC-to-dc point of load applications

MOSFET

ADP2323

TYPICAL APPLICATION CIRCUIT

R

TOP1

C

FB1

FB2

C1

R

C1

COMP1

ADP2323

COMP2

R

C2

C

C2

C

SS1

SS1

EN1

BST1

PVIN1

SW1

M1

DL1

PGND

DL2

M2

SW2

SS2

EN2

PVIN2

BST2

C

SS2

C

IN2

R

BOT1

DRV

R

OSC

R

BOT2

INTVCC
MODE
SCFG
TRK2
TRK1
VDRV

GND

PGOOD2

PGOOD1

SYNC

RT

R

TOP2

C

INT

C

Figure 1.

C

C

BST1

BST2

V

IN

C

IN1

V

L1

OUT1

C

OUT1

C

OUT2

V

OUT2

L2

V

IN

09357-001

GENERAL DESCRIPTION

The ADP2323 is a full featured, dual output, step-down dc-to­dc regulator based on current-mode architecture. The ADP2323
integrates two high-side power MOSFETs and two low-side drivers
for the external N-channel MOSFETs. The two pulse-width mod­ulation (PWM) channels can be configured to deliver dual 3 A
outputs or a parallel-to-single 6 A output. The regulator operates
from input voltages of 4.5 V to 20 V, and the output voltage can
be as low as 0.6 V.

The switching frequency can be programmed between 250 kHz
and 1.2 MHz, or synchronized to an external clock to minimize
interference in multirail applications. The dual PWM channels
run 180° out of phase, thereby reducing input current ripple as
well as reducing the size of the input capacitor.

The bidirectional synchronization pin can be programmed at
a 60°, 90°, or 120° phase shift, providing the possibility for a
stackable multiphase power solution.

The ADP2323 can be set to operate in pulse-frequency modulation
(PFM) mode at a light load for higher efficiency or in forced
PWM for noise sensitive applications. External compensation
and soft start provide design flexibility. Independent enable

inputs and power good outputs provide reliable power sequencing.
To enhance system reliability, the device also includes undervoltage
lockout (UVLO), overvoltage protection (OVP), overcurrent pro­tection (OCP), and thermal shutdown (TSD).

The ADP2323 operates over the −40°C to +125°C junction
temperature range and is available in a 32-lead LFCSP_WQ
package.

100

95

90

85

80

75

70

EFFICIENCY (%)

65

V

60

55

50

0 0.5 1.0 1.5 2.0 2.5 3.0

Figure 2. Efficiency vs. Output Current at V

= 5V

OUT

V

= 3.3V

OUT

OUTPUT CURRENT (A)

= 12 V, fSW = 600 kHz

IN

09357-002

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2011 Analog Devices, Inc. All rights reserved.

ADP2323

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Typical Application Circuit ............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Functional Block Diagram .............................................................. 3

Specifications..................................................................................... 4

Absolute Maximum Ratings............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 9

Theory of Operation ...................................................................... 15

Control Scheme .......................................................................... 15

PWM Mode................................................................................. 15

PFM Mode................................................................................... 15

Precision Enable/Shutdown ...................................................... 15

Separate Input Voltages ............................................................. 15

Internal Regulator (INTVCC).................................................. 15

Bootstrap Circuitry .................................................................... 16

Low-Side Driver.......................................................................... 16

Oscillator ..................................................................................... 16

Synchronization.......................................................................... 16

Soft Start ...................................................................................... 16

Peak Current-Limit and Short-Circuit Protection................. 16

Voltage Tracking......................................................................... 17

Parallel Operation....................................................................... 17

Power Good................................................................................. 17

Overvoltage Protection.............................................................. 17

Undervoltage Lockout............................................................... 18

Thermal Shutdown .................................................................... 18

Applications Information.............................................................. 19

Input Capacitor Selection.......................................................... 19

Output Voltage Setting .............................................................. 19

Voltage Conversion Limitations............................................... 19

Current-Limit Setting................................................................ 19

Inductor Selection...................................................................... 19

Output Capacitor Selection....................................................... 20

Low-Side Power Device Selection............................................ 20

Programming UVLO Input ...................................................... 21

Compensation Components Design ....................................... 21

Design Example.............................................................................. 23

Output Voltage Setting .............................................................. 23

Current-Limit Setting................................................................ 23

Frequency Setting....................................................................... 23

Inductor Selection...................................................................... 23

Output Capacitor Selection....................................................... 23

Low-Side MOSFET Selection ................................................... 24

Compensation Components..................................................... 24

Soft Start Time Programming .................................................. 24

Input Capacitor Selection.......................................................... 24

External Components Recommendation.................................... 25

Typical Application Circuits ......................................................... 26

Outline Dimensions....................................................................... 31

Ordering Guide .......................................................................... 31

REVISION HISTORY

7/11—Revision 0: Initial Version

Rev. 0 | Page 2 of 32

ADP2323

FUNCTIONAL BLOCK DIAGRAM

EN1

COMP1

SS1

TRK1

FB1

PGOOD1

MODE

SCFG

SYNC

RT

1.2V

4µA1µA

SLOPE RAMP1

0.6V

I

SS1

0.7V

0.54V

+

+

AMP1

+

–

OVP

–

+

–

+

OSCILLATOR

EN1_BUF

SKIP MODE

THRESHOLD

MODE_BUF

CLK1

SLOPE RAMP1

CLK2

SLOPE RAMP2

ADP2323

+

HICCUP

OCP

MODE

–

I1

MAX

Σ

+
CMP1

–

SKIP

–

CMP1

+

MODE_BUF

CLK1

CONTROL

LOGIC

AND MOSFET

DRIVER WITH

ANTICROSS

PROTECTION

I1

MAX

EN1_BUF

EN2_BUF

UVLO

+

A

CS1

–

DRIVER

VDRV

DRIVER

ZERO CURRENT

CMP

CURRENT-

LIMIT

SELECTION

5V REGULATO R

BOOST

REGULATOR

–

+

PVIN1

PVIN1

BST1

NFET1

SW1

DL1

PGND

VDRV

INTVCC

GND

EN2

COMP2

SS2

TRK2

FB2

PGOOD2

1.2V

4µA1µA

SLOPE RAMP2

0.6V

I

SS2

0.7V

0.54V

+

+

+

–

–

+

–

+

AMP2

OVP

EN2_BUF

Σ

SKIP MODE

THRESHOLD

UVLO

+

A

CS2

–

DRIVER

VDRV

CMP

BOOST

REGULATOR

–

+

NFET2

+

HICCUP

OCP

MODE

–

I2

MAX

+
CMP2

–

SKIP

–

CMP2

+

MODE_BUF

CLK2

CONTROL

LOGIC

AND MOSFET

DRIVER WITH

ANTICROSS

PROTECTION

I2

MAX

DRIVER

ZERO CURRENT

CURRENT-

LIMIT

SELECTION

PVIN2

BST2

SW2

DL2

09357-042

Figure 3. Functional Block Diagram

Rev. 0 | Page 3 of 32

ADP2323

SPECIFICATIONS

PVIN1 = PVIN2 = 12 V at TJ = −40°C to +125°C, unless otherwise noted.

Table 1.

Parameters Symbol Test Conditions/Comments Min Typ Max Units

POWER INPUT (PVINx PINS)

Power Input Voltage Range V
Quiescent Current (PVIN1 + PVIN2) IQ MODE = GND, no switching 3 5 mA
Shutdown Current (PVIN1 + PVIN2) I
PVINx Undervoltage Lockout Threshold UVLO

PVINx Rising 4.3 4.5 V
PVINx Falling 3.5 3.8 V

FEEDBACK (FBx PINS)

FBx Regulation Voltage1 V
FBx Bias Current IFB 0.01 0.1 µA

ERROR AMPLIFIER (COMPx PINS)

Transconductance gm 230 300 370 µS
EA Source Current I
EA Sink Current I

INTERNAL REGULATOR (INTVCC PIN)

INTVCC Voltage 4.75 5 5.25 V
Dropout Voltage I
Regulator Current Limit 40 75 120 mA

SWITCH NODE (SWx PINS)

High-Side On Resistance2 V
SWx Peak Current Limit R
R
R
SWx Minimum On Time3 t
SWx Minimum Off Time3 t

LOW-SIDE DRIVER (DLx PINS )

Rising Time3 C
Falling Time3 C
Sourcing Resistor 4 6 Ω
Sinking Resistor 2 4.5 Ω

OSCILLATOR (RT PIN)

PWM Switching Frequency fSW R
PWM Frequency Range 250 1200 kHz

SYNCHRONIZATION (SYNC PIN)

SYNC Input SYNC configured as input

Synchronization Range 300 1200 kHz
Minimum On Pulse Width 100 ns
Minimum Off Pulse Width 100 ns
High Threshold 1.3 V
Low Threshold 0.4 V

SYNC Output SYNC configured as output

Frequency on SYNC Pin f
Positive Pulse Time 100 ns

SOFT START (SSx PINS)

SSx Pin Source Current ISS 2.5 3.5 4.5 µA

4.5 20 V

PVIN

EN1 = EN2 = GND 50 100 µA

SHDN

PVINx = 4.5 V to 20 V 0.594 0.6 0.606 V

FB

25 45 65 µA

SOURCE

25 45 65 µA

SINK

= 30 mA 400 mV

INTVCC

to VSW = 5 V 90 130 mΩ

BST

= floating, V

ILIM

= 47 kΩ, V

ILIM

= 15 kΩ, V

ILIM

130 ns

MIN_ON

150 ns

MIN_OFF

= 2.2 nF, see Figure 19 20 ns

DL

= 2.2 nF, see Figure 22 10 ns

DL

= 100 kΩ 530 600 670 kHz

OSC

f

CLKOUT

to VSW = 5 V 4 4.8 5.8 A

BST

to VSW = 5 V 2.3 3 3.7 A

BST

to VSW = 5 V 0.8 1.5 2.2 A

BST

kHz

SW

Rev. 0 | Page 4 of 32

ADP2323

Parameters Symbol Test Conditions/Comments Min Typ Max Units

TRACKING INPUT (TRKx PINS)

TRKx Input Voltage Range 0 600 mV

TRKx-to-FBx Offset Voltage TRKx = 0 mV to 500 mV −10 +10 mV

TRKx Input Bias Current 100 nA

POWER GOOD (PGOODx PINS)

Power Good Rising Threshold 87 90 93 %

Power Good Hysteresis 5 %

Power Good Deglitch Time From FBx to PGOODx 16 Clock cycle

PGOODx Leakage Current V

PGOODx Output Low Voltage I

ENABLE (ENx PINS)

ENx Rising Threshold 1.2 1.28 V

ENx Falling Threshold 1.02 1.1 V

ENx Source Current EN voltage below falling threshold 5 µA

EN voltage above rising threshold 1 µA
MODE (MODE PIN)

Input High Voltage 1.3 V

Input Low Voltage 0.4 V

THERMAL

Thermal Shutdown Threshold 150 °C

Thermal Shutdown Hysteresis 15 °C

1

Tested in a feedback loop that adjusts VFB to achieve a specified voltage on the COMPx pin.

2

Pin-to-pin measurements.

3

Guaranteed by design.

= 5 V 0.1 1 µA

PGOOD

= 1 mA 50 100 mV

PGOOD

Rev. 0 | Page 5 of 32

ADP2323

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

PVIN1, PVIN2, EN1, EN2 −0.3 V to +22 V
SW1, SW2 −1 V to +22 V
BST1, BST2 VSW + 6 V
FB1, FB2, SS1, SS2,COMP1, COMP2,

PGOOD1, PGOOD2, TRK1, TRK2, SCFG,
SYNC, RT, MODE

INTVCC, VDRV, DL1, DL2 −0.3 V to +6 V
PGND to GND −0.3 V to +0.3 V
Temperature Range

Operating (Junction) −40°C to +125°C
Storage −65°C to +150°C

Soldering Conditions JEDEC J-STD-020

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

−0.3 V to +6 V

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Boundary Condition

θJA is measured using natural convection on a JEDEC 4-layer
board, and the exposed pad is soldered to the printed circuit
board (PCB) with thermal vias.

Table 3. Thermal Resistance

Package Type θJA Unit

32-Lead LFCSP_WQ 32.7 °C/W

ESD CAUTION

Rev. 0 | Page 6 of 32

ADP2323

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

FB1

COMP1

SS1

TRK1

EN1

PVIN1

PVIN1

SW1

32313029282726

PGOOD1

1SW1
2

SCFG
SYNC

3
4
5
6
7
8

ADP2323

TOP VIEW

(Not to Scale)

9

10111213141516

FB2

SS2

TRK2

COMP2

GND

INTVCC

RT

MODE

PGOOD2

NOTES

1. THE EXPOSED PAD SHOULD BE SOLDERED TO AN EXTERNAL GND PLANE.

Figure 4. Pin Configuration (Top View)

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 PGOOD1 Power-Good Output (Open Drain) for Channel 1. A pull-up resistor of 10 kΩ to 100 kΩ is recommended.
2 SCFG

Synchronization Configuration Input. The SCFG pin configures the SYNC pin as an input or output.
Connect SCFG to INTVCC to configure SYNC as an output. Using a resistor to pull down to GND
configures SYNC as an input with various phase shift degrees.

3 SYNC

Synchronization. This pin can be configured as an input or an output. When configured as an output,
it provides a clock at the switching frequency. When configured as an input, this pin accepts an
external clock to which the regulators are synchronized and the phase shift is configured by SCFG.
Note that when SYNC is configured as an input, the PFM mode is disabled and the device works only

in continuous conduction mode (CCM).
4 GND Analog Ground. Connect to the ground plane.
5 INTVCC

Internal 5 V Regulator Output. The IC control circuits are powered from this voltage. Place a 1 F

ceramic capacitor between INTVCC and GND.
6 RT

Connect a resistor between RT and GND to program the switching frequency between 250 kHz and

1.2 MHz.

7 MODE

Mode Selection. When this pin is connected to INTVCC, the PFM mode is disabled and the regulator

works only in CCM. When this pin is connected to ground, the PFM mode is enabled. If the low-side

device is a diode, the MODE pin must be connected to ground.
8 PGOOD2

Power-Good Output (Open Drain) for Channel 2. A pull-up resistor of 10 kΩ to 100 kΩ is

recommended.
9 FB2

10 COMP2

Feedback Voltage Sense Input for Channel 2. Connect to a resistor divider from the Channel 2 output

voltage, V

. Connect FB2 to INTVCC for parallel applications.

OUT2

Error Amplifier Output for Channel 2. Connect an RC network from COMP2 to GND. Connect COMP1

and COMP2 together for parallel applications.
11 SS2

Soft Start Control for Channel 2. Connect a capacitor from SS2 to GND to program the soft start time.

For parallel applications, SS2 remains open.
12 TRK2

Tracking Input for Channel 2. To track a master voltage, drive this pin from a voltage divider from the

master voltage. If the tracking function is not used, connect TRK2 to INTVCC.
13 EN2

Enable Pin for Channel 2. An external resistor divider can be used to set the turn-on threshold. When

not using the enable pin, connect EN2 to PVIN2.
14, 15 PVIN2

Power Input for Channel 2. Connect PVIN2 to the input power source, and connect a bypass capacitor

between PVIN2 and ground.
16, 17 SW2 Switch Node for Channel 2.
18 BST2 Supply Rail for the Gate Drive of Channel 2. Place a 0.1 µF capacitor between SW2 and BST2.
19 DL2

Low-Side Gate Driver Output for Channel 2. Connect a resistor between DL2 and PGND to program

the current-limit threshold of Channel 2.
20 VDRV

Low-Side Driver Supply Input. Connect VDRV to INTVCC. Place a 1 µF ceramic capacitor between the

VDRV pin and PGND.
21 PGND Driver Power Ground. Connect to the source of the synchronous N-channel MOSFET.

25

24
23

BST1
DL1

22

PGND

21
20

VDRV

19

DL2

18

BST2
SW2

17

EN2

SW2

PVIN2

PVIN2

09357-003

Rev. 0 | Page 7 of 32

ADP2323

Pin No. Mnemonic Description

22 DL1

23 BST1 Supply Rail for the Gate Drive of Channel 1. Place a 0.1 µF capacitor between SW1 and BST1.
24, 25 SW1 Switch Node for Channel 1.
26, 27 PVIN1

28 EN1

29 TRK1

30 SS1 Soft Start Control for Channel 1. To program the soft start time, connect a capacitor from SS1 to GND.
31 COMP1

32 FB1

Exposed Pad Solder the exposed pad to an external GND plane.

Low-Side Gate Driver Output for Channel 1. Connect a resistor between this pin and PGND to
program the current-limit threshold of Channel 1.

Power Input for Channel 1. This pin is the power input for Channel 1 and also provides power for the
internal regulator. Connect to the input power source and connect a bypass capacitor between PVIN1
and ground.

Enable Pin for Channel 1. An external resistor divider can be used to set the turn-on threshold. When
not using the enable pin, connect the EN1 pin to PVIN1.

Tracking Input for Channel 1. To track a master voltage, drive this pin from a voltage divider from the
master voltage. If the tracking function is not used, connect TRK1 to INTVCC.

Error Amplifier Output for Channel 1. Connect an RC network from COMP1 to GND. Connect COMP1
and COMP2 together for a parallel application.

Feedback Voltage Sense Input for Channel 1. Connect to a resistor divider from the Channel 1 output
voltage, V

OUT1

.

Rev. 0 | Page 8 of 32

ADP2323

TYPICAL PERFORMANCE CHARACTERISTICS

Operating conditions: TA = 25°C, VIN = 12 V, V

100

95

90

85

80

75

70

EFFICIENCY (%)

65

60

55

50

100

90

80

70

60

50

40

EFFICIENCY (%)

30

20

10

40

INDUCTOR: CDRH105RNP-3R3N
MOSFET: FDS8880

0 0.5 1.0 1.5 2.0 2.5 3.0

OUTPUT CURRENT (A)

Figure 5. Efficiency at V

= 12 V, fSW = 600 kHz, FPWM

IN

V

= 3.3V, FPWM

OUT

V

= 3.3V, PFM

OUT

V

= 5V, FPWM

OUT

V

= 5V, PFM

OUT

INDUCTOR: CDRH105RNP- 3R3N
MOSFET: FDS8880

0

0.01 0. 1 1 10

OUTPUT CURRENT (A)

Figure 6. Efficiency at V

= 12 V, fSW = 600 kHz, PFM

IN

= 3.3 V, L = 4.7 µH, C

OUT

V

= 5.0V

OUT

V

= 3.3V

OUT

V

= 2.5V

OUT

V

= 1.8V

OUT

V

= 1.5V

OUT

V

= 1.2V

OUT

= 2 × 47 µF, fSW = 600 kHz, unless otherwise noted.

OUT

100

95

90

85

80

75

70

EFFICIENCY (%)

65

60

INDUCTOR: CDRH105RNP- 6R8N

55

MOSFET: FDS8880

50

0 0.5 1.0 1.5 2.0 2.5 3.0

09357-005

Figure 8. Efficiency at V

100

90

80

70

60

50

40

EFFICIENCY (%)

30

20

INDUCTOR: CDRH105RNP- 6R8N

10

MOSFET: FDS8880

0

0.01 0. 1 1 10

09357-006

Figure 9. Efficiency at V

3.20

OUTPUT CURRENT (A)

= 12 V, fSW = 300 kHz, FPWM

IN

OUTPUT CURRENT (A)

= 12 V, fSW = 300 kHz, PFM

IN

V

= 3.3V, FPWM

OUT

V

= 3.3V, PFM

OUT

V

= 5V, FPWM

OUT

V

= 5V, PFM

OUT

V

= 5.0V

OUT

V

= 3.3V

OUT

V

= 2.5V

OUT

V

= 1.8V

OUT

V

= 1.5V

OUT

V

= 1.2V

OUT

09357-008

09357-009

35

30

25

20

SHUTDOWN CURRENT (μ A)

15

10

4 6 8 10 12 14 16 18 20

TJ = –40°C
TJ = +25°C
TJ = +125°C

VIN (V)

Figure 7. Shutdown Current vs. V

IN

09357-007

Rev. 0 | Page 9 of 32

3.15

3.10

3.05

3.00

2.95

2.90

QUIESCENT CURRENT (mA)

2.85

2.80
4 6 8 101214161820

TJ = –40°C
TJ = +25°C
TJ = +125°C

VIN (V)

Figure 10. Quiescent Current vs. V

IN

09357-010

ADP2323

T

C

4.5

4.4

4.3

4.2

4.1

4.0

3.9

3.8

UVLO THRESHOLD (V)

3.7

3.6

3.5
–40 –20 0 20 40 60 80 100 120

1.10

1.08

1.06

1.04

1.02

1.00

0.98

0.96

EN SOURCE CURRENT (µA)

0.94

0.92

0.90
–40 –20 0 20 40 60 80 100 120

606

604

602

AGE (mV)

600

598

FEEDBACK VOL

596

594

–40 –20 0 20 40 60 80 100 120

RISING

FALL ING

TEMPERATURE (°C)

Figure 11. UVLO Threshold vs. Temperature

TEMPERATURE (°C)

Figure 12. EN Source Current at V

= 1.5 V

EN

TEMPERATURE (°C)

Figure 13. FB Voltage vs. Temperature

1.30

1.25

RISING

1.20

1.15

1.10

ENABLE THRESHOL D (V)

1.05

1.00
–40 –20 0 20 40 60 80 100 120

09357-011

FALL ING

TEMPERATURE (°C)

09357-014

Figure 14. EN Threshold vs. Temperature

5.10

5.05

5.00

4.95

4.90

4.85

4.80

4.75

EN SOURCE CURRENT (µA)

4.70

4.65

4.60
–40 –20 0 20 40 60 80 100 120

09357-012

Figure 15. EN Source Current at V

350

340

330

320

310

TANC E (µ S )

300

290

280

TRANSCONDU

270

260

250

–40 –20 0 20 40 60 80 100 120

09357-013

TEMPERATURE (°C)

TEMPERATURE (°C)

Figure 16. g

vs. Temperature

m

= 1 V

EN

09357-015

09357-016

Rev. 0 | Page 10 of 32

ADP2323

C

660

5.4

640

620

Y (kHz)

600

580

FREQUEN

R

= 100kΩ

560

540

–40 –20 0 20 40 60 80 100 120

OSC

TEMPERATURE (°C)

Figure 17. Frequency vs. Temperature

130

120

110

100

90

80

MOSFET RESISTOR (mΩ)

70

60

50

–40 –20 0 20 40 60 80 100 120

Figure 18. MOSFET R

TEMPERATURE (°C)

vs. Temperature

DSON

5.2

5.0

4.8

4.6

VOLTAGE (V)

4.4

4.2

4.0
4 6 8 10 12 14 16 18 20

09357-017

Figure 20. INTVCC Voltage vs. V

4.5

4.3

4.1

3.9

3.7

3.5

3.3

3.1

2.9

SSx PIN SOURCE CURRENT (µA)

2.7

2.5
–40 –20 0 20 40 60 80 100 120

09357-018

VIN (V)

TEMPERATURE (°C)

09357-020

IN

09357-021

Figure 21. SSx Pin Source Current vs. Temperature

1

2

CH1 5.00V CH2 2.00V M20.0ns A CH1 1.10V

Figure 19. Low-Side Driver Rising Edge Waveform, C

SW

DL

T 31.20%

DL

= 2.2 nF

1

2

09357-019

CH1 5.00V CH2 2.00V M20.0ns A CH1 1.10V

Figure 22. Low-Side Driver Falling Edge Waveform, C

SW

DL

T 60.20%

= 2.2 nF

DL

09357-022

Rev. 0 | Page 11 of 32

ADP2323

5.8

5.6

5.4

5.2

5.0

4.8

4.6

PEAK CURRENT LIMI T (A)

4.4

4.2

4.0
–40 –20 0 20 40 60 80 100 120

Figure 23. Current-Limit Threshold vs. Temperature, R

2.0

1.8

1.6

TEMPERATURE (°C)

= Floating

ILIM

3.2

3.1

3.0

2.9

2.8

2.7

PEAK CURRENT LIMI T (A)

2.6

2.5
–40 –20 0 20 40 60 80 100 120

09357-023

Figure 26. Current-Limit Threshold vs. Temperature, R

1

V

(AC)

OUT

I

L

TEMPERATURE (°C)

= 47 kΩ

ILIM

09357-026

1.4

1.2

PEAK CURRENT LIMI T (A)

1.0

0.8
–40 –20 0 20 40 60 80 100 120

TEMPERATURE (°C)

Figure 24. Current-Limit Threshold vs. Temperature, R

V

(AC)

I

SW

L

OUT

B

W

CH2 10.0V
CH4 500mA Ω

M2.00µs A CH2 9.40V

T 50.20%

1

4

2

CH1 10.0mV

Figure 25. Discontinuous Conduction Mode (DCM)

= 15 kΩ

ILIM

4

2

CH1 10.0mV

09357-024

SW

B

CH2 10.0V

W

CH4 2.00A Ω

M2.00µs A CH2 5.80V

T 50.00%

09357-027

Figure 27. Continuous Conduction Mode (CCM)

1

V

(AC)

OUT

I

4

2

09357-025

CH1 100mV

L

SW

B

W

CH2 10.0V
CH4 1.00A Ω

M400µs A CH1 –12.0mV

T 60.40%

09357-028

Figure 28. Power Saving Mode

Rev. 0 | Page 12 of 32

ADP2323

EN

3

V

OUT

1

PGOOD

2

I

OUT

4

CH1 2.00V

CH3 10.0V

B

W

CH2 5.00V
CH4 2.00A Ω

M1.00ms A CH2 1.80V

T 50.40%

Figure 29. Soft Start With Full Load

V

(AC)

1

4

CH1 100mV

OUT

I

OUT

B

W

CH4 1.00A Ω

M200µs A CH4 1.00A

T 70.20%

Figure 30. Load Transient Response, 0.5 A to 2.5 A

EN

3

V

OUT

1

PGOOD

2

I

L

4

09357-029

CH1 2.00V

CH3 10.0V

B

W

CH2 5.00V
CH4 1.00A Ω

M1.00ms A CH2 1.80V

T 50.40%

09357-032

Figure 32. Precharged Output

(AC)

V

OUT

1

V

IN

3

SW

I

OUT

2

OUT

09357-033

= 3 A

09357-030

CH1 20.0mV

CH3 5.00V

Figure 33. Line Transient Response, V

B

CH2 5.00V M1.00ms A CH1 –8.00mV

W

B

W

T 72.00%

from 8 V to 14 V, I

IN

1

2

4

CH1 2.00V

V

OUT

SW

I

L

B

CH2 10.0V

W

CH4 2.00A Ω

Figure 31. Output Short

M10.0ms A CH1 960mV

T 20.60%

09357-031

Rev. 0 | Page 13 of 32

1

2

4

CH1 2.00V

V

OUT

SW

I

L

B

W

CH2 10.0V
CH4 2.00A Ω

M10.0ms A CH1 1.28V

T 60.40%

Figure 34. Output Short Recovery

09357-034

ADP2323

SYNC

3

SW1

1

SW2

2

CH1 10.0V

CH3 5.00V

CH2 10.0V M1.00µs A CH3 2.90V

T 50.20%

Figure 35. External Synchronization with 60° Phase Shift

SYNC

3

SW1

1

SW2

2

SYNC

3

SW1

1

SW2

2

09357-035

CH1 10.0V

CH3 5.00V

CH2 10.0V M1.00µs A CH3 2.90V

T 50.20%

09357-038

Figure 38. External Synchronization with 90° Phase Shift

SW1

1

2

I

3

L1

SW2

I

L2

CH1 10.0V

CH3 5.00V

CH2 10.0V M1.00µs A CH3 2.90V

T 50.20%

Figure 36. External Synchronization with 120° Phase Shift

V

MASTER

V

SLAVE

3

CH3 1.00V

B

W

CH2 1.00V

B

M2.00ms A CH2 660mV

W

T 43.00%

Figure 37. Coincident Tracking

09357-036

09357-037

CH1 10.0V

CH3 2.00A Ω CH4 2.00A Ω

CH2 10.0V M1.00µs A CH2 5.80V

T 50.00%

Figure 39. Dual Phase, Single Output, V

V

MASTER

V

3

CH3 1.00V

B

W

CH2 1.00V

B

M2.00ms A CH2 660mV

W

= 3.3 V, I

OUT

SLAVE

T 43.00%

OUT

09357-039

= 6 A

09357-040

Figure 40. Ratiometric Tracking

Rev. 0 | Page 14 of 32

ADP2323

THEORY OF OPERATION

The ADP2323 is a full featured, dual output, step-down dc­to-dc regulator based on current-mode architecture. It integrates
two high-side power MOSFETs and two low-side drivers for
external MOSFETs. The ADP2323 targets high performance
applications that require high efficiency and design flexibility.

The ADP2323 can operate with an input voltage from 4.5 V
to 20 V, and can regulate the output voltage down to 0.6 V.
Additional features for flexible design include programmable
switching frequency, programmable soft start, external compen­sation, independent enable inputs, and power good outputs.

CONTROL SCHEME

The ADP2323 uses a fixed frequency, current-mode PWM
control architecture during medium to full loads, but shifts to
a power save mode (PFM) at light loads when the PFM mode
is enabled. The power save mode reduces switching losses and
boosts efficiency under light loads. When operating in the
fixed frequency PWM mode, the duty cycle of the integrated
N-channel MOSFET (referred to interchangeably as NFET or
MOSFET) is adjusted, which, in turn, regulates the output
voltage. When operating in power save mode, the switching
frequency is adjusted to regulate the output voltage.

PWM MODE

In PWM mode, the ADP2323 operates at a fixed frequency
that is set by an external resistor. At the start of each oscillator
cycle, the high-side NFET turns on, placing a positive voltage
across the inductor. The inductor current increases until the
current sense signal crosses the peak inductor current threshold
that turns off the high-side NFET and turns on the low-side
NFET (diode). This places a negative voltage across the
inductor causing the inductor current to reduce. The low­side NFET (diode) stays on for the remainder of the cycle or
until the inductor current reaches zero.

PFM MODE

Pull the MODE pin to ground to enable the PFM mode.
When the COMPx voltage is below the PFM threshold
voltage, the device enters the PFM mode.

When the device enters the PFM mode, it monitors the FBx
voltage to regulate the output voltage. Because the high-side
and low-side NFETs are turned off, the output voltage drops
due to the load current discharging the output capacitor. When
the FBx voltage drops below 0.605 V, the device starts switching
and the output voltage increases as the output capacitor is
charged by the inductor current. When the FBx voltage exceeds

0.62 V, the device turns off both the high-side and low-side
NFETs until the FBx voltage drops to 0.605 V. In the PFM
mode, the output voltage ripple is larger than the ripple in
the PWM mode.

PRECISION ENABLE/SHUTDOWN

The ADP2323 has two independent enable pins (EN1 and
EN2) for each channel. The ENx pin has an internal pull­down current source (5 μA) that provides default turn off
when an ENx pin is open.

When the voltage on the EN1 or EN2 pin exceeds 1.2 V
(typical), Channel 1 or Channel 2 is enabled and the internal
pull-down current source at the EN1 or EN2 pin is reduced
to 1 μA, which allows the user to program the input voltage
undervoltage lockout (UVLO).

When the voltage on the EN1 or EN2 pin drops below 1.1 V
(typical), Channel 1 or Channel 2 turns off. When EN1 and
EN2 are both below 1.1 V, all of the internal circuits turn off
and the device enters the shutdown mode.

SEPARATE INPUT VOLTAGES

The ADP2323 supports two separate input voltages. This means
that the PVIN1 and PVIN2 voltages can be connected to two
different supply voltages. In these types of applications, the
PVIN1 voltage needs to be above the UVLO voltage before the
PVIN2 voltage begins to rise because the PVIN1voltage provides
the power supply for the internal regulator and control circuitry.

This feature makes it possible for a cascading supply operation
as shown in Figure 41, where PVIN2 is sourced from the
Channel 1 output. In this configuration, the Channel 1 output
voltage needs to be high enough to maintain Channel 2 in
regulation, and the Channel 1 output voltage needs to be
higher than the input voltage UVLO threshold.

V

OUT1

C

OUT1

V

IN

L1

M1

PVIN1

SW1

DL1

Figure 41. Cascading Supply Operation

ADP2323

PGND

PVIN2

SW2

DL2

M2

L2

C

V

OUT2

OUT2

INTERNAL REGULATOR (INTVCC)

The internal regulator provides a stable voltage supply for the
internal control circuits and bias voltage for the low-side gate
drivers. A 1 μF ceramic capacitor is recommended to be placed
between INTVCC and GND. The internal regulator also in­cludes a current-limit circuit for protection.

The internal regulator is active when either one of the channels
is enabled. The PVIN1 pin provides power for the internal
regulator that is used by both channels.

09357-043

Rev. 0 | Page 15 of 32

ADP2323



BOOTSTRAP CIRCUITRY

The ADP2323 integrates the boot regulators to provide the
gate drive voltage for the high-side NFETs. The regulators
generate 5 V bootstrap voltages between the BSTx pin and
the SWx pin.

It is recommended that an X7R or an X5R, 0.1 µF ceramic
capacitor be placed between the BSTx and the SWx pins.

LOW-SIDE DRIVER

The DLx pin provides the gate drive for the low-side
N-channel MOSFET. Internal circuitry monitors the gate
driver signal to ensure break-before-make switching to
prevent cross conduction.

The VDRV pin provides the power supply to the low-side
drivers. It is limited to a 5.5 V maximum input, and placing
a 1 µF ceramic capacitor close to this pin is recommended.

OSCILLATOR

A resistor from RT to GND programs the switching
frequency according to the following equation:

000,60

[kHz] =

f

SW

R

OSC

A 200 kΩ resistor sets the frequency to 300 kHz, and a
100 kΩ resistor sets the frequency to 600 kHz. Figure 42
shows the typical relationship between f

1200

1100

1000

900

800

700

600

FREQUENCY ( kHz)

500

400

300

200

70 110 150 190 230 250

50 90 130 170 210

SYNCHRONIZATION

The SYNC pin can be configured as an input or an output by
setting the SCFG pin as shown in Table 5.

Table 5. SCFG Configuration

SCFG SYNC Phase Shift

High Output 0°
GND Input 90°
180 kΩ to GND Input 120°
100 kΩ to GND Input 60°

]k[

R

Figure 42. f

OSC

SW

(kΩ)

vs. R

OSC

SW

and R

OSC

.

09357-044

When the SYNC pin is configured as an output, it generates a
clock with a frequency that is equal to the internal switching
frequency.

When the SYNC pin is configured as an input, the ADP2323
synchronizes to the external clock that is applied to the SYNC
pin, and the internal clock must be programmed lower than
the external clock. The phase shift can be programmed by the
SCFG pin.

When working in synchronization mode, the ADP2323
disables the PFM mode and works only in the CCM mode.

SOFT START

The SSx pins are used to program the soft start time. Place a
capacitor between SSx and GND; an internal current charges
this capacitor to establish the soft start ramp. The soft start
time can be calculated using the following equation:

6.0

CV



T

SS

SS

I

SS

where:

C

is the soft start capacitance.

SS

I

is the soft start pull-up current (3.5 µA).

SS

If the output voltage is precharged prior to power up, the
ADP2323 prevents the low-side MOSFET from turning on
until the soft start voltage exceeds the voltage on the FBx pin.

During soft start, the ADP2323 uses frequency foldback to
prevent output current runaway. The switching frequency is
reduced according to the voltage present at the FBx pin, which
allows more time for the inductor to discharge. The correla­tion between the switching frequency and the FBx pin voltage
is listed in Table 6.

Table 6. FBx Pin Voltage and Switching Frequency

FBx Pin Voltage Switching Frequency

VFB ≥ 0.4 V fSW

0.4 V > VFB ≥ 0.2 V 1/2 fSW
VFB < 0.2 V 1/4 fSW

PEAK CURRENT-LIMIT AND SHORT-CIRCUIT PROTECTION

The ADP2323 uses a peak current-limit protection circuit to
prevent current runaway. Place a resistor between DLx and
PGND to program the current-limit value listed in Table 7. The
programmable current-limit threshold feature allows for the
use of a small size inductor for low current applications.

Table 7. Peak Current-Limit Threshold Setting

R

Peak Current-Limit Threshold

ILIM

Floating 4.8 A
47 kΩ 3 A
15 kΩ 1.5 A

Rev. 0 | Page 16 of 32

ADP2323

V

The ADP2323 uses hiccup mode for overcurrent protection.
When the peak inductor current reaches the current-limit
threshold, the high-side MOSFET turns off and the low-side
driver turns on until the next cycle while the overcurrent
counter increments.

If the overcurrent counter reaches 10, or the FBx pin voltage
falls to 0.51 V after the soft start, the device enters hiccup mode.
During this mode, the high-side MOSFET and low-side driver
are both turned off. The device remains in this mode for seven
soft start times and then attempts to restart from soft start. If the
current-limit fault is cleared, the device resumes normal oper­ation; otherwise, it reenters hiccup mode.

In some cases, the input voltage (PVIN) ramp rate is too slow
or the output capacitor is too large to support the setting regu­lation voltage during the soft start causing the device to enter
the hiccup mode. To avoid such cases, use a resistor divider
at the ENx pin to program the input voltage UVLO or use a
longer soft start time.

VOLTAGE TRACKING

The ADP2323 has tracking input, TRKx, that allows the output
voltage to track an external (master) voltage. It allows power
sequencing applicable to FPGAs, DSPs, and ASICs, which may
require a power sequence between the core and the I/O voltages.

The internal error amplifier includes three positive inputs:
the internal reference voltage, the soft start voltage, and the
tracking input voltage. The error amplifier regulates the feed­back voltage to the lowest of the three voltages. To track a master
voltage, tie the TRKx pin to a resistor divider from the master
voltage as shown in Figure 43.

MASTER

R

TRK_TOP

TRKx SWx

R

TRK_BOT

ADP2323

FBx

Figure 43. Voltage Tracking

A common application is coincident tracking, which is shown in
Figure 44. Coincident tracking limits the slave output voltage
to be the same as the master voltage until it reaches regulation.

= R

For coincident tracking, set R

VOLTAGE

TRK_TOP

TOP

and R

V

V

R

TOP

R

BOT

MASTER

SLAVE

V

TRK_BOT

SLAVE

= R

09357-045

BOT

.

Ratiometric tracking is shown in Figure 45. The slave output is
limited to a fraction of the master voltage. In this application, the
slave and master voltages reach the final value at the same time.

V

MASTER

V

SLAVE

VOLTAGE

TIME

Figure 45. Ratiometric Tracking

09357-047

The ratio of the slave output voltage to the master voltage is a
function of the two dividers, as follows:

R

TOP

+

V

V

MASTER

SLAVE

R

11+

BOT

R

R

TOPTRK

_

BOTTRK

_

=

The final TRKx pin voltage must be higher than 0.54 V. If the
TRK function is not used, connect the TRKx pin to INTVCC.

PARALLEL OPERATION

ADP2323 supports a two phase parallel operation to provide

a single output of 6 A. To configure the ADP2323 as a two
phase single output

Connect the FB2 pin to INTVCC, thereby disabling the

1.
Channel 2 error amplifier.

Connect COMP1 to COMP2 and connect EN1 to EN2.

2.

Use SS1 to set the soft start time and keep SS2 open.

3.

During parallel operation, the voltages of PVIN1 and PVIN2
should be the same.

POWER GOOD

The power good (PGOODx) pin is an active high, open drain
output that indicates if the regulator output voltage is within
regulation. High indicates that the voltage at an FBx pin (and,
hence, the output voltage) is above 90% of the reference voltage.
Low indicates that the voltage at an FBx pin (and, hence, the
output voltage) is below 85% of the reference voltage. There
is a 16-cycle deglitch time between FBx and PGOODx.

OVERVOLTAGE PROTECTION

The ADP2323 provides an overvoltage protection (OVP)
feature to protect the system against the output shorting to a
higher voltage supply or when a strong load transient occurs.
If the feedback voltage increases to 0.7 V, the internal high­side MOSFET and low-side driver turn off until the voltage at
the FBx pin reduces to 0.63 V, at which time the ADP2323
resumes normal operation.

TIME

Figure 44. Coincident Tracking

09357-046

Rev. 0 | Page 17 of 32

ADP2323

UNDERVOLTAGE LOCKOUT

The undervoltage lockout (UVLO) threshold is 4.2 V with

0.5 V hysteresis to prevent the device from power-on glitches.
When the PVIN1 or PVIN2 voltage rises above 4.2 V, Channel 1
or Channel 2 is enabled and the soft start period initiates. When
either PVIN1 or PVIN2 drops below 3.7 V, it turns off Channel 1
or Channel 2, respectively.

THERMAL SHUTDOWN

In the event that the ADP2323 junction temperature exceeds
150°C, the thermal shutdown circuit turns off the regulator. A
15°C hysteresis is included so that the ADP2323 does not
recover from thermal shutdown until the on-chip tempera­ture drops below 135°C. Upon recovery, soft start is initiated
prior to normal operation.

Rev. 0 | Page 18 of 32

ADP2323







APPLICATIONS INFORMATION

INPUT CAPACITOR SELECTION

The input decoupling capacitor attenuates high frequency
noise on the input and acts as an energy reservoir. This capa­citor should be a ceramic capacitor in the range of 10 μF to
47 μF and must be placed close to the PVINx pin. The loop
composed of this input capacitor, high-side NFET, and low­side NFET must be kept as small as possible. The voltage rating
of the input capacitor must be greater than the maximum input
voltage. The rms current rating of the input capacitor should
be larger than the following equation:



DDII

_

rmsC

IN

OUT

 1

OUTPUT VOLTAGE SETTING

The output voltage of the ADP2323 can be set by an external
resistive divider using the following equation:

V 16.0

OUT








R

TOP







R

BOT



To limit output voltage accuracy degradation due to FBx pin
bias current (0.1 μA maximum) to less than 0.5% (maximum),
ensure that R

is less than 30 kΩ.

BOT

Table 8 provides the recommended resistive divider for various
output voltage options.

Table 8. Resistive Divider for Various Output Voltages

V

(V) R

OUT

, ±1% (kΩ) R

TOP

, ±1% (kΩ)

BOT

1.0 10 15

1.2 10 10

1.5 15 10

1.8 20 10

2.5 47.5 15

3.3 10 2.21

5.0 22 3

VOLTAGE CONVERSION LIMITATIONS

The minimum output voltage for a given input voltage and
switching frequency is constrained by the minimum on time.
The minimum on time of the ADP2323 is typically 130 ns.
The minimum output voltage in CCM mode at a given input
voltage and frequency can be calculated by using the following
equation:

V

= VIN × t

OUT_MIN

× t

MIN_ON

× fSW − (R

where:

V
t
I
f
R
R
R

is the minimum output voltage.

OUT_MIN

is the minimum on time.

MIN_ON

is the minimum output current.

OUT_MIN

is the switching frequency.

SW

is the high-side MOSFET on resistance.

DSON1

is the low-side MOSFET on resistance.

DSON2

is the series resistance of output inductor.

L

MIN_ON

DSON2

× fSW − (R

+ RL) × I

− R

DSON1

OUT_MIN

DSON2

) × I

OUT_MIN

The maximum output voltage for a given input voltage and
switching frequency is constrained by the minimum off time
and the maximum duty cycle. The minimum off time is typically
150 ns and the maximum duty is typically 90% in the ADP2323.

The maximum output voltage that is limited by the minimum
off time at a given input voltage and frequency can be calcu­lated using the following equation:

V
I

OUT_MAX

OUT_MAX

= VIN × (1 – t

× (1 – t

MIN_OFF

× fSW) – (R

MIN_OFF

× fSW) – (R

DSON2

– R

DSON1

+ RL) × I

DSON2

OUT_MAX

) ×

where:

V
t
I

is the maximum output voltage.

OUT_MAX

is the minimum off time.

MIN_OFF

is the maximum output current.

OUT_MAX

The maximum output voltage limited by the maximum duty
cycle at a given input voltage can be calculated by using the
following equation:

V

where D

= D

OUT_MAX

is the maximum duty.

MAX

MAX

× VIN

As the previous equations show, reducing the switching
frequency alleviates the minimum on time and minimum off
time limitation.

CURRENT-LIMIT SETTING

The ADP2323 has three selectable current-limit thresholds.
Make sure that the selected current-limit value is larger than
the peak current of the inductor, I

PEAK

.

INDUCTOR SELECTION

The inductor value is determined by the operating frequency,
input voltage, output voltage, and inductor ripple current. Using
a small inductor leads to a faster transient response but degrades
efficiency due to larger inductor ripple current, whereas a large
inductor value leads to smaller ripple current and better effi­ciency but results in a slower transient response. Thus, there is a
trade-off between the transient response and efficiency. As a
guideline, the inductor ripple current, ΔI
1/3 of the maximum load current. The inductor value can be
calculated using the following equation:

VV D

IN OUT

L



If



LSW



where:

V

is the input voltage.

IN

is the output voltage.

V

OUT

ΔI

is the inductor ripple current.

L

is the switching frequency.

f

SW

D is the duty cycle.

V

OUT

D 

V

IN

, is typically set to

L

Rev. 0 | Page 19 of 32

ADP2323

Δ

Δ

The ADP2323 uses adaptive slope compensation in the
current loop to prevent subharmonic oscillations when the
duty cycle is larger than 50%. The internal slope compensation
limits the minimum inductor value.

For a duty cycle that is larger than 50%, the minimum
inductor value is determined by the following equation:

1

VD

×−

()

OUT

2

×

The inductor peak current is calculated using the following
equation:

PEAK

The saturation current of the inductor must be larger than
the peak inductor current. For the ferrite core inductors with
a quick saturation characteristic, the saturation current rating of
the inductor should be higher than the current-limit threshold
of the switch to prevent the inductor from getting into
saturation.

The rms current of the inductor can be calculated by the
following equation:

RMS

Shielded ferrite core materials are recommended for low core
loss and low EMI.

Table 9. Recommended Inductors

Vendor Part No.

Sumida

Coilcraft

Wurth
Elektronik

OUTPUT CAPACITOR SELECTION

The output capacitor selection affects both the output voltage
ripple and the loop dynamics of the regulator. For example,
during load step transient on the output, when the load is
suddenly increased, the output capacitor supplies the load
until the control loop has a chance to ramp up the inductor
current, which causes an undershoot of the output voltage.

f

SW

I

Δ

OUT

+=

2

2 L

+=

L

2

IIIΔ

12

Value
[μH]

I

SAT

[A]

I

DCR

RMS

[A]

[mΩ]

II

OUT

CDRH105RNP-1R5N 1.5 10.5 8.3 5.8
CDRH105RNP-2R2N 2.2 9.25 7.5 7.2
CDRH105RNP-3R3N 3.3 7.8 6.5 10.4
CDRH105RNP-4R7N 4.7 6.4 6.1 12.3
CDRH105RNP-6R8N 6.8 5.4 5.4 18
MSS1048-152NL 1.5 10.5 10.8 5.8
MSS1048-222NL 2.2 8.4 9.78 7.2
MSS1048-332NL 3.3 7.38 7.22 10.4
MSS1048-472NL 4.7 6.46 6.9 12.3
MSS1048-682NL 6.8 5.94 6.01 18
7447797180 1.8 13.3 7.3 16
7447797300 3.0 10.5 7.0 18
7447797470 4.7 8.0 5.8 27
7447797620 6.2 7.5 5.5 30

Use the following equation to calculate the output capacitance
that is required to meet the voltage droop requirement:

2

LIK

STE

×Δ×

P

VVV

UVOUTOUT

_

C

=

UVOUT

_

UV

()

2 Δ×−×

IN

where:

is the load step.

I

STEP

V
K

is the allowable undershoot on the output voltage.

OUT_UV

is a factor, typically setting KUV = 2.

UV

Another case is when a load is suddenly removed from the
output and the energy stored in the inductor rushes into the
output capacitor, which causes the output to overshoot. The
output capacitance required to meet the overshoot require­ment can be calculated using the following equation:

2

22

_

C

OUT OV

×Δ ×

KI L

=

_

OV STEP

+Δ −

VV V

()

OUT OUT OV OUT

where:
V

K

is the allowable overshoot on the output voltage.

OUT_OV

is a factor, typically setting KOV = 2.

OV

The output ripple is determined by the ESR of the output
capacitor and its capacitance value. Use the following equation
to select a capacitor that can meet the output ripple
requirements:

I

Δ

C

R

ESR

=

RIPPLEOUT

_

=

8 Δ××

V

RIPPLEOUT

_

Δ

I

L

SW

L

Vf

RIPPLEOUT

_

where:
V

OUT_RIPPLE

R

ESR

Select the largest output capacitance given by C
C

OUT_OV

is the allowable output voltage ripple.

is the equivalent series resistance of the output capacitor.

,

OUT_UV

, and C

OUT_RIPPLE

to meet both load transient and

output ripple performance.

The selected output capacitor voltage rating must be greater
than the output voltage. The minimum rms current rating of
the output capacitor is determined by the following equation:

I

OUT

=

_LrmsC

12

I

LOW-SIDE POWER DEVICE SELECTION

The ADP2323 has integrated low-side MOSFET drivers,
which can drive the low-side N-channel MOSFETs (NFETs).
The selection of the low-side N-channel MOSFET affects the
dc-to-dc regulator performance.

The selected MOSFET must meet the following requirements:

• Drain source voltage (V

• Drain current (I

where I

LIMIT_MAX

D

is the selected maximum current-limit

threshold.

) must be higher than 1.2 × VIN.

DS

) must be greater than the 1.2 × I

LIMIT_MAX

,

Rev. 0 | Page 20 of 32

ADP2323

×

The ADP2323 low-side gate drive voltage is 5 V. Make sure
that the selected MOSFET can be fully turned on at 5 V.

Total gate charge (Qg at 5 V) must be less than 30 nC. Lower
Qg characteristics constitute higher efficiency.

When the high-side MOSFET is turned off, the low-side
MOSFET carries the inductor current. For low duty cycle
applications, the low-side MOSFET carries the current for
most of the period. To achieve higher efficiency, it is
important to select a low on-resistance MOSFET. The power
conduction loss for the low-side MOSFET can be calculated
using the following equation:

2

= I

× R

P

where R

FET_LOW

OUT

is the on resistance of the low-side MOSFET.

DSON

× (1 − D)

DSON

Make sure that the MOSFET can handle the thermal
dissipation due to the power loss.

In some cases, efficiency is not critical for the system;
therefore, the diode can be selected as the low-side power
device. The average current of the diode can be calculated
using the following equation:

I

DIODE (AVG)

= (1 − D) × I

OUT

The reverse breakdown voltage rating of the diode must be
greater than the input voltage with an appropriate margin to
allow for ringing, which may be present at the SWx node. A
Schottky diode is recommended because it has low forward
voltage drop and fast switching speed.

If a diode is used for the low-side device, the ADP2323 must
enable the PFM mode by connecting the MODE pin to
ground.

Table 10. Recommended MOSFETs

Vendor Part No. VDS ID

R

DSON

Qg

Fairchild FDS8880 30 V 10.7 A 12 mΩ 12 nC
Fairchild FDMS7578 25 V 14 A 8 mΩ 8 nC
Fairchild FDS6898A 20 V 9.4 A 14 mΩ 16 nC
Vishay Si4804CDY 30 V 7.9 A 27 mΩ 7 nC
Vishay SiA430DJ 20 V 10.8 A 18.5 mΩ 5.3 nC
AOS AON7402 30 V 39 A 15 mΩ 7.1 nC
AOS AO4884L 40 V 10 A 16 mΩ 13.6 nC

PROGRAMMING UVLO INPUT

The precision enable input can be used to program the UVLO
threshold and hysteresis of the input voltage as shown in
Figure 46.

PVINx

R

TOP_EN

R

BOT_EN

ENx

4µA1µA

Figure 46. Programming UVLO Input

Use the following equation to calculate R

R

R

=

_

ENTOP

V2.1

×

=

_

ENBOT

_

RISINGIN

R

RV

_

EN CMP

1.2V

9357-048

and R

TOP_EN

VV

V2.1V1.1

×−

__

FALLINGINRISINGIN

A1V2.1A5V1.1

×−×

_

ENTOP

V2.15

ENTOP

−Α×−

BOT_EN

:

where:

V
V

is the VIN rising threshold.

IN_RISING

is the VIN falling threshold.

IN_FALLING

COMPENSATION COMPONENTS DESIGN

For peak current-mode control, the power stage can be
simplified as a voltage controlled current source supplying
current to the output capacitor and load resistor. It is composed
of one domain pole and a zero contributed by the output
capacitor ESR. The control-to-output transfer function is
shown in the following equations:

⎛
⎜

+

1

⎜

)(

sG

vd

f

=

z

f

=

p

)(

sV

COMP

2

2

ESR

()

RA

VI

1

CR

××π×

OUT

1

ESR

)(

sV

OUT

2

⎝

××==

⎛
⎜

+

1

⎜

2

⎝

CRR

×+×π×

OUT

where:

= 5 A/V

A

VI

R is the load resistance.
C

is the output capacitance.

OUT

is the equivalent series resistance of the output capacitor.

R

ESR

⎞

s

⎟
⎟

×π×

f

z

⎠
⎞

s

⎟
⎟

×π×

f

p

⎠

Rev. 0 | Page 21 of 32

ADP2323

V

V

(

×

+

×

The ADP2323 uses a transconductance amplifier for the
error amplifier to compensate the system. Figure 47 shows
the simplified peak current-mode control small signal circuit.

OUT

R

TOP

V

–

g

m

R

BOT

Figure 47. Simplified Peak Current-Mode Control Small Signal Circuit

+

COMP

R

C

C

C

C

CP

A

+

VI

–

C

OUT

R

ESR

The compensation components, RC and CC, contribute a zero,
and the optional C

and RC contribute an optional pole.

CP

The closed-loop transfer equation is as follows:

R

)( sG

sT

V

BOT

=

RR

+

TOPBOT

g

−

m

×

×

CC

+

CPC

1

⎛
⎜

1

s

+×

⎜
⎝

CC

××

CC

+

OUT

R

sCR

××+

CCR

CPC

×

⎞

CPCC

⎟

s

×

⎟
⎠

The following design guideline shows how to select the
compensation components, R

, CC, and CCP, for ceramic

C

output capacitor applications.

Determine the cross frequency (f

1.

2

=

=

/12 and fSW/6.

SW

××

V6.0

m

)

CRR

ESR

OUT

R

C

×××π×

OUTOUT

Ag

VI

between f

R

can be calculated using the following equation:

2.

C

R

C

Place the compensation zero at the domain pole (f

3.
C can be determined by

4.

C

C

C

C

is optional. It can be used to cancel the zero caused

CP

09357-049

). Generally, the fC is

C

fCV

C

).

P

by the ESR of the output capacitor.

CR

ESR

)(

vd

=

C

CP

OUT

R

C

The ADP2323 has a 10 pF capacitor internally at the
COMPx pin; therefore, if C

is smaller than 10 pF, no

CP

external capacitor is needed.

Rev. 0 | Page 22 of 32

ADP2323





















DESIGN EXAMPLE

This section explains design procedure and component selection
as shown in Figure 50; Table 11 provides a list of the required
settings.

Table 11. Dual Step-Down DC-to-DC Regulator Requirements

Parameter Specification

Channel 1

Input Voltage V
Output Voltage V
Output Current I
Output Voltage Ripple ΔV

= 12.0 V ± 10%

IN1

= 1.2 V

OUT1

= 3 A

OUT1

OUT1_RIPPLE

= 12 mV

Load Transient ±5%, 0.5 A to 3A, 1 A/μs

Channel 2

Input Voltage V
Output Voltage V
Output Current I
Output Voltage Ripple ΔV

= 12.0 V ± 10%

IN2

= 3.3 V

OUT2

= 3 A

OUT2

OUT2_RIPPLE

= 33 mV

Load Transient ±5%, 0.5 A to 3 A, 1 A/μs

Switching Frequency fSW = 500 kHz

OUTPUT VOLTAGE SETTING

Choose a 10 kΩ top feedback resistor (R
bottom feedback resistor by using the following equation:

6.0

6.0









RR

TOPBOT



V

OUT



To set the output voltage to 1.2 V, the resistor values are R
10 kΩ and R
the resistors values are R

= 10 kΩ. To set the output voltage to 3.3 V,

BOT1

= 10 kΩ and R

TOP2

); calculate the

TOP

= 2.21 kΩ.

BOT2

TOP1

=

CURRENT-LIMIT SETTING

For 3 A output current operation, the typical peak current
limit is 4.8 A. In this case, no R

is required.

ILIM

FREQUENCY SETTING

To set the switching frequency to 500 kHz, use the following
equation to calculate the resistor value, R



R 

OSC

Therefore, R

k

OSC

000,60



kHz

f

SW

=100 kΩ.

OSC

:

INDUCTOR SELECTION

The peak-to-peak inductor ripple current, IL, is set to 30%
of the maximum output current. Use the following equation
to estimate the value of the inductor:

DVV

IN

L



For V

= 1.2 V, Inductor L1 = 2.4 µH, and for V

OUT1

Inductor L2 = 5.3 µH.

Select the standard inductor value of 2.2 µH and 4.7 µH for
the 1.2 V and 3.3 V rails.



OUT



L

fI

SW

= 3.3 V,

OUT2

Calculate the peak-to-peak inductor ripple current as follows:

OUT

fL

SW

DVV

= 3.3 V, IL2 = 1.02 A.

OUT2

For V

IN

I



L

= 1.2 V, IL1 = 0.98 A. For V

OUT1



Find the peak inductor current by using the following equation:

I

L



II

PEAK

OUT

2

For the 1.2 V rail, the peak inductor current is 3.49 A, and for
the 3.3 V rail, the peak inductor current is 3.51 A.

The rms current through the inductor can be estimated by

2

III

L

2

RMS

OUT



12

The rms current of the inductor for both 1.2 V and 3.3 V is
approximately 3.01 A.

For the 1.2 V rail, select an inductor with a minimum rms
current rating of 3.01 A and a minimum saturation current
rating of 3.49 A. For the 3.3 V rail, select an inductor with a
minimum rms current rating of 3.01 A and a minimum
saturation current rating of 3.51 A.

Based on these requirements, for the 1.2 V rail, select a

2.2 µH inductor, such as the Sumida CDRH105RNP-2R2N,

with a DCR = 7.2 mΩ; for the 3.3 V rail, select a 4.7 µH
inductor, such as the Sumida CDRH105RNP-4R7N, with a
DCR = 12.3 mΩ.

OUTPUT CAPACITOR SELECTION

The output capacitor is required to meet the output voltage
ripple and load transient requirement. To meet the output
voltage ripple requirement, use the following equation to
calculate the ESR and capacitance:

I



L

Vf

SW

= 20 µF and R

= 7.7 µF and R

For V
V

OUT2

C

RIPPLEOUT

_

R



ESR

= 1.2 V, C

OUT1

= 3.3 V, C



8 

V

_

I

L

OUT_RIPPLE2

RIPPLEOUT

OUT_RIPPLE1

To meet the ±5% overshoot and undershoot requirement, use
the following equation to calculate the capacitance:

OV

UV

STEP

_

STEP

= KUV = 2. For V

OV

OUT_UV1

= 20 µF.

OUT_UV2

C

C



OVOUT

_





UVOUT

_



2 

IN

For estimation purposes, use K
use C
use C

= 191 µF and C

OUT_OV1

= 54 µF and C

OUT_OV2

RIPPLEOUT

_

= 12 mΩ. For

ESR1

= 32 mΩ.

ESR2

2

LIK



2



2



VVV

2

VVV

OUTOVOUTOUT

LIK

UVOUTOUT

_

= 21 µF. For V

OUT1

OUT2

= 1.2 V,

= 3.3 V,

Rev. 0 | Page 23 of 32

ADP2323

(

)

×××π×

(

)

+

×

×

For the 1.2 V rail, the output capacitor ESR needs to be smaller
than 12 mΩ, and the output capacitance needs to be larger than
191 µF. It is recommend that three pieces of 100 µF/X5R/6.3 V
ceramic capacitor be used, such as the GRM32ER60J107ME20
from Murata, with an ESR = 2 mΩ.

For the 3.3 V rail, the ESR of the output capacitor must be
smaller than 32 mΩ and the output capacitance must be
larger than 54 µF. It is recommended that two pieces of
47 µF/X5R/6.3 V ceramic capacitor be used, such as the
Murata GRM32ER60J476ME20, with an ESR = 2 mΩ.

LOW-SIDE MOSFET SELECTION

A low R
solutions. The MOSFET breakdown voltage needs to be
greater than 1.2 V × V
greater than 1.2 V × I

It is recommended that a 30 V, N-channel MOSFET be used, such
as the FDS8880 from Fairchild. The R

4.5 V driver voltage is 12 mΩ, and the total gate charge is 12 nC.

COMPENSATION COMPONENTS

For better load transient and stability performance, set the
cross frequency, f
500 kHz; therefore, the f

For the 1.2 V rail, the 100 µF ceramic output capacitor has
a derated value of 64 µF.

Choose standard components, R
No C

Figure 48 shows the 1.2 V rail bode plot at 3 A. The cross
frequency is 49 kHz and the phase margin is 59°.

60

48

36

24

12

–12

MAGNITUDE (d B)

–24

–36

–48

–60

N-channel MOSFET is selected for high efficiency

DSON

, and the drain current needs to be

IN

.

LIMIT

of the FDS8880 at a

DSON

, to fSW/10. In this case, fSW is running at

C

is set to 50 kHz.

C

kHz50F643V2.12

=

R

C1

=

C

C

1

=

C

CP1

is needed.

CP1

0

1k 10k 100k 1M

Figure 48. Bode Plot for 1.2 V Rail

k4.80

××

k4.80

FREQUENCY (Hz)

××××π×

A/V5s300V6.0

××

××+

F643001.0

=

= 82 kΩ and CC1 = 1000 pF.

C1

=

F643001.04.0

=

pF4.2

k4.80

pF957

180

144

108

72

36

0

–36

PHASE (Deg rees)

–72

–108

–144

–180

For the 3.3 V rail, the 47µF ceramic output capacitor has a
derated value of 32 µF.

kHz50F322V3.32

=

R

C2

=

C

C

2

=

C

CP2

k7.73

×

A/V5s300V6.0

××

F322001.01.1

××

k7.73

F322001.0

pF1

=

Choose standard component values of R

= 1000 pF. No C

C

C2

is needed.

CP2

=

C2

k7.73

=

pF956

= 75 kΩ and

Figure 49 shows the 3.3 V rail bode plot at 3 A. The cross
frequency is 59 kHz and phase margin is 61°.

60

48

36

24

12

0

–12

MAGNITUDE (d B)

–24

–36

–48

–60

1k 10k 100k 1M

FREQUENCY (Hz)

Figure 49. Bode Plot for 3.3 V Rail

180

144

108

72

36

0

–36

–72

–108

–144

–180

PHASE (Deg rees)

09357-149

SOFT START TIME PROGRAMMING

The soft start feature allows the output voltage to ramp up in
a controlled manner, eliminating output voltage overshoot
during soft start and limiting inrush current. The soft start
time is set to 3 ms.

ms3A5.3

×

TI

SSSS

=

C

SS

=

V6.0

Choose a standard component value of C

×

V6.0

nF5.17

=

SS1

= C

= 22 nF.

SS2

INPUT CAPACITOR SELECTION

A minimum 10 µF ceramic capacitor is required, placed near
the PVINx pin. In this application, one piece of 10 µF, X5R,
25 V ceramic capacitor is recommended.

09357-148

Rev. 0 | Page 24 of 32

ADP2323

EXTERNAL COMPONENTS RECOMMENDATION

Table 12. Recommended External Components for Typical Applications with 3 A Output Current

fSW (kHz) VIN (V) V

300

12 1 3.3 330 10 15 62 1500 33
12 1.2 4.7 330 10 10 82 1500 22
12 1.5 4.7 330 15 10 100 1500 22
12 1.8 4.7 2 × 100 20 10 47 1500 4.7
12 2.5 6.8 100 + 47 47.5 15 47 1500 4.7
12 3.3 10 100 + 47 10 2.21 62 1500 3.3
12 5 10 100 22 3 62 1500 2.2
5 1 3.3 330 10 15 62 1500 33
5 1.2 3.3 330 10 10 82 1500 22
5 1.5 3.3 330 15 10 100 1500 22
5 1.8 4.7 2 × 100 20 10 47 1500 4.7
5 2.5 4.7 100 + 47 47.5 15 47 1500 4.7

5 3.3 4.7 100 10 2.21 47 1500 3.3
600 12 1.5 2.2 2 × 100 15 10 82 820 2.2
12 1.8 3.3 100 + 47 20 10 75 820 3.3
12 2.5 3.3 2 × 47 47.5 15 62 820 2.2
12 3.3 4.7 2 × 47 10 2.21 82 820 2.2
12 5 4.7 47 22 3 62 820 2.2
5 1 1.5 2 × 100 10 15 56 820 2.2
5 1.2 1.5 2 × 100 10 10 62 820 2.2
5 1.5 2.2 100 + 47 15 10 62 820 2.2
5 1.8 2.2 2 × 47 20 10 47 820 2.2
5 2.5 2.2 2 × 47 47.5 15 62 820 2.2
5 3.3 2.2 2 × 47 10 2.21 82 820 2.2
1000

12 1.8 1.5 100 20 10 82 470 2.2

12 2.5 2.2 47 47.5 15 56 470 2.2

12 3.3 2.2 47 10 2.21 68 470 2.2

12 5 3.3 47 22 3 100 470 2.2

5 1 1 2 × 100 10 15 82 470 2.2

5 1.2 1 100 + 47 10 10 82 470 2.2

5 1.5 1 2 × 47 15 10 68 470 2.2

5 1.8 1 2 × 47 20 10 82 470 2.2

5 2.5 1 47 47.5 15 56 470 2.2

5 3.3 1 47 10 2.21 62 470 2.2

1

330 µF: 6.3 V, Sanyo 6TPD330M; 100 µF: 6.3 V, X5R, Murata GRM32ER60J107ME20; 47 µF: 6.3 V, X5R, Murata GRM32ER60J476ME20.

(V) L (μH) C

OUT

(μF)1 R

OUT

(kΩ) R

TOP

(kΩ) RC (kΩ) CC (pF) CCP (pF)

BOT

Rev. 0 | Page 25 of 32

ADP2323

TYPICAL APPLICATION CIRCUITS

R

TOP1

10kΩ

R

BOT1

10kΩ

FB1

BOT2

INTVCC
MODE
SCFG
TRK2
TRK1
VDRV

GND

PGOOD2

PGOOD1
SYNC

RT

R

TOP2

10kΩ

FB2

C

INT

1µF

C

DRV

1µF

R

OSC

120kΩ

R

2.21kΩ

C

C1

1000pF

R

C1

82kΩ

COMP1

ADP2323

COMP2

R

C2

75kΩ

C

C2

1000pF

C
22nF

SS1

SS2

C

SS2

22nF

SS1

EN2

EN1

PVIN1

SW1

PGND

SW2

PVIN2

BST2

C

IN2

10µF, 25V

DL1

DL2

V

IN

12V

C

IN1

10µF, 25V

C

BST1

BST1

0.1µF

C

BST2

0.1µF

L1

2.2µH

M1
FDS8880

M2
FDS8880

L2

4.7µH

V

IN

12V

C

OUT1

100µF

C

OUT4

47µF

C

OUT2

100µF

C

OUT5

47µF

V

3.3V, 3A

OUT2

V

OUT1

1.2V, 3A

C

OUT3

100µF

Figure 50. Using External MOSFET Application, V

R

TOP1

R

BOT1

3kΩ

22kΩ

C

C1

1.2nF

R

C1

75kΩ

FB1

C

INT

1µF

C

DRV

1µF

INTVCC
SCFG
TRK2
TRK1
VDRV

GND
MODE

COMP1

PGOOD2
PGOOD1

SYNC

BOT2

RT

R

TOP2

10kΩ

FB2

COMP2

R

C2

47kΩ

C

C2

1.5nF

R

OSC

100kΩ

R

2.21kΩ

Figure 51. Using External Diode Application, V

= V

IN1

C
22nF

SS1

ADP2323

SS2

C

SS2

22nF

= V

IN1

IN2

= 12 V, V

IN2

SS1

EN2

= 12 V, V

OUT1

EN1

PVIN1

SW1

PGND

SW2

PVIN2

BST2

C

IN2

10µF, 25V

OUT1

= 1.2 V, I

BST1

DL1

DL2

= 5 V, I

C

BST1

0.1µF

R

ILIM2

47kΩ

C

BST2

0.1µF

OUT1

= 3 A, V

OUT1

V

12V

C

IN1

10µF, 25V

8.2µH

D1
B220A

D2
B220A

8.2µH

V

IN

12V

= 2 A, V

09357-050

= 3.3 V, I

OUT2

IN

OUT2

= 3 A, fSW = 500 kHz

V

OUT1

5V, 2A

L1

L2

OUT2

C
22µF

C
22µF

= 3.3 V, I

C

OUT1

OUT2

22µF

C

OUT3

OUT4

22µF

V

3.3V, 1.5A

= 1.5 A, fSW = 600 kHz

OUT2

OUT2

09357-051

Rev. 0 | Page 26 of 32

ADP2323

R

TOP1

R

BOT1

10kΩ

20kΩ

C

C1

470pF

R

C1

150kΩ

C

SS1

22nF

V

IN

12V

C

IN1

10µF, 25V

FB1

C

INT

1µF

R

OSC

100kΩ

C

DRV

1µF

R

OK1

100kΩ

R

OK2

100kΩ

TRK1

PGOOD1
SCFG
SYNC

INTVCC

RT

MODE

PGOOD2

TRK2

VDRV

COMP1

ADP2323

GND

FB2

COMP2

Figure 52. Parallel Single Output Application, V

R

TOP1

C

INT

1µF

C

DRV

1µF

R

OSC

50kΩ

R

15kΩ

R

BOT2

BOT1

3kΩ

22kΩ

INTVCC
MODE
SCFG
TRK2
TRK1
VDRV

GND

PGOOD2

PGOOD1
SYNC

RT

R

TOP2

10kΩ

FB1

FB2

C

C1

390pF

R

C1

62kΩ

COMP1

ADP2323

COMP2

R

C2

82kΩ

C

C2

390pF

SS2

SS1

EN2

C
22nF

SS1

SS2

C

SS2

22nF

SS1

EN1

PVIN2

EN2

PVIN1

PVIN1

SW1
SW1

PGND

SW2
SW2

PVIN2

BST2

C

IN2

10µF, 25V

IN

EN1

PVIN1

PGND

PVIN2

BST2

C

IN2

10µF, 25V

BST1

DL1

DL2

= 12 V, V

BST1

SW1

M1

DL1

DL2

SW2

C

BST1

0.1µF

C

BST2

0.1µF

OUT

C

0.1µF

C

BST2

0.1µF

BST1

L1

1µH

M1
FDS8880

M2
FDS8880

L2

1µH

V

IN

12V

= 1.8 V, I

V

IN

12V

C

IN1

10µF, 25V

L1

3.3µH

M1
FDS6898A

L2

1µH

C

C

OUT1

100µF

100µF

= 6 A, fSW = 600 kHz

OUT

C
22µF

OUT2

C
100µF

C
100µF

OUT2

OUT1

OUT3

V

OUT2

1.0V, 3A

C
100µF

V

OUT1

5V, 2A

V

OUT1

1.8V, 6A

OUT3

09357-052

Figure 53. Cascading Supply Application, V

= 12 V, V

IN1

OUT1

= 5 V, I

Rev. 0 | Page 27 of 32

OUT1

= 2 A, V

OUT2

= 1 V, I

= 3 A, fSW = 1.2 MHz

OUT2

09357-053

ADP2323

R

TOP1

20kΩ

R

BOT1

10kΩ

SYNC

SCFG

C

INT1

1µF

C

DRV1

1µF

INTVCC
MODE
TRK2
TRK1
VDRV

GND

PGOOD2

C

C1

820pF

R
75kΩ

FB1

COMP1

C

C1

SS1

22nF

SS1

EN1

BST1

PVIN1

SW1

ADP2323

DL1

PGND

DL2

PGOOD1

R

OSC1

100kΩ

R

BOT2

2.21kΩ

RT

R

10kΩ

TOP2

FB2

COMP2

SS2

R

C2

C

82kΩ

C
820pF

SS2

22nF

C2

EN2

SW2

PVIN2

BST2

C

IN2

10µF, 25V

C

BST1

0.1µF

C

BST2

0.1µF

V

IN

12V

C

IN1

10µF, 25V

L1

3.3µH

M1
FDS8880

M2
FDS8880

L2

4.7µH

V

IN

12V

C

OUT1

100µF

C

OUT3

47µF

V

1.8V, 3A

C

OUT2

47µF

C

OUT4

47µF

V

OUT2

3.3V, 3A

OUT1

R

TOP3

20kΩ

R

BOT3

10kΩ

SYNC

SCFG

C

INT2

1µF

C

DRV2

1µF

INTVCC
MODE
TRK2
TRK1
VDRV

GND
PGOOD2

C

C3

820pF

R
75kΩ

FB1

COMP1

C

C3

SS3

22nF

SS1

EN1

BST1

PVIN1

SW1

ADP2323

DL1

PGND

DL2

PGOOD1

R

OSC2

120kΩ

R

BOT4

2.21kΩ

SYNC

RT

R

TOP4

10kΩ

FB2

COMP2

SS2

R

C4

C

82kΩ

C
820pF

SS4

22nF

C4

EN2

SW2

PVIN2

BST2

C

IN4

10µF, 25V

C

BST3

0.1µF

C

BST4

0.1µF

V

IN

12V

C

IN1

10µF, 25V

L3

3.3µH

M3
FDS8880

M4
FDS8880

L4

4.7µH

V

IN

12V

C

OUT5

100µF

C

OUT7

47µF

V

1.8V, 3A

C

OUT6

47µF

C

OUT8

47µF

V

OUT4

3.3V, 3A

OUT3

09357-054

Figure 54. Synchronization with 90° Phase Shift Between Each Channel

Rev. 0 | Page 28 of 32

ADP2323

R

TOP1

C

1µF

INT

R

10kΩ

15kΩ

BOT1

INTVCC

SCFG

TRK2

C

C1

820pF

R
68kΩ

FB1

C

C1

SS1

22nF

SS1

COMP1

TRK1

C

DRV

1µF

VDRV

GND
MODE

ADP2323

PGOOD2
PGOOD1
SYNC

BOT2

RT

R

TOP2

47.5kΩ

FB2

COMP2

SS2

R

C2

C

75kΩ

C
820pF

SS2

22nF

C2

R

OSC

100kΩ

R

15kΩ

Figure 55. Enable PFM Mode with MODE Pin Pulled to GND, V

EN2

IN1

EN1

PVIN1

SW1

PGND

SW2

PVIN2

BST2

C

IN2

10µF, 25V

= V

IN2

BST1

DL1

DL2

= 9 V, V

C

BST1

0.1µF

C

BST2

0.1µF

OUT1

V

IN

9V

C

IN1

10µF, 25V

L1

2.2µH

M1
FDS8880

M2
FDS8880

L2

3.3µH

V

IN

9V

= 1.5 V, I

OUT1

C

OUT1

47µF

C

OUT4

47µF

= 3 A, V

OUT2

C
47µF

C
47µF

OUT2

OUT5

= 2.5 V, I

V

OUT1

1.5V, 3A

C

OUT3

47µF

V

OUT2

2.5V, 3A

09357-055

= 3 A, fSW = 600 kHz

OUT2

R

BOT1

2.21kΩ

R

PGOOD1

100kΩ

C

INT

1µF

C

DRV

1µF

R

OSC

200kΩ

R

BOT2

10kΩ

Figure 56. Programmable V

V

= V

IN1

R

TOP1

10kΩ

SYNC
PGOOD2
PGOOD1

INTVCC
MODE
SCFG
TRK2
TRK1
VDRV

GND

RT

R

TOP2

20kΩ

= 12 V, V

IN2

R

R

EN_BOT

EN_TOP

68kΩ

330kΩ

C

C1

1500pF

R

C

C1

100kΩ

FB1

COMP1

SS1

22nF

SS1

EN1

BST1

PVIN1

SW1

ADP2323

DL1

C

BST1

0.1µF

V

IN

12V

C

IN1

10µF, 25V

L1

8.2µH

M1
FDS8880

C

OUT1

100µF

3.3V, 3A

C

OUT2

100µF

V

OUT1

PGND

DL2

SW2

FB2

COMP2

SS2

EN2

PVIN2

BST2

R

C2

C

OUT1

51kΩ

C
1500pF

C2

IN_RISING

= 3.3 V, I

SS2

22nF

= 8.7 V, V

= 3 A, V

OUT1

C

IN2

10µF, 25V

IN_FALLING

OUT2

= 1.8 V, I

C

BST2

0.1µF

M2
FDS8880

5.6µH

V

12V

C
100µF

L2

IN

OUT3

C

OUT4

100µF

1.8V, 3A

= 6.7 V, 3.3 V Start Up Before 1.8 V,

= 3 A, fSW = 300 kHz

OUT2

V

OUT2

09357-056

Rev. 0 | Page 29 of 32

ADP2323

R

TRK_TOP

47.5kΩ

R

TRK_BOT

C

INT

1µF

C

15kΩ

DRV

1µF

120kΩ

R

TOP1

R

BOT1

15kΩ

47.5kΩ

TRK2

PGOOD2

PGOOD1

C

C1

1000pF

R
68kΩ

FB1

COMP1

C

C1

SS1

22nF

SS1

EN1

BST1

PVIN1

SW1

SYNC

INTVCC

TRK2

MODE

SCFG

VDRV

ADP2323

DL1

PGND

DL2

GND

EN2

SW2

PVIN2

BST2

C

IN2

10µF, 25V

R

OSC

R

BOT2

12kΩ

RT

R

13kΩ

TOP2

FB2

COMP2

SS2

R

C2

58kΩ

C

SS2

10nF

C

C2

1000pF

C

BST1

0.1µF

C

BST2

0.1µF

V

IN

12V

C

IN1

10µF, 25V

L1

4.7µH

M1
FDS8880

M2
FDS8880

L2

2.2µH

V

IN

12V

C

OUT1

47µF

C

OUT3

100µF

V

OUT1

2.5V, 3A

C

OUT2

47µF

C

OUT4

100µF

V

OUT2

1.25V, 3A

9357-057

Figure 57. Channel 2 Tracking with Channel 1

= V

V

= 12 V, V

IN1

IN2

OUT1

= 2.5 V, I

OUT1

= 3 A, V

= 1.25 V, I

OUT2

= 3 A, fSW = 500 kHz

OUT2

Rev. 0 | Page 30 of 32

ADP2323

C

S

OUTLINE DIMENSIONS

INDI

EATING

PLANE

PIN 1

ATO R

0.80

0.75

0.70

5.10

5.00 SQ

4.90

0.05 MAX

0.02 NOM

0.20 REF

0.50

BSC

0.50

0.40

0.30

COPLANARITY

0.08

0.30

0.25

0.18

25

N

1

P

32

24

EXPOSED

PAD

17

BOTTOM VIEWTOP VIEW

1

8

916

FOR PROPER CO NNECTION O F
THE EXPOSED PAD, REFER TO
THE PIN CONF IGURATIO N AND
FUNCTION DESCRI PTIONS
SECTION O F THIS DAT A SHEET.

I

D

N

I

3.25

3.10 SQ

2.95

0.25 MIN

R

O

T

C

I

A

COMPLIANT TO JEDEC ST ANDARDS MO-220-W HHD.

112408-A

Figure 58. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

5 mm × 5 mm Body, Very Very Thin Quad

(CP-32-7)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Output Voltage Package Description Package Option

ADP2323ACPZ-R7 −40°C to +125°C Adjustable 32-Lead LFCSP_WQ CP-32-7
ADP2323-EVALZ Evaluation Board

1

Z = RoHS Compliant Part.

Rev. 0 | Page 31 of 32

ADP2323

NOTES

©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09357-0-7/11(0)

Rev. 0 | Page 32 of 32