Input voltage range: 2.5 V to 5.5 V
Small, 8-lead, 2 mm × 2 mm LFCSP package
Initial accuracy: ±1%
High PSRR: 70 dB at 10 kHz, 60 dB at 100 kHz, 40 dB at 1 MHz
Low noise: 27 µV rms at V
Excellent transient response
Low dropout voltage: 170 mV at 300 mA load
65 µA typical ground current at no load, both LDOs enabled
Fixed output voltage from 0.8 V to 3.3 V (ADP222/ADP224)
Adjustable output voltage range from 0.5 V to 5.0 V
(ADP223/ADP225)
Quick output discharge (QOD)—ADP224/ADP225
Overcurrent and thermal protection
APPLICATIONS
Portable and battery-powered equipment
Portable medical devices
Post dc-to-dc regulation
Point of sale terminals
Credit card readers
Automatic meter readers
Wireless network equipment
= 1.2 V, 50 µV rms at V
OUT
= 2.8 V
OUT
Dual, 300 mA Output, Low Noise,
TYPICAL APPLICATION CIRCUITS
Figure 1. ADP223/ADP225
GENERAL DESCRIPTION
The 300 mA, adjustable dual output ADP223/ADP225 and
fixed dual output ADP222/ADP224 combine high PSRR, low
noise, low quiescent current, and low dropout voltage in a
voltage regulator that is ideally suited for wireless applications
with demanding performance and board space requirements.
The ADP222/ADP224are available with fixed outputs voltages
from 0.8V to 3.3V. The adjustable output ADP223/ADP225 may
be set to output voltages from 0.5 V to 5.0 V. The low quiescent
current, low dropout voltage, and wide input voltage range of
the ADP222/ADP223/ADP224/ADP225 extend the battery life
of portable devices.
The ADP222/ADP223/ADP224/ADP225maintain power
supply rejection greater than 60 dB for frequencies as high as
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Figure 2. ADP222/ADP224
100 kHz while operating with a low headroom voltage. The
ADP222/ADP223/ADP224/ADP225 offer much lower noise
performance than competing LDOs without the need for a
noise bypass capacitor. Overcurrent and thermal protection
circuitry prevent damage in adverse conditions.
The ADP224 and ADP225 are identical to the ADP222 and
ADP223, respectively, but with the addition of a quick output
discharge (QOD) feature.
The ADP222/ADP223/ADP224/ADP225 are available in a
small 8-lead, 2 mm × 2 mm LFCSP package and are stable with
tiny 1 µF, ±30% ceramic output capacitors, resulting in the smallest
possible board area for a wide variety of portable power needs.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Page 2
ADP222/ADP223/ADP224/ADP225 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
+ 0.5 V) or 2.5 V (whichever is greater), EN1 = EN2 = VIN, I
OUT
OUT1
= I
= 10 mA, CIN = C
OUT2
OUT1
= C
= 1 µF, TA = 25°C,
OUT2
OPERATING SUPPLY CURRENT
I
I
GND
= 0 µA 65 µA
OUT
WITH BOTH REGULATORS ON
I
I
I
I
I
SHUTDOWN CURRENT I
OUTPUT VOLTAGE ACCURACY1 V
EN1 = EN2 = GND 0.2 2 µA
GND-SD
TJ = −40°C to +125°C
OUT
I
0 µA < I
ADJUSTABLE-OUTPUT VOLTAGE
ACCURACY
1
TJ = −40°C to +125°C
V
ADJ
I
0 µA < I
LINE REGULATION ΔV
/ΔVIN VIN = (V
OUT
VIN = (V
LOAD REGULATION2 ΔV
OUT
/ΔI
OUT
I
DROPOUT VOLTAGE3 V
DROPOUT
I
I
I
SENSE INPUT BIAS CURRENT SENSE
ADJx INPUT BIAS CURRENT ADJ
START-UP TIME4 t
CURRENT-LIMIT THRESHOLD5 I
I-BIAS
2.5 V ≤ VIN ≤ 5.5 V, ADJx connected to VOUTx 10 nA
I-BIAS
V
STA RT-UP
340 400 mA
LIMIT
= 0 µA, TJ = −40°C to +125°C 150 µA
OUT
= 10 mA 100 µA
OUT
= 10 mA, TJ = −40°C to +125°C 200 µA
OUT
= 300 mA 300 µA
OUT
= 300 mA, TJ = −40°C to +125°C 450 µA
OUT
= 10 mA −1 +1 %
OUT
< 300 mA, VIN = (V
OUT
= 10 mA 0.495 0.500 0.505 V
OUT
< 300 mA, VIN = (V
OUT
+ 0.5 V) to 5.5 V 0.01 %/V
OUT
+ 0.5 V ) to 5.5 V, TJ = −40°C to +125°C −0.05 +0.05 %/V
OUT
I
= 1 mA to 300 mA 0.001 %/mA
OUT
= 1 mA to 300 mA, TJ = −40°C to +125°C 0.002 %/mA
OUT
V
= 3.3 V
OUT
I
= 10 mA 6 mV
OUT
= 10 mA, TJ = −40°C to +125°C 9 mV
OUT
= 300 mA 170 mV
OUT
= 300 mA, TJ = −40°C to +125°C A 260 mV
OUT
+ 0.5 V) to 5.5 V −2 +2 %
OUT
+ 0.5 V) to 5.5 V 0.490 0.510 V
OUT
2.5 V ≤ VIN ≤ 5.5 V, SENSEx connected to VOUTx 10 nA
= 3.3 V 240 µs
OUT
OUT
THERMAL SHUTDOWN
Thermal Shutdown Threshold TSSD TJ rising 155 °C
Thermal Shutdown Hysteresis TS
15 °C
SD-HYS
EN INPUT
EN Input Logic High VIH 2.5 V ≤ VIN ≤ 5.5 V 1.2 V
EN Input Logic Low VIL 2.5 V ≤ VIN ≤ 5.5 V 0.4 V
I-LEAKAGE
EN1 = EN2 = VIN or GND, TJ = −40°C to +125°C 1 µA
Input Voltage Falling UVLO
Hysteresis UVLO
OUTPUT DISCHARGE TIME t
OUTPUT DISCHARGE RESISTANCE R
RISE
2.2 V
FAL L
HYS
V
DIS
140 Ω
QOD
= 2.8 V 1000 µs
OUT
Rev. B | Page 3 of 24
120
mV
Page 4
ADP222/ADP223/ADP224/ADP225 Data Sheet
10 kHz
68 dB
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
OUTPUT NOISE OUT
10 Hz to 100 kHz, VIN = 5 V, V
10 Hz to 100 kHz, VIN = 3.6 V, V
10 Hz to 100 kHz, VIN = 3.6 V, V
POWER SUPPLY REJECTION RATIO PSRR VIN = 2.5 V, V
100 Hz 76 dB
1 kHz 76 dB
10 kHz 70 dB
100 kHz 60 dB
1 MHz 40 dB
VIN = 3.8 V, V
100 Hz 68 dB
1 kHz 68 dB
100 kHz 60 dB
1 MHz 40 dB
1
Accuracy when VOUTx is connected directly to ADJx or SENSEx. When the VOUTx voltage is set by external feedback resistors, the absolute accuracy in adjust mode
depends on the tolerances of resistors used.
2
Based on an end-point calculation using 1 mA and 300 mA loads.
3
Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output
voltages above 2.5 V.
4
Start-up time is defined as the time between the rising edge of EN to V
5
Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V or 2.7 V.
10 Hz to 100 kHz, VIN = 5 V, V
NOISE
= 0.8 V, I
OUT
= 2.8 V, I
OUT
being at 90% of its nominal value.
OUT
= 3.3 V 56 µV rms
OUT
= 2.8 V 50 µV rms
OUT
= 2.5 V 45 µV rms
OUT
= 1.2 V 27 µV rms
OUT
= 100 mA
OUT
= 100 mA
OUT
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
The minimum input and output capacitance should be greater than 0.70 µF over the full range of the operating conditions. The full range of the
operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification
is met. X7R and X5R type capacitors are recommended for use with the LDOs, but Y5V and Z5U capacitors are not recommended for use
with the LDOs.
Table 2.
Parameter Symbol Conditions Min Typ Max Unit
MINIMUM INPUT AND OUTPUT CAPACITANCE C
CAPACITOR ESR R
TA = −40°C to +125°C 0.70 µF
MIN
TA = −40°C to +125°C 0.001 1 Ω
ESR
Rev. B | Page 4 of 24
Page 5
Data Sheet ADP222/ADP223/ADP224/ADP225
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
VIN to GND −0.3 V to +6 V
ADJ1, ADJ2, VOUT1, VOUT2 to GND −0.3 V to VIN
EN1, EN2 to GND −0.3 V to +6 V
Storage Temperature Range −65°C to +150°C
Operating Junction Temperature Range −40°C to +125°C
Soldering Conditions JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination.
The ADP222/ADP223/ADP224/ADP225 can be damaged when
the junction temperature limits are exceeded. Monitoring
ambient temperature does not guarantee that T
specified temperature limits. In applications with high power
dissipation and poor thermal resistance, the maximum ambient
temperature may have to be derated. In applications with
moderate power dissipation and low PCB thermal resistance, the
maximum ambient temperature can exceed the maximum limit as
long as the junction temperature is within specification limits.
The junction temperature (T
ambient temperature (T
(P
), and the junction-to-ambient thermal resistance of the
D
package (θ
). Maximum junction temperature (TJ) is calculated
JA
from the ambient temperature (T
) of the device is dependent on the
J
), the power dissipation of the device
A
) and power dissipation (PD)
A
using the formula
T
= TA + (PD × θJA)
J
is within the
J
Junction-to-ambient thermal resistance (θ
based on modeling and calculation using a 4-layer board. θ
is highly dependent on the application and board layout. In
applications where high maximum power dissipation exists,
close attention to thermal board design is required. The value
of θ
may vary, depending on PCB material, layout, and
JA
environmental conditions. The specified value of θ
on a 4-layer, 4 in × 3 in, 2½ oz copper board, as per JEDEC
standards. For more information, see the AN-772 Application
Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP).
Ψ
is the junction-to-board thermal characterization parameter
JB
with units of °C /W. Ψ
of the package is based on modeling and
JB
calculation using a 4-layer board. The JESD51-12, Guidelines for Reporting and Using Package Thermal Information, states that
thermal characterization parameters are not the same as thermal
resistances. Ψ
measures the component power flowing
JB
through multiple thermal paths rather than a single path as in
thermal resistance, θ
. Therefore, ΨJB thermal paths include
JB
convection from the top of the package as well as radiation from
the package, factors that make Ψ
more useful in real-world
JB
applications. Maximum junction temperature (T
from the board temperature (T
) and power dissipation (PD)
B
using the formula
T
= TB + (PD × ΨJB)
J
Refer to JESD51-8 and JESD51-12 for more detailed
information about Ψ
.
JB
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type θJA θJC ΨJB Unit
8-Lead 2 mm × 2 mm LFCSP 50.2 31.7 18.2 °C/W
ESD CAUTION
) of the package is
JA
is based
JA
) is calculated
J
JA
Rev. B | Page 5 of 24
Page 6
ADP222/ADP223/ADP224/ADP225 Data Sheet
EN1
VOUT1
VIN
EN2
GND
6
4
3
2
SENSE2VOUT2
1
8
5
7
SENSE1
NOTES
1. CONNECT EXPOSED PAD TO GND.
09376-102
ADP222/
ADP224
EN1
VOUT1
VIN
EN2
ADP223/
ADP225
GND
6
4
3
2
ADJ2VOUT2
18
5
7
ADJ1
NOTES
1. CONNECT EXPOSED PAD TO GND.
09376-002
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. ADP222/ADP224 Pin Configuration
Figure 4. ADP223/ADP225 Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
ADP222/ADP224ADP223/ADP225 Mnemonic Description
1 1 EN1 Enable Input for the Second Regulator. Drive EN1 high to turn on Regulator 1 and
drive EN1 low to turn off Regulator 1. For automatic startup, connect EN1 to VIN.
2 2 EN2 Enable Input for the First Regulator. Drive EN2 high to turn on Regulator 2 and drive
EN2 low to turn off Regulator 2. For automatic startup, connect EN2 to VIN.
3 3 GND Ground Pin.
N/A1 4 ADJ2 Adjust Pin for VOUT2. A resistor divider from VOUT2 to ADJ2 sets the output
voltage.
4 N/A1 SENSE2 Sense Pin for VOUT2.
5 5 VOUT2 Regulated Output Voltage. Connect an 1 µF or greater output capacitor between
VOUT2 and GND.
6 6 VIN Regulator Input Supply. Bypass VIN to GND with a 1 µF or greater capacitor.
7 7 VOUT1 Regulated Output Voltage. Connect 1 µF or greater output capacitor between
VOUT1 and GND.
N/A1 8 ADJ1 Adjust Pin for VOUT1. A resistor divider from VOUT1 to ADJ1 sets the output
voltage.
8 N/A1 SENSE1 Sense Pin for VOUT1.
EPAD The exposed paddle must be connected to ground.
The ADP222/ADP223/ADP224/ADP225 are low quiescent
current, fixed and adjustable dual output, low dropout linear
regulators that operate from 2.5 V to 5.5 V and provide up to
300 mA of current from each output. Drawing a low 300 μA
quiescent current (typical) at full load make the ADP222/
ADP223/ADP224/ADP225 ideal for battery-operated portable
equipment. Shutdown current consumption is typically 200 nA.
Optimized for use with small 1 μF ceramic capacitors, the
ADP222/ADP223/ADP224/ADP225 provide excellent
transient performance.
ADJ1
ADP223/ADP225
VINVOUT1
140Ω
ADP225 ONLY
140Ω
VOUT2
ADJ2
EN1
EN2
ND
THERMAL
SHUTDOW N
CONTROL
LOGIC
AND
ENABLE
CURRENT
LIMIT
REFERENCE
CURRENT
LIMIT
Figure 62. Internal Block Diagram, ADP223/ADP225
SENSE1
ADP222/ADP224
VINVOUT1
140Ω
140Ω
VOUT2
SENSE2
EN1
EN2
GND
THERMAL
SHUTDOWN
CONTRO L
LOGIC
AND
ENABLE
CURRENT
LIMIT
REFERENCE
CURRENT
LIMIT
ADP224
ONLY
Figure 63. Internal Block Diagram, ADP222/ADP224
Internally, the ADP222/ADP223/ADP224/ADP225 consist of a
reference, two error amplifiers, and two PMOS pass transistors.
Output current is delivered via the PMOS pass device, which is
09376-062
09376-063
Rev. B | Page 17 of 24
controlled by the error amplifier. The error amplifier compares
the reference voltage with the feedback voltage from the output
and amplifies the difference. If the feedback voltage is lower
than the reference voltage, the gate of the PMOS device is
pulled lower, allowing more current to flow and increasing the
output voltage. If the feedback voltage is higher than the
reference voltage, the gate of the PMOS device is pulled higher,
allowing less current to flow and decreasing the output voltage.
= 4.2V
IN
+
C1
OFF
OFF
1µF
ON
18
ON
EN1
2
EN2
3
GND
4
ADJ2VOUT2
ADP223/
ADP225
VOUT1
ADJ1
VIN
7
6
5
R2
R1
VOUT2 = 2.0V
+
C2
1µF
VOUT1 = 2.8V
+
R3
R4
C3
1µF
09376-064
Figure 64. Typical Application Circuit for Setting Output Voltages,
ADP223/ADP225
The ADP223/ADP225 are exactly the same as the ADP222/
ADP224 except that the output voltage dividers are internally
disconnected and the feedback input of the error amplifiers is
brought out for each output. The output voltages can be set
according to the following equations:
V
= 0.50 V(1 + R1/R2)
OUT1
V
= 0.50 V(1 + R3/R4)
OUT2
The value of R1 and R3 should be less than 200 kΩ to minimize
errors in the output voltage caused by the ADJx pin input current.
For example, when R1 and R2 each equal 200 kΩ, the output
voltage is 1.0 V. The output voltage error introduced by the ADJx
pin input current is 2 mV or 0.20%, assuming a typical ADJx pin
input current of 10 nA at 25°C.
The output voltage of the ADP223/ADP225
may be set from
0.5 V to 5.0 V.
The ADP222/ADP224 are available in multiple output voltage
options ranging from 0.8 V to 3.3 V.
The ADP224/ADP225 are identical to the ADP222/ADP223
with the addition of a quick output discharge (QOD) feature.
This allows the output voltage to start up from a known state.
The ADP222/ADP223/ADP224/ADP225 use the EN1/EN2 pins
to enable and disable the VOUT1/VOUT2 pins under normal
operating conditions. When EN1/EN2 are high, VOUT1/VOUT2
turn on; when EN1/EN2 are low, VOUT1/VOUT2 turn off. For
automatic startup, EN1/EN2 can be tied to VIN.
Page 18
ADP222/ADP223/ADP224/ADP225 Data Sheet
A CH1 200mA
1
M10µs
T 10.20%
3
2
CH1 200mA
CH3 10mV
CH2 50mV
B
W
B
W
Ω
B
W
09376-043
V
OUT2
V
OUT1
LOAD CURRENT
ON V
OUT1
1.2
1.0
0.8
0.6
0.4
0.2
0
0246810
CAPACITANCE (µ F)
VOLTAGE (V)
09376-044
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Output Capacitor
The ADP222/ADP223/ADP224/ADP225 are designed for
operation with small, space-saving ceramic capacitors but
function with most commonly used capacitors as long as care is
taken with regard to the effective series resistance (ESR) value.
The ESR of the output capacitor affects the stability of the LDO
control loop. A minimum of 0.7 µF capacitance with an ESR of
1 Ω or less is recommended to ensure the stability of the ADP222/
ADP223/ADP224/ADP225. Transient response to changes in
load current is also affected by output capacitance. Using a
larger value of output capacitance improves the transient response
of the ADP222/ADP223/ADP224/ADP225 to large changes in
load current. Figure 65 shows the transient responses for an
output capacitance value of 1 µF.
Figure 66 depicts the capacitance vs. voltage bias characteristic
of an 0402, 1 µF, 10 V, X5R capacitor. The voltage stability of a
capacitor is strongly influenced by the capacitor size and voltage
rating. In general, a capacitor in a larger package or higher voltage
rating exhibits better stability. The temperature variation of the
X5R dielectric is ~±15% over the −40°C to +85°C temperature
range and is not a function of package or voltage rating.
Figure 65. Output Transient Response, C
Input Bypass Capacitor
Connecting a 1 µF capacitor from VIN to GND reduces the
circuit sensitivity to the printed circuit board (PCB) layout,
especially when long input traces or high source impedance
are encountered. If greater than 1 µF of output capacitance is
required, the input capacitor should be increased to match it.
Input and Output Capacitor Properties
Any good quality ceramic capacitors can be used with the
ADP222/ADP223/ADP224/ADP225, as long as they meet the
minimum capacitance and maximum ESR requirements.
Ceramic capacitors are manufactured with a variety of
dielectrics, each with different behavior over temperature and
applied voltage. Capacitors must have a dielectric adequate to
ensure the minimum capacitance over the necessary temperature
range and dc bias conditions. X5R or X7R dielectrics with a
voltage rating of 6.3 V or 10 V are recommended, but Y5V and
Z5U dielectrics are not recommended, due to their poor
temperature and dc bias characteristics.
OUT
= 1 µF
Rev. B | Page 18 of 24
Figure 66. Capacitance vs. Voltage Bias Characteristic
Use Equation 1 to determine the worst-case capacitance accounting
for capacitor variation over temperature, component tolerance,
and voltage.
C
= C
EFF
× (1 − TEMPCO) × (1 − TOL) (1)
BIAS
where:
C
is the effective capacitance at the operating voltage.
BIAS
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, the worst-case temperature coefficient (TEMPCO)
over −40°C to +85°C is assumed to be 15% for an X5R dielectric.
The tolerance of the capacitor (TOL) is assumed to be 10%, and
C
is 0.94 µF at 1.8 V, as shown in Figure 66.
BIAS
Substituting these values in Equation 1 yields
C
= 0.94 µF × (1 − 0.15) × (1 − 0.1) = 0.719 µF
EFF
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over temperature
and tolerance at the chosen output voltage.
To guarantee the performance of the ADP222/ADP223/
ADP224/ADP225, it is imperative that the effects of dc bias,
temperature, and tolerances on the behavior of the capacitors
be evaluated for each application.
Page 19
Data Sheet ADP222/ADP223/ADP224/ADP225
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0.50.60.70.80.91.01.11.2
OUTPUT VOLTAGE (V)
ENABLE VOLTAGE (V)
VIN = 5.5V
09376-045
0
0.2
0.4
0.6
0.8
1.0
1.2
2.32.73.13.5
3.94.34.75.15.5
ENABLE THRES HOLDS (V)
VIN (V)
ENx FALL
ENx RISE
09376-046
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0100 200 300 400 500 600 700 800 900 1000
OUTPUT VOLTAGE (V)
TIME (µs)
ENx
3.3V
2.8V
1.8V
1.2V
09376-047
EN1
VOUT1
VIN
EN2
GND
6
4
3
2
ADJ2VOUT2
18
5
7
ADJ1
R1
R2
ON
OFF
V
IN
= 3.3V
+
C1
1µF
+
C2
1µF
VOUT2 = 2.8V
09376-053
ENABLE FEATURE
The ADP222/ADP223/ADP224/ADP225 use the ENx pins to
enable and disable the VOUTx pins under normal operating
conditions. Figure 67 shows a rising voltage on ENx crossing
the active threshold, where V
voltage on ENx crosses the inactive threshold, V
turns on. When a falling
OUTx
OUTx
turns off.
Figure 67. Typical ENx Pin Operation, V
= 5.5 V
IN
As shown in Figure 67, the ENx pins have built-in hysteresis.
This prevents on/off oscillations that can occur due to noise on
the ENx pins as it passes through the threshold points.
The active/inactive thresholds of the ENx pins are derived from
the VIN voltage. Therefore, these thresholds vary with changing
input voltage. Figure 68 shows typical ENx active/inactive thresholds
when the input voltage varies from 2.5 V to 5.5 V.
Figure 69. Typical Start-Up Time
PARALLELING OUTPUTS TO INCREASE OUTPUT
CURRENT
The ADP223/ADP225 use a single band gap to generate the
reference voltage for each LDO. The reference voltages are
trimmed to plus or minus a couple of millivolts of each other.
This allows paralleling of the LDOs to increase the output
current to 600 mA. The adjust pins of each LDO are tied
together and a single output voltage divider sets the output
voltage. Even though the output voltage of each LDO is slightly
different, at high load currents, the resistance of the package
and the board layout absorbs the difference. Figure 70 shows
the schematic of a typical application where the LDO outputs
are paralleled.
Figure 68. Typical Enable Thresholds vs. Input Voltage
The ADP222/ADP223/ADP224/ADP225 use an internal soft
start to limit the inrush current when the output is enabled. The
start-up time for the 2.8 V option is approximately 240 µs from
the time the ENx active threshold is crossed to when the output
reaches 90% of its final value. The start-up time is somewhat
dependent on the output voltage setting and increases slightly as
the output voltage increases.
Figure 70. Paralleling Outputs for Higher Output Current
QUICK OUTPUT DISCHARGE (QOD) FUNCTION
The ADP224/ADP225 include an output discharge resistor to
force the voltage on each output to zero when the respective
LDO is disabled. This ensures that the outputs of the LDOs are
always in a well-defined state, regardless if it is enabled or not.
The ADP222/ADP223 do not include the output discharge
function. Figure 71 compares the turn-off time of a 3.3 V output
LDO with and without the QOD function. Both LDOs have a
1 kΩ resistor connected to each output. The LDO with the
QOD function discharges the output to 0 V in less than 1 ms,
Rev. B | Page 19 of 24
whereas the 1 kΩ load takes over 5 ms to do the same.
Page 20
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0200040006000800010000
VOLTS (V)
TIME (µs)
ENABLE
V
OUT
, NO QOD
V
OUT
, WITH QOD
09376-169
6400
51
ADP222/ADP223/ADP224/ADP225 Data Sheet
THERMAL CONSIDERATIONS
In most applications, the ADP222/ADP223/ADP224/ADP225
do not dissipate much heat due to its high efficiency. However,
in applications with high ambient temperature, and high supply
voltage to output voltage differential, the heat dissipated in
the package is large enough that it can cause the junction
temperature of the die to exceed the maximum junction
temperature of 125°C.
When the junction temperature exceeds 155°C, the converter
enters thermal shutdown. It recovers only after the junction
temperature has decreased below 140°C to prevent any permanent
damage. Therefore, thermal analysis for the chosen application
is very important to guarantee reliable performance over all
conditions. The junction temperature of the die is the sum of
the ambient temperature of the environment and the temperature
rise of the package due to the power dissipation, as shown in
Equation 2.
To guarantee reliable operation, the junction temperature of
the ADP222/ADP223/ADP224/ADP225 must not exceed
125°C. To ensure that the junction temperature stays below this
maximum value, the user must be aware of the parameters that
contribute to junction temperature changes. These parameters
include ambient temperature, power dissipation in the power
device, and thermal resistances between the junction and ambient
air (θ
). The θJA number is dependent on the package assembly
JA
compounds that are used and the amount of copper used to
solder the package GND pin to the PCB.
Table 6 shows typical θ
values of the 8-lead LFCSP package for
JA
various PCB copper sizes, and Ta b l e 7 shows the typical Ψ
of the 8-lead LFCSP.
Table 6. Typical θJA Values
Copper Size (mm2) θJA (°C/W)
251 175.1
100 135.6
500 77.3
1000 65.2
1
Device soldered to minimum size pin traces.
Table 7. Typical ΨJB Value
Model ΨJB (°C/W)
8-Lead LFCSP 18.2
Figure 71. Typical Turn-Off Time with and Without QOD Function
CURRENT LIMIT AND THERMAL OVERLOAD
PROTECTION
The ADP222/ADP223/ADP224/ADP225 are protected against
damage due to excessive power dissipation by current and
thermal overload protection circuits. The ADP222/ADP223/
ADP224/ADP225 are designed to current limit when the output
load reaches 300 mA (typical). When the output load exceeds
300 mA, the output voltage is reduced to maintain a constant
current limit.
Thermal overload protection is included, which limits the
junction temperature to a maximum of 155°C (typical). Under
extreme conditions (that is, high ambient temperature and
power dissipation) when the junction temperature starts to rise
above 155°C, the output is turned off, reducing the output current
to 0. When the junction temperature drops below 140°C, the
output is turned on again, and output current is restored to its
nominal value.
Consider the case where a hard short from VOUTx to ground
occurs. At first, the ADP222/ADP223/ADP224/ADP225 current limits, so that only 300 mA is conducted into the short. If
self-heating of the junction is great enough to cause its temperature to rise above 155°C, thermal shutdown activates, turning
off the output and reducing the output current to 0 mA. As the
junction temperature cools and drops below 135°C, the output
turns on and conducts 300 mA into the short, again causing the
junction temperature to rise above 155°C. This thermal oscillation between 140°C and 155°C causes a current oscillation
between 300 mA and 0 mA that continues as long as the short
remains at the output.
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For reliable
operation, device power dissipation must be externally limited
so that junction temperatures do not exceed 125°C.
value
JB
Rev. B | Page 20 of 24
Page 21
Data Sheet ADP222/ADP223/ADP224/ADP225
140
120
100
80
60
40
20
0
JUNCTION T E M P E R ATURE T
J
(°C)
TOTAL POWER DISSIPATION (W)
00.20.40.60.81.01.2
6400mm
2
1000mm
2
500mm
2
100mm
2
25mm
2
JEDEC
T
J
MAX
09376-048
140
120
100
80
60
40
20
0
JUNCTION T E M P E R ATURE T
J
(°C)
TOT
AL POWER DISSIPATION (W)
00.20.40.60.81.01.2
6400mm
2
1000mm
2
500mm
2
100mm
2
25mm
2
JEDEC
T
J
MAX
09376-049
140
120
100
80
60
40
20
0
JUNCTION T E M P E R ATURE T
J
(°C)
TOTAL POWER DISSIPATION (W)
00.20.40.60.81.01.2
6400mm
2
1000mm
2
500mm
2
100mm
2
25mm
2
JEDEC
T
J
MAX
09376-050
140
120
100
80
60
40
20
0
JUNCTION T E M P E R ATURE T
J
(°C)
TOTAL POWER DISSIPATION (W)
02134567
TB = 25°C
T
B
= 50°C
T
B
= 85°C
T
J
MAX
09376-051
The junction temperature of the ADP222/ADP223/ADP224/
ADP225 can be calculated by
T
= TA + (PD × θJA) (2)
J
where:
T
is the ambient temperature.
A
P
is the power dissipation in the die, given by
D
= [(VIN − V
P
D
where:
I
is the load current.
LOAD
I
is the ground current.
GND
V
and V
IN
are input and output voltages, respectively.
OUT
Power dissipation due to ground current is quite small and can
be ignored. Therefore, the junction temperature equation
simplifies to the following:
T
= TA + {[(VIN − V
J
As shown in the simplified equation, for a given ambient
temperature, input- to-output voltage differential, and continuous
load current, there exists a minimum copper size requirement
for the PCB to ensure that the junction temperature does not rise
above 125°C. Figure 72 to Figure 75 show junction temperature
calculations for different ambient temperatures, power dissipation,
and areas of PCB copper.
OUT
) × I
OUT
LOAD
) × I
] + (VIN × I
] × θJA}
LOAD
GND
)
Figure 73. 8-Lead LFCSP, T
= 50°C
A
Figure 72. 8-Lead LFCSP, T
= 25°C
A
Figure 74. 8-Lead LFCSP, T
= 85°C
A
Figure 75. 8-Lead LFCSP, T
= 85°C
A
In the case where the board temperature is known, use the
thermal characterization parameter, Ψ
, to estimate the
JB
junction temperature rise (see Figure 75). Maximum junction
temperature (T
and power dissipation (P
T
= TB + (PD × ΨJB) (3)
J
The typical value of Ψ
) is calculated from the board temperature (TB)
J
) using the following formula:
D
is 18.2°C/W for the 8-lead LFCSP package.
JB
Rev. B | Page 21 of 24
Page 22
ADP222/ADP223/ADP224/ADP225 Data Sheet
09376-052
U1
J1
TB2
TB5
EN1
C2
C1
C3
R3
R4
R1 R2
VOUT1
J2
TB6
ADP223 - ________- EVALZ
VOUT2
TB7
GND
ANALOG
DEVICES
TB1
GND
TB4
VIN
TB3
EN2
PRINTED CIRCUIT BOARD LAYOUT
CONSIDERATIONS
Heat dissipation from the package can be improved by
increasing the amount of copper attached to the pins of the
ADP222/ADP223/ADP224/ADP225. However, as listed in
Table 6, a point of diminishing returns is eventually reached
beyond which an increase in the copper size does not yield
significant heat dissipation benefits.
Place the input capacitor as close as possible to the VIN and
GND pins. Place the output capacitor as close as possible to the
VOUTx and GND pins. Use of 0402 or 0603 size capacitors and
resistors achieves the smallest possible footprint solution on
boards where area is limited.
Figure 76. Example 8-Lead LFCSP PCB La yout
Rev. B | Page 22 of 24
Page 23
Data Sheet ADP222/ADP223/ADP224/ADP225
1.70
1.60
1.50
0.425
0.350
0.275
TOP VIEW
8
1
5
4
0.30
0.25
0.20
BOTTOM VIEW
PIN 1 INDEX
AREA
2.00
BSC SQ
SEATING
PLANE
0.60
0.55
0.50
1.10
1.00
0.90
0.20 REF
0.175 REF
0.05 MAX
0.02 NOM
0.50 BSC
EXPOSED
PAD
PIN 1
INDICATOR
(R 0.15)
FOR PROP E R CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CO NFIGURATI ON AND
FUNCTIO N DE S CRIPTIONS
SECTION OF THIS DATA SHEET.
07-11-2011-B
ADP222ACPZ-1815-R7
−40°C to +125°C
1.8
1.5
8-Lead Lead Frame Chip Scale
CP-8-10
LL0
OUTLINE DIMENSIONS
ORDERING GUIDE
Output Voltage (V)
Model1 Temperature Range VOUT1 VOUT2 Package Description Package Option Branding
ADP222ACPZ-1218-R7 −40°C to +125°C 1.2 1.8 8-Lead Lead Frame Chip Scale
ADP222ACPZ-1228-R7 −40°C to +125°C 1.2 2.8 8-Lead Lead Frame Chip Scale
ADP222ACPZ-1233-R7 −40°C to +125°C 1.2 3.3 8-Lead Lead Frame Chip Scale
ADP222ACPZ-1528-R7 −40°C to +125°C 1.5 2.8 8-Lead Lead Frame Chip Scale
ADP222ACPZ-1533-R7 −40°C to +125°C 1.5 3.3 8-Lead Lead Frame Chip Scale
ADP222ACPZ-1825-R7 −40°C to +125°C 1.8 2.5 8-Lead Lead Frame Chip Scale
ADP222ACPZ-1827-R7 −40°C to +125°C 1.8 2.7 8-Lead Lead Frame Chip Scale
ADP222ACPZ-1833-R7 −40°C to +125°C 1.8 3.3 8-Lead Lead Frame Chip Scale
ADP222ACPZ-2818-R7 −40°C to +125°C 2.8 1.8 8-Lead Lead Frame Chip Scale
ADP222ACPZ-2827-R7 −40°C to +125°C 2.8 2.7 8-Lead Lead Frame Chip Scale
ADP222ACPZ-3325-R7 −40°C to +125°C 3.3 2.5 8-Lead Lead Frame Chip Scale
ADP222ACPZ-3328-R7 −40°C to +125°C 3.3 2.8 8-Lead Lead Frame Chip Scale
ADP222ACPZ-3330-R7 −40°C to +125°C 3.3 3.0 8-Lead Lead Frame Chip Scale
ADP224ACPZ-2818-R7 −40°C to +125°C 2.8 1.8 8-Lead Lead Frame Chip Scale
ADP225ACPZ-R7 −40°C to +125°C Adjustable Adjustable 8-Lead Lead Frame Chip Scale
Figure 77. 8-Lead Lead Frame Chip Scale Package [LFCSP_UD]