Datasheet ADP221 Datasheet (ANALOG DEVICES)

Dual, 200 mA, Low Noise,

FEATURES

Input voltage range: 2.5 V to 5.5 V
Dual independent 200 mA low dropout voltage regulators
Miniature 6-ball, 1.0 mm × 1.5 mm WLCSP
Initial accuracy: ±1%
Stable with 1 μF ceramic output capacitors
No noise bypass capacitor required
Two independent logic controlled enables
Overcurrent and thermal protection
Active output pull-down (ADP221)
Key specifications

High PSRR

76 dB PSRR up to 1 kHz
70 dB PSRR at 10 kHz
60 dB PSRR at 100 kHz
40 dB PSRR at 1 MHz

Low output noise

27 μV rms typical output noise at V

50 μV rms typical output noise at V
Excellent transient response
Low dropout voltage: 150 mV @ 200 mA load
60 μA typical ground current at no load, both LDOs enabled
100 μs fast turn-on circuit
Guaranteed 200 mA output current per regulator

−40°C to +125°C junction temperature

= 1.2 V

OUT

= 2.8 V

OUT

High PSRR Voltage Regulator

ADP220/ADP221

TYPICAL APPLICATION CIRCUITS

1

ON

A

OFF

ON

OFF

EN1 VOUT1

B

GND VIN

C

EN2 VOUT2

TOP VIEW

(Not to Scale)

Figure 1. Typical Application Circuit

VIN VOUT1

CURRENT

LIMIT

REFERENCE

EN1

EN2

THERMAL

SHUTDOWN

CONTROL

LOGIC

AND

ENABLE

2

V

= 2.8V

OUT1

1µF

V

= 3.3V

IN

1µF

V

= 2.8V

OUT2

1µF

60Ω

ADP221

ONLY

07572-001

APPLICATIONS

Mobile phones
Digital cameras and audio devices
Portable and battery-powered equipment
Portable medical devices
Post dc-to-dc regulation

GENERAL DESCRIPTION

The 200 mA dual output ADP220/ADP221 combine high PSRR,
low noise, low quiescent current, and low dropout voltage in a
voltage regulator ideally suited for wireless applications with
demanding performance and board space requirements.

The low quiescent current, low dropout voltage, and wide input
voltage range of the ADP220/ADP221 extend the battery life of
portable devices. The ADP220/ADP221 maintain power supply
rejection greater than 60 dB for frequencies as high as 100 kHz
while operating with a low headroom voltage. The ADP220
offers much lower noise performance than competing LDOs

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

ADP220

GND

CURRENT

LIMIT

60Ω

Figure 2. Block Diagram of the ADP220/ADP221

without the need for a noise bypass capacitor. The ADP221 also
includes an active pull-down to quickly discharge output loads.

The ADP220/ADP221 are available in a miniature 6-ball
WLCSP package and is stable with tiny 1 µF ± 30% ceramic
output capacitors, resulting in the smallest possible board
area for a wide variety of portable power needs.

The ADP220/ADP221 are available in many output voltage
combinations, ranging from 0.8 V to 3.3 V, and offer overcur­rent and thermal protection to prevent damage in adverse
conditions.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2008–2010 Analog Devices, Inc. All rights reserved.

VOUT2

07572-002

ADP220/ADP221

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

Typical Application Circuits ............................................................ 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Input and Output Capacitor, Recommended Specifications .. 4

Absolute Maximum Ratings ............................................................ 5

Thermal Data ................................................................................ 5

Thermal Resistance ...................................................................... 5

ESD Caution .................................................................................. 5

Pin Configuration and Function Descriptions ............................. 6

REVISION HISTORY

5/10—Rev. C to Rev. D

Changes to Figure 1 .......................................................................... 1

Changes to Ordering Guide .......................................................... 17

1/10—Rev. B to Rev. C

Changes to Figure 24 ...................................................................... 10

10/09—Rev. A to Rev. B

Changes to Features Section............................................................ 1

Changes to Table 3 and Table 4 ....................................................... 5

Changes to Figure 4, Figure 6, Figure 7, and Figure 9 ................. 7

Changes to Figure 10 and Figure 12 ............................................... 8

Changes to Figure 17 ........................................................................ 9

Typical Performance Characteristics ..............................................7

Theory of Operation ...................................................................... 11

Applications Information .............................................................. 12

Capacitor Selection .................................................................... 12

Undervoltage Lockout ............................................................... 13

Enable Feature ............................................................................ 13

Current-Limit and Thermal Overload Protection ................. 14

Thermal Considerations ............................................................ 14

Printed Circuit Board (PCB) Layout Considerations ................ 16

Outline Dimensions ....................................................................... 17

Ordering Guide .......................................................................... 17

Changes to Figure 25 ...................................................................... 10

Changes to Enable Feature Section and Figure 32 ..................... 13

Changes to Current-Limit and Thermal Overland Protection

Section and Thermal Considerations Section ............................ 14

Changes to Ordering Guide .......................................................... 17

3/09—Rev. 0 to Rev. A

Changes to Figure 15 ......................................................................... 8

Changes to Figure 16 ......................................................................... 9

Changes to Ordering Guide .......................................................... 17

10/08—Revision 0: Initial Version

Rev. D | Page 2 of 20

ADP220/ADP221

SPECIFICATIONS

VIN = (V
unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

INPUT VOLTAGE RANGE VIN T
OPERATING SUPPLY CURRENT WITH

BOTH REGULATORS ON
I
I
I
I
I
SHUTDOWN CURRENT I
EN1= EN2 = GND, TJ = −40°C to +125°C 2 µA
FIXED OUTPUT VOLTAGE ACCURACY V

LINE REGULATION V
V
LOAD REGULATION
I
DROPOUT VOLTAGE

I
I
I
START-UP TIME
V
V
V
ACTIVE PULL-DOWN RESISTANCE t
CURRENT-LIMIT THRESHOLD
THERMAL SHUTDOWN

Thermal Shutdown Threshold TSSD T

Thermal Shutdown Hysteresis TS
EN INPUT

EN Input Logic High VIH 2.5 V ≤ VIN ≤ 5.5 V 1.2 V

EN Input Logic Low VIL 2.5 V ≤ VIN ≤ 5.5 V 0.4 V

EN Input Leakage Current V

EN1 = EN2 = VIN or GND, TJ = −40°C to +125°C 1 µA
UNDERVOLTAGE LOCKOUT UVLO

Input Voltage Rising UVLO

Input Voltage Falling UVLO

Hysteresis UVLO
OUTPUT NOISE OUT
10 Hz to 100 kHz, VIN = 5 V, V
10 Hz to 100 kHz, VIN = 3.6 V, V
10 Hz to 100 kHz, VIN = 3.6 V, V

+ 0.5 V) or 2.5 V (whichever is greater), EN1 = EN2 = VIN, I

OUT

= −40°C to +125°C 2.5 5.5 V

J

I

I

GND

EN1= EN2 = GND 0.1 µA

GND-SD

−1 +1 %

OUT

= 0 µA 60 µA

OUT

= 0 µA, TJ = −40°C to +125°C 120 µA

OUT

= 10 mA 70 µA

OUT

= 10 mA, TJ = −40°C to +125°C 140 µA

OUT

= 200 mA 120 µA

OUT

= 200 mA, TJ = −40°C to +125°C 220 µA

OUT

100 µA < I

5.5 V, T

/VIN VIN = (V

OUT

= (V

1

V

2

V

3

t

4

I

/I

OUT

DROPOUT

V

START-UP

SHUTDOWN

240 300 440 mA

LIMIT

SD-HYS

I-LEAKAGE

RISE

FAL L

HYS

NOISE

IN

I

OUT

V

= 1 mA to 200 mA 0.001 %/mA

OUT

= 1 mA to 200 mA, TJ = −40°C to +125°C 0.003 %/mA

OUT

V

= 3.3 V mV

OUT

I

= 10 mA 7.5 mV

OUT

= 10 mA, TJ = −40°C to +125°C 12 mV

OUT

= 200 mA 150 mV

OUT

= 200 mA, TJ = −40°C to +125°C 230 mV

OUT

= 3.3 V, both initially off, enable one 240 µs

OUT

= 0.8 V, both initially off, enable one 100 µs

OUT

= 3.3 V, one initially on, enable second 180 µs

OUT

= 0.8 V, one initially on, enable second 20 µs

OUT

= 2.8 V, R

OUT

rising 155 °C

J

15 °C

EN1 = EN2 = VIN or GND 0.1 µA

2.45 V

2.2 V
100 mV
10 Hz to 100 kHz, VIN = 5 V, V

= I

OUT1

< 200 mA, VIN = (V

OUT

= −40°C to +125°C

J

+ 0.5 V) to 5.5 V 0.01 %/V

OUT

+ 0.5 V) to 5.5 V, TJ = −40°C to +125°C −0.03 +0.03 %/V

OUT

= ∞, C

LOAD

= 10 mA, CIN = C

OUT2

+ 0.5 V) to

OUT

= 1 F, ADP221 only 80 Ω

OUT

= 3.3 V 56 µV rms

OUT

= 2.8 V 50 µV rms

OUT

= 2.5 V 45 µV rms

OUT

= 1.2 V 27 µV rms

OUT

OUT1

= C

= 1 µF, TA = 25°C,

OUT2

−2 +2 %

Rev. D | Page 3 of 20

ADP220/ADP221

Parameter Symbol Conditions Min Typ Max Unit

POWER SUPPLY REJECTION RATIO PSRR VIN = 2.5 V, V
100 Hz 76 dB
1 kHz 76 dB
10 kHz 70 dB
100 kHz 60 dB
1 MHz 40 dB
V

= 3.8 V, V

IN

100 Hz 68 dB
1 kHz 68 dB
10 kHz 68 dB
100 kHz 60 dB
1 MHz 40 dB

1

Based on an end-point calculation using 1 mA and 200 mA loads.

2

Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output

voltages above 2.5 V.

3

Start-up time is defined as the time between the rising edge of ENx to V

4

Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V

output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.

being at 90% of its nominal value.

OUTx

INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS

= 0.8 V, I

OUT

= 2.8 V, I

OUT

= 100 mA

OUT

= 100 mA

OUT

Table 2.

Parameter Symbol Conditions Min Typ Max Unit

MINIMUM INPUT AND OUTPUT CAPACITANCE
CAPACITOR ESR R

1

The minimum input and output capacitance should be greater than 0.70 µF over the full range of operating conditions. The full range of operating conditions in the

application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended;
Y5V and Z5U capacitors are not recommended for use with LDOs.

1

C

TA = −40°C to +125°C 0.70 µF

MIN

T

ESR

= −40°C to +125°C 0.001 1 Ω

A

Rev. D | Page 4 of 20

ADP220/ADP221

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

VIN to GND –0.3 V to +6.5 V
VOUT1, VOUT2 to GND –0.3 V to VIN
EN1, EN2 to GND –0.3 V to +6.5 V
Storage Temperature Range –65°C to +150°C
Operating Junction Temperature Range –40°C to +125°C
Soldering Conditions JEDEC J-STD-020

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL DATA

Absolute maximum ratings apply individually only, not in
combination.

The ADP220/ADP221 can be damaged when the junction
temperature limits are exceeded. Monitoring ambient temper­ature does not guarantee that the junction temperature (T
is within the specified temperature limits. In applications
with high power dissipation and poor thermal resistance, the
maximum ambient temperature may have to be derated. In
applications with moderate power dissipation and low PCB
thermal resistance, the maximum ambient temperature can
exceed the maximum limit as long as the junction temperature
is within specification limits. The junction temperature (T
the device is dependent on the ambient temperature (T
power dissipation of the device (P
thermal resistance of the package (θ
temperature (T
(T

) and power dissipation (PD) using the following formula:

A

T

= TA + (PD × θJA)

J

) is calculated from the ambient temperature

J

), and the junction-to-ambient

D

). Maximum junction

JA

J

), the

A

)

) of

J

Junction-to-ambient thermal resistance (θ
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent
on the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θ
on PCB material, layout, and environmental conditions. The
specified values of θ
circuit board. Refer to JEDEC JESD 51-9 for detailed informa­tion on the board construction. For additional information,
see the AN-617 Application Note, MicroCSP
Scale Package.

Ψ

is the junction-to-board thermal characterization parameter

JB

with units of °C/W. Ψ
calculation using a 4-layer board. The JESD51-12, Guidelines
for Reporting and Using Package Thermal Information, states
that thermal characterization parameters are not the same as
thermal resistances. Ψ
through multiple thermal paths rather than a single path as in
thermal resistance, θ
convection from the top of the package as well as radiation
from the package. Factors that make Ψ
world applications. Maximum junction temperature (T
calculated from the board temperature (T
dissipation (P

= TB + (PD × ΨJB)

T

J

Refer to JEDEC JESD51-8 and JESD51-12 for more detailed
information on Ψ

THERMAL RESISTANCE

θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.

Table 4.

Package Type θJA ΨJB Unit

6-Ball, 0.5 mm Pitch WLCSP 260 43.8 °C/W

are based on a four-layer, 4 inch × 3 inch,

JA

of the package is based on modeling and

JB

measures the component power flowing

JB

. Therefore, ΨJB thermal paths include

JB

) using the following formula:

D

.

JB

) of the package is

JA

may vary, depending

JA

TM

Wafer L ev e l Chi p

more useful in real-

JB

) is

J

) and power

B

ESD CAUTION

Rev. D | Page 5 of 20

ADP220/ADP221

A

C

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

EN1 VOUT1

B

GND VIN

EN2 VOUT2

TOP VIEW

(BALL SIDE DOWN)

Not to Scal e

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

A1 EN1

Enable Input for Regulator 1. Drive EN1 high to turn on Regulator 1; drive it low to turn off Regulator 1.

For automatic startup, connect EN1 to VIN.
B1 GND Ground Pin.
C1 EN2

Enable Input for Regulator 2. Drive EN2 high to turn on Regulator 2; drive it low to turn off Regulator 2.

For automatic startup, connect EN2 to VIN.
A2 VOUT1 Regulated Output Voltage 1. Connect a 1 µF or greater output capacitor between VOUT1 and GND.
B2 VIN Regulator Input Supply. Bypass VIN to GND with a 1 µF or greater capacitor.
C2 VOUT2 Regulated Output Voltage 2. Connect a 1 µF or greater output capacitor between VOUT2 and GND.

2

7572-003

Rev. D | Page 6 of 20

ADP220/ADP221

TYPICAL PERFORMANCE CHARACTERISTICS

VIN = 3.3 V, V

OUT1

= V

= 2.8 V, I

OUT2

= 10 mA, CIN = C

OUT

OUT1

= C

= 1 µF, TA = 25°C, unless otherwise noted.

OUT2

2.85

2.83

2.81

2.79

OUTPUT VOLTAGE (V)

2.77

2.75
–40–52585125

JUNCTION TE MPERATURE (°C)

Figure 4. Output Voltage vs. Junction Temperature

2.85

V

= 2.8V

OUT

V

= 3.3V

IN

T

= 25°C

2.83

2.81

2.79

OUTPUT VOLTAGE (V)

2.77

A

I

LOAD

I

LOAD

I

LOAD

I

LOAD

I

LOAD

I

LOAD

= 10µA
= 100µA
= 1mA
= 10mA
= 100mA
= 200mA

140

120

100

80

60

I

= 10µA

40

GROUND CURRENT (µA)

20

0

–40–52585125

07572-004

JUNCTION TE MPERATURE (°C)

LOAD

I

LOAD

I

LOAD

I

LOAD

I

LOAD

I

LOAD

= 100µA
= 1mA
= 10mA
= 100mA
= 200mA

07572-007

Figure 7. Ground Current vs. Junction Temperature, Single Output Loaded

120

V

= 2.8V

OUT

V

= 3.3V

IN

100

T

= 25°C

A

80

60

40

GROUND CURRENT (µA)

20

2.75

0.01 0.1 1 10 100 1k

LOAD CURRENT (mA)

Figure 5. Output Voltage vs. Load Current

2.85

I

V

= 2.8V

OUT

T

= 25°C

2.83

2.81

2.79

OUTPUT VOLTAGE (V)

2.77

2.75

A

3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5

INPUT VOLTAGE (V)

LOAD

I

LOAD

I

LOAD

I

LOAD

I

LOAD

I

LOAD

= 10µA
= 100µA
= 1mA
= 10mA
= 100mA
= 200mA

Figure 6. Output Voltage vs. Input Voltage

07572-005

07572-006

Rev. D | Page 7 of 20

0

0.01 0.1 1 10 100 1k

LOAD CURRENT (mA)

Figure 8. Ground Current vs. Load Current, Single Output Loaded

120

100

80

60

I

= 10µA

40

GROUND CURRENT (µA)

20

0

3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5

INPUT VOLTAGE (V)

LOAD

I

LOAD

I

LOAD

I

LOAD

I

LOAD

I

LOAD

= 100µA
= 1mA
= 10mA
= 100mA
= 200mA

Figure 9. Ground Current vs. Input Voltage, Single Output Loaded

07572-008

07572-009

ADP220/ADP221

160

140

120

100

80

60

GROUND CURRENT (µA)

40

20

0

–40–52585125

JUNCTION TE MPERATURE (°C)

I

LOAD

I

LOAD

I

LOAD

I

LOAD

I

LOAD

I

LOAD

= 10µA
= 100µA
= 1mA
= 10mA
= 100mA
= 200mA

07572-010

Figure 10. Ground Current vs. Junction Temperature, Both Outputs Loaded

140

V

= 2.8V

OUT

V

= 3.3V

IN

120

T

= 25°C

A

100

80

0.9

0.8

0.7

0.6

3.3V

3.6V

4.0V

4.3V

4.9V

5.5V

0.5

0.4

0.3

SHUTDOWN CURRENT ( µA)

0.2

0.1

0

–50 –25 1251007550250

TEMPERATURE ( °C)

Figure 13. Shutdown Current vs. Temperature at Various Input Voltages

250

200

150

2.5V

2.8V

3.3V

07572-013

60

40

GROUND CURRENT (µA)

20

0

0.01 0.1 1 10 100 1k

LOAD CURRRENT (mA)

Figure 11. Ground Current vs. Load Current, Both Outputs Loaded

140

120

100

80

60

I

= 10µA

LOAD

I

= 100µA

40

GROUND CURRENT (µA)

20

0

3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5. 5

LOAD

I

LOAD

I

LOAD

I

LOAD

I

LOAD

= 1mA
= 10mA
= 100mA
= 200mA

INPUT VOLTAGE (V)

Figure 12. Ground Current vs. Input Voltage, Both Outputs Loaded

100

DROPOUT VOLTAGE (mV)

50

0

110100

07572-011

LOAD CURRENT (mA)

1k

07572-014

Figure 14. Dropout Voltage vs. Load Current and Output Voltage

2.90

2.85

2.80

2.75

2.70

2.65

2.60

I

2.55

OUTPUT VOLTAGE (V)

2.50

2.45

2.40

2.6 2.7 2.8 2.9 3.0 3.1

07572-012

INPUT VOLTAGE (V)

LOAD

I

LOAD

I

LOAD

I

LOAD

I

LOAD

I

LOAD

= 1mA
= 5mA
= 10mA
= 50mA
= 100mA
= 200mA

07572-015

Figure 15. Output Voltage vs. Input Voltage (In Dropout)

Rev. D | Page 8 of 20

ADP220/ADP221

–

–

180

160

140

120

100

80

60

GROUND CURRENT (µA)

40

20

0

I

= 1mA

LOAD

I

= 5mA

LOAD

I

= 10mA

LOAD

I

= 50mA

LOAD

I

= 100mA

LOAD

I

= 200mA

LOAD

2.6 2.7 2.8 2.9 3.0 3.1

INPUT VOLTAGE (V)

Figure 16. Ground Current vs. Input Voltage (In Dropout)

07572-016

10

V

–20

–30

–40

RIPPLE

V

IN

V

OUT

C

OUT

= 2.5V

= 0.8V
= 1µF

= 50mV

200mA
100mA
10mA
1mA
100µA

–50

–60

PSRR (dB)

–70

–80

–90

–100

–110

10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 19. Power Supply Rejection Ratio vs. Frequency, 0.8 V

07572-019

10

V

–20

–30

–40

RIPPLE

V

IN

V

OUT

C

OUT

= 3.8V

= 2.8V
= 2.2µF

= 50mV

200mA
100mA
10mA
1mA
100µA

–50

–60

PSRR (dB)

–70

–80

–90

–100

–110

10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 17. Power Supply Rejection Ratio vs. Frequency, 2.8 V

0

V

–10

–20

–30

RIPPLE

V

IN

V

OUT

C

OUT

= 4.3V

= 3.3V
= 1µF

= 50mV

200mA
100mA
10mA
1mA
100µA

–40

–50

PSRR (dB)

–60

–70

–80

–90

–100

10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 18. Power Supply Rejection Ratio vs. Frequency, 3.3 V

0

–10

3.3V/200mA 0.8V/200mA 1.8V/ 200mA

3.3V/100µA 0.8V/100µA 1.8V/100µA

–20

–30

–40

–50

PSRR (dB)

–60

–70

–80

–90

–100

10 100 1k 10k 100k 1M 10M

07572-017

FREQUENCY (Hz)

07572-020

Figure 20. Power Supply Rejection Ratio vs. Frequency, at Various Output

Voltages and Load Currents

10

1

0.1

OUTPUT NOI SE SPECTRUM ( µV/ Hz)

0.01
10 100 1k 10k 100k

07572-018

FREQUENCY (Hz)

Figure 21. Output Noise Spectrum, VIN = 5 V, I

3.3V µV/ Hz

2.8V µV/ Hz

0.8V µV/ Hz

= 10 mA

LOAD

07572-021

Rev. D | Page 9 of 20

ADP220/ADP221

60

50

40

2

30

T

VIN = 4V TO 5V, I

V

IN

LOAD1

= 200mA, I

V

OUT1

LOAD2

= 100mA

NOISE (µV rms)

20

3.3V

10

0

0.001 0. 01 0.1 1 10 100 1k

2.8V

1.8V

0.8V

LOAD CURRENT (mA)

Figure 22. Output Noise vs. Load Current and Output Voltage, VIN = 5 V

1

2

3

CH1 200mA Ω

CH3 10.0mV

T

I

LOAD1

V

OUT1

V

B

W

B

W

OUT2

I

LOAD1

CH2 50.0mV

= 1mA TO 200mA, I

B

M40.0μs A CH1 132mA

W

T 10.00%

LOAD2

= 1mA

Figure 23. Load Transient Response,

= 1 mA to 200 mA, I

I

LOAD1

CH1 = I

LOAD1

, CH2 = V

OUT1

= 1 mA

LOAD2

, CH3 = V

OUT2

V

1
3

CH1 1.00V

07572-022

CH3 5.00mV

OUT2

B

W

B

W

CH2 5.00mV

B

M20.0μs A CH1 4.46V

W

T 13.60%

07572-025

Figure 25. Line Transient Response,

= 4 V to 5 V, I

V

IN

CH1 = V

T

VIN = 4V TO 5V, I

V

CH1 1.00V

CH3 5.00mV

OUT1

V

B

OUT2

CH2 5.00mV

W

B

W

2

1

3

07572-023

LOAD1

, CH2 = V

IN

V

IN

= 200 mA, I

LOAD2

, CH3 = V

OUT1

= 200mA, I

LOAD1

B

M20.0μs A CH1 4.46V

W

T 10.00%

= 100 mA

OUT2

= 1mA

LOAD2

07572-026

Figure 26. Line Transient Response

= 4 V to 5 V, I

V

IN

CH1 = V

LOAD1

, CH2 = V

IN

= 200 mA, I

, CH3 = V

OUT1

LOAD2

= 1 mA

OUT2

T

1

I

LOAD1

2

3

CH1 200mA Ω

CH3 10.0mV

I

LOAD1

= 1mA TO 200mA, I

V

OUT1

V

OUT2

B

CH2 50.0mV

W

B

W

= 100mA

LOAD2

B

M40.0μs A CH1 132mA

W

T 10.00%

Figure 24. Load Transient Response,

= 1 mA to 200 mA, I

I

LOAD1

CH1 = I

LOAD1

, CH2 = V

LOAD2

OUT1

= 100 mA,

, CH3 = V

OUT2

07572-024

1

2

3

CH1 5.00V

CH3 2.00V

T

B

W

B

W

CH2 2.00V

B

M40.0μs A CH1 2.10V

W

T 9.80%

Figure 27. Shutdown Response, ADP221

07572-027

Rev. D | Page 10 of 20

ADP220/ADP221

THEORY OF OPERATION

The ADP220/ADP221 are low quiescent current, low dropout
linear regulators that operate from 2.5 V to 5.5 V and provide
up to 200 mA of current from each output. Drawing a low 120 A
quiescent current (typical) at full load makes the ADP220/
ADP221 ideal for battery-operated portable equipment. Shut­down current consumption is typically 100 nA.

Optimized for use with small 1 µF ceramic capacitors, the
ADP220/ADP221 provide excellent transient performance.

VIN VOUT1

60Ω

EN1

EN2

GND

THERMAL

SHUTDOWN

CONTROL

LOGIC

AND

ENABLE

ADP220

CURRENT

LIMIT

REFERENCE

CURRENT

LIMIT

Figure 28. Internal Block Diagram

ADP221

ONLY

60Ω

VOUT2

07572-028

Internally, the ADP220/ADP221 consist of a reference, two error
amplifiers, two feedback voltage dividers, and two PMOS pass
transistors. Output current is delivered via the PMOS pass device,
which is controlled by the error amplifier. The error amplifier
compares the reference voltage with the feedback voltage from
the output and amplifies the difference. If the feedback voltage
is lower than the reference voltage, the gate of the PMOS device
is pulled lower, allowing more current to flow and increasing
the output voltage. If the feedback voltage is higher than the
reference voltage, the gate of the PMOS device is pulled higher,
allowing less current to flow and decreasing the output voltage.

The ADP221 also includes an active pull-down circuit to rapidly
discharge the output load capacitance when each output is
disabled.

The ADP220/ADP221 are available in multiple output voltage
options ranging from 0.8 V to 3.3 V. The ADP220/ADP221 use
the EN1/EN2 pins to enable and disable the VOUT1/VOUT2
pins under normal operating conditions. When EN1/EN2 are high,
VOUT1/VOUT2 turn on; when EN1/EN2 are low, VOUT1/
VOUT2 turn off. For automatic startup, EN1/EN2 can be tied
to VIN.

Rev. D | Page 11 of 20

ADP220/ADP221

APPLICATIONS INFORMATION

CAPACITOR SELECTION

Output Capacitor

The ADP220/ADP221 are designed for operation with small,
space-saving ceramic capacitors, but the parts function with
most commonly used capacitors as long as care is taken with
regards to the effective series resistance (ESR) value. The ESR
of the output capacitor affects stability of the LDO control loop.
A minimum of 0.70 µF capacitance with an ESR of 1 Ω or less
is recommended to ensure stability of the ADP220/ADP221.
Transient response to changes in load current is also affected by
output capacitance. Using a larger value of output capacitance
improves the transient response of the ADP220/ADP221 to large
changes in the load current. Figure 29 and Figure 30 show the
transient responses for output capacitance values of 1 µF and

4.7 µF, respectively.

T

I

LOAD1

1

I

= 1mA TO 200mA, I

LOAD1

2

V

OUT1

3

CH1 200mA Ω

CH3 10.0mV

B

CH2 50.0mV

W

B

W

B

W

T 26.60%

Figure 29. Output Transient Response

I

= 1 mA to 200 mA, I

LOAD1

CH1 = I

LOAD1

, CH2 = V

OUT1

, CH3 = V

T

1

I

LOAD1

2

V

OUT1

I

LOAD1

= 1mA TO 200mA, I

= 1mA

LOAD2

V

OUT2,COUT

M200ns A CH1 132mA

LOAD2

= 1 mA

OUT2

LOAD2

, C

OUT

= 1mA

= 1µF

= 1 μF

07572-029

Input Bypass Capacitor

Connecting a 1 µF capacitor from VIN to GND reduces the
circuit sensitivity to the PCB layout, especially when long input
traces or high source impedance are encountered. If an output
capacitance greater than 1 µF is required, the input capacitor
should be increased to match it.

Input and Output Capacitor Properties

Any good quality ceramic capacitor can be used with the ADP220/
ADP221, as long as the capacitor meets the minimum capacit­ance and maximum ESR requirements. Ceramic capacitors are
manufactured with a variety of dielectrics, each with a different
behavior over temperature and applied voltage. Capacitors must
have an adequate dielectric to ensure the minimum capacitance
over the necessary temperature range and dc bias conditions.
X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are
recommended. Y5V and Z5U dielectrics are not recommended,
due to their poor temperature and dc bias characteristics.

Figure 31 depicts the capacitance vs. voltage bias characteristic
of an 0402 1 µF, 10 V, X5R capacitor. The voltage stability of a
capacitor is strongly influenced by the capacitor size and voltage
rating. In general, a capacitor in a larger package or higher voltage
rating exhibits better stability. The temperature variation of the
X5R dielectric is about ±15% over the −40°C to +85°C tempera­ture range and is not a function of the package or voltage rating.

1.2

1.0

0.8

0.6

0.4

CAPACITANCE (µF)

0.2

0

024681

VOLTAGE (V)

Figure 31. Capacitance vs. Voltage Bias Characteristic

0

07572-031

3

CH1 200mA Ω

CH3 10.0mV

CH1 = I

V

OUT2,COUT

B

CH2 50.0mV

W

B

W

B

M1.00µs A CH1 132mA

W

T 11.40%

Figure 30. Output Transient Response

I

= 1 mA to 200 mA, I

LOAD1

, CH2 = V

LOAD1

OUT1

, CH3 = V

LOAD2

OUT2

= 1 mA

, C

OUT

= 4.7µF

= 4.7 μF

07572-030

Rev. D | Page 12 of 20

ADP220/ADP221

Equation 1 can be used to determine the worst-case capacitance
accounting for capacitor variation over temperature, compo­nent tolerance, and voltage.

C

= C

EFF

× (1 − TEMPCO) × (1 − TOL) (1)

BIAS

where:
C

is the effective capacitance at the operating voltage.

BIAS

TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.

In this example, TEMPCO over −40°C to +85°C is assumed to
be 15% for an X5R dielectric. TOL is assumed to be 10%, and
C

is 0.94 F at 1.8 V from the graph in Figure 31.

BIAS

Substituting these values into Equation 1 yields

C

= 0.94 F × (1 − 0.15) × (1 − 0.1) = 0.719 F

EFF

Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over
temperature and tolerance at the chosen output voltage.

To guarantee the performance of the ADP220/ADP221, it is
imperative that the effects of dc bias, temperature, and toler­ances on the behavior of the capacitors be evaluated for each
application.

UNDERVOLTAGE LOCKOUT

The ADP220/ADP221 have an internal undervoltage lockout
circuit that disables all inputs and the output when the input
voltage is less than approximately 2.2 V. This ensures that the
inputs of the ADP220/ADP221 and the output behave in a
predictable manner during power-up.

ENABLE FEATURE

The ADP220/ADP221 use the ENx pins to enable and disable
the VOUTx pins under normal operating conditions. Figure 32
shows a rising voltage on ENx crossing the active threshold,
then V
inactive threshold, V

turns on. When a falling voltage on ENx crosses the

OUTx

turns off.

OUTx

As shown in Figure 32, the ENx pins have built-in hysteresis.
This prevents on/off oscillations that can occur due to noise on
the ENx pins as it passes through the threshold points.

The active/inactive thresholds of the ENx pins are derived from
the VIN voltage. Therefore, these thresholds vary with changing
input voltage. Figure 33 shows typical ENx active/inactive thresh­olds when the input voltage varies from 2.5 V to 5.5 V.

1.00

0.95

0.90

0.85

0.80

0.75

0.70

ENx PINS THRES HOLD (V)

0.65

0.60

2.5 3.0 3. 5 4 .0 4.5 5. 0 5.5

EN ACTIVE

EN INACTIVE

INPUT VOLTAGE (V)

07572-033

Figure 33. Typical ENx Pins Thresholds vs. Input Voltage

The ADP220/ADP221 utilize an internal soft start to limit the
inrush current when the output is enabled. The start-up time
for the 2.8 V option is approximately 220 µs from the time the
ENx active threshold is crossed to when the output reaches 90%
of its final value. The start-up time is somewhat dependent on
the output voltage setting and increases slightly as the output
voltage increases.

T

1

1

CH1 500mV

T

V

OUTx

ENx

B

CH2 500mV

W

B

M10.0ms A CH2 1.76V

W

T 27.40%

Figure 32. Typical ENx Pin Operation

07572-032

Rev. D | Page 13 of 20

2

3

CH1 5.00V

CH3 2.00V

B

W

B

W

CH2 2.00V

B

M40.0µs A CH1 2.10V

W

T 9.80%

Figure 34. Typical Start-Up Time

07572-034

ADP220/ADP221

CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION

The ADP220/ADP221 are protected against damage due to
excessive power dissipation by current and thermal overload
protection circuits. The ADP220/ADP221 are designed to
current limit when the output load reaches 300 mA (typical).
When the output load exceeds 300 mA, the output voltage is
reduced to maintain a constant current limit.

Thermal overload protection is built-in, which limits the
junction temperature to a maximum of 155°C (typical). Under
extreme conditions (that is, high ambient temperature and
power dissipation) when the junction temperature starts to
rise above 155°C, the output is turned off, reducing the output
current to zero. When the junction temperature drops below
140°C, the output is turned on again and the output current
is restored to its nominal value.

Consider the case where a hard short from VOUTx to GND
occurs. At first, the ADP220/ADP221 current limit, so that only
300 mA is conducted into the short. If self-heating of the junction
is great enough to cause its temperature to rise above 155°C,
thermal shutdown activates, turning off the output and reducing
the output current to zero. As the junction temperature cools
and drops below 140°C, the output turns on and conducts 300 mA
into the short, again causing the junction temperature to rise
above 155°C. This thermal oscillation between 140°C and
155°C causes a current oscillation between 0 mA and 300 mA
that continues as long as the short remains at the output.

Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For reliable
operation, device power dissipation must be externally limited
so that junction temperatures do not exceed 125°C.

THERMAL CONSIDERATIONS

In most applications, the ADP220/ADP221 do not dissipate
much heat due to high efficiency. However, in applications with
a high ambient temperature and high supply voltage to output
voltage differential, the heat dissipated in the package is large
enough that it can cause the junction temperature of the die
to exceed the maximum junction temperature of 125°C.

When the junction temperature exceeds 155°C, the converter
enters thermal shutdown. It recovers only after the junction
temperature has decreased below 140°C to prevent any permanent
damage. Therefore, thermal analysis for the chosen application
is very important to guarantee reliable performance over all
conditions. The junction temperature of the die is the sum of
the ambient temperature of the environment and the tempera­ture rise of the package due to the power dissipation, as shown
in Equation 2.

To guarantee reliable operation, the junction temperature of
the ADP220/ADP221 must not exceed 125°C. To ensure that
the junction temperature stays below this maximum value, the
user needs to be aware of the parameters that contribute to junction
temperature changes. These parameters include ambient tem­perature, power dissipation in the power device, and thermal
resistances between the junction and ambient air (θ

). The θJA

JA

number is dependent on the package assembly compounds used
and the amount of copper to which the GND pins of the package
are soldered on the PCB. Tab l e 6 shows typical θ

values for the

JA

ADP220/ADP221 for various PCB copper sizes.

Table 6. Typical θ

Values

JA

Copper Size (mm2) ADP220/ADP221 (°C/W)

01 200
50 119
100 118
300 115
500 113

1

Device soldered to minimum size pin traces.

The junction temperature of the ADP220/ADP221 can be
calculated from the following equation:

T

= TA + (PD × θJA) (2)

J

where:

T

is the ambient temperature.

A

P

is the power dissipation in the die, given by

D

= Σ[(VIN − V

P

D

OUT

) × I

] + Σ(VIN × I

LOAD

) (3)

GND

where:

I

is the load current.

LOAD

I

is the ground current.

GND

V

and V

IN

are input and output voltages, respectively.

OUT

Power dissipation due to ground current is quite small and
can be ignored. Therefore, the junction temperature equation
simplifies to

T

= TA + {Σ[(VIN − V

J

OUT

) × I

] × θJA} (4)

LOAD

As shown in Equation 4, for a given ambient temperature,
input-to-output voltage differential, and continuous load
current, there exists a minimum copper size requirement
for the PCB to ensure the junction temperature does not rise
above 125°C. Figure 35 to Figure 39 show junction temperature
calculations for different ambient temperatures, total power
dissipation, and areas of PCB copper.

In cases where the board temperature is known, the thermal
characterization parameter, Ψ
junction temperature rise. T

, can be used to estimate the

JB

is calculated from TB and PD using

J

the formula

T

= TB + (PD × ΨJB) (5)

J

The typical Ψ

value for the 6-ball WLCSP is 43.8°C/W.

JB

Rev. D | Page 14 of 20

ADP220/ADP221

145

135

125

115

105

95

85

75

65

55

JUNCTION TEM PERATURE (°C)

45

35

25

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

TOTAL PO WER DISSIPATION (W )

500mm
50mm
0mm
T

JMAX

2

2

2

Figure 35. Junction Temperature vs. Total Power Dissipation, TA = 25°C

07572-035

135

125

115

105

2

95

JUNCTION TEM PERATURE (°C)

85

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

TOTAL PO WER DISSIPATION (W )

500mm
50mm
0mm
T

JMAX

2

2

Figure 38. Junction Temperature vs. Total Power Dissipation, TA = 85°C

07572-038

140

130

120

110

100

90

80

70

JUNCTION TEM PERATURE (°C)

60

50

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

TOTAL PO WER DISSIPATION (W )

500mm
50mm
0mm
T

JMAX

2

2

2

Figure 36. Junction Temperature vs. Total Power Dissipation, TA = 50°C

145

135

125

115

105

95

140

120

100

80

60

40

JUNCTION TEM PERATURE (°C)

20

0

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.22.0 2.4

07572-036

TOTAL PO WER DISSIPATION (W )

TB = 25°C
T

= 50°C

B

T

= 65°C

B

T

= 85°C

B

T

JMAX

07572-039

Figure 39. Junction Temperature vs. Total Power Dissipation and

Board Temperature

85

JUNCTION TEM PERATURE (°C)

75

65

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

TOTAL PO WER DISSIPATION (W )

500mm
50mm
0mm
T

JMAX

2

2

Figure 37. Junction Temperature vs. Total Power Dissipation, TA = 65°C

2

07572-037

Rev. D | Page 15 of 20

ADP220/ADP221

PRINTED CIRCUIT BOARD (PCB) LAYOUT CONSIDERATIONS

Heat dissipation from the package can be improved by
increasing the amount of copper attached to the pins of the
ADP220/ADP221. However, as shown in Tab l e 6, a point of
diminishing returns eventually is reached, beyond which an
increase in the copper size does not yield significant heat
dissipation benefits.

Place the input capacitor as close as possible to the VIN and
GND pins. Place the output capacitors as close as possible to
the VOUT1, VOUT2, and GND pins. Use 0402 or 0603
size capacitors and resistors to achieve the smallest possible
footprint solution on boards where area is limited.

Figure 40. Example of PCB Layout, Top Side

07572-040

07572-041

Figure 41. Example of PCB Layout, Bottom Side

Rev. D | Page 16 of 20

ADP220/ADP221

OUTLINE DIMENSIONS

0.675

0.595

0.515

SEATING
PLANE

0.345

1.00

0.295
BSC

0.245

0.50
BSC

0.075
COPLANARITY

(CB-6-2)

Package Description

12

BOTTOM VIEW

(BALL SIDE UP)

A

B

C

0.50 BSC

081607-B

Package
Option

Branding

1.50

1.45

1.40

0.380

0.355

0.330

0.270

0.240

0.210

A1 BALL
CORNER

1.00

0.95

0.90

TOP VIEW

(BALL SIDE DOWN)

Figure 42. 6-Ball Wafer Level Chip Scale Package [WLCSP]

Dimensions show in millimeters

ORDERING GUIDE

Te mp e ra tu r e
Range

Model

1

ADP220ACBZ-1118R7 −40°C to +125°C 1.1/1.8 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-2 LFY
ADP220ACBZ-1812R7 −40°C to +125°C 1.8/1.2 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-2 LEK
ADP220ACBZ-1827R7 −40°C to +125°C 1.8/2.7 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-2 LEH
ADP220ACBZ-2623R7 −40°C to +125°C 2.6/2.3 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-2 LGD
ADP220ACBZ-26235R7 −40°C to +125°C 2.6/2.35 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-2 L9L
ADP220ACBZ-2812R7 −40°C to +125°C 2.8/1.2 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-2 L8X
ADP220ACBZ-2818R7 −40°C to +125°C 2.8/1.8 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-2 LEL
ADP220ACBZ-2827R7 −40°C to +125°C 2.8/2.7 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-2 L8Y
ADP220ACBZ-2828R7 −40°C to +125°C 2.8/2.8 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-2 L8W
ADP220ACBZ275275R7 −40°C to +125°C 2.75/2.75 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-2 L8Z
ADP221ACBZ3033-R7 −40°C to +125°C 3.0/3/3 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-2 LH4
ADP221ACBZ2828-R7 −40°C to +125°C 2.8/2.8 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-2 L90
ADP220-2828-EVALZ −40°C to +125°C 2.8/2.8 2.8 V/2.8 V Evaluation Board
ADP221-2828-EVALZ −40°C to +125°C 2.8/2.8 2.8 V/2.8 V with Output Discharge Evaluation Board

1

Z = RoHS Compliant Part.

2

For additional voltage options, contact a local Analog Devices sales or distribution representative.

Output
Voltage (V)

2

Rev. D | Page 17 of 20

ADP220/ADP221

NOTES

Rev. D | Page 18 of 20

ADP220/ADP221

NOTES

Rev. D | Page 19 of 20

ADP220/ADP221

NOTES

©2008–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07572-0-5/10(D)

Rev. D | Page 20 of 20