Datasheet ADP220 Datasheet (ANALOG DEVICES)

High PSRR Voltage Regulator

ADP220/ADP221

Rev. F

rights of third parties that may result from its use. Specifications subject to change without notice. No

Trademarks and registered trademarks are the prop erty of their respective owner s.

Fax: [phone] ©2008–2012 Analog Devices, Inc. All rights reserved.

EN1 VOUT1

GND VIN

EN2 VOUT2

TOP VIEW

(Not to S cale)

1

A

B

C

2

V

OUT1

= 2.8V

1µF

1µF

1µF

V

IN

= 3.3V

V

OUT2

= 2.8V

07572-001

OFF

ON

OFF

ON

THERMAL

SHUTDOWN

EN1

EN2

GND

CURRENT

LIMIT

CURRENT

LIMIT

60Ω

60Ω

REFERENCE

ADP221

ONLY

CONTROL

LOGIC

AND

ENABLE

VIN VOUT1

VOUT2

ADP220

07572-002

Data Sheet

FEATURES

Input voltage range: 2.5 V to 5.5 V
Dual independent 200 mA low dropout voltage regulators
Miniature 6-ball, 1.0 mm × 1.5 mm WLCSP
Initial accuracy: ±1%
Stable with 1 µF ceramic output capacitors
No noise bypass capacitor required
Two independent logic controlled enables
Overcurrent and thermal protection
Active output pull-down (ADP221)
Key specifications

High PSRR

76 dB PSRR up to 1 kHz
70 dB PSRR at 10 kHz
60 dB PSRR at 100 kHz
40 dB PSRR at 1 MHz

Low output noise

27 µV rms typical output noise at V

50 µV rms typical output noise at V
Excellent transient response
Low dropout voltage: 150 mV @ 200 mA load
60 µA typical ground current at no load, both LDOs enabled
100 µs fast turn-on circuit
Guaranteed 200 mA output current per regulator

−40°C to +125°C junction temperature

= 1.2 V

OUT

= 2.8 V

OUT

Dual, 200 mA, Low Noise,

TYPICAL APPLICATION CIRCUITS

Figure 1. Typical Application Circuit

APPLICATIONS

Mobile phones
Digital cameras and audio devices
Portable and battery-powered equipment
Portable medical devices
Post dc-to-dc regulation

GENERAL DESCRIPTION

The 200 mA dual output ADP220/ADP221 combine high PSRR,
low noise, low quiescent current, and low dropout voltage in a
voltage regulator ideally suited for wireless applications with
demanding performance and board space requirements.

The low quiescent current, low dropout voltage, and wide input
voltage range of the ADP220/ADP221 extend the battery life of
portable devices. The ADP220/ADP221 maintain power supply
rejection greater than 60 dB for frequencies as high as 100 kHz
while operating with a low headroom voltage. The ADP220
offers much lower noise performance than competing LDOs

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Figure 2. Block Diagram of the ADP220/ADP221

without the need for a noise bypass capacitor. The ADP221 also
includes an active pull-down to quickly discharge output loads.

The ADP220/ADP221 are available in a miniature 6-ball
WLCSP package and is stable with tiny 1 µF ± 30% ceramic
output capacitors, resulting in the smallest possible board
area for a wide variety of portable power needs.

The ADP220/ADP221 are available in many output voltage
combinations, ranging from 0.8 V to 3.3 V, and offer overcur­rent and thermal protection to prevent damage in adverse
conditions.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com

ADP220/ADP221 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Typical Application Circuits ............................................................ 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Input and Output Capacitor, Recommended Specifications .. 4

Absolute Maximum Ratings ............................................................ 5

Thermal Data ................................................................................ 5

Thermal Resistance ...................................................................... 5

ESD Caution .................................................................................. 5

Pin Configuration and Function Descriptions ............................. 6

REVISION HISTORY

/12—Rev. E to R e v. F

C

hanges to Ordering Guide .......................................................... 17

11/10—Rev. D t o R e v. E

Changes to Ordering Guide .......................................................... 17

5/10—Rev. C to R e v. D

Changes to Figure 1 .......................................................................... 1

Changes to Ordering Guide .......................................................... 17

1/10—Rev. B to R e v. C

Changes to Figure 24 ...................................................................... 10

10/09—Rev. A to Rev. B

Changes to Features Section............................................................ 1

Changes to Table 3 an

d Table 4 ....................................................... 5

Typical Performance Characteristics ..............................................7

Theory of Operation ...................................................................... 11

Applications Information .............................................................. 12

Capacitor Selection .................................................................... 12

Undervoltage Lockout ............................................................... 13

Enable Feature ............................................................................ 13

Current-Limit and Thermal Overload Protection ................. 14

Thermal Considerations ............................................................ 14

Printed Circuit Board (PCB) Layout Considerations ................ 16

Outline Dimensions ....................................................................... 17

Ordering Guide .......................................................................... 17

Changes to Figure 4, Figure 6, Figure 7, and Figure 9 .................. 7

Changes to Figure 10 and Figure 12................................................ 8

Changes to Figure 17 ......................................................................... 9

Changes to Figure 25 ...................................................................... 10

Changes to Enable Feature Section and Figure 32 ..................... 13

Changes to Current-Limit and Thermal Overland Protection

Section and Thermal Considerations Section ............................ 14

Changes to Ordering Guide .......................................................... 17

3/09—Rev. 0 to R e v. A

Changes to Figure 15 ......................................................................... 8

Changes to Figure 16 ......................................................................... 9

Changes to Ordering Guide .......................................................... 17

10/08—Revision 0: Initial Version

Rev. F | Page 2 of 20

Data Sheet ADP220/ADP221

INPUT VOLTAGE RANGE

VIN

TJ = −40°C to +125°C

2.5 5.5

V

I

= 0 µA, TJ = −40°C to +125°C

120

µA

DROPOUT VOLTAGE2

V

V

= 3.3 V

mV

V

= 0.8 V, one initially on, enable second

20 µs

THERMAL SHUTDOWN

Hysteresis

UVLO

100 mV

10 Hz to 100 kHz, VIN = 3.6 V, V

= 2.5 V

45 µV rms

SPECIFICATIONS

VIN = (V
unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

+ 0.5 V) or 2.5 V (whichever is greater), EN1 = EN2 = VIN, I

OUT

OUT1

= I

= 10 mA, CIN = C

OUT2

OUT1

= C

= 1 µF, TA = 25°C,

OUT2

OPERATING SUPPLY CURRENT WITH

I

I

GND

= 0 µA 60 µA

OUT

BOTH REGULATORS ON

OUT

I
I
I
I
SHUTDOWN CURRENT I

EN1= EN2 = GND 0.1 µA

GND-SD

= 10 mA 70 µA

OUT

= 10 mA, TJ = −40°C to +125°C 140 µA

OUT

= 200 mA 120 µA

OUT

= 200 mA, TJ = −40°C to +125°C 220 µA

OUT

EN1= EN2 = GND, TJ = −40°C to +125°C 2 µA
FIXED OUTPUT VOLTAGE ACCURACY V

LINE REGULATION ∆V
VIN = (V
LOAD REGULATION1 ∆V
I

I
I
I
STA RT-UP TIME3 t
V
V

ACTIVE PULL-DOWN RESISTANCE t
CURRENT-LIMIT THRESHOLD4 I

−1 +1 %

OUT

100 µA < I

5.5 V, T

/∆VIN VIN = (V

OUT

/∆I

I

OUT

OUT

DROPOUT

V

STA RT-UP

V

SHUTDOWN

240 300 440 mA

LIMIT

= 1 mA to 200 mA 0.001 %/mA

OUT

= 1 mA to 200 mA, TJ = −40°C to +125°C 0.003 %/mA

OUT

OUT

I

= 10 mA 7.5 mV

OUT

= 10 mA, TJ = −40°C to +125°C 12 mV

OUT

= 200 mA 150 mV

OUT

= 200 mA, TJ = −40°C to +125°C 230 mV

OUT

= 3.3 V, both initially off, enable one 240 µs

OUT

= 0.8 V, both initially off, enable one 100 µs

OUT

= 3.3 V, one initially on, enable second 180 µs

OUT

OUT

= 2.8 V, R

OUT

< 200 mA, VIN = (V

OUT

= −40°C to +125°C

J

+ 0.5 V) to 5.5 V 0.01 %/V

OUT

+ 0.5 V) to 5.5 V, TJ = −40°C to +125°C −0.03 +0.03 %/V

OUT

LOAD

= ∞, C

= 1 μF, ADP221 only 80 Ω

OUT

+ 0.5 V) to

OUT

−2 +2 %

Thermal Shutdown Threshold TSSD TJ rising 155 °C
Thermal Shutdown Hysteresis TS

EN INPUT

EN Input Logic High VIH 2.5 V ≤ VIN ≤ 5.5 V 1.2 V
EN Input Logic Low VIL 2.5 V ≤ VIN ≤ 5.5 V 0.4 V
EN Input Leakage Current V
EN1 = EN2 = VIN or GND, TJ = −40°C to +125°C 1 µA

UNDERVOLTAGE LOCKOUT UVLO

Input Voltage Rising UVLO
Input Voltage Falling UVLO

OUTPUT NOISE OUT
10 Hz to 100 kHz, VIN = 5 V, V

10 Hz to 100 kHz, VIN = 3.6 V, V

15 °C

SD-HYS

EN1 = EN2 = VIN or GND 0.1 µA

I-LEAKAGE

2.45 V

RISE

2.2 V

FAL L

HYS

10 Hz to 100 kHz, VIN = 5 V, V

NOISE

Rev. F | Page 3 of 20

= 3.3 V 56 µV rms

OUT

= 2.8 V 50 µV rms

OUT

OUT

= 1.2 V 27 µV rms

OUT

ADP220/ADP221 Data Sheet

100 kHz

60 dB

100 kHz

60 dB

Parameter Symbol Conditions Min Typ Max Unit

POWER SUPPLY REJECTION RATIO PSRR VIN = 2.5 V, V
100 Hz 76 dB
1 kHz 76 dB
10 kHz 70 dB

1 MHz 40 dB
VIN = 3.8 V, V
100 Hz 68 dB
1 kHz 68 dB
10 kHz 68 dB

1 MHz 40 dB

1

Based on an end-point calculation using 1 mA and 200 mA loads.

2

Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output

voltages above 2.5 V.

3

Start-up time is defined as the time between the rising edge of ENx to V

4

Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V

output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.

being at 90% of its nominal value.

OUTx

INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS

= 0.8 V, I

OUT

= 2.8 V, I

OUT

= 100 mA

OUT

= 100 mA

OUT

Table 2.

Parameter Symbol Conditions Min Typ Max Unit

MINIMUM INPUT AND OUTPUT CAPACITANCE1 C
CAPACITOR ESR R

1

The minimum input and output capacitance should be greater than 0.70 µF over the full range of operating conditions. The full range of operating conditions in the

application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended;
Y5V and Z5U capacitors are not recommended for use with LDOs.

TA = −40°C to +125°C 0.70 µF

MIN

TA = −40°C to +125°C 0.001 1 Ω

ESR

Rev. F | Page 4 of 20

Data Sheet ADP220/ADP221

VOUT1, VOUT2 to GND

–0.3 V to VIN

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

VIN to GND –0.3 V to +6.5 V

EN1, EN2 to GND –0.3 V to +6.5 V
Storage Temperature Range –65°C to +150°C
Operating Junction Temperature Range –40°C to +125°C
Soldering Conditions JEDEC J-STD-020

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL DATA

Absolute maximum ratings apply individually only, not in
combination.

The ADP220/ADP221 can be damaged when the junction
temperature limits are exceeded. Monitoring ambient temper­ature does not guarantee that the junction temperature (T
is within the specified temperature limits. In applications
with high power dissipation and poor thermal resistance, the
maximum ambient temperature may have to be derated. In
applications with moderate power dissipation and low PCB
thermal resistance, the maximum ambient temperature can
exceed the maximum limit as long as the junction temperature
is within specification limits. The junction temperature (T
the device is dependent on the ambient temperature (T
power dissipation of the device (P
thermal resistance of the package (θ
temperature (T
(T

) and power dissipation (PD) using the following formula:

A

= TA + (PD × θJA)

T

J

) is calculated from the ambient temperature

J

), and the junction-to-ambient

D

). Maximum junction

JA

J

), the

A

)

) of

J

Junction-to-ambient thermal resistance (θ
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent
on the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θ
on PCB material, layout, and environmental conditions. The
specified values of θ

are based on a four-layer, 4 inch × 3 inch,

JA

circuit board. Refer to JEDEC JESD 51-9 for detailed informa­tion on the board construction. For additional information,
see the AN-617 Application Note, MicroCSP
Scale Package.

Ψ

is the junction-to-board thermal characterization parameter

JB

with units of °C / W. Ψ

of the package is based on modeling and

JB

calculation using a 4-layer board. The JESD51-12, Guidelines
for Reporting and Using Package Thermal Information, states
that thermal characterization parameters are not the same as
thermal resistances. Ψ

measures the component power flowing

JB

through multiple thermal paths rather than a single path as in
thermal resistance, θ

. Therefore, ΨJB thermal paths include

JB

convection from the top of the package as well as radiation
from the package. Factors that make Ψ
world applications. Maximum junction temperature (T
calculated from the board temperature (T
dissipation (P

= TB + (PD × ΨJB)

T

J

) using the following formula:

D

Refer to JEDEC JESD51-8 and JESD51-12 for more detailed
information on Ψ

.

JB

THERMAL RESISTANCE

θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.

Table 4.

Package Type θJA ΨJB Unit

6-Ball, 0.5 mm Pitch WLCSP 260 43.8 °C/W

) of the package is

JA

may vary, depending

JA

TM

Wafer Level Chip

more useful in real-

JB

) is

J

) and power

B

ESD CAUTION

Rev. F | Page 5 of 20

ADP220/ADP221 Data Sheet

TOP VIEW

(BALL SI DE DOWN)

Not to Scale

07572-003

1

A

2

EN1 VOUT1

GND VIN

EN2 VOUT2

B

C

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

A1 EN1

Enable Input for Regulator 1. Drive EN1 high to turn on Regulator 1; drive it low to turn off Regulator 1.

For automatic startup, connect EN1 to VIN.
B1 GND Ground Pin.
C1 EN2

Enable Input for Regulator 2. Drive EN2 high to turn on Regulator 2; drive it low to turn off Regulator 2.

For automatic startup, connect EN2 to VIN.
A2 VOUT1 Regulated Output Voltage 1. Connect a 1 µF or greater output capacitor between VOUT1 and GND.
B2 VIN Regulator Input Supply. Bypass VIN to GND with a 1 µF or greater capacitor.
C2 VOUT2 Regulated Output Voltage 2. Connect a 1 µF or greater output capacitor between VOUT2 and GND.

Rev. F | Page 6 of 20

Data Sheet ADP220/ADP221

2.85

2.83

2.81

2.79

2.77

OUTPUT VOLTAGE (V)

JUNCTION T E M P E RATURE (°C)

2.75
–40 –5 25 85 125

I

LOAD

= 10µA

I

LOAD

= 100µA

I

LOAD

= 1mA

I

LOAD

= 10mA

I

LOAD

= 100mA

I

LOAD

= 200mA

07572-004

2.85

2.83

2.81

2.79

2.77

OUTPUT VOLTAGE (V)

LOAD CURRENT ( mA)

2.75

0.01 0.1 1 10 100 1k

V

OUT

= 2.8V

V

IN

= 3.3V

T

A

= 25°C

07572-005

3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
INPUT VOLTAGE (V)

V

OUT

= 2.8V

T

A

= 25°C

I

LOAD

= 10µA

I

LOAD

= 100µA

I

LOAD

= 1mA

I

LOAD

= 10mA

I

LOAD

= 100mA

I

LOAD

= 200mA

2.85

2.83

2.81

2.79

2.77

OUTPUT VOLTAGE (V)

2.75

07572-006

140

120

100

80

60

40

20

GROUND CURRENT ( µ A)

JUNCTION T E M P E RATURE (°C)

0

–40 –5 25 85 125

I

LOAD

= 10µA

I

LOAD

= 100µA

I

LOAD

= 1mA

I

LOAD

= 10mA

I

LOAD

= 100mA

I

LOAD

= 200mA

07572-007

120

100

80

60

40

20

GROUND CURRENT ( µ A)

0

V

OUT

= 2.8V

V

IN

= 3.3V

T

A

= 25°C

LOAD CURRENT ( mA)

0.01

0.1 1 10 100 1k

07572-008

3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
INPUT VOLTAGE (V)

120

100

80

60

40

20

GROUND CURRENT ( µ A)

0

I

LOAD

= 10µA

I

LOAD

= 100µA

I

LOAD

= 1mA

I

LOAD

= 10mA

I

LOAD

= 100mA

I

LOAD

= 200mA

07572-009

TYPICAL PERFORMANCE CHARACTERISTICS

VIN = 3.3 V, V

OUT1

= V

OUT2

= 2.8 V, I

= 10 mA, CIN = C

OUT

OUT1

= C

= 1 µ F, TA = 25°C, unless otherwise noted.

OUT2

Figure 4. Output Voltage vs. Junction Temperature

Figure 5. Output Voltage vs. Load Current

Figure 7. Ground Current vs. Junction Temperature, Single Output Loaded

Figure 8. Ground Current vs. Load Current, Single Output Loaded

Figure 6. Output Voltage vs. Input Voltage

Figure 9. Ground Current vs. Input Voltage, Single Output Loaded

Rev. F | Page 7 of 20

ADP220/ADP221 Data Sheet

160

140

120

100

80

60

40

20

GROUND CURRENT ( µ A)

JUNCTION T E M P E RATURE (°C)

0

–40 –5 25 85 125

I

LOAD

= 10µA

I

LOAD

= 100µA

I

LOAD

= 1mA

I

LOAD

= 10mA

I

LOAD

= 100mA

I

LOAD

= 200mA

07572-010

140

120

100

80

60

40

20

GROUND CURRENT ( µ A)

0

LOAD CURRRENT ( mA)

0.01 0.1 1 10 100 1k

V

OUT

= 2.8V

V

IN

= 3.3V

T

A

= 25°C

07572-011

3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
INPUT VOLTAGE (V)

140

120

100

80

60

40

20

GROUND CURRENT ( µ A)

0

I

LOAD

= 10µA

I

LOAD

= 100µA

I

LOAD

= 1mA

I

LOAD

= 10mA

I

LOAD

= 100mA

I

LOAD

= 200mA

07572-012

–50 –25 1251007550250

TEMPERATURE (°C)

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

SHUTDOWN CURRE NT (µA)

0

3.3V

3.6V

4.0V

4.3V

4.9V

5.5V

07572-013

1 10 100 1k

LOAD CURRENT ( mA)

250

200

150

100

50

DROPOUT VOLTAGE (mV)

0

2.5V

2.8V

3.3V

07572-014

2.6 2.7 2.8 2.9 3.0 3.1
INPUT VOLTAGE (V)

2.90

2.85

2.80

2.75

2.70

2.65

2.60

2.55

2.50

2.45

OUTPUT VOLTAGE (V)

2.40

I

LOAD

= 1mA

I

LOAD

= 5mA

I

LOAD

= 10mA

I

LOAD

= 50mA

I

LOAD

= 100mA

I

LOAD

= 200mA

07572-015

Figure 10. Ground Current vs. Junction Temperature, Both Outputs Loaded

Figure 11. Ground Current vs. Load Current, Both Outputs Loaded

Figure 13. Shutdown Current vs. Temperature at Various Input Voltages

Figure 14. Dropout Voltage vs. Load Current and Output Voltage

Figure 12. Ground Current vs. Input Voltage, Both Outputs Loaded

Figure 15. Output Voltage vs. Input Voltage (In Dropout)

Rev. F | Page 8 of 20

Data Sheet ADP220/ADP221

2.6 2.7 2.8 2.9 3.0 3.1
INPUT VOLTAGE (V)

180

120

140

160

100

80

60

40

20

GROUND CURRENT ( µ A)

0

I

LOAD

= 1mA

I

LOAD

= 5mA

I

LOAD

= 10mA

I

LOAD

= 50mA

I

LOAD

= 100mA

I

LOAD

= 200mA

07572-016

10 100 1k 10k 100k 1M 10M

FREQUENCY ( Hz )

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

PSRR (dB)

–110

V

RIPPLE

= 50mV

V

IN

= 3.8V

V

OUT

= 2.8V

C

OUT

= 2.2µF

200mA
100mA
10mA
1mA
100µA

07572-017

10 100 1k 10k 100k 1M 10M

FREQUENCY ( Hz )

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

PSRR (dB)

–100

V

RIPPLE

= 50mV

V

IN

= 4.3V

V

OUT

= 3.3V

C

OUT

= 1µF

200mA
100mA
10mA
1mA
100µA

07572-018

10 100 1k 10k 100k 1M 10M

FREQUENCY ( Hz )

–10

–20

–30

–40

–50

–60

–70

–80

–90

PSRR (dB)

–110

–100

V

RIPPLE

= 50mV
VIN = 2.5V
V

OUT

= 0.8V

C

OUT

= 1µF

200mA
100mA
10mA
1mA
100µA

07572-019

10 100 1k 10k 100k 1M 10M

FREQUENCY ( Hz )

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

PSRR (dB)

–100

3.3V/200mA 0.8V/200mA

1.8V/200mA

3.3V/100µA 0.8V/100µA

1.8V/100µA

07572-020

10 100 1k 10k 100k

FREQUENCY ( Hz )

10

0.1

1

OUTPUT NOISE SPECTRUM (µV/ Hz)

0.01

3.3V µV/ Hz

2.8V µV/ Hz

0.8V µV/ Hz

07572-021

Figure 16. Ground Current vs. Input Voltage (In Dropout)

Figure 17. Power Supply Rejection Ratio vs. Frequency, 2.8 V

Figure 19. Power Supply Rejection Ratio vs. Frequency, 0.8 V

Figure 20. Power Supply Rejection Ratio vs. Frequency, at Various Output

Voltages and Load Currents

Figure 18. Power Supply Rejection Ratio vs. Frequency, 3.3 V

Figure 21. Output Noise Spectrum, VIN = 5 V, I

LOAD

= 10 mA

Rev. F | Page 9 of 20

ADP220/ADP221 Data Sheet

0.001 0.01 0.1 1 10 100 1k
LOAD CURRENT ( mA)

60

50

40

30

20

10

NOISE (µ V rms)

0

3.3V

2.8V

1.8V

0.8V

07572-022

CH1 200mA Ω

B

W

CH2 50.0mV

B

W

CH3 10.0mV

B

W

M40.0μs A CH1 132mA

T 10.00%

1

2

3

I

LOAD1

V

OUT1

V

OUT2

I

LOAD1

= 1mA TO 200mA, I

LOAD2

= 1mA

T

07572-023

T

CH1 200mA Ω

B

W

CH2 50.0mV

B

W

CH3 10.0mV

B

W

M40.0μs A CH1 132mA

T 10.00%

1

2

3

I

LOAD1

V

OUT1

V

OUT2

I

LOAD1

= 1mA TO 200mA, I

LOAD2

= 100mA

07572-024

CH1 1.00V

B

W

CH2 5.00mV

B

W

CH3 5.00mV

B

W

M20.0μs A CH1 4.46V

T 13.60%

2

1

3

V

IN

V

OUT1

V

OUT2

VIN = 4V TO 5V, I

LOAD1

= 200mA, I

LOAD2

= 100mA

T

07572-025

CH1 1.00V

B

W

CH2 5.00mV

B

W

CH3 5.00mV

B

W

M20.0μs A CH1 4.46V

T 10.00%

2

1

3

V

IN

V

OUT1

V

OUT2

VIN = 4V TO 5V, I

LOAD1

= 200mA, I

LOAD2

= 1mA

T

07572-026

CH1 5.00V

B

W

CH2 2.00V

B

W

CH3 2.00V

B

W

M40.0μs A CH1 2.10V

T 9.80%

2

1

3

T

07572-027

Figure 22. Output Noise vs. Load Current and Output Voltage, VIN = 5 V

Figure 23. Load Transient Response,

= 1 mA to 200 mA, I

I

LOAD1

CH1 = I

LOAD1

, CH2 = V

OUT1

= 1 mA

LOAD2

, CH3 = V

OUT2

Figure 25. Line Transient Response,

= 4 V to 5 V, I

V

IN

CH1 = V

LOAD1

, CH2 = V

IN

= 200 mA, I

OUT1

Figure 26. Line Transient Response

= 4 V to 5 V, I

V

IN

CH1 = V

LOAD1

, CH2 = V

IN

= 200 mA, I

OUT1

LOAD2

, CH3 = V

LOAD2

, CH3 = V

= 100 mA

OUT2

= 1 mA

OUT2

Figure 24. Load Transient Response,

= 1 mA to 200 mA, I

I

LOAD1

CH1 = I

, CH2 = V

LOAD1

OUT1

LOAD2

= 100 mA,

, CH3 = V

Figure 27. Shutdown Response, ADP221

OUT2

Rev. F | Page 10 of 20

Data Sheet ADP220/ADP221

THERMAL

SHUTDOWN

EN1

EN2

GND

CURRENT

LIMIT

CURRENT

LIMIT

60Ω

60Ω

REFERENCE

ADP221

ONLY

CONTROL

LOGIC

AND

ENABLE

VIN VOUT1

VOUT2

ADP220

07572-028

THEORY OF OPERATION

The ADP220/ADP221 are low quiescent current, low dropout
linear regulators that operate from 2.5 V to 5.5 V and provide
up to 200 mA of current from each output. Drawing a low 120 μA
quiescent current (typical) at full load makes the ADP220/
ADP221 ideal for battery-operated portable equipment. Shut­down current consumption is typically 100 nA.

Optimized for use with small 1 µF ceramic capacitors, the
ADP220/ADP221 provide excellent transient performance.

Internally, the ADP220/ADP221 consist of a reference, two error
amplifiers, two feedback voltage dividers, and two PMOS pass
transistors. Output current is delivered via the PMOS pass device,
which is controlled by the error amplifier. The error amplifier
compares the reference voltage with the feedback voltage from
the output and amplifies the difference. If the feedback voltage
is lower than the reference voltage, the gate of the PMOS device
is pulled lower, allowing more current to flow and increasing
the output voltage. If the feedback voltage is higher than the
reference voltage, the gate of the PMOS device is pulled higher,
allowing less current to flow and decreasing the output voltage.

The ADP221 also includes an active pull-down circuit to rapidly
discharge the output load capacitance when each output is
disabled.

The ADP220/ADP221 are available in multiple output voltage
options ranging from 0.8 V to 3.3 V. The ADP220/ADP221 use
the EN1/EN2 pins to enable and disable the VOUT1/VOUT2
pins under normal operating conditions. When EN1/EN2 are high,
VOUT1/VOUT2 turn on; when EN1/EN2 are l o w, VOUT1/
VOUT2 turn off. For automatic startup, EN1/EN2 can be tied
to VIN.

Figure 28. Internal Block Diagram

Rev. F | Page 11 of 20

ADP220/ADP221 Data Sheet

2

1

3

CH1 200mA Ω

B

W

CH2 50.0mV

B

W

CH3 10.0mV

B

W

M200ns A CH1 132mA

T 26.60%

T

I

LOAD1

= 1mA TO 200mA, I

LOAD2

= 1mA

I

LOAD1

V

OUT1

V

OUT2,COUT

= 1µF

07572-029

2

1

3

CH1 200mA Ω

B

W

CH2 50.0mV

B

W

CH3 10.0mV

B

W

M1.00µs A CH1 132mA

T 11.40%

T

I

LOAD1

= 1mA TO 200mA, I

LOAD2

= 1mA

I

LOAD1

V

OUT1

V

OUT2,COUT

= 4.7µF

07572-030

1.2

1.0

0.8

0.6

0.4

0.2

0

0 2 4 6 8 10

VOLTAGE (V)

CAPACITANCE (µ F)

07572-031

APPLICATIONS INFORMATION

CAPACITOR SELECTION

Output Capacitor

The ADP220/ADP221 are designed for operation with small,
space-saving ceramic capacitors, but the parts function with
most commonly used capacitors as long as care is taken with
regards to the effective series resistance (ESR) value. The ESR
of the output capacitor affects stability of the LDO control loop.
A minimum of 0.70 µF capacitance with an ESR of 1 Ω or less
is recommended to ensure stability of the ADP220/ADP221.
Transient response to changes in load current is also affected by
output capacitance. Using a larger value of output capacitance
improves the transient response of the ADP220/ADP221 to large
changes in the load current. Figure 29 and Figure 30 show the
transient responses for output capacitance values of 1 µF and

4.7 µF, respectively.

Input Bypass Capacitor

Connecting a 1 µF capacitor from VIN to GND reduces the
circuit sensitivity to the PCB layout, especially when long input
traces or high source impedance are encountered. If an output
capacitance greater than 1 µF is required, the input capacitor
should be increased to match it.

Input and Output Capacitor Properties

Any good quality ceramic capacitor can be used with the ADP220/
ADP221, as long as the capacitor meets the minimum capacit­ance and maximum ESR requirements. Ceramic capacitors are
manufactured with a variety of dielectrics, each with a different
behavior over temperature and applied voltage. Capacitors must
have an adequate dielectric to ensure the minimum capacitance
over the necessary temperature range and dc bias conditions.
X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are
recommended. Y5V and Z5U dielectrics are not recommended,
due to their poor temperature and dc bias characteristics.

Figure 31 depicts the capacitance vs. voltage bias characteristic
of an 0402 1 µF, 10 V, X5R capacitor. The voltage stability of a
capacitor is strongly influenced by the capacitor size and voltage
rating. In general, a capacitor in a larger package or higher voltage
rating exhibits better stability. The temperature variation of the
X5R dielectric is about ±15% over the −40°C to +85°C tempera­ture range and is not a function of the package or voltage rating.

Figure 29. Output Transient Response

I

= 1 mA to 200 mA, I

LOAD1

CH1 = I

LOAD1

, CH2 = V

OUT1

, CH3 = V

Figure 30. Output Transient Response

I

= 1 mA to 200 mA, I

LOAD1

CH1 = I

, CH2 = V

LOAD1

OUT1

, CH3 = V

LOAD2

LOAD2

OUT2

= 1 mA

OUT2

= 1 mA

, C

, C

OUT

OUT

= 1 µF

Figure 31. Capacitance vs. Voltage Bias Characteristic

= 4.7 µF

Rev. F | Page 12 of 20

Data Sheet ADP220/ADP221

1

CH1 500mV

B

W

CH2 500mV

B

W

M10.0ms A CH2 1.76V

T 27.40%

T

07572-032

ENx

V

OUTx

2.5 3.0 3.5 4.0 4.5 5.0 5.5
INPUT VOLTAGE (V)

1.00

0.95

0.90

0.85

0.80

0.75

0.70

0.65

ENx PINS THRE S HOLD (V)

0.60

EN INACTIV E

EN ACTIVE

07572-033

1

CH1 5.00V

B

W

CH2 2.00V

B

W

M40.0µs A CH1 2.10V

T 9.80%

T

CH3 2.00V

B

W

2

3

07572-034

Equation 1 can be used to determine the worst-case capacitance
accounting for capacitor variation over temperature, compo­nent tolerance, and voltage.

C

= C

EFF

× (1 − TEMPCO) × (1 − TOL) (1)

BIAS

where:
C

is the effective capacitance at the operating voltage.

BIAS

TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.

In this example, TEMPCO over −40°C to +85°C is assumed to
be 15% for an X5R dielectric. TOL is assumed to be 10%, and
C

is 0.94 μF at 1.8 V from the graph in Figure 31.

BIAS

Substituting these values into Equation 1 yields

= 0.94 μF × (1 − 0.15) × (1 − 0.1) = 0.719 μF

C

EFF

Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over
temperature and tolerance at the chosen output voltage.

To guarantee the performance of the ADP220/ADP221, it is
imperative that the effects of dc bias, temperature, and toler­ances on the behavior of the capacitors be evaluated for each
application.

UNDERVOLTAGE LOCKOUT

The ADP220/ADP221 have an internal undervoltage lockout
circuit that disables all inputs and the output when the input
voltage is less than approximately 2.2 V. This ensures that the
inputs of the ADP220/ADP221 and the output behave in a
predictable manner during power-up.

ENABLE FEATURE

The ADP220/ADP221 use the ENx pins to enable and disable
the VOUTx pins under normal operating conditions. Figure 32
shows a rising voltage on ENx crossing the active threshold,
then V
inactive threshold, V

turns on. When a falling voltage on ENx crosses the

OUTx

turns off.

OUTx

As shown in Figure 32, the ENx pins have built-in hysteresis.
This prevents on/off oscillations that can occur due to noise on
the ENx pins as it passes through the threshold points.

The active/inactive thresholds of the ENx pins are derived from
the VIN voltage. Therefore, these thresholds vary with changing
input voltage. Figure 33 shows typical ENx active/inactive thresh­olds when the input voltage varies from 2.5 V to 5.5 V.

Figure 33. Typical ENx Pins Thresholds vs. Input Voltage

The ADP220/ADP221 utilize an internal soft start to limit the
inrush current when the output is enabled. The start-up time
for the 2.8 V option is approximately 220 µs from the time the
ENx active threshold is crossed to when the output reaches 90%
of its final value. The start-up time is somewhat dependent on
the output voltage setting and increases slightly as the output
voltage increases.

Figure 32. Typical ENx Pin Operation

Figure 34. Typical Start-Up Time

Rev. F | Page 13 of 20

ADP220/ADP221 Data Sheet

Copper Size (mm2)

ADP220/ADP221 (°C/W)

50

119

CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION

The ADP220/ADP221 are protected against damage due to
excessive power dissipation by current and thermal overload
protection circuits. The ADP220/ADP221 are designed to
current limit when the output load reaches 300 mA (typical).
When the output load exceeds 300 mA, the output voltage is
reduced to maintain a constant current limit.

Thermal overload protection is built-in, which limits the
junction temperature to a maximum of 155°C (typical). Under
extreme conditions (that is, high ambient temperature and
power dissipation) when the junction temperature starts to
rise above 155°C, the output is turned off, reducing the output
current to zero. When the junction temperature drops below
140°C, the output is turned on again and the output current
is restored to its nominal value.

Consider the case where a hard short from VOUTx to GND
occurs. At first, the ADP220/ADP221 current limit, so that only
300 mA is conducted into the short. If self-heating of the junction
is great enough to cause its temperature to rise above 155°C,
thermal shutdown activates, turning off the output and reducing
the output current to zero. As the junction temperature cools
and drops below 140°C, the output turns on and conducts 300 mA
into the short, again causing the junction temperature to rise
above 155°C. This thermal oscillation between 140°C and
155°C causes a current oscillation between 0 mA and 300 mA
that continues as long as the short remains at the output.

Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For reliable
operation, device power dissipation must be externally limited
so that junction temperatures do not exceed 125°C.

THERMAL CONSIDERATIONS

In most applications, the ADP220/ADP221 do not dissipate
much heat due to high efficiency. However, in applications with
a high ambient temperature and high supply voltage to output
voltage differential, the heat dissipated in the package is large
enough that it can cause the junction temperature of the die
to exceed the maximum junction temperature of 125°C.

When the junction temperature exceeds 155°C, the converter
enters thermal shutdown. It recovers only after the junction
temperature has decreased below 140°C to prevent any permanent
damage. Therefore, thermal analysis for the chosen application
is very important to guarantee reliable performance over all
conditions. The junction temperature of the die is the sum of
the ambient temperature of the environment and the tempera­ture rise of the package due to the power dissipation, as shown
in Equation 2.

To guarantee reliable operation, the junction temperature of
the ADP220/ADP221 must not exceed 125°C. To ensure that
the junction temperature stays below this maximum value, the
user needs to be aware of the parameters that contribute to junction
temperature changes. These parameters include ambient tem­perature, power dissipation in the power device, and thermal
resistances between the junction and ambient air (θ

). The θJA

JA

number is dependent on the package assembly compounds used
and the amount of copper to which the GND pins of the package
are soldered on the PCB. Tabl e 6 shows typical θ

values for the

JA

ADP220/ADP221 for various PCB copper sizes.

Table 6. Typical θ

Values

JA

01 200

100 118
300 115
500 113

1

Device soldered to minimum size pin traces.

The junction temperature of the ADP220/ADP221 can be
calculated from the following equation:

T

= TA + (PD × θJA) (2)

J

where:

T

is the ambient temperature.

A

P

is the power dissipation in the die, given by

D

= Σ[(VIN − V

P

D

OUT

) × I

] + Σ(VIN × I

LOAD

) (3)

GND

where:

I

is the load current.

LOAD

I

is the ground current.

GND

V

and V

IN

are input and output voltages, respectively.

OUT

Power dissipation due to ground current is quite small and
can be ignored. Therefore, the junction temperature equation
simplifies to

T

= TA + {Σ[(VIN − V

J

OUT

) × I

] × θJA} (4)

LOAD

As shown in Equation 4, for a given ambient temperature,
input-to-output voltage differential, and continuous load
current, there exists a minimum copper size requirement
for the PCB to ensure the junction temperature does not rise
above 125°C. Figure 35 to Figure 39 show junction temperature
calculations for different ambient temperatures, total power
dissipation, and areas of PCB copper.

In cases where the board temperature is known, the thermal
characterization parameter, Ψ
junction temperature rise. T

, can be used to estimate the

JB

is calculated from TB and PD using

J

the formula

T

= TB + (PD × ΨJB) (5)

J

The typical Ψ

value for the 6-ball WLCSP is 43.8° C/ W.

JB

Rev. F | Page 14 of 20

Data Sheet ADP220/ADP221

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

TOTAL POWER DISSIPATION (W)

145

35

45

55

65

75

85

95

105

115

125

135

JUNCTION T E M P E RATURE (°C)

25

500mm

2

50mm

2

0mm

2

T

JMAX

07572-035

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

TOTAL POWER DISSIPATION (W)

140

60

70

80

90

100

110

120

130

JUNCTION T E M P E RATURE (°C)

50

500mm

2

50mm

2

0mm

2

T

JMAX

07572-036

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

TOTAL POWER DISSIPATION (W)

145

135

125

115

105

95

85

75

JUNCTION T E M P E RATURE (°C)

65

500mm

2

50mm

2

0mm

2

T

JMAX

07572-037

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

TOTAL POWER DISSIPATION (W)

135

95

105

115

125

JUNCTION T E M P E RATURE (°C)

85

500mm

2

50mm

2

0mm

2

T

JMAX

07572-038

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.22.0 2.4

TOTAL POWER DISSIPATION (W)

140

20

60

100

40

80

120

JUNCTION T E M P E RATURE (°C)

0

TB = 25°C
T

B

= 50°C

T

B

= 65°C

T

B

= 85°C

T

JMAX

07572-039

Figure 35. Junction Temperature vs. Total Power Dissipation, TA = 25°C

Figure 36. Junction Temperature vs. Total Power Dissipation, TA = 50°C

Figure 38. Junction Temperature vs. Total Power Dissipation, TA = 85°C

Figure 39. Junction Temperature vs. Total Power Dissipation and

Board Temperature

Figure 37. Junction Temperature vs. Total Power Dissipation, TA = 65°C

Rev. F | Page 15 of 20

ADP220/ADP221 Data Sheet

07572-040

07572-041

PRINTED CIRCUIT BOARD (PCB) LAYOUT CONSIDERATIONS

Heat dissipation from the package can be improved by
increasing the amount of copper attached to the pins of the
ADP220/ADP221. However, as shown in Tabl e 6, a point of
diminishing returns eventually is reached, beyond which an
increase in the copper size does not yield significant heat
dissipation benefits.

Place the input capacitor as close as possible to the VIN and
GND pins. Place the output capacitors as close as possible to
the VOUT1, VOUT2, and GND pins. Use 0402 or 0603
size capacitors and resistors to achieve the smallest possible
footprint solution on boards where area is limited.

Figure 40. Example of PCB Layout, Top Side

Figure 41. Example of PCB Layout, Bottom Side

Rev. F | Page 16 of 20

Data Sheet ADP220/ADP221

0.50 BSC

1.00
BSC

1.50

1.45

1.40

1.00

0.95

0.90

SEATING
PLANE

0.675

0.595

0.515

0.075
COPLANARITY

0.380

0.355

0.330

0.345

0.295

0.245

0.270

0.240

0.210

A1 BALL
CORNER

0.50
BSC

A

12

B

C

TOP VIEW

(BALL SIDE DOWN)

BOTTOM VIEW

(BALL SIDE UP)

081607-B

ADP220ACBZ-2818R7

−40°C to +125°C

2.8/1.8

6-Ball Wafer Level Chip Scale Package [WLCSP]

CB-6-2

LEL

OUTLINE DIMENSIONS

Figure 42. 6-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-6-2)

Dimensions show in millimeters

ORDERING GUIDE

Model1

Range

ADP220ACBZ-1118R7 −40°C to +125°C 1.1/1.8 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-2 LFY
ADP220ACBZ-1812R7 −40°C to +125°C 1.8/1.2 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-2 LEK
ADP220ACBZ-1827R7 −40°C to +125°C 1.8/2.7 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-2 LEH
ADP220ACBZ-2623R7 −40°C to +125°C 2.6/2.3 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-2 LGD
ADP220ACBZ-26235R7 −40°C to +125°C 2.6/2.35 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-2 L9L
ADP220ACBZ-2812R7 −40°C to +125°C 2.8/1.2 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-2 L8W

ADP220ACBZ-2827R7 −40°C to +125°C 2.8/2.7 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-2 L8X
ADP220ACBZ-2828R7 −40°C to +125°C 2.8/2.8 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-2 L8Y
ADP220ACBZ275275R7 −40°C to +125°C 2.75/2.75 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-2 L8Z
ADP220ACBZ-3033R7 −40°C to +125°C 3.0/3.3 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-2 LH4

Temperature

ADP220ACBZ-1212R7
ADP220ACBZ-2525R7

ADP221ACBZ-2828-R7
ADP221ACBZ-1818-R7

−40°C to +125°C 1.2/1.2 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-2

−40°C to +125°C 2.5/2.5 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-2

−40°C to +125°C 2.8/2.8 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-2 L90

−40°C to +125°C 1.8/1.8 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-2 LJ0

ADP220-2828-EVALZ −40°C to +125°C 2.8/2.8 2.8 V/2.8 V Evaluation Board
ADP221-2828-EVALZ −40°C to +125°C 2.8/2.8 2.8 V/2.8 V with Output Discharge Evaluation Board

1

Z = RoHS Compliant Part.

2

For additional voltage options, contact a local Analog Devices sales or distribution representative.

V

OUT1/VOUT2

Output Voltage (V)

2

Package Description

Package
Option Branding

LLT
LLU

Rev. F | Page 17 of 20

ADP220/ADP221 Data Sheet

NOTES

Rev. F | Page 18 of 20

Data Sheet ADP220/ADP221

NOTES

Rev. F | Page 19 of 20

ADP220/ADP221 Data Sheet

©2008–2012 Analog Devices, Inc. All rights reserved. Trademarks and

NOTES

registered trademarks are the property of their respective owners.

D07572-0-/2(F)

Rev. F | Page 20 of 20