Page 1
Compact, 800 mA, 3 MHz,
A
FEATURES
Input voltage: 2.3 V to 5.5 V
Peak efficiency: 95%
3 MHz fixed frequency operation
Typical quiescent current: 24 μA
Very small solution size
6-lead, 1 mm × 1.5 mm WLCSP package
Fast load and line transient response
100% duty cycle low dropout mode
Internal synchronous rectifier, compensation, and soft start
Current overload and thermal shutdown protections
Ultralow shutdown current: 0.2 μA (typical)
Forced PWM and automatic PWM/PSM modes
APPLICATIONS
PDAs and palmtop computers
Wireless handsets
Digital audio, portable media players
Digital cameras, GPS navigation units
Step-Down DC-to-DC Converter
ADP2138/ADP2139
GENERAL DESCRIPTION
The ADP2138 and ADP2139 are high efficiency, low quiescent
current, synchronous step-down dc-to-dc converters. The
ADP2139 has the additional feature of an internal discharge
switch. The total solution requires only three tiny external
components. When the MODE pin is set high, the buck
regulator operates in forced PWM mode, which provides low
peak-to-peak ripple for power supply noise sensitive loads at
the expense of light load efficiency. When the MODE pin is set
low, the buck regulator automatically switches operating modes,
depending on the load current level. At higher output loads, the
buck regulator operates in PWM mode. When the load current
falls below a predefined threshold, the regulator operates in power
save mode (PSM), improving light load efficiency.
The ADP2138/ADP2139 operate on input voltages of 2.3 V to
5.5 V, which allows for single lithium or lithium polymer cell,
multiple alkaline or NiMH cell, PCMCIA, USB, and other
standard power sources. The maximum load current of 800 mA
is achievable across the input voltage range.
The ADP2138/ADP2139 are available in fixed output voltages of
3.3 V, 3.0 V, 2.8 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, 1.0 V, and 0.8 V. All
versions include an internal power switch and synchronous rectifier for minimal external part count and high efficiency. The
ADP2138/ADP2139 have internal soft start and they are internally
compensated. During logic controlled shutdown, the input is
disconnected from the output and the ADP2138/ADP2139
draw 0.2 A (typical) from the input source.
Other key features include undervoltage lockout to prevent deep
battery discharge, and soft start to prevent input current overshoot at startup. The ADP2138/ADP2139 are available in a 6-ball
wafer level chip scale package (WLCSP).
TYPICAL APPLICATIONS CIRCUIT
2.3V TO 5. 5V
4.7µF 4.7µF
OFF
FORCE
PWM
UTO
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
ON
VIN SW
ADP2138/
ADP2139
EN
MODE
VOUT
GND
Figure 1.
1.0µH
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved.
V
OUT
9496-001
Page 2
ADP2138/ADP2139
TABLE OF CONTENTS
Features.............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Typical Applications Circuit............................................................ 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Input and Output Capacitor, Recommended Specifications.. 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Typical Performance Characteristics ............................................. 6
Theory of Operation ...................................................................... 11
Control Scheme .......................................................................... 11
PWM Mode................................................................................. 11
Power Save Mode........................................................................ 11
Enable/Shutdown....................................................................... 11
Short-Circuit Protection............................................................ 12
Undervoltage Lockout............................................................... 12
Thermal Protection.................................................................... 12
Soft Start ...................................................................................... 12
Current Limit.............................................................................. 12
100% Duty Operation................................................................ 12
Discharge Switch ........................................................................ 12
Applications Information.............................................................. 13
External Component Selection ................................................ 13
Thermal Considerations............................................................ 14
PCB Layout Guidelines.............................................................. 14
Evaluation Board............................................................................ 15
Evaluation Board Layout........................................................... 15
Outline Dimensions....................................................................... 16
Ordering Guide .......................................................................... 16
REVISION HISTORY
4/11—Rev. 0 to Rev. A
Change to Features Section............................................................. 1
Added Figure 32, Renumbered Figures Sequentially ................ 10
Changes to Ordering Guide.......................................................... 16
1/11—Revision 0: Initial Version
Rev. A | Page 2 of 16
Page 3
ADP2138/ADP2139
SPECIFICATIONS
VIN = 3.6 V, V
unless otherwise noted. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Input Voltage Range 2.3 5.5 V
Undervoltage Lockout Threshold VIN rising 2.3 V
V
OUTPUT CHARACTERISTICS
Output Voltage Accuracy PWM mode −2 +2 %
Line Regulation VIN = 2.3 V to 5.5 V, PWM mode 0.25 %/V
Load Regulation I
PWM TO POWER SAVE MODE CURRENT THRESHOLD 100 mA
INPUT CURRENT CHARACTERISTICS
DC Operating Current I
Shutdown Current EN = 0 V, TA = TJ = −40°C to +85°C 0.2 1.0 A
SW CHARACTERISTICS
SW On Resistance PFET 155 240 mΩ
NFET 115 200 mΩ
Current Limit PFET switch peak current limit 1100 1500 1650 mA
Discharge Switch (ADP2139) 100 Ω
ENABLE AND MODE CHARACTERISTICS
Input High Threshold 1.2 V
Input Low Threshold 0.4 V
Input Leakage Current EN/MODE = 0 V (min), 3.6 V (max ) −1 0 +1 A
OSCILLATOR FREQUENCY 2.6 3.0 3.4 MHz
START-UP TIME 250 s
THERMAL CHARACTERISTICS
Thermal Shutdown Threshold 150 °C
Thermal Shutdown Hysteresis 20 °C
= 0.8 V − 3.3 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications,
OUT
falling 2.00 2.15 2.25 V
IN
= 0 mA − 800 mA −0.95 %/A
LOAD
= 0 mA, device not switching 23 30 A
LOAD
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
TA = −40°C to +125°C, unless otherwise specified. All limits at temperature extremes are guaranteed via correlation using standard
statistical quality control (SQC).
Table 2.
Parameter Symbol Min Typ Max Unit
MINIMUM INPUT AND OUTPUT CAPACITANCE C
CAPACITOR ESR R
Rev. A | Page 3 of 16
4.7 µF
MIN
0.001 1 Ω
ESR
Page 4
ADP2138/ADP2139
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
VIN, EN, MODE −0.4 V to +6.5 V
VOUT, SW to GND −1.0 V to (VIN + 0.2 V)
Temperature Range
Operating Ambient −40°C to +85°C
Operating Junction −40°C to +125°C
Storage Temperature −65°C to +150°C
Lead Temperature Range −65°C to +150°C
Soldering (10 sec) 300°C
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
ESD Model
Human Body ±1500 V
Charged Device ±500 V
Machine ±100 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination.
ADP2138/ADP2139 can be damaged when the junction temperature limits are exceeded. Monitoring ambient temperature does
not guarantee that the junction temperature (T
specified temperature limits. In applications with high power
dissipation and poor thermal resistance, the maximum ambient
temperature may need to be derated. In applications with moderate power dissipation and low printed circuit board (PCB)
thermal resistance, the maximum ambient temperature can
exceed the maximum limit for as long as the junction temperature
is within specification limits. The junction temperature (T
the device is dependent on the ambient temperature (T
power dissipation of the device (P
thermal resistance of the package (θ
temperature (T
(T
) and power dissipation (PD) using the formula
A
= TA + (PD × θJA)
T
J
) is calculated from the ambient temperature
J
), and the junction-to-ambient
D
). Maximum junction
JA
) is within the
J
) of
J
), the
A
Junction-to-ambient thermal resistance (θ
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on
the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θ
PCB material, layout, and environmental conditions. The specified
values of θ
to JEDEC JESD 51-9 for detailed information pertaining to board
construction. For additional information, see AN-617 Application Note, MicroCSP
Ψ
is the junction-to-board thermal characterization parameter
JB
measured in units of °C/W. Ψ
and calculation using a 4-layer board. The JESD51-12, Guidelines
for Reporting and Using Package Thermal Information, states that
thermal characterization parameters are not the same as thermal
resistances. Ψ
multiple thermal paths rather than through a single path, which
is the procedure for measuring thermal resistance, θ
fore, Ψ
package as well as radiation from the package; factors that make
Ψ
more useful in real-world applications than θJB. Maximum
JB
junction temperature (T
(T
) and power dissipation (PD) using the formula
B
T
J
Refer to JEDEC JESD51-8 and JESD51-12 for more detailed
information about Ψ
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type θJA Ψ
6-Ball WLCSP 170 80 °C/W
ESD CAUTION
) of the package is
JA
may vary, depending on
JA
are based on a 4-layer, 4 in. × 3 in., circuit board. Refer
JA
TM
Wafer Le v el C h ip S c ale P a ckag e.
of the package is based on modeling
JB
measures the component power flowing through
JB
. There-
JB
thermal paths include convection from the top of the
JB
) is calculated from the board temperature
J
= TB + (PD × ΨJB)
.
JB
Unit
JB
Rev. A | Page 4 of 16
Page 5
ADP2138/ADP2139
(
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VIN EN
4
1
SW
MODE
5
2
GND VOUT
6
3
TOP VIEW
BALL SIDE DOW N)
Not to Scal e
Figure 2. Pin Configuration (Top View)
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 VIN
Power Source Input. VIN is the source of the PFET high-side switch. Bypass VIN to GND with a 4.7 µF or greater
capacitor as close to the ADP2138/ADP2139 as possible.
2 SW
Switch Node Output. SW is the drain of the P-channel MOSFET switch and N-channel synchronous rectifier.
Connect the output LC filter between SW and the output voltage.
3 GND Ground. Connect the input and output capacitors to GND.
4 EN Buck Activation. To turn on the buck, set EN to high. To turn off the buck, set EN to low.
5 MODE
Mode Input. Drive the MODE pin high for the operating mode to force continuous PWM switching. Drive the MODE
pin low to allow automatic PWM/PSM operating mode.
6 VOUT Output Voltage Sensing Input.
09496-002
Rev. A | Page 5 of 16
Page 6
ADP2138/ADP2139
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 3.6 V, TA = 25°C, VEN = VIN, unless otherwise noted.
100
90
80
70
60
50
40
EFFICIENCY (%)
30
20
10
0
0.001 0.01 0.1 1
I
OUT
(A)
Figure 3. Efficiency vs. Load Current, Across Input Voltage,
= 1.8 V, PSM Mode
V
OUT
100
90
80
70
60
50
40
EFFICIENCY (%)
30
20
10
0
0.001 0.01 0.1 1
I
OUT
(A)
Figure 4. Efficiency vs. Load Current, Across Input Voltage,
= 1.8 V, PWM Mode
V
OUT
100
90
80
70
60
50
40
EFFICIENCY (%)
30
20
10
0
0.001 0.01 0.1 1
I
OUT
(A)
Figure 5. Efficiency vs. Load Current, Across Input Voltage,
= 0.8 V, PSM Mode
V
OUT
VIN = 2.3V
V
= 3.6V
IN
V
= 4.2V
IN
V
= 5.5V
IN
VIN = 2.3V
V
= 3.6V
IN
V
= 4.2V
IN
V
= 5.5V
IN
VIN = 2.3V
= 3.6V
V
IN
= 4.2V
V
IN
= 5.5V
V
IN
09496-003
09496-004
09496-005
100
90
80
70
60
50
40
EFFICIENCY (%)
30
20
10
0
0.001 0.01 0.1 1
(A)
I
OUT
VIN = 2.3V
V
= 3.6V
IN
V
= 4.2V
IN
V
= 5.5V
IN
Figure 6. Efficiency vs. Load Current, Across Input Voltage,
= 0.8 V, PWM Mode
V
OUT
100
90
80
70
60
50
40
EFFICIENCY (%)
30
20
10
0
0.001 0.01 0.1 1
(A)
I
OUT
VIN = 3.9V
V
= 4.2V
IN
V
= 5.5V
IN
Figure 7. Efficiency vs. Load Current, Across Input Voltage,
= 3.3 V, PSM Mode
V
OUT
100
90
80
70
60
50
40
EFFICIENCY (%)
30
20
10
0
0.001 0.01 0.1 1
I
OUT
(A)
VIN = 3.9V
= 4.2V
V
IN
= 5.5V
V
IN
Figure 8. Efficiency vs. Load Current, Across Input Voltage,
= 3.3 V, PWM Mode
V
OUT
09496-006
09496-007
09496-008
Rev. A | Page 6 of 16
Page 7
ADP2138/ADP2139
1.825
1.815
1.805
A (V)
OUT
V
1.795
1.785
1.775
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
I
OUT
(A)
Figure 9. Load Regulation Across Input Voltage, V
0.815
0.810
0.805
0.800
A (V)
OUT
0.795
V
0.790
0.785
0.780
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
I
OUT
(A)
Figure 10. Load Regulation Across Input Voltage, V
3.378
3.358
3.338
3.318
A (V)
3.298
OUT
V
3.278
3.258
3.238
3.218
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
I
OUT
(A)
Figure 11. Load Regulation Across Input Voltage, V
VIN = 2.3V
V
= 3.6V
IN
V
= 4.2V
IN
V
= 5.5V
IN
= 1.8 V, PWM Mode
OUT
VIN = 2.3V
V
= 3.6V
IN
V
= 4.2V
IN
V
= 5.5V
IN
= 0.8 V, PWM Mode
OUT
VIN = 3.9V
= 4.2V
V
IN
= 5.5V
V
IN
= 3.3 V, PWM Mode
OUT
09496-009
09496-010
09496-011
3.5
3.4
3.3
3.2
3.1
3.0
2.9
FREQUENCY (MHz)
2.8
2.7
2.6
2.5
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
(A)
I
OUT
–40°C
+25°C
+85°C
+125°C
Figure 12. Frequency vs. Output Current, Across Temperature,
= 1.8 V, PWM Mode
V
OUT
3.5
3.4
3.3
3.2
3.1
3.0
2.9
FREQUENCY (MHz )
2.8
2.7
2.6
2.5
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
(A)
I
OUT
VIN = 2.3V
= 3.6V
V
IN
= 4.2V
V
IN
= 5.5V
V
IN
Figure 13. Frequency vs. Output Current, Across Supply Voltage,
V
= 1.8 V
OUT
90
80
70
60
50
40
30
OUTPUT VOLTAGE (mV)
20
10
I
= 100µA
OUT
I
= 25mA
OUT
I
= 500mA
OUT
0
2.3 2.8 3.3 3. 8 4.3 4.8 5.3
INPUT VOLTAGE (V)
Figure 14. Output Voltage Ripple vs. Input Voltage,
Across Output Current, V
OUT
= 1.8 V
09496-012
09496-013
09496-034
Rev. A | Page 7 of 16
Page 8
ADP2138/ADP2139
350
300
250
200
(mΩ)
150
DSON
R
100
–40°C
+25°C
+125°C
T
4
4
1
1
SW
V
OUT
I
OUT
50
0
2.3 2.8 3.3 3. 8 4.3 4.8 5.3
Figure 15. R
DSON
INPUT VOLTAGE (V)
PFET vs. Input Voltage, Across Temperature
250
200
150
(mΩ)
DSON
100
R
50
0
2.3 2.8 3.3 3. 8 4.3 4.8 5.3
Figure 16. R
DSON
INPUT VOLTAGE (V)
NFET vs. Input Voltage, Across Temperature
T
SW
–40°C
+25°C
+125°C
2
CH1 100mV
09496-036
CH2 250mA Ω
CH4 5.00V
M 40.0µs A CH2 215mA
T
2
6
0
.
0
%
09496-015
Figure 18. Response to Load Transient, 50 mA to 200 mA,
= 1.8 V, Automatic Mode
V
OUT
T
4
4
1
1
2
CH1 100mV
09496-037
CH2 250mA Ω
CH4 5.00V
SW
V
OUT
I
OUT
M 40.0µs A CH2 215mA
T
2
6
.
0
0
%
09496-016
Figure 19. Response to Load Transient, 150 mA to 500 mA,
V
= 0.8 V, PWM Mode
OUT
T
SW
4
4
V
1
1
2
CH1 100mV
CH2 250mA Ω
CH4 5.00V
OUT
I
OUT
M 40.0µs A CH2 215mA
T
2
6
.
0
0
%
Figure 17. Response to Load Transient, 150 mA to 500 mA,
V
= 1.8 V, PWM Mode
OUT
09496-014
Rev. A | Page 8 of 16
4
4
V
OUT
1
1
I
OUT
2
CH1 100mV
CH2 100mA Ω M 40.0µs A CH2 134mA
CH4 5.00V
T
2
6
.
0
0
%
Figure 20. Response to Load Transient, 50 mA to 200 mA, V
Automatic Mode
= 0.8 V,
OUT
09496-017
Page 9
ADP2138/ADP2139
T
4
4
1
1
SW
V
IN
V
OUT
I
OUT
1
V
OUT
T
2
CH1 100mV
CH2 250mA Ω
CH4 5.00V
M 40.0µs A CH2 275mA
T
2
6
.
0
0
%
Figure 21. Response to Load Transient, 150 mA to 500 mA,
= 3.3 V, PWM Mode
V
OUT
4
4
1
1
2
CH1 100mV
T
CH2 100mA Ω
CH4 5.00V
SW
V
OUT
I
OUT
M 40.0µs A CH2 114mA
T
2
6
.
0
0
%
Figure 22. Response to Load Transient, 50 mA to 200 mA,
= 3.3 V, Automatic Mode
V
OUT
T
3
CH1 20.0mV
09496-018
CH3 1.00V
Figure 24. Response to Line Transient, V
= 4.0 V to 4.8 V, PWM Mode
V
IN
1
3
CH1 20.0mV
09496-019
CH3 1.00V
Figure 25. Response to Line Transient, V
V
= 4.0 V to 4.8 V, PWM Mode
IN
T
M 40.0µs A CH3 4.50V
T –84.0000µs
= 0.8 V,
OUT
T
V
IN
V
OUT
M 40.0µs A CH3 4.50V
T –84.0000µs
= 1.8 V,
OUT
SW
09496-021
09496-033
V
IN
V
1
3
CH1 20.0mV
CH3 1.00V
OUT
M 40.0µs A CH3 4.50V
T –84.0000µs
Figure 23. Response to Line Transient, V
PWM Mode
= 3.3 V, VIN = 4.0 V to 4.8 V,
OUT
09496-020
Rev. A | Page 9 of 16
4
2
1
1
1
3
CH1 2.00V Ω
CH3 5.00V
I
IN
V
OUT
E
N
CH2 500mA Ω M 40.0µs A CH3 2.50V
CH4 5.00V
Figure 26. Startup, V
= 1.8 V, I
OUT
T
1
0
.
4
0
%
OUT
= 10 mA
09496-022
Page 10
ADP2138/ADP2139
T
4
2
1
1
1
3
SW
I
IN
V
OUT
E
N
4
2
1
1
SW
I
L
V
OUT
T
CH1 1.00V Ω
CH3 5.00V
CH2 500mA Ω M 40.0µs A CH3 2.50V
CH4 5.00V
Figure 27. Startup, V
T
4
2
1
1
1
3
CH1 5.00V Ω
CH3 5.00V
CH2 500mA Ω M 40.0µs A CH3 2.50V
CH4 5.00V
Figure 28. Startup, V
SW
4
4
I
L
2
V
OUT
1
1
CH1 10.0mV Ω
CH2 500mA Ω
CH4 2.00V
Figure 29. Typical Waveform, V
T
1
0
.
4
0
%
= 0.8 V, I
OUT
= 10 mA
OUT
SW
I
IN
V
OUT
E
N
T
1
0
.
4
0
%
= 0.8 V, I
OUT
T
T
= 1.8 V, PSM Mode, I
OUT
= 10 mA
OUT
A CH1 3.80mVM 1.00µs
5
0
.
0
0
%
= 10 mA
OUT
CH1 10.0mVΩ CH2 500m A Ω
09496-023
Figure 30. Typical Waveform, V
CH4 2.00V
T
= 1.8 V, PWM Mode, I
OUT
A CH4 1.32VM 40.0µs
5
0
.
0
0
%
OUT
09496-026
= 200 mA
T
V
1
1
1
3
4
CH1 100mV
09496-024
CH3 2.00V
CH4 2.00V
Figure 31. Mode Transition from PSM to PWM to PSM, V
130
120
110
100
RIPPLE (mV)
OUT
V
09496-025
Figure 32. V
1.8V, VIN = 5.5V, AUTO
1.8V, VIN = 3.6V, AUTO
1.8V, VIN = 2.3V, AUTO
1.8V, VIN = 5.5V, PWM
1.8V, VIN = 3.6V, PWM
90
1.8V, VIN = 2.3V, PWM
80
70
60
50
40
30
20
10
0
0.001 0.01 0.1 1
Peak-to-Peak Ripple vs. Output Current, V
OUT
OUT
MODE
SW
M 40.0µs A CH3 1.36V
T
2
9
.
6
0
%
I
(A)
OUT
= 1.8 V
OUT
OUT
09496-035
= 1.8 V
09496-100
Rev. A | Page 10 of 16
Page 11
ADP2138/ADP2139
THEORY OF OPERATION
PWM
GM ERROR
AMP
COMP
SOFT START
VOUT
PSM
COMP
CONTROL
OSCILLATOR
UNDERVOLTAGE
LOCK OUT
MODE
ADP2138
Figure 33. ADP2138 Functional Block Diagram
The ADP2138 and ADP2139 are step-down dc-to-dc converters
that use a fixed frequency and high speed current-mode architecture. The high switching frequency and tiny 6-ball WLCSP
package allow for a small step-down dc-to-dc converter solution.
The ADP2138/ADP2139 operate with an input voltage of 2.3 V
to 5.5 V, and regulate an output voltage down to 0.8 V.
CONTROL SCHEME
The ADP2138/ADP2139 operate with a fixed frequency, currentmode PWM control architecture at medium to high loads for
high efficiency, but shift to a power save mode control scheme
at light loads to lower the regulation power losses. When operating
in PWM mode, the duty cycle of the integrated switches is adjusted
and regulates the output voltage. When operating in power save
mode at light loads, the output voltage is controlled in a hysteretic manner, with higher V
ripple. During part of this time,
OUT
the converter is able to stop switching and enters an idle mode,
which improves conversion efficiency. Each ADP2138/ADP2139
has a MODE pin, which determines the operation of the buck
regulator in either PWM mode (when the MODE pin is set
high) or power save mode (when the mode pin is set low).
PWM MODE
In PWM mode, the ADP2138/ADP2139 operate at a fixed
frequency of 3 MHz, set by an internal oscillator. At the start
of each oscillator cycle, the PFET switch is turned on, sending
a positive voltage across the inductor. Current in the inductor
increases until the current sense signal crosses the peak inductor
current threshold that turns off the PFET switch and turns on
the NFET synchronous rectifier. This sends a negative voltage
across the inductor, causing the inductor current to decrease.
The synchronous rectifier stays on for the rest of the cycle.
Rev. A | Page 11 of 16
PWM/
PSM
EN
VIN
I
LIMIT
LOW
CURRENT
DRIVER
AND
ANTISHOOT
THROUGH
THERMAL
SHUTDOWN
SW
GND
09496-027
The ADP2138/ADP2139 regulate the output voltage by adjusting
the peak inductor current threshold.
POWER SAVE MODE
The ADP2138/ADP2139 smoothly transition to the power save
mode of operation when the load current decreases below the
power save mode current threshold. When the ADP2138 and
ADP2139 enter power save mode, an offset is induced in the PWM
regulation level, which makes the output voltage rise. When the
output voltage reaches a level approximately 1.5% above the PWM
regulation level, PWM operation turns off. At this point, both
power switches are off, and the ADP2138/ ADP2139 enter into
idle mode. C
discharges until V
OUT
falls to the PWM regulation
OUT
voltage, at which point the device drives the inductor to cause
V
to rise again to the upper threshold. This process is repeated
OUT
for as long as the load current is below the power save mode
current threshold.
Power Save Mode Current Threshold
The power save mode current threshold is set to 100 mA. The
ADP2138/ADP2139 employ a scheme that enables this current
to remain accurately controlled, independent of V
and V
IN
levels. This scheme also ensures that there is very little hysteresis
between the power save mode current threshold for entry to and
exit from the power save mode. The power save mode current
threshold is optimized for excellent efficiency across all load
currents.
ENABLE/SHUTDOWN
The ADP2138/ADP2139 start operating with soft start when
the EN pin is toggled from logic low to logic high. Pulling the
EN pin low forces the device into shutdown mode, reducing the
shutdown current to 0.2 A (typical).
OUT
Page 12
ADP2138/ADP2139
SHORT-CIRCUIT PROTECTION
The ADP2138/ADP2139 include frequency fold back to prevent
output current runaway on a hard short. When the voltage at
the feedback pin falls below half the target output voltage, indicating the possibility of a hard short at the output, the switching
frequency is reduced to half the internal oscillator frequency.
The reduction in the switching frequency allows more time for
the inductor to discharge, preventing a runaway of output current.
UNDERVOLTAGE LOCKOUT
To protect against battery discharge, undervoltage lockout
(UVLO) circuitry is integrated on the ADP2138/ADP2139. If
the input voltage drops below the 2.15 V UVLO threshold, the
ADP2138/ADP2139 shut down, and both the power switch and
the synchronous rectifier turn off. When the voltage rises above
the UVLO threshold, the soft start period is initiated, and the
part is enabled.
THERMAL PROTECTION
In the event that the ADP2138/ADP2139 junction temperature
rises above 150°C, the thermal shutdown circuit turns off the
converter. Extreme junction temperatures can be the result of
high current operation, poor circuit board design, or high ambient
temperature. A 20°C hysteresis is included so that when thermal
shutdown occurs, the ADP2138/ADP2139 do not return to
operation until the on-chip temperature drops below 130°C.
When coming out of thermal shutdown, soft start is initiated.
SOFT START
The ADP2138/ADP2139 have an internal soft start function
that ramps the output voltage in a controlled manner upon
startup, thereby limiting the inrush current. This prevents
possible input voltage drops when a battery or a high impedance
power source is connected to the input of the converter.
After the EN pin is driven high, internal circuits begin to power
up. Start-up time in the ADP2138/ADP2139 is the measure of
when the output is in regulation after the EN pin is driven high.
Start-up time consists of the power-up time and the soft start time.
CURRENT LIMIT
Each ADP2138/ADP2139 has protection circuitry to limit the
amount of positive current flowing through the PFET switch
and the synchronous rectifier. The positive current limit on the
power switch limits the amount of current that can flow from
the input to the output. The negative current limit prevents the
inductor current from reversing direction and flowing out of
the load.
100% DUTY OPERATION
With a drop in VIN or with an increase in I
ADP2139 reach a limit where, even with the PFET switch on
100% of the time, V
drops below the desired output voltage.
OUT
At this limit, the ADP2138/ADP2139 smoothly transition to a
mode where the PFET switch stays on 100% of the time. When the
input conditions change again and the required duty cycle falls,
the ADP2138/ADP2139 immediately restart PWM regulation
without allowing overshoot on V
OUT
.
, the ADP2138/
LOAD
DISCHARGE SWITCH
The ADP2139 has an integrated switched resistor (of typically
100 ) to discharge the output capacitor when the EN pin goes
low or when the device enters undervoltage lockout or thermal
shutdown. The time to discharge is typically 200 s.
PWM
GM ERROR
AMP
SOFT START
VOUT
PSM
COMP
OSCILLATOR
UNDER-VOLTAGE
LOCK OUT
MODE
ADP2139
Figure 34. ADP2139 Functional Block Diagram
PWM/
PSM
CONTROL
EN
Rev. A | Page 12 of 16
COMP
I
LIMIT
LOW
CURRENT
DRIVER
AND
ANTISHOOT
THROUGH
THERMAL
SHUTDOWN
VIN
SW
GND
09496-028
Page 13
ADP2138/ADP2139
APPLICATIONS INFORMATION
EXTERNAL COMPONENT SELECTION
Trade-offs between performance parameters such as efficiency
and transient response can be made by varying the choice of
external components in the applications circuit, as shown in
Figure 1.
Inductor
The high switching frequency of the ADP2138/ADP2139 allows
for the selection of small chip inductors. For best performance,
use inductor values between 0.7 H and 3 H. Recommended
inductors are shown in Tab le 6.
The peak-to-peak inductor current ripple is calculated using
the following equation:
VVV
−×
××
I
RIPPLE
)(
OUT
LfV
2
I
RIPPLE
OUT
=
IN
IN
SW
where:
f
is the switching frequency.
SW
L is the inductor value.
The minimum dc current rating of the inductor must be greater
than the inductor peak current. The inductor peak current is
calculated using the following equation:
II +=
PEAK
)(
MAXLOAD
Inductor conduction losses are caused by the flow of current
through the inductor, which has an associated internal DCR.
Larger sized inductors have smaller DCR, which may decrease
inductor conduction losses. Inductor core losses are related to
the magnetic permeability of the core material. Because the
ADP2138/ADP2139 are high switching frequency dc-to-dc
converters, shielded ferrite core material is recommended for its
low core losses and low electromagnetic interference (EMI).
Capacitors must have a dielectric adequate to ensure the
minimum capacitance over the necessary temperature range
and dc bias conditions. X5R or X7R dielectrics with a voltage
rating of 6.3 V or 10 V are recommended for best performance.
Y5V and Z5U dielectrics are not recommended for use with any
dc-to-dc converter because of their poor temperature and dc bias
characteristics.
The worst-case capacitance accounting for capacitor variation
over temperature, component tolerance, and voltage is calculated using the following equation:
C
= C
EFF
× (1 − TEMPCO) × (1 − TOL)
OUT
where:
is the effective capacitance at the operating voltage.
C
EFF
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, the worst-case temperature coefficient (TEMPCO)
over −40°C to +85°C is assumed to be 15% for an X5R dielectric.
The tolerance of the capacitor (TOL) is assumed to be 10%, and
is 4.0466 F at 1.8 V, as shown in Figure 35.
C
OUT
Substituting these values in the equation yields
= 4.0466 F × (1 − 0.15) × (1 − 0.1) = 3.0956 F
C
EFF
To guarantee the performance of the ADP2138/ADP2139, it is
imperative that the effects of dc bias, temperature, and tolerances
on the behavior of the capacitors be evaluated for each application.
6
5
4
3
Table 6. Suggested 1.0 μH Inductors
Vendor Model
Murata LQM2MPN1R0NG0B 2.0 × 1.6 × 0.9 1400 85
LQM18PN1R0 1.6 × 0.8 × 0.33 700 52
Taiyo Yuden CBMF1608T1R0M 1.6 × 0.8 × 0.8 290 90
EPL2014-102ML 2.0 × 2.0 × 1.4 900 59
Coilcraft TDK GLFR1608T1R0M-LR 1.6 × 0.8 × 0.8 360 80
0603LS-102 1.8 × 1.27 × 1.1 400 81
Coilcraft
Toko
MDT2520-CN 2.5 × 2.0 × 1.2 1800 100
Dimensions
(mm)
I
SAT
(mA)
DCR
(mΩ)
Output Capacitor
Higher output capacitor values reduce the output voltage ripple
and improve load transient response. When choosing this value,
it is also important to account for the loss of capacitance due to
output voltage dc bias.
Ceramic capacitors are manufactured with a variety of dielectrics,
each with different behavior over temperature and applied voltage.
Rev. A | Page 13 of 16
2
CAPACITANCE (µF )
1
0
012345
DC BIAS VOLT AGE (V)
Figure 35. Typical Capacitor Performance
6
09496-029
The peak-to-peak output voltage ripple for the selected output
capacitor and inductor values is calculated using the following
equation:
V
RIPPLE
SW
IN
CLf
××××
22
OUT
=
()
π
RIPPLE
SW
CfI××=8
OUT
V
Capacitors with lower equivalent series resistance (ESR) are
preferred to guarantee low output voltage ripple, as shown in
the following equation:
V
ESR ≤
COUT
RIPPLE
I
RIPPLE
Page 14
ADP2138/ADP2139
The effective capacitance needed for stability, which includes
temperature and dc bias effects, is 3 µF.
Table 7. Suggested 4.7 μF Capacitors
Case
Vendor Type Model
Size
Murata X5R GRM188R60J475 0603 6.3
Taiyo Yuden X5R JMK107BJ475 0603 6.3
Coilcraft TDK X5R C1608X5R0J475 0603 6.3
Input Capacitor
Higher value input capacitors help to reduce the input voltage
ripple and improve transient response. Maximum input
capacitor current is calculated using the following equation:
VVV
)(
−
IN
II
≥
CIN
OUT
MAXLOAD
)(
OUT
V
IN
To minimize supply noise, place the input capacitor as close to
the VIN pin of the ADP2138/ADP2139 as possible. As with the
output capacitor, a low ESR capacitor is recommended. The list
of recommended capacitors is shown in Tab l e 8 .
Table 8. Suggested 4.7 μF Capacitors
Case
Vendor Type Model
Size
Murata X5R GRM188R60J475 0603 6.3
Taiyo Yuden X5R JMK107BJ475 0603 6.3
Coilcraft TDK X5R C1608X5R0J475 0603 6.3
THERMAL CONSIDERATIONS
Because of the high efficiency of the ADP2138/ADP2139, only a
small amount of power is dissipated inside the ADP2138/ADP2139
package, which reduces thermal constraints.
However, in applications with maximum loads at high ambient
temperature, low supply voltage, and high duty cycle, the heat
dissipated in the package is great enough that it may cause the
junction temperature of the die to exceed the maximum junction temperature of 125°C. If the junction temperature exceeds
150°C, the converter enters thermal shutdown. It recovers when
the junction temperature falls below 130°C.
Voltage
Rating (V)
Voltage
Rating (V)
The junction temperature of the die is the sum of the ambient
temperature of the environment and the temperature rise of the
package due to power dissipation, as shown in the following
equation:
T
= TA + TR
J
where:
is the junction temperature.
T
J
T
is the ambient temperature.
A
is the rise in temperature of the package due to power
T
R
dissipation.
The rise in temperature of the package is directly proportional
to the power dissipation in the package. The proportionality
constant for this relationship is the thermal resistance from the
junction of the die to the ambient temperature, as shown in the
following equation:
T
= θJA × PD
R
where:
T
is the rise in temperature of the package.
R
θ
is the thermal resistance from the junction of the die to the
JA
ambient temperature of the package.
P
is the power dissipation in the package.
D
PCB LAYOUT GUIDELINES
Poor layout can affect ADP2138/ADP2139 performance, causing
EMI and electromagnetic compatibility problems, ground
bounce, and voltage losses. Poor layout can also affect regulation
and stability. To implement a good layout, use the following rules:
• Place the inductor, input capacitor, and output capacitor
close to the IC using short tracks. These components carry
high switching frequencies, and large tracks act as antennas.
• Route the output voltage path away from the inductor and
SW node to minimize noise and magnetic interference.
• Maximize the size of ground metal on the component side
to help with thermal dissipation.
• Use a ground plane with several vias connecting to the com-
ponent side ground to further reduce noise interference on
sensitive circuit nodes.
Rev. A | Page 14 of 16
Page 15
ADP2138/ADP2139
EVALUATION BOARD
TB1
VIN
TB2
EN
TB6
MODE
T5
EVALUATION BOARD LAYOUT
EN
CIN
4.7µF
L1
1µH
VIN
1
3
4
5
VIN
GND
EN
MODE
U1
SW
VOUT
221
6
Figure 36. Evaluation Board Schematic
COUT
4.7µF
TB3
TB4
VOUT
GND OUTGND IN
09496-030
09496-032
Figure 37. Top Layer
09496-031
Figure 38. Bottom Layer
Rev. A | Page 15 of 16
Page 16
ADP2138/ADP2139
OUTLINE DIMENSIONS
1.070
1.030
0.990
BALL A1
IDENTIFIER
0.640
0.595
0.550
SEATING
PLANE
TOP VIEW
(BALL SIDE DOWN)
SIDE VIEW
0.340
0.320
0.300
1.545
1.505
1.465
0.370
0.355
0.340
1.00
REF
0.50
REF
0.50 REF
COPLANARITY
0.05
0.270
0.240
0.210
Figure 39. 6-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-6-12)
nsions sho
Dime
wn in millimeters
ORDERING GUIDE
Temperature
Model1
Range
ADP2138ACBZ-0.8-R7 −40°C to +125°C 0.8 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-12 LJH
ADP2138ACBZ-1.0-R7 −40°C to +125°C 1.0 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-12 L88
ADP2138ACBZ-1.2-R7 −40°C to +125°C 1.2 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-12 L89
ADP2138ACBZ-1.5-R7 −40°C to +125°C 1.5 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-12 L8A
ADP2138ACBZ-1.8-R7 −40°C to +125°C 1.8 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-12 L8C
ADP2138ACBZ-2.5-R7 −40°C to +125°C 2.5 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-12 L93
ADP2138ACBZ-2.8-R7 −40°C to +125°C 2.8 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-12 LDH
ADP2138ACBZ-3.0-R7 −40°C to +125°C 3.0 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-12 LDJ
ADP2138ACBZ-3.3-R7 −40°C to +125°C 3.3 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-12 LDP
ADP2139ACBZ-0.8-R7 −40°C to +125°C 0.8 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-12 LJJ
ADP2139ACBZ-1.0-R7 −40°C to +125°C 1.0 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-12 LHN
ADP2139ACBZ-1.2-R7 −40°C to +125°C 1.2 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-12 LHP
ADP2139ACBZ-1.5-R7 −40°C to +125°C 1.5 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-12 LHQ
ADP2139ACBZ-1.8-R7 −40°C to +125°C 1.8 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-12 LHR
ADP2139ACBZ-2.5-R7 −40°C to +125°C 2.5 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-12 LHS
ADP2139ACBZ-2.8-R7 −40°C to +125°C 2.8 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-12 LHT
ADP2139ACBZ-3.0-R7 −40°C to +125°C 3.0 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-12 LHU
ADP2139ACBZ-3.3-R7 −40°C to +125°C 3.3 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-12 LHV
1
Z = RoHS Compliant Part.
Output
Voltage (V)
Package Description
12
BOTTOM VIEW
(BALL SIDE UP)
A
B
C
12-07-2010-A
Package
Option
Branding
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09496-0-4/11(A)
Rev. A | Page 16 of 16
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