Datasheet ADP2126 Datasheet (ANALOG DEVICES)

Ultralow Profile, 500 mA, 6 MHz, Synchronous,

Data Sheet

FEATURES

1.20 V and 1.26 V fixed output voltage options
Clock signal enable

Logic signal enable also available on certain models
6 MHz operating frequency
Spread spectrum frequency modulation to reduce EMI
500 mA continuous output current
Input voltage: 2.1 V to 5.5 V

0.3 μA (typical) shutdown supply current
Pin-selectable power-saving mode
Compatible with tiny multilayer inductors
Internal synchronous rectifier
Internal compensation
Internal soft start
Output-to-ground short-circuit protection
Current-limit protection
Undervoltage lockout
Thermal shutdown protection

0.330 mm height (maximum), 6-ball BUMPED_CHIP (ADP2126)

0.200 mm height (maximum), 6-pad EWLP (ADP2127)

Step-Down, DC-to-DC Converters

ADP2126/ADP2127

TYPICAL APPLICATIONS CIRCUIT

ADP2126/

INPUT

VOLTAGE

2.1V TO 5.5V
C

IN

2.2µF

OFF ON

*LOGIC HI G H E NABL E I S O NL Y AVAI LABLE ON CERTAI N M O DELS.

ADP2127

A2

VIN

C2

GND FB

EXTCLK MODE

B2 A1

AUTO

OR

OFF

SW

PWM

Figure 1.

ON

L

1.0µH

B1

C1

*

OUTPUT
VOLTAGE

1.20V OR 1.26V

C

OUT

2.2µF

09658-001

APPLICATIONS

Mobile phones
Digital still/video cameras
Digital audio
Portable equipment
Camera modules

Image stabilization systems

GENERAL DESCRIPTION

The ADP2126/ADP2127 are high frequency, step-down, dc-to­dc converters optimized for portable applications in which board
area and battery life are critical constraints. The fixed 6 MHz
operating frequency enables the use of tiny ceramic inductors
and capacitors and the regulators use spread spectrum frequency
modulation to reduce EMI. Additionally, synchronous rectification
improves efficiency and results in fewer external components.

At high load currents, the ADP2126/ADP2127 use a voltage
regulating pulse-width modulation (PWM) mode that maintains
a constant frequency with excellent stability and transient response.
Light load operation is determined by the state of the MODE pin.
In forced PWM mode, the converter continues operating in PWM
for light loads. Under light load conditions in auto mode, the
ADP2126/ADP2127 automatically enter a power-saving mode,
which uses pulse frequency modulation (PFM) to reduce the
effective switching frequency, thus ensuring the longest battery
life in portable applications.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

The ADP2126/ADP2127 are enabled by a 6 MHz to 27 MHz
external clock signal applied to the EXTCLK pin. Certain models
can also be enabled with a logic high signal. When the external clock
is not switching and in a low logic state, the ADP2126/ADP2127
stop regulating and shut down to draw less than 0.3 μA (typical)
from the source.

The ADP2126/ADP2127 have an input voltage range of 2.1 V to

5.5 V, allowing the use of single Li+/Li polymer cell, three-cell
alkaline, NiMH cell, and other standard power sources. The
ADP2126/ADP2127 are internally compensated to minimize
external components and can source up to 500 mA. Other key
features, such as cycle-by-cycle peak current limit, soft start,
undervoltage lockout (UVLO), output-to-ground short-circuit
protection, and thermal shutdown provide protection for internal
and external circuit components.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2011–2012 Analog Devices, Inc. All rights reserved.

ADP2126/ADP2127 Data Sheet

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Typical Applications Circuit............................................................ 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Diagrams.......................................................................... 4

Absolute Maximum Ratings............................................................ 5

Thermal Considerations.............................................................. 5

Thermal Resistance ...................................................................... 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 7

Theory of Operation ...................................................................... 11

Overview...................................................................................... 11

External Clock (EXTCLK) Enable........................................... 11

Spread Spectrum Oscillator ...................................................... 12

Mode Selection ........................................................................... 12

Internal Control Features.......................................................... 12

Protection Features .................................................................... 13

Timing Constraints.................................................................... 13

Applications Information.............................................................. 14

Inductor Selection...................................................................... 14

Input Capacitor Selection.......................................................... 14

Output Capacitor Selection....................................................... 15

Thermal Considerations............................................................ 15

PCB Layout Guidelines.................................................................. 16

Outline Dimensions....................................................................... 17

Ordering Guide .......................................................................... 18

REVISION HISTORY

3/12—Rev. A to Rev. B

Combined Figure 1 and Figure 2; Renumbered Sequentially..... 1

Changes to Undervoltage Lockout (UVLO) Section,

Added Figure 29, Renumbered Sequentially .............................. 13

Changes to Table 6.......................................................................... 14

Changes to Ordering Guide.......................................................... 18

5/11—Rev. 0 to Rev. A

Changes to Figure 35...................................................................... 17

5/11—Revision 0: Initial Version

Rev. B | Page 2 of 20

Data Sheet ADP2126/ADP2127

SPECIFICATIONS

VIN = 3.6 V, TA = 25°C for typical specifications, and TA = TJ = −40°C to +85°C for minimum and maximum specifications, unless
otherwise noted.
(SQC) methods. Typical specifications are not guaranteed.

Table 1.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

SUPPLY

Operating Input Voltage Range VIN 2.1 5.5 V
PWM Mode Quiescent Current No load, V
Auto Mode Quiescent Current No load, V
Shutdown Current1 V

UNDERVOLTAGE LOCKOUT

Rising VIN Threshold 1.9 2.1 V
Falling VIN Threshold 1.5 1.8 V

OUTPUT

Continuous Output Current2 I
PWM Mode Output Accuracy
PFM Mode Output Accuracy
FB Bias Current VFB = V
FB Pull-Down Resistance R

SWITCHING CHARACTERISTICS

PMOS On Resistance ISW = 500 mA 180 340 mΩ
NMOS On Resistance ISW = 500 mA 250 mΩ
SW Leakage Current VSW = 0 V, VIN = 5.5 V 10 μA
PMOS Switch Current Limit Open loop 770 1000 1291 mA
PFM Current Limit V
Oscillator Frequency fSW 4.8 6 6.8 MHz

SHORT-CIRCUIT PROTECTION

Rising V
Falling V

EXTCLK INPUT

High Threshold Voltage V
Low Threshold Voltage V
Leakage Current VIN = 5.5 V, V
Duty Cycle Operating Range D
Frequency Operating Range f

MODE INPUT LOGIC

High Threshold Voltage V
Low Threshold Voltage V
Leakage Current V

THERMAL SHUTDOWN5 PWM mode only

Thermal Shutdown Threshold 146 °C
Thermal Shutdown Hysteresis 13 °C

All specifications at temperature extremes are guaranteed via correlation using the standard statistical quality control

= VIN 12 mA

MODE

= 0 V, VFB > V

MODE

= 0 V, open loop 0.3 1.5 μA

EXTCLK

VIN = 2.1 V to 5.5 V 500 mA

LOAD

3

V

VIN = 2.1 V to 5.5 V, no load V

3, 4

Threshold 0.55 0.7 V

OUT

Threshold 0.4 0.52 V

OUT

OUT

VIN = 2.1 V to 5.5 V V

4 9 μA

OUT

V

DSCHG

VIN = 2.1 V to 5.5 V 1.3 V

EXTCLK(H)

VIN = 2. 1 V to 5.5 V 0.4 V

EXTCLK(L)

40 60 %

EXTCLK

6 27 MHz

EXTCLK

VIN = 2.1 V to 5.5 V 1.3 V

MODE(H)

VIN = 2.1 V to 5.5 V 0.4 V

MODE(L)

= 0 V, IFB = 10 mA 110 180 Ω

EXTCLK

= 0 V, VIN = 3.6 V 170 260 305 mA

MODE

= 2.1 V to 5.5 V 0.01 1 μA

EXTCLK

= 0 V, VIN = V

EXTCLK

MODE

, SW = open 300 500 μA

OUT

− 2% V

OUT

− 3% V

OUT

+ 2% V

OUT

+ 3% V

OUT

= 5.5 V 0.005 1 μA

Rev. B | Page 3 of 20

ADP2126/ADP2127 Data Sheet

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

TIMING See Figure 2 and Figure 3

VIN High to EXTCLK On2 t1 V
EXTCLK On to V

Rising t

OUT

2 (CLOCK)

D
EXTCLK On to V
V

Power-Up Time (Soft Start)2 t3 C

OUT

EXTCLK Off to V
EXTCLK Off to V
V

Power-Down Time t6 C

OUT

Rising t

OUT

Falling t

OUT

Falling t

OUT

2 (LOGIC)

5 (CLOCK)

5 (LOGIC)

C
Minimum Shutdown Time2 t
Minimum Power-Off Time2 t

1

The total shutdown current is the addition of VIN shutdown current and SW leakage.

2

Guaranteed by design.

3

Transients not included in voltage accuracy specifications.

4

The PFM output voltage will be higher than the PWM output voltage. See the Typi section. cal Performance Characteristics

5

Thermal shutdown protection is only active in PWM mode.

+ t6 C

5

500 μs

7

TIMING DIAGRAMS

= 2.1 V to 5.5 V 200 μs

IN

D

= 40% to 60%, f

EXTCLK

= 40% to 60%, f

EXTCLK

= 6 MHz 250 320 400 μs

EXTCLK

= 27 MHz 250 320 400 μs

EXTCLK

EXTCLK = logic high 285 315 385 μs

OUT

D

EXTCLK

= 2.2 μF, R

= 40% to 60%, f

= 3.6 Ω 70 200 μs

LOAD

= 6 MHz to 27 MHz 9 17 μs

EXTCLK

EXTCLK = logic high, no load 0 μs

= 2.2 μF, R

OUT

= 2.2 μF, no load 465 μs

OUT

= 2.2 μF, no load 1400 μs

OUT

= 3.6 Ω 16 μs

LOAD

VIN

V

OUT

EXTCLK

t

1

VIN × 90%

t

3

t

2

t

6

V

OUT(NOM)

t

5

× 10%

t

7

V

× 10%

IN

09658-003

Figure 2. Clock Enable I/O Timing Diagram

VIN

V

OUT

EXTCLK

VIN × 90%

t

t

3

t

2

t

1

t

5

6

Figu re 3. Logic E nable I/O T iming D iagram (Logic High Enable Feature Available Only on Certain Models)

V

OUT(NOM)

× 10%

t

7

V

× 10%

IN

09658-004

Rev. B | Page 4 of 20

Data Sheet ADP2126/ADP2127

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

VIN to GND −0.3 V to +6 V
EXTCLK to GND −0.3 V to +6 V
SW, MODE to GND −0.3 V to VIN
FB to GND −0.3 V to +3.6 V
Operating Ambient Temperature (TA) –40°C to +85°C1
Operating Junction Temperature (TJ)

= 500 mA

at I

LOAD

–40°C to +125°C

Soldering Conditions JEDEC J-STD-020

1

The maximum operating junction temperature (T

maximum operating ambient temperature (T
Considerations section for more information.

) supersedes the

J (MAX)

). See the Thermal

A (MAX)

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Absolute maximum ratings apply individually only, not in
combination.

THERMAL CONSIDERATIONS

The maximum operating junction temperature (T
supersedes the maximum operating ambient temperature
(T

) because the ADP2126/ADP2127 may be damaged

A (MAX)

when the junction temperature limits are exceeded. Monitoring
ambient temperature does not guarantee that T
specified temperature limits.

In applications with high power dissipation and poor PCB
thermal resistance, the maximum ambient temperature may
need to be derated. In applications with moderate power
dissipation and good PCB thermal resistance, the maximum

)

J (MAX)

is within the

J

ambient temperature can exceed the maximum limit as long as
the junction temperature is within specification limits.

The operating junction temperature (T
on the ambient temperature (T
device (P
the package (θ

), and the junction-to-ambient thermal resistance of

D

). TJ is calculated using the following formula:

JA

= TA + (PD × θJA) (1)

T

J

) of the device is dependent

J

), the power dissipation of the

A

See the Applications Information section for further information
on calculating the operating junction temperature for a specific
application.

THERMAL RESISTANCE

θJA of the package is based on modeling and calculation using a
4-layer board. θ

is highly dependent on the application and

JA

board layout. In applications where high maximum power
dissipation exists, attention to thermal board design is required.
The value of θ

may vary, depending on PCB material, layout,

JA

and environmental conditions.

θ

is specified for worst-case conditions, that is, a device soldered

JA

on a circuit board for surface-mount packages. θ

is determined

JA

according to JEDEC Standard JESD51-9 on a 4-layer printed
circuit board (PCB).

Table

3. Thermal Resistance (4-Layer PCB)

Package Type θJA Unit

6-Ball Bumped Bare Die Sales 105 °C/W
6-Pad Embedded Wafer Level Package 105 °C/W

ESD CAUTION

Rev. B | Page 5 of 20

ADP2126/ADP2127 Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

BALLA1
INDICATOR

2

1

MODE VIN

A

SW

EXTCLK

B

FB GND

C

TOP VIEW

BALL/PAD SIDE DOWN

4. Pin Function Descriptions

Table

Pin No. Mnemonic Description
A1 MODE

Mode Select. This pin toggles between auto mode (PFM and PWM switching) and PWM mode. Set MODE low to
allow the part to operate in auto mode. Pull MODE high to force the part to operate in PWM mode. The voltage

applied to MODE should never be higher than the voltage applied to VIN. Do not leave this pin floating.
A2 VIN Power Supply Input.
B1 SW Switch Node.
B2 EXTCLK

External Clock Enable Signal. The ADP2126/ADP2127 power up when a clock signal (6 MHz to 27 MHz) or a logic high

signal (EXTCLK ≥ 1.3 V) is detected on this pin. (The logic high enable feature is only available on certain models.)
C1 FB

Feedback Divider Input. Connect the output capacitor from FB to GND to set the output voltage ripple and to

complete the control loop.
C2 GND Ground.

BUMPS/PADS ON OPPOSITE SIDE

(Not to Scale)

Figure 4. Pin Configuration

09658-005

Rev. B | Page 6 of 20

Data Sheet ADP2126/ADP2127

TYPICAL PERFORMANCE CHARACTERISTICS

VIN = 3.6 V, f
(GRM153R60G225M), and T

90

80

70

60

50

40

EFFICIENCY (%)

30

20

10

0

1 10 100 1000

90

= 10 MHz, V

EXTCLK

AUTO MO DE

LOAD CURRENT (mA)

= 1.20 V, L = 1.0 µH (CKP1608S1R0), CIN = 2.2 µF (GRM153R60J225ME95), C

OUT

= 25°C, unless otherwise noted.

A

PWM MODE

Figure 5. Efficiency vs. Load Current

VIN = 2.1V
VIN = 2.5V
VIN = 3.6V
VIN = 4.2V
VIN = 5.5V

= 2.2 µF

OUT

1.205

1.204

1.203

OUTPUT VOLTAGE (V)

1.202

09658-006

VIN = 2.1V
VIN = 2.5V
VIN = 3.6V
VIN = 4.2V
VIN = 5.5V

1 10 100 1000

LOAD CURRENT (mA)

09658-009

Figure 8. PWM Mode Output Voltage Accuracy

250

EFFICIENCY (%)

OUTPUT VOLTAGE (V)

80

70

60

50

40

30

2.1 5.14.64.13.63.12.6

1.24

1.23

1.22

1.21

1.20

I

= 50mA, PWM MODE

LOAD

I

= 100mA, PWM MODE

LOAD

I

= 10mA, PFM MODE

LOAD

I

= 50mA, PFM MODE

LOAD

I

= 100mA, PFM MODE

LOAD

I

= 250mA, PFM MODE

LOAD

INPUT VOLTAGE (V)

Figure 6. Efficiency vs. Input Voltage

VIN = 2.1V
VIN = 2.5V
VIN = 3.6V
VIN = 4.2V
VIN = 5.5V

200

PWM OPERATION

150

100

LOAD CURRENT (mA)

50

0

2.3 5.55.14.74. 33.93.53.12.7

09658-007

PFM OPERATION

INPUT VOLTAGE (V)

09658-010

Figure 9. Auto Mode Switching Threshold vs. Input Voltage

60

50

40

30

20

OUTPUT VOLTAGE RIPPLE (mV)

10

VIN = 2.1V
VIN = 3.6V
VIN = 5.5V

1.19
1 10 100 1000

LOAD CURRENT (mA)

Figure 7. Auto Mode Output Voltage Accuracy

09658-008

Rev. B | Page 7 of 20

0

0 100 200 300 400 500

LOAD CURRENT (mA)

Figure 10. Output Voltage Ripple vs. Load Current

09658-011

ADP2126/ADP2127 Data Sheet

1.2

1.0

TA = –40°C
TA = +25°C
TA = +85°C

450

400

ISW = 500mA

TA = –40°C
TA = +25°C
TA = +105°C

0.8

0.6

0.4

SHUTDOWN CURRENT (µA)

0.2

0

2.1 5.14.64.13.63.12.6

INPUT VOLTAGE (V)

Figure 11. Shutdown Current vs. Input Voltage

500

450

400

350

300

250

PFM MOD E QUIESCE NT CURRENT ( µA)

200

2.1 5.14.64.13.63.12.6

INPUT VOLTAGE (V)

Figure 12. PFM Mode Quiescent Current vs. Input Voltage

17

15

13

TA = –40°C
TA = +25°C
TA = +85°C

350

300

250

N-CHANNEL RDSON (mΩ)

200

150

2.1 5.14.64.13.63.12.6

09658-012

INPUT VOLTAGE (V)

09658-015

Figure 14. NMOS Drain-to-Source On Resistance

400

ISW = 500mA

350

300

250

200

P-CHANNEL RDSO N (mΩ)

150

100

2.1 5.14.64.13.63.12.6

09658-013

INPUT VOLTAGE (V)

TA = –40°C
TA = +25°C
TA = +105°C

09658-016

Figure 15. PMOS Drain-to-Source On Resistance

OUTPUT VOLTAGE (200mV/DIV)

1

11

9

7

PWM MODE QUIESCENT CURRENT (mA)

5

2.1 5.14.64.13.63.12.6

INPUT VOLTAGE (V)

Figure 13. PWM Mode Quiescent Current vs. Input Voltage

TA = –40°C
TA = +25°C
TA = +85°C

09658-014

Rev. B | Page 8 of 20

INDUCTOR CURRENT (1A/DIV)

4

TIME (200µs/DIV)

09658-017

Figure 16. Output Short-Circuit Response

Data Sheet ADP2126/ADP2127

1

VIN = 2.1V

OUTPUT VOLTAGE (50mV/DIV)

1.20V OF FSET

LOAD CURRENT (100mA/DIV)

1

VIN = 2.1V

OUTPUT VOLTAGE (50mV/DIV)

1.20V OF FSET

LOAD CURRENT (200mA/DIV)

4

TIME (40µs/DIV )

Figure 17. Load Transient Response, 0 mA to 150 mA, V

VIN = 3.6V

OUTPUT VOLTAGE (50mV/DIV)

1.20V OF FSET

1

LOAD CURRENT (100mA/DIV)

4

TIME (40µs/DIV )

Figure 18. Load Transient Response, 0 mA to 150 mA, V

VIN = 5.5V

OUTPUT VOLTAGE (50mV/DIV)

1.20V OF FSET

1

= 2.1 V

IN

= 3.6 V

IN

4

09658-018

Figure 20. Load Transient Response, 250 mA to 420 mA, V

TIME (20µs/DIV )

= 2.1 V

IN

09658-021

VIN = 3.6V

1

4

09658-019

Figure 21. Load Transient Response, 250 mA to 420 mA, V

OUTPUT VOLTAGE (50mV/DIV)

1.20V OF FSET

LOAD CURRENT (200mA/DIV)

TIME (20µs/DIV )

= 3.6 V

IN

09658-022

VIN = 5.5V

1

OUTPUT VOLTAGE (50mV/DIV)

1.20V OF FSET

LOAD CURRENT (100mA/DIV)

4

TIME (40µs/DIV )

Figure 19. Load Transient Response, 0 mA to150 mA, V

= 5.5 V

IN

09658-020

Rev. B | Page 9 of 20

LOAD CURRENT (200mA/DIV)

4

TIME (20µs/DIV )

Figure 22. Load Transient Response, 250 mA to 420 mA, V

= 5.5 V

IN

09658-023

ADP2126/ADP2127 Data Sheet

NO LOAD

OUTPUT VOLTAGE (500mV/DIV)

1

INDUCTOR CURRENT (200mA/DI V)

4

EXTCLK PIN VOLTAGE (5V/DIV)

2

I

= 100mA

LOAD

1

4

2

OUTPUT VOLTAGE (20mV/DIV)

1.20V OFFSET

INDUCTOR CURRE NT (200mA/DIV )

SW PIN VOLTAGE (5V/DIV)

TIME (100µs/DIV)

Figure 23. Startup, No Load

R

= 3.6Ω

LOAD

1

INDUCTOR CURRENT (200mA/DIV)

4

2

OUTPUT VOLTAGE (500mV/DIV)

EXTCLK PIN VOLTAGE (5V/DIV)

TIME (100µs/DIV)

Figure 24. Startup, R

5.50

5.45

5.40

09658-024

Figure 26. Typical PFM Mode Operation, I

I

= 150mA

LOAD

1

4

4

09658-025

LOAD

= 3.6 Ω

Figure 27. Typical PWM Mode Operation, I

TIME ( 400ns/DI V)

OUTPUT VOLTAGE (10mV/DIV)

1.20V OF FSET

INDUCTOR CURRE NT (200mA/DIV )

SW PIN VOLTAGE (5V/DIV)

TIME ( 100ns/DI V)

= 100 mA

LOAD

= 150 mA

LOAD

09658-027

09658-028

5.35

FREQUENCY (MHz)

5.30

5.25

–2.0 –1.5 –1.0 –0. 5 0 0.5 1.0 1. 5 2.0

TIME (ns)

09658-026

Figure 25. Spread Spectrum Switching Frequency

Rev. B | Page 10 of 20

Data Sheet ADP2126/ADP2127

V

*

V

THEORY OF OPERATION

IN

PILIM

ZXCOMP

THRESHOLD

PDRIVE

NDRIVE

DETECT

C

IN

AUTO

PV

AVIN

IN

PREF

NREF

A1

PWM

MODE

VIN

A2

V

L

OUT

1.20V OR

1.26V

C

OUT

PGND

AGND

SW

B1

GND

C2

OUT

FB

C1

AGND

DISCHARGE

ADP2126/ADP2127

R1

EAMP

R2

BG

COMPENSATIO N

FB

R

DSCHG

110Ω

V

OUT

AGND

BG

BANDGAP

ON

OFF

AGND

6MHz

OSCILLAT OR

B2

EXTCLK

OR

FB

OFF

RAMP

ON

PWM
COMP

V(V

)

IN

THERMAL

SHUTDOWN

SOFT START

SHORT-CIRCUIT

PROTECTION

CLK

DETECT

THRESHOLD

DETECT*

*

2.1V TO 5.5V

SHOOT­THROUGH
CONTROL

LOGIC

AND
PFM/PWM
CONTRO L

THE LOGIC HIGH ENABLE FEATURE IS ONLY AVAIL ABLE ON CERTAI N MODELS.

Figure 28. Internal Block Diagram

OVERVIEW

The ADP2126/ADP2127 are high efficiency, synchronous, step­down, dc-to-dc regulators that operate from a 2.1 V to 5.5 V
input voltage. They provide up to 500 mA of continuous output
current at a fixed output voltage. The 6 MHz operating frequency
enables the use of tiny external components. External control
for mode selection provides a power-saving option. The internal
control schemes of the ADP2126/ADP2127 give excellent
stability and transient response. Other internal features, such
as cycle-by-cycle peak current limit, soft start, undervoltage
lockout, output-to-ground short-circuit protection, and thermal
shutdown provide protection for internal circuit components.

09658-029

EXTERNAL CLOCK (EXTCLK) ENABLE

The ADP2126/ADP2127 are enabled by a 6 MHz to 27 MHz
external clock signal applied to the EXTCLK pin. Certain models
can also be enabled with a logic high signal (see Figure 2, Figure 3,
and Figure 28). When the ADP2126/ ADP2127 are enabled, the
converter is able to power up, and the output voltage rises to its
nominal value. When the external clock is not switching and in
a low logic state, the ADP2126/ADP2127 stop regulating and
shut down to draw less than 0.3 µA (typical) from the source.

Rev. B | Page 11 of 20

ADP2126/ADP2127 Data Sheet

SPREAD SPECTRUM OSCILLATOR

The ADP2126/ADP2127 incorporate spread spectrum
functionality to modulate electromagnetic interference (EMI)
for EMI sensitive applications. A typical switching converter
with a regulated switching frequency has a narrow frequency
spectrum centered at the target switching frequency. This
results in a high spectral density around the target frequency
with peak emission levels that can exceed the regulatory levels
for EMI in many portable, cellular, and wireless applications.

To maintain acceptable levels of EMI, the ADP2126/ADP2127
employs spread spectrum via a controlled variance of the switching
frequency over a wider band of frequencies. Figure 25 shows the
variance of the frequency over time. This distribution of the
frequency content spreads the spectral density over a wider
bandwidth, resulting in lower peak emission levels.

MODE SELECTION

The ADP2126/ADP2127 have two modes of operation (PWM
mode and auto mode), determined by the state of the MODE pin.

Pull the MODE pin high to force the converter to operate in
PWM mode, regardless of the output current. Otherwise, set
MODE low to put the converter into auto mode and allow the
converter to automatically transition from PWM mode to the
power-saving PFM mode at light load currents. Do not leave
this pin floating.

Pulse-Width Modulation (PWM) Mode

The PWM mode forces the part to maintain a fixed frequency
of 6 MHz (maximum) under all load conditions. The ADP2126/
ADP2127 use a proprietary, hybrid voltage-mode control scheme
to control the duty cycle under all load current and line voltage
variations. This control scheme provides excellent stability,
transient response, and output regulation. PWM mode results
in lower efficiencies at light load currents.

Auto Mode (PFM and PWM Switching)

Auto mode is a power-saving feature that enables the converter
to switch between PWM and PFM in response to the output
load. Auto mode is enabled when the MODE pin is pulled low.
In auto mode, the ADP2126/ADP2127 operate in PFM mode for
light load currents and switch to PWM mode for medium and
heavy load currents.

Pulse Frequency Modulation (PFM) Mode

When the converter is operating under light load conditions,
the effective switching frequency and supply current are decreased
and varied using PFM to regulate the output voltage. This results in
improved efficiencies and lower quiescent currents. In PFM mode,
the converter only switches when necessary to keep the output
voltage within the PFM limits set by an internal comparator.
Switching stops when the upper limit is reached and resumes
when the lower limit is reached.

When the upper level is reached, the output stage and most
control circuitry turn off to reduce the quiescent current. During
this stage, the output capacitor supplies the current to the load.
As the output capacitor discharges and the output voltage reaches
the lower PFM comparator threshold, switching resumes and the
process repeats.

Mode Transition

When the MODE pin is low, the converter switches between
PFM and PWM modes automatically to maintain optimal
transient response and efficiency. The mode transition point
depends on the input voltage. Hysteresis exists in the transition
point to prevent instability and decreased efficiencies that could
result if the converter were able to oscillate between PFM and
PWM for a fixed input voltage and load current. See Figure 9 for
the typical PFM and PWM mode boundaries of the
ADP2126/ADP2127.

A switch from PFM to PWM occurs when the output voltage dips
below the nominal value of the output voltage option. Switching
to PWM allows the converter to maintain efficiency and supply
a larger current to the load. The output voltage in PFM mode is
slightly higher to keep the ADP2126/ADP2127 from oscillating
between modes, ensuring stable operation.

The switch from PWM to PFM occurs when the output current
is below the PFM threshold for multiple consecutive switching
cycles. Switching to PFM allows the converter to save power by
supplying the lighter load current with fewer switching cycles.

INTERNAL CONTROL FEATURES

Synchronous Rectification

In addition to the P-channel MOSFET switch, the ADP2126/
ADP2127 include an N-channel MOSFET switch to build the
synchronous rectifier. The synchronous rectifier improves
efficiency, especially for small load currents, and reduces cost
and board space by eliminating the need for an external rectifier.

Soft Start

To prevent excessive input inrush current at startup, the ADP2126/
ADP2127 operate with an internal soft start. When EXTCLK
begins to oscillate, or when the part recovers from a fault (UVLO,
TSD, or SCP), a soft start timer begins. During this time, the
peak current limit is gradually increased to its maximum. The
output voltage increases in stages to ensure that the converter is
able to start up effectively and in proper sequence. After the soft
start period expires, the peak PMOS switch current limit remains
at 1 A (typical), and the part begins normal operation.

Rev. B | Page 12 of 20

Data Sheet ADP2126/ADP2127

PROTECTION FEATURES

Overcurrent Protection

To ensure that excessively high currents do not damage the
MOSFET switches, the ADP2126/ADP2127 incorporate cycle-by-
cycle overcurrent protection. This function is accomplished by
monitoring the instantaneous peak current on the power PMOS
switch. If this current exceeds the PMOS switch current limit
(1 A typical), then the PMOS is immediately turned off. This
minimizes the potential for damage to power components during
certain faults and transient events.

Output Short-Circuit Protection (SCP)

If the output voltage is shorted to GND, a standard dc-to-dc
controller delivers maximum power into that short. This may
result in a potentially catastrophic failure. To prevent this, the
ADP2126/ADP2127 sense when the output voltage is below the
SCP threshold (typically 0.52 V). At this point, the controller
turns off for approximately 450 µs and then automatically initiates a
soft start sequence. This cycle repeats until the short is removed
or the part is disabled. Figure 16 shows the operating behavior of
the ADP2126/ADP2127 during a short-circuit fault. The SCP
dramatically reduces the power delivered into the short circuit,
yet still allows the converter to recover when the fault is removed.

Thermal Shutdown (TSD) Protection

The ADP2126/ADP2127 also include TSD protection when the
part is in PWM mode only. If the die temperature exceeds 146°C
(typical), the TSD protection activates and turns off both MOSFET
power devices. They remain off until the die temperature falls to
133°C (typical), at which point the regulator restarts.

Undervoltage Lockout (UVLO)

If the input voltage drops below the UVLO falling threshold, the
ADP2126/ADP2127 automatically turn off the power switches and
enter a low power consumption mode. This prevents potentially
erratic operation at low input voltages. The parts remain in this
state until the input voltage rises above the UVLO rising threshold.
The UVLO levels have approximately 100 mV of hysteresis to
ensure glitch-free startup.

For the logic high enable option, during startup and UVLO
recovery after the input voltage drops below the UVLO falling

reshold, EXTCLK must be powered with the logic high signal

th

after VIN. If V
EXTCLK is powered before VIN with a logic high signal, the
UVLO does not become active. If VIN and EXTCLK are
powered from the same source, an RC circuit (see Figure 1)
is recommended to ensure that the ADP2126/ADP2127 are
powered correctly. R
RC time constant (τ) is greater than the 200 µs minimum
specification for VIN high to EXTCLK on (t
using the following equation:

τ = R

re τ ≥ t

whe

See Tab le 1 an
diagrams.

TIMING CO

Shutdown Time

When the ADP212
EXTCLK signal is removed, the ADP2126/ADP2127 must remain
in shutdown mode for a minimum of 1400 µs, if no load is applied,
before the EXTCLK signal can be reapplied. This allows all internal
nodes to discharge to an off state.

Power-Off Time

When VIN drops, th
ADP2127 have a minimum power-off time (t
must elapse before V
nodes to discharge enough power so that all internal devices are
in an off state.

dips below the UVLO falling threshold and

IN

and Cτ should be selected so that the

τ

). τ is calculat

1

× Cτ

τ

.

1

d Figure 3 for the timing specifications and

A2

B2

C2

VIN

EXTCLK

GND

ON

()

OFF

09658-036

rcu

V

IN

C

Figure 29. Recommended Logic Enable Startup Ci it

R

IN

C

NSTRAINTS

6/ADP2127 enter shutdown mode after the

ereby triggering UVLO, the ADP2126/

) of 500 µs tha

7

can be reapplied. This allows all intern

IN

t

7

Figure 30. Power-Off Time

VIN × 10%

09658-030

ed

t

al

Rev. B | Page 13 of 20

ADP2126/ADP2127 Data Sheet

(

)

APPLICATIONS INFORMATION

The low-profile ADP2126/ADP2127 are compatible with chip
inductors and multilayer ceramic capacitors that are ideal for
use in portable applications due to their small footprint and low
height. The recommended components for low-profile applications
may change as this technology advances. Ta b le 5 and Table 6 list
compatible inductors and capacitors.

This section describes the selection of external components.
The component value ranges are limited to optimize efficiency
and transient performance while maintaining stability over the
full operating range.

INDUCTOR SELECTION

The high switching frequency of the ADP2126/ADP2127 allows for
minimal output voltage ripple, even with small inductors. Inductor
sizing is a trade-off between efficiency and transient response.
A small value inductor leads to a larger inductor current ripple,
which provides excellent transient response but degrades efficiency.
A small footprint and low height chip inductor can be used for an
overall smaller solution size but has a higher dc resistance (DCR)
value and lower current rating that can degrade performance.
Shielded ferrite core inductors are advantageous for their low core
losses and low electromagnetic interference (EMI). For optimal
performance and stability, use inductor values between 1.5 µH
and 0.5 µH. Recommended inductors are shown in Tabl e 5.

The inductor peak-to-peak current ripple, I

VVV

−×

IN

OUT

I

=Δ

L

IN

OUT

(2)

fLV

××

SW

where:

f

is the switching frequency.

SW

L is the inductor value.

, is calculated from

L

It is important that the minimum dc current rating of the inductor
be greater than the peak inductor current (I
I

is calculated from

PK

I

PK

= I

LOAD(MAX)

+ IL/2 (3)

) in the application.

PK

The dc current rating of the inductor should be greater than the
calculated I

to prevent core saturation.

PK

INPUT CAPACITOR SELECTION

The input capacitor must be rated to support the maximum input
operating voltage. Higher value input capacitors reduce the input
voltage ripple caused by the switch currents on the VIN pin.
Maximum rms input current for the application is calculated using

()

VVV

−×

IN

II

MAXLOADCINMAXRMS

OUT

×=

)()(_

V

Place the input capacitor as close as possible to the VIN pin to
minimize supply noise.

In principle, different types of capacitors can be considered, but
for battery-powered applications, the best choice is the multilayer
ceramic capacitor, due to its small size, low equivalent series
resistance (ESR), and low equivalent series inductance (ESL).

It is recommended that the VIN pin be bypassed with at least a

2.2 µF input capacitor. For a 0.22 mm height solution using the
ADP2127, at least 2 × 1.0 µF capacitors will be necessary on the
input. The input capacitor can be increased without any limit for
better input voltage filtering. X5R or X7R dielectrics with a voltage
rating of 6.3 V or higher are recommended.

OUT

(4)

IN

Table 5. Inductor Selection

Current

Manufacturer Series Inductance (μH) DCR (mΩ) (Typ)

Murata LQM18PN1R0-A52 1.0 520 500 1.6 × 0.8 × 0.33 0603
Taiyo Yuden CKP1608S1R5M 1.5 420 500 1.6 × 0.8 × 0.33 0603

Rating (mA) Size (L × W × H) (mm) Package

Table 6. Input/Output Capacitor Selection

Temperature

Manufacturer Part Number Capacitance (μF) Voltage Rating (V)

Murata GRM153R60J225ME95 2.2 ± 20% 6.3 X5R 1.0 × 0.5 × 0.33 0402
GRM153R60G225M 2.2 ± 20% 4 X5R 1.0 × 0.5 × 0.33 0402
Taiyo Yuden JMK105BJ225MP 2.2 ± 20% 6.3 X5R 1.0 × 0.5 × 0.33 0402
AMK105BJ225MP 2.2 ± 20% 4 X5R 1.0 × 0.5 × 0.33 0402
AMK105BJ105MC 1.0 ± 20% 4 X5R 1.0 × 0.5 × 0.22 0402
ADC105BJ105ME 1.0 ± 20% 4 X5R 1.0 × 0.5 × 0.20 0402
JMK105BJ474KC 0.47 ± 10% 6.3 X5R 1.0 × 0.5 × 0.22 0402
JMK105BJ474MC 0.47 ± 20% 6.3 X5R 1.0 × 0.5 × 0.22 0402
TDK CGB2A3X5R0J105K 1.0 ± 10% 6.3 X5R 1.0 × 0.5 × 0.33 0402
CGB2A3X5R0J105M 1.0 ± 20% 6.3 X5R 1.0 × 0.5 × 0.33 0402

Coefficient Size (L × W × H) (mm) Package

Rev. B | Page 14 of 20

Data Sheet ADP2126/ADP2127

(

)

OUTPUT CAPACITOR SELECTION

The output capacitor selection affects both the output voltage
ripple and the loop dynamics of the converter. For a given loop
crossover frequency (the frequency at which the loop gain drops
to 0 dB), the maximum voltage transient excursion (overshoot)
is inversely proportional to the value of the output capacitor.

When choosing output capacitors, it is important to account for
the loss of capacitance due to output voltage dc bias. This may
result in using a capacitor with a higher rated voltage to achieve
the desired capacitance value. Additionally, if ceramic output
capacitors are used, the capacitor’s rms ripple current rating

The power dissipation (P

portion of the power loss of the overall application. For a given
application with known operating conditions, the application
power loss is calculated by combining the following equations
for power loss (P

= PIN − P

P

LOSS

P

OUT

η

P

IN

The resulting equation uses the output power and the efficiency
to determine the P

should always meet or exceed the application requirements.
The rms ripple current is calculated from

−×

I

()

COUTRMS

1

OUT

×= (5)

32

SW

VVV

OUT

)(

MAXIN

××

VfL

)(

MAXIN

At nominal load currents, the converter operates in forced PWM
mode, and the overall output voltage ripple is the sum of the voltage
spike caused by the output capacitor ESR plus the voltage ripple
caused by charging and discharging the output capacitor.

V

= IL × (ESR + 1/(8 × C

OUT

× fSW)) (6)

OUT

The largest voltage ripple occurs at the highest input voltage.

LOSS

The power loss calculated using this approach is the combined
loss of the ADP2126/ADP2127 device (P
input capacitor (P
shown in the following equation:

= PD + PL + P

P

LOSS

The power loss for the inductor, input capacitor, and output
capacitor is calculated using

P

= I

L

RMS

The ADP2126/ADP2127 are designed to operate with one

=

P ×

small 2.2 µF capacitor. For a 0.22 mm height solution using the

CIN

ADP2127, at least 2 × 1.0 µF capacitors will be necessary on the

= (∆

P

output. X5R or X7R dielectrics that have low ESR, low ESL, and
a voltage rating of 4 V or higher are recommended. These low
ESR components help the ADP2126/ADP2127 meet tight
output voltage ripple specifications.

THERMAL CONSIDERATIONS

The operating junction temperature (TJ) of the device is
dependent on the ambient operating temperature (T
application, the power dissipation of the ADP2126/ADP2127
(P

), and the junction-to-ambient thermal resistance of the

D

package (θ

). The operating junction temperature (TJ) is

JA

calculated from

T

= TA + (PD × θJA) (7)

J

where θ

is 105°C/W, as provided in Tabl e 3 .

JA

) of the

A

COUT

If multilayer chip capacitors with low ESR are used, the power
loss in the input and output capacitors is negligible and

P

+ PL >> P

D

≈ PD + PL (16)

P

LOSS

The final equation for calculating P
ensure that the operating junction temperature is not exceeded.

D

LOSS

The ADP2126/ADP2127 may be damaged when the operating
junction temperature limits are exceeded. Monitoring ambient
temperature does not guarantee that the junction temperature
(T

) is within the specified temperature limits.

J

• In applications with high P

and poor PCB thermal

D

resistance, the maximum ambient temperature may
need to be derated.

• In applications with moderate P

and good PCB thermal

D

resistance, the maximum ambient temperature can exceed
the maximum limit as long as the junction temperature is
within specification limits.

LOSS

100×=

⎛
⎜

PP (10)

OUT

⎜
⎝

CIN

2

× DCR (12)

I

⎛

RMS

⎜

2

⎝

IOUT

CIN

) of the ADP2126/ADP2127 is only a

D

) and efficiency (η):

(8)

OUT

(9)

.

LOSS

⎞

100

⎟

−= 1

⎟

η

⎠

), the inductor (PL),

D

), and the output capacitor (P

+ P

CIN

2

⎞

ESR

⎟
⎠

)2 × ESR

+ P

COUT

L

OUT

(11)

COUT

(13)

CIN

(14)

COUT

(15)

can be used in Equation 7 to

D

100

η

−≈−≈ 1

⎞
⎟

PPPPP −

(17)

L

⎟
⎠

⎛
⎜

⎜
⎝

COUT

), as

Rev. B | Page 15 of 20

ADP2126/ADP2127 Data Sheet

PCB LAYOUT GUIDELINES

To ensure package reliability, consider the following guidelines
when designing the footprint for the ADP2126/ADP2127. The
BUMPED_CHIP device footprint must ultimately be determined
according to application and customer specific reliability
requirements, PCB fabrication quality, and PCB assembly
capabilities.

The Cu pad on the PCB for each solder bump should be

•

80% to 100% of the width of the solder bump. A smaller
pad opening favors solder joint reliability (SJR) performance,
whereas a larger pad opening favors drop test performance.
The maximum pad size, including tolerance, should not
exceed 180 µm.

Electroplated nickel, immersion gold (ENIG) and organic

•

solderability preservative (OSP) were used for internal
reliability testing and are recommended.

Nonsolder mask defined (NSMD) Cu pads are recommended

•

for the BUMPED_CHIP package.

The solder mask opening should be approximately 100 µm

•

larger than the pad opening.

•

The trace width should be less than two-thirds the size of

the pad opening.

•

The routing of traces from the Cu pads should be symmetrical

in X and Y directions. Symmetrical routing of the traces
prevents part rotation due to uneven solder wetting/surface
tension forces.

Stencil design is important for proper transfer of paste onto

•

the Cu pads. Area ratio (AR), the relationship between the
surface area of the stencil aperture and the inside surface
area of the aperture walls, is critically important. Stencil
thickness has the greatest impact on this ratio. AR values
from 0.66 to 0.8 provide the best paste transfer efficiency
and repeatability. The AR is calculated from

Ap

Aw

AR =

where:

Ap is the area of the aperture opening.
Aw is the wall area.

Figure 31. ADP2126/ADP2127 Recommended Top Layer Layout

Figure 32. ADP2126/ADP2127 Recommended Bottom Layer Layout

For high efficiency, good regulation, and stability, a well-designed
and manufactured PCB is required.

Use the following guidelines when designing PCBs:

Keep the low ESR input capacitor, C

•

, close to VIN

IN

and GND.

•

Keep high current traces as short and as wide as possible.

•

Avoid routing high impedance traces near any node

connected to SW or near the inductor to prevent
radiated noise injection.

•

Keep the low ESR output capacitor, C

, close to the FB

OUT

and GND pins of the ADP2126/ADP2127. Long trace
lengths from the part to the output capacitor add series
inductance that may cause instability or increased ripple.

09658-031

09658-032

Rev. B | Page 16 of 20

Data Sheet ADP2126/ADP2127

OUTLINE DIMENSIONS

0.940

0.900

BALL A1

IDENTIFIER

0.330

0.315

0.300

SEATING

PLANE

0.860

TOP VIE W

(BALL SIDE DOWN)

END VIEW

0.190

0.170

0.150

1.340

1.300

1.260

0.225 TYP

0.80
REF

COPLANARITY

0.05 NOM

0.09 TYP

0.40
REF

0.40 REF

Figure 33. 6-Ball Bumped Bare Die Sales [BUMPED_CHIP]

(CD-6-4)

Dimensions shown in millimeters

12

BOTTOM VIEW

(BALL SIDE UP)

A

B

C

05-10-2010-A

0.200

1.340

1.300

1.260

MIN

ROTATED 90° CCW

0.175

0.150

DETAIL A

SEATING
PLANE

BARE Cu FIDUCIAL

PAD PITCH

DETAIL A

0.15 DIA.

0.80

REF

0.40

0.17

DIA.

BOTTOM VIEW

(PAD SIDE UP)

0.40 REF

12

A

B

C

0.13
DIA.

04-25-2011-A

0.940

0.900

0.860

TOP VIEW

(PAD SIDE DOWN)

0.008

Figure 34. 6-Pad Embedded Wafer Level Package [EWLP]

(CN-6-1)

Dimensions shown in millimeters

THE ADP2126 HAS AN A1 BALL IDENTIFIER THAT IS VI SIBLE
ON THE TOP OF THE PART.
THE ADP2127 HAS NO VISIBLE MARKING ON THE TOP,
BUT THE A1 PIN LOCATION IS THE SAME.

1

2

A
B
C

DIRECTI ON OF FEED

09658-035

Figure 35. Tape and Reel Orientation for the ADP2126/ADP2127

Rev. B | Page 17 of 20

ADP2126/ADP2127 Data Sheet

ORDERING GUIDE

Output

Model1

Voltage

ADP2126ACDZ-1.20R7 1.20 V Clock and logic −40°C to +85°C 6-Ball Bumped Bare Die Sales [BUMPED_CHIP] CD-6-4 LHY
ADP2127ACNZ-1.20R7 1.20 V Clock and logic −40°C to +85°C 6-Pad Embedded Wafer Level [EWLP] CN-6-1
ADP2127ACNZ1.260R7 1.26 V Clock only −40°C to +85°C 6-Pad Embedded Wafer Level [EWLP] CN-6-1
ADP2126-1.2-EVALZ 1.20 V Clock and logic Evaluation Board for ADP2126

1

Z = RoHS Compliant Part.

2

These package options are halide free.`

3

The ADP2127 does not have a Pin 1 indicator or a branding code. The bare Cu fiducial on the pad side can be used for device orientation.

EXTCLK
Enable Type

Temperature
Range Package Description

Package
Option2 Branding3

Rev. B | Page 18 of 20

Data Sheet ADP2126/ADP2127

NOTES

Rev. B | Page 19 of 20

ADP2126/ADP2127 Data Sheet

NOTES

©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09658-0-3/12(B)

Rev. B | Page 20 of 20