Datasheet ADP1875 Datasheet (ANALOG DEVICES)

Synchronous Buck Controller with Constant

V

V

V

FEATURES

Power input voltage range: 2.95 V to 20 V
On-board bias regulator
Minimum output voltage: 0.6 V

0.6 V reference voltage with ±1.0% accuracy
Supports all N-channel MOSFET power stages
Available in 300 kHz, 600 kHz, and 1.0 MHz options
No current-sense resistor required
Power saving mode (PSM) for light loads (ADP1875 only)
Resistor programmable current limit
Power good with internal pull-up resistor
Externally programmable soft start
Thermal overload protection
Short-circuit protection
Standalone precision enable input
Integrated bootstrap diode for high-side drive
Starts into a precharged output
Available in a 16-lead QSOP package

APPLICATIONS

Telecom and networking systems
Mid- to high-end servers
Set-top boxes
DSP core power supplies

GENERAL DESCRIPTION

The ADP1874/ADP1875 are versatile current mode, synchronous
step-down controllers. They provide superior transient response,
optimal stability, and current-limit protection by using a constant
on-time, pseudo fixed frequency with a programmable current
limit, current control scheme. In addition, these devices offer
optimum performance at low duty cycles by using a valley, current
mode control architecture. This allows the ADP1874/ADP1875
to drive all N-channel power stages to regulate output voltages
to as low as 0.6 V.

The ADP1875 is the power saving mode (PSM) version of
the device and is capable of pulse skipping to maintain output
regulation while achieving improved system efficiency at light
loads (see the ADP1875 Power Saving Mode (PSM) section for
more information).

Available in three frequency options (300 kHz, 600 kHz, and

1.0 MHz, plus the PSM option), the ADP1874/ADP1875 are well
suited for a wide range of applications that require a single-input
power supply range from 2.95 V to 20 V. Low voltage biasing is
supplied via a 5 V internal low dropout regulator (LDO).

On-Time and Valley Current Mode

ADP1874/ADP1875

TYPICAL APPLICATIONS CIRCUIT

= 2.95V TO 20

IN

C

C

C

C2

R

C

10k

REG

R

TOP

V

OUT

R

BOT

C

VREG2

C

VREG

R

RES

100

VIN = 5V (PSM)

95
90
85
80
75
70
65
60

VIN = 13V (PSM)

55

EFFICIENCY (%)

50
45

VIN = 16.5V (PSM)

40
35
30
25

10 100 1k 10k 100k

Figure 2. ADP1874/ADP1875 Efficiency vs. Load Current (V

In addition, soft start programmability is included to limit input in­rush current from the input supply during startup and to
provide reverse current protection during precharged output
conditions. The low-side current sense, current gain scheme, and
integration of a boost diode, along with the PSM/forced pulse­width modulation (PWM) option, reduce the external part count
and improve efficiency.

The ADP1874/ADP1875 operate over the −40°C to +125°C
junction temperature range and are available in a 16-lead QSOP
package.

VIN

ADP1874/

ADP1875

COMP BST

EN

DRVH

FB

GND

VREG

VREG_IN
RES

SW

DRVL

PGOOD

TRACK

PGND

SS

C

IN

C

Q1

BST

C

Q2

R

PGD

V

EXT

C

SS

R

TRK2

R

TRK1

Figure 1. Typical Applications Circuit

VIN = 16.5V

VIN = 13V

TA = 25°C
V

= 1.8V

OUT

f

= 300kHz

SW

WÜRTH INDUCTOR:
744325120, L = 1.2µH, DCR = 1.8m

INFINEON FETs:
BSC042N03MS G (UPPER/LOWER)

LOAD CURRENT (mA)

L

OUT

LOAD

V

MASTER

= 1.8 V, 300 kHz)

OUT

V

OUT

09347-001

09347-102

Rev. 0

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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: [phone] www.analog.com
Fax: [phone] ©2011 Analog Devices, Inc. All rights reserved.

ADP1874/ADP1875

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Typical Applications Circuit............................................................ 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 6

Thermal Resistance ...................................................................... 6

Boundary Condition .................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

ADP1874/ADP1875 Block Digram.............................................. 18

Theory of Operation ...................................................................... 19

Startup.......................................................................................... 19

Soft Start ...................................................................................... 19

Precision Enable Circuitry ........................................................19

Undervoltage Lockout ............................................................... 19

On-Board Low Dropout Regulator.......................................... 20

Thermal Shutdown..................................................................... 20

Programming Resistor (RES) Detect Circuit.......................... 20

Valley Current-Limit Setting .................................................... 20

Hiccup Mode During Short Circuit......................................... 22

Synchronous Rectifier................................................................ 22

ADP1875 Power Saving Mode (PSM) ..................................... 22

Timer Operation ........................................................................ 23

Pseudo-Fixed Frequency........................................................... 24

Power Good Monitoring ........................................................... 24

Voltage Tracking......................................................................... 25

Applications Information.............................................................. 27

Feedback Resistor Divider ........................................................ 27

Inductor Selection...................................................................... 27

Output Ripple Voltage (VRR) .................................................. 27

Output Capacitor Selection....................................................... 27

Compensation Network ............................................................ 28

Efficiency Consideration........................................................... 29

Input Capacitor Selection.......................................................... 30

Thermal Considerations............................................................ 31

Design Example.......................................................................... 32

External Component Recommendations.................................... 34

Layout Considerations................................................................... 36

IC Section (Left Side of Evaluation Board)............................. 38

Power Section ............................................................................. 38

Differential Sensing.................................................................... 39

Typical Application Circuits ......................................................... 40

12 A, 300 kHz High Current Application Circuit.................. 40

5.5 V Input, 600 kHz Application Circuit ............................... 40

300 kHz High Current Application Circuit............................ 41

Outline Dimensions....................................................................... 42

Ordering Guide .......................................................................... 42

REVISION HISTORY

2/11—Revision 0: Initial Version

Rev. 0 | Page 2 of 44

ADP1874/ADP1875

SPECIFICATIONS

All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). VREG = 5 V,
BST − SW = VREG − V

RECT_DROP

unless otherwise specified.

Table 1.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

POWER SUPPLY CHARACTERISTICS

High Input Voltage Range VIN C
ADP1874ARQZ-0.3/ADP1875ARQZ-0.3 (300 kHz) 2.95 12 20 V
ADP1874ARQZ-0.6/ADP1875ARQZ-0.6 (600 kHz) 2.95 12 20 V
ADP1874ARQZ-1.0/ADP1875ARQZ-1.0 (1.0 MHz) 3.25 12 20 V
Quiescent Current I
Shutdown Current I
Undervoltage Lockout UVLO Rising VIN (see Figure 35 for temperature variation) 2.65 V
UVLO Hysteresis Falling VIN from operational state 190 mV

INTERNAL REGULATOR

CHARACTERISTICS

VREG Operational Output Voltage VREG C
ADP1874ARQZ-0.3/ADP1875ARQZ-0.3 (300 kHz) 2.75 5 5.5 V
ADP1874ARQZ-0.6/ADP1875ARQZ-0.6 (600 kHz) 2.75 5 5.5 V
ADP1874ARQZ-1.0/ADP1875ARQZ-1.0 (1.0 MHz) 3.05 5 5.5 V
VREG Output in Regulation VIN = 7 V, 100 mA 4.82 4.981 5.16 V
V
Load Regulation 0 mA to 100 mA, VIN = 7 V 32 mV
0 mA to 100 mA, VIN = 20 V 34 mV
Line Regulation VIN = 7 V to 20 V, 20 mA 2.5 mV
V
VIN to VREG Dropout Voltage 100 mA out of VREG, VIN ≤ 5 V 300 415 mV
Short VREG to PGND VIN = 20 V 229 320 mA

SOFT START

Soft Start Period Calculation

ERROR AMPLIFER

FB Regulation Voltage VFB T
T
T
Transconductance Gm 320 496 670 μS
FB Input Leakage Current I

CURRENT-SENSE AMPLIFIER GAIN

Programming Resistor (RES)

Value from RES to PGND
RES = 22 kΩ ± 1% 5.5 6 6.5 V/V
RES = none 11 12 13 V/V
RES = 100 kΩ ± 1% 22 24 26 V/V

SWITCHING FREQUENCY

ADP1874ARQZ-0.3/

ADP1875ARQZ-0.3 (300 kHz)

On-Time VIN = 5 V, V

Minimum On-Time VIN = 20 V 145 190 ns

Minimum Off-Time 84% duty cycle (maximum) 340 400 ns

(see Figure 40 to Figure 42). VIN = 12 V. The specifications are valid for TJ = −40°C to +125°C,

= 22 μF(25 V rating) to PGND (at Pin 1)

VIN

+ I

Q_REG

REG,SD

FB = 1.5 V, no switching 1.1 mA

Q_BST

+ I

EN < 600 mV 140 225 μA

BST,SD

VREG and VREG_IN tied together and should not be
loaded externally because they are intended to only
bias internal circuitry

= 4.7 μF to PGND, 0.22 μF to GND, VIN = 2.95 V to 20 V

VREG

= 12 V, 100 mA 4.83 4.982 5.16 V

IN

= 7 V to 20 V, 100 mA 2 mV

IN

Connect external capacitor from SS pin to GND,

= 10 nF/ms

C

SS

= 25°C 600 mV

J

= −40°C to +85°C 596 600 604 mV

J

= −40°C to +125°C 594.2 600 605.8 mV

J

FB = 0.6 V, EN = VREG 1 50 nA

FB, LEAK

10 nF/ms

RES = 47 kΩ ± 1% 2.7 3 3.3 V/V

Typical values measured at 50% time points with
0 nF at DRVH and DRVL; maximum values are
guaranteed by bench evaluation

1

300 kHz

= 2 V, TJ = 25°C 1120 1200 1280 ns

OUT

Rev. 0 | Page 3 of 44

ADP1874/ADP1875

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

ADP1874ARQZ-0.6/

ADP1875ARQZ-0.6 (600 kHz)
On-Time VIN = 5 V, V
Minimum On-Time VIN = 20 V, V
Minimum Off-Time 65% duty cycle (maximum) 340 400 ns

ADP1874ARQZ-1.0/

ADP1875ARQZ-1.0 (1.0 MHz)
On-Time VIN = 5 V, V
Minimum On-Time VIN = 20 V 52 85 ns
Minimum Off-Time 45% duty cycle (maximum) 340 400 ns

OUTPUT DRIVER CHARACTERISTICS

High-Side Driver

Output Source Resistance2 I
Output Sink Resistance2 I
Rise Time3 t
Fall Time3 t

Low-Side Driver

Output Source Resistance2 I
Output Sink Resistance2 I
Rise Time3 t
Fall Time3 t

Propagation Delays

DRVL Fall to DRVH Rise3 t

DRVH Fall to DRVL Rise3 t
SW Leakage Current I
Integrated Rectifier

Channel Impedance I

PRECISION ENABLE THRESHOLD

Logic High Level VIN = 2.9 V to 20 V, VREG = 2.75 V to 5.5 V 605 634 663 mV
Enable Hysteresis VIN = 2.9 V to 20 V, VREG = 2.75 V to 5.5 V 31 mV

COMP VOLTAGE

COMP Clamp Low Voltage V

COMP Clamp High Voltage V
COMP Zero Current Threshold V

THERMAL SHUTDOWN T

Thermal Shutdown Threshold Rising temperature 155 °C
Thermal Shutdown Hysteresis 15 °C

CURRENT LIMIT

Hiccup Current Limit Timing COMP = 2.4 V 6 ms

OVERVOLTAGE AND POWER GOOD

THRESHOLDS
FB Power Good Threshold FB
FB Power Good Hysteresis 30 mV
FB Overvoltage Threshold FBOV V
FB Overvoltage Hysteresis 30 mV
PGOOD Low Voltage During Sink V
PGOOD Leakage Current PGOOD = 5 V 1 400 nA

600 kHz

= 2 V, TJ = 25°C 500 540 580 ns

OUT

= 0.8 V 82 110 ns

OUT

1.0 MHz

= 2 V, TJ = 25°C 285 312 340 ns

OUT

= 1.5 A, 100 ns, positive pulse (0 V to 5 V) 2.25 3 Ω

SOURCE

= 1.5 A, 100 ns, negative pulse (5 V to 0 V) 0.70 1 Ω

SINK

BST − SW = 4.4 V, CIN = 4.3 nF (see Figure 59) 25 ns

r, DR VH

BST − SW = 4.4 V, CIN = 4.3 nF (see Figure 60) 11 ns

f, DRV H

= 1.5 A, 100 ns, positive pulse (0 V to 5 V) 1.6 2.2 Ω

SOURCE

= 1.5 A, 100 ns, negative pulse (5 V to 0 V) 0.7 1 Ω

SINK

VREG = 5.0 V, CIN = 4.3 nF (see Figure 60) 18 ns

r,DR VL

VREG = 5.0 V, CIN = 4.3 nF (see Figure 59) 16 ns

f,DRV L

BST − SW = 4.4 V (see Figure 59) 15.4 ns

tpdhDRVH

BST − SW = 4.4 V (see Figure 60) 18 ns

tpdhDRVL

BST = 25 V, SW = 20 V, VREG = 5 V 110 μA

SWLEAK

= 10 mA 22 Ω

SINK

COMP(LOW )

Tie EN pin to VREG to enable device

0.47 V

(2.75 V ≤ VREG ≤ 5.5 V)

(2.75 V ≤ VREG ≤ 5.5 V) 2.55 V

COMP(H IGH)

(2.75 V ≤ VREG ≤ 5.5 V) 1.15 V

COMP_ZC T

TMSD

PGOOD

PGD

PGOOD

VFB rising during system power-up 542 566 mV

rising during overvoltage event, I

FB

I

= 1 mA 143 200 mV

PGOOD

Rev. 0 | Page 4 of 44

= 1 mA 691 710 mV

PGOOD

ADP1874/ADP1875

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

TRACKING

Track Input Voltage Range 0 5 V
FB-to-Tracking Offset Voltage 0.5 V < TRACK < 0.6 V, offset = VFB − V
Leakage Current V

1

The maximum specified values are with the closed loop measured at 10% to 90% time points (see Figure and Figure 60), C

MOSFETs being Infineon BSC042N03MS G.

2

Guaranteed by design.

3

Not automatic test equipment (ATE) tested.

= 5 V 1 50 nA

TRACK

63 mV

TRACK

59

= 4.3 nF, and the upper- and lower-side

GATE

Rev. 0 | Page 5 of 44

ADP1874/ADP1875

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

VREG, VREG_IN, TRACK to PGND, GND −0.3 V to +6 V
VIN, EN, PGOOD to PGND −0.3 V to +28 V
FB, COMP, RES, SS to GND −0.3 V to (VREG + 0.3 V)
DRVL to PGND −0.3 V to (VREG + 0.3 V)
SW to PGND −2.0 V to +28 V
BST to SW −0.6 V to (VREG + 0.3 V)
BST to PGND −0.3 V to +28 V
DRVH to SW −0.3 V to VREG
PGND to GND ±0.3 V
PGOOD Input Current 35 mA
θJA (16-Lead QSOP)

4-Layer Board 104°C/W

Operating Junction Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Soldering Conditions JEDEC J-STD-020
Maximum Soldering Lead Temperature

(10 sec)

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all other voltages are
referenced to PGND.

300°C

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 3. Thermal Resistance

Package Type θJA Unit

θJA (16-Lead QSOP)

4-Layer Board 104° °C/W

BOUNDARY CONDITION

In determining the values given in Ta b le 2 and Tabl e 3, natural
convection is used to transfer heat to a 4-layer evaluation board.

ESD CAUTION

Rev. 0 | Page 6 of 44

ADP1874/ADP1875

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VIN

1

COMP

2

3

EN

ADP1874/

ADP1875

FB

4

GND

RES

VREG

VREG_IN

TOP VIEW

5

(Not to Scale)

6

7

8

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin

No.

Mnemonic Description

1 VIN High-Side Input Voltage. Connect VIN to the drain of the upper-side MOSFET.

2 COMP

Output of the Error Amplifier. Connect the compensation network between this pin and AGND to achieve stability

(see the Compensation Network section).
3 EN Connect to VREG to Enable IC. When pulled down to AGND externally, disables the IC.
4 FB Noninverting Input of the Internal Error Amplifier. This is the node where the feedback resistor is connected.
5 GND

Analog Ground Reference Pin of the IC. All sensitive analog components should be connected to this ground plane

(see the Layout Considerations section).
6 RES Current Sense Gain Resistor (External). Connect a resistor between the RES pin and GND (Pin 5).
7 VREG

Internal Regulator Supply Bias Voltage for the ADP1874/ADP1875 Controller (Includes the Output Gate Drivers). A

bypass capacitor of 1 μF directly from this pin to PGND and a 0.1 μF across VREG and GND are recommended.
8 VREG_IN Input to the Internal LDO. Tie this pin directly to Pin 7 (VREG).
9 TRACK

Tracking Input. If the tracking function is not used, it is recommended to connect TRACK to VREG through a resistor

higher than 1 MΩ or simply connect TRACK between 0.7 V and 2 V to reduce the bias current going into the pin.
10 SS

Soft Start Input. Connect an external capacitor to GND to program the soft start period. Capacitance value of 10 nF for

every 1 ms of soft start delay.
11 PGOOD

Open-Drain Power Good Output. Sinks current when FB is out of regulation or during thermal shutdown. Connect a

3 kΩ resistor between PGOOD and VREG. Leave unconnected if not used.
12 DRVL

Drive Output for the External Lower-Side, N-Channel MOSFET. This pin also serves as the current-sense gain setting

pin (see Figure 69).
13 PGND Power GND. Ground for the lower-side gate driver and lower-side, N-channel MOSFET.
14 DRVH Drive Output for the External Upper-Side, N-Channel MOSFET.
15 SW Switch Node Connection.
16 BST

Bootstrap for the Upper-Side MOSFET Gate Drive Circuitry. An internal boot rectifier (diode) is connected between

VREG and BST. A capacitor from BST to SW is required. An external Schottky diode can also be connected between

VREG and BST for increased gate drive capability.

16

15

14

13

12

11

10

9

BST
SW

DRVH
PGND
DRVL
PGOOD

SS
TRACK

09347-003

Rev. 0 | Page 7 of 44

ADP1874/ADP1875

TYPICAL PERFORMANCE CHARACTERISTICS

100

95
90

VIN = 13V (PSM)

85
80
75
70
65
60
55
50
45
40

EFFICIENCY (%)

35

VIN = 16.5V (PSM)

30
25
20
15
10

5
0

10 100 1k 10k 100k

TA = 25°C
V

OUT

f

= 300kHz

SW

WÜRTH INDUCTOR:
744325072, L = 0.72µH, DCR = 1.3m

INFINEON FETs:
BSC042N03MS G (UPPER/LOWER)

LOAD CURRENT (mA)

Figure 4. Efficiency—300 kHz, V

VIN = 13V

= 0.8V

VIN = 16.5V

= 0.8 V

OUT

09347-104

100

95
90
85
80
75
70
65
60
55
50
45
40

EFFICIENCY (%)

35
30
25
20
15
10

5
0

10 100 1k 10k 100k

VIN = 13V (PSM)

VIN = 16.5V

(PSM)

Figure 7. Efficiency—600 kHz, V

VIN = 13V

VIN = 16.5V

TA = 25°C

= 0.8V

V

OUT

f

= 600kHz

SW

WÜRTH INDUCTOR:
744355147, L = 0.47µH, DCR = 0.67m

INFINEON FETs:
BSC042N03MS G (UPPER/LOWER)

LOAD CURRENT (mA)

= 0.8 V

OUT

09347-107

100

95

VIN = 5V (PSM)

90
85
80
75
70
65
60
55
50
45
40

EFFICIENCY (%)

35
30
25
20
15
10

5
0

VIN = 13V (PSM)

VIN = 16.5V (PSM)

10 100 1k 10k 100k

LOAD CURRENT (mA)

Figure 5. Efficiency—300 kHz, V

VIN = 16.5V

VIN = 13V

TA = 25°C

= 1.8V

V

OUT

f

= 300kHz

SW

WÜRTH INDUCTOR:
744325120, L = 1.2µH, DCR = 1.8m

INFINEON FETs:
BSC042N03MS G (UPPER/LOWER)

= 1.8 V

OUT

100

VIN = 16.5V (PSM)

95
90
85
80
75

VIN = 13V (PSM)

70
65
60
55
50
45
40

EFFICIENCY (%)

35
30
25
20
15
10

5
0

10 100 1k 10k 100k

Figure 6. Efficiency—300 kHz, V

VIN = 13V

VIN = 16.5V

TA = 25°C

= 7V

V

OUT

f

= 300kHz

SW

WÜRTH INDUCTOR:
7443551200, L = 2.0µH, DCR = 2.6m

INFINEON FETs:
BSC042N03MS G (UPPER/LOWER)

LOAD CURRENT (mA)

= 7 V

OUT

100

95
90
85

VIN = 13V (PSM)

80
75
70
65
60
55
50

VIN = 16.5V (PSM)

45
40

EFFICIENCY (%)

35
30
25
20
15
10

5
0

10 100 1k 10k 100k

09347-105

Figure 8. Efficiency—600 kHz, V

VIN = 13V

VIN = 16.5V

TA = 25°C

= 1.8V

V

OUT

f

= 600kHz

SW

WÜRTH INDUCTOR:
744325072, L = 0.72µH, DCR = 1.3m

INFINEON FETs:
BSC042N03MS G (UPPER/LOWER)

LOAD CURRENT (mA)

= 1.8 V

OUT

09347-108

100

95
90

VIN = 16.5V (PSM)

85
80
75
70
65
60
55
50
45
40

EFFICIENCY (%)

35
30
25
20
15
10

5
0

10 100 1k 10k 100k

09347-106

VIN = 13V (PSM)

VIN = 20V (PSM)

VIN = 20V

TA = 25°C
V

OUT

f

= 600kHz

SW

WÜRTH INDUCTOR:
744318180, L = 1.4µH, DCR = 3.2m

INFINEON FETs:
BSC042N03MS G (UPPER/LOWER)

LOAD CURRENT (mA)

Figure 9. Efficiency—600 kHz, V

VIN = 16.5V

= 5V

OUT

= 5 V

09347-109

Rev. 0 | Page 8 of 44

ADP1874/ADP1875

100

95
90
85
80
75
70

VIN = 13V (PSM)

65
60
55
50
45
40

EFFICIENCY (%)

35
30

VIN = 16.5V (PSM)

25
20
15
10

5
0

10 100 1k 10k 100k

Figure 10. Efficiency—1.0 MHz, V

VIN = 13V

VIN = 16.5V

TA = 25°C

= 0.8V

V

OUT

f

= 1.0MHz

SW

WÜRTH INDUCTOR:
744303012, L = 0.12µH, DCR = 0.33m

INFINEON FETs:
BSC042N03MS G (UPPER/LOWER)

LOAD CURRENT (mA)

= 0.8 V

OUT

09347-110

0.807

0.806

0.805

0.804

0.803

0.802

0.801

0.800

0.799

0.798

0.797

OUTPUT VOLTAGE (V)

0.796

0.795
VIN = 13V

0.794

0.793

0.792

+125°C
+25°C
–40°C

0 2000 4000 6000 8000 10,000

VIN = 16.5V

+125°C
+25°C
–40°C

LOAD CURRENT (mA)

Figure 13. Output Voltage Accuracy—300 kHz, V

OUT

= 0.8 V

09347-013

100

95
90
85
80

VIN = 13V (PSM)

75
70
65
60
55
50
45
40

VIN = 16.5V (PSM)

EFFICIENCY (%)

35
30
25
20
15
10

5
0

10 100 1k 10k 100k

Figure 11. Efficiency—1.0 MHz, V

VIN = 13V

VIN = 16.5V

TA = 25°C

= 1.8V

V

OUT

f

= 1.0MHz

SW

WÜRTH INDUCTOR:
744303022, L = 0.22µH, DCR = 0.33m

INFINEON FETs:
BSC042N03MS G (UPPER/LOWER)

LOAD CURRENT (mA)

= 1.8 V

OUT

100

95
90
85

VIN = 13V (PSM)

80
75
70
65
60
55

VIN = 16.5V (PSM)

50
45
40

EFFICIENCY (%)

35
30
25
20
15
10

5
0

10 100 1k 10k 100k

TA = 25°C
V

OUT

f

SW

WÜRTH INDUCTOR:
744355090, L = 0.9µH, DCR = 1.6m

INFINEON FETs:
BSC042N03MS G (UPPER/LOWER)

LOAD CURRENT (mA)

Figure 12. Efficiency—1.0 MHz, V

VIN = 16.5V

= 5V

= 1.0MHz

VIN = 13V

= 5 V

OUT

1.821

1.816

1.811

1.806

1.801

OUTPUT VOLTAGE (V)

1.796

1.791

1.786

0 1500 3000 4500 6000 7500 9000 10,500 12,000 13,500 15,000

09347-111

VIN = 5.5V

+125°C
+25°C
–40°C

Figure 14. Output Voltage Accuracy—300 kHz, V

VIN = 13V

+125°C
+25°C
–40°C

LOAD CURRENT (mA)

VIN = 16.5V

+125°C
+25°C
–40°C

OUT

= 1.8 V

09347-014

7.100

7.095

7.090

7.085

7.080

7.075

7.070

7.065

7.060

7.055

7.050

7.045

7.040

7.035

7.030

OUTPUT VOLTAGE (V)

7.025

7.020

7.015

7.010

7.005

7.000

09347-112

Figure 15. Output Voltage Accuracy—300 kHz, V

+125°C
+25°C
–40°C

0 1000 2000 3000 4000 5000 6000 7000 8000 9000

VIN = 13V
VIN = 16.5V

LOAD CURRENT (mA)

OUT

= 7 V

09347-015

Rev. 0 | Page 9 of 44

ADP1874/ADP1875

0.808

0.806

0.804

0.802

0.800

0.798

FREQUENCY (kHz)

0.796

0.794

0.792

+125°C
+25°C
–40°C

0 1000 2000 3000 4000 5000 6000 7000 8000 10,0009000

VIN = 13V
VIN = 16.5V

LOAD CURRENT (mA)

Figure 16. Output Voltage Accuracy—600 kHz, V

OUT

= 0.8 V

09347-115

0.807

0.805

0.803

0.801

0.799

0.797

0.795

0.793

OUTPUT VOLTAGE (V)

0.791

0.789

0.787
0 2000 4000 6000 8000 10,000

VIN = 13V

LOAD CURRENT (mA)

+125°C
+25°C
–40°C

VIN = 16.5V

+125°C
+25°C
–40°C

Figure 19. Output Voltage Accuracy—1.0 MHz, V

OUT

= 0.8 V

09347-118

1.818

1.816

1.814

1.812

1.810

1.808

1.806

1.804

1.802

1.800

1.798

1.796

1.794

1.792

1.790

1.788

1.786

1.784

OUTPUT VOLTAGE (V)

1.782

1.780

1.778

1.776

1.774

1.772

1.770
0 12,00010,500900075006000450030001500

VIN = 13V

LOAD CURRENT (mA)

+125°C
+25°C
–40°C

VIN = 16.5V

+125°C
+25°C
–40°C

Figure 17. Output Voltage Accuracy—600 kHz, V

5.030

5.025

5.020

5.015

5.010

5.005

5.000

4.995

4.990

OUTPUT VOLTAGE (V)

4.985

4.980

4.975

4.970

+125°C
+25°C
–40°C

0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000

VIN = 13V
VIN = 16.5V
VIN = 20V

LOAD CURRENT (mA)

Figure 18. Output Voltage Accuracy—600 kHz, V

OUT

OUT

= 1.8 V

= 5 V

1.820

1.815

1.810

1.805

1.800

OUTPUT VOLTAGE (V)

1.795

1.790

0

09347-016

VIN = 13V

LOAD CURRENT (mA)

Figure 20. Output Voltage Accuracy—1.0 MHz, V

+125°C
+25°C
–40°C

VIN = 16.5V

+125°C
+25°C
–40°C

OUT

= 1.8 V

10,0000 1000 2000 3000 4000 5000 6000 7000 8000 9000

09347-019

5.04

5.03

5.02

5.01

5.00

4.99

4.98

4.97

4.96

4.95

OUTPUT VOLTAGE (V)

4.94

4.93

4.92

4.91

4.90

09347-017

Figure 21. Output Voltage Accuracy—1.0 MHz, V

VIN = 13V

LOAD CURRENT (mA)

+125°C
+25°C
–40°C

VIN = 16.5V

+125°C
+25°C
–40°C

7200640056004800400024001600 32000 960088008000800

OUT

=5 V

09347-020

Rev. 0 | Page 10 of 44

ADP1874/ADP1875

601.0

600.5

600.0

599.5

599.0

598.5

FEEDBACK VOLTAGE (V)

598.0

597.5

597.0
–40.0 –7.5 25.0 57.5 90.0 122.5

VREG = 5V, V

VREG = 5V, VIN = 13V

= 20V

IN

TEMPERATURE (° C)

Figure 22. Feedback Voltage vs. Temperature

09347-121

900

880

860

840

820

800

780

760

SWITCHING FREQUENCY (kHz)

740

720

700

13.0 13.5 14. 0 14.5 15. 0 15.5 16.0 16.5

+125°C
+25°C
–40°C

VIN (V)

Figure 25. Switching Frequency vs. High Input Voltage, 1.0 MHz,

Range = 13 V to 16.5 V

V

IN

09347-124

325

315

305

295

285

275

SWITCHING FREQUENCY (kHz)

265

255

10.8 11. 0 11.2 11.4 11.6 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2

+125°C
+25°C
–40°C

VIN (V)

NO LOAD

09347-022

Figure 23. Switching Frequency vs. High Input Voltage, 300 kHz, ±10% of 12 V

650

600

550

500

SWITCHING FREQUENCY (kHz)

450

400

13.0 13.4 13.8 14.2 14.6 15.0 15.4 15.8 16. 2 16.5

Figure 24. Switching Frequency vs. High Input Voltage, 600 kHz, V

+125°C
+25°C
–40°C

Range = 13 V to 16.5 V

V

IN

VIN (V)

NO LOAD

= 1.8 V,

OUT

09347-123

280

265

250

235

220

FREQUENCY (kHz)

205

190

VIN = 13V
VIN = 20V
VIN = 16.5V

0 10,0008000600040002000

+125°C
+25°C
–40°C

LOAD CURRENT (mA)

Figure 26. Frequency vs. Load Current, 300 kHz, V

330

320

310

300

290

280

270

FREQUENCY (kHz)

260

250

240

0 15,00012,000 13,50010,500900075006000450030001500

VIN = 20V
VIN = 13V
VIN = 16.5V

+125°C
+25°C
–40°C

LOAD CURRENT (mA)

Figure 27. Frequency vs. Load Current, 300 kHz, V

OUT

OUT

= 0.8 V

= 1.8 V

09347-025

09347-026

Rev. 0 | Page 11 of 44

ADP1874/ADP1875

338

334

330

326

322

318

314

FREQUENCY (kHz)

310

306

302

298

0 6400 7200 8000 8800560048004000320024001600800

VIN = 13V
VIN = 16.5V

+125°C
+25°C
–40°C

LOAD CURRENT (mA)

Figure 28. Frequency vs. Load Current, 300 kHz, V

OUT

= 7 V

09347-027

740
733
726
719
712
705
698
691
684
677
670
663

FREQUENCY (kHz)

656
649
642
635
628
621

0 96008800800072006400560048004000320024001600800

VIN = 13V
VIN = 16.5V

+125°C
+25°C
–40°C

LOAD CURRENT (mA)

Figure 31. Frequency vs. Load Current, 600 kHz, V

OUT

= 5 V

09347-030

540

510

480

450

420

390

FREQUENCY (kHz)

360

330

300

VIN = 13V
VIN = 16.5V

0 12,0001200 2400 3600 4800 6000 7200 8400 9600 10,800

+125°C
+25°C
–40°C

LOAD CURRENT (mA)

Figure 29. Frequency vs. Load Current, 600 kHz, V

675

655

635

615

595

575

555

FREQUENCY (kHz)

535

515

495

VIN = 13V
VIN = 16.5V

0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000

LOAD CURRENT (mA)

Figure 30. Frequency vs. Load Current, 600 kHz, V

OUT

OUT

= 0.8 V

+125°C
+25°C
–40°C

= 1.8 V

850

775

700

625

550

FREQUENCY (kHz)

475

400

09347-028

Figure 32. Frequency vs. Load Current, V

VIN = 13V
VIN = 16.5V

0 12,00010,0008000600040002000

+125°C
+25°C
–40°C

LOAD CURRENT (mA)

= 1.0 MHz, 0.8 V

OUT

09347-031

1225

1150

1075

1000

925

850

775

FREQUENCY (kHz)

700

625

550

09347-029

Figure 33. Frequency vs. Load Current, 1.0 MHz, V

VIN = 13V +125°C
VIN = 16.5V

0 12,0009600 10,8008400720060004800360024001200

+25°C
–40°C

LOAD CURRENT (mA)

= 1.8 V

OUT

09347-032

Rev. 0 | Page 12 of 44

ADP1874/ADP1875

1450

1400

1350

1300

1250

1200

1150

FREQUENCY (kHz)

1100

1050

1000

08000

Figure 34. Frequency vs. Load Current, 1.0 MHz, V

= 13V +125°C

V

IN

= 16.5V

V

IN

800 1600 2400 3200 4000 4800 5600 6400 7200

LOAD CURRENT (mA)

+25°C
–40°C

OUT

= 5 V

09347-033

82

80

78

76

74

72

70

68

MAXIMUM DUTY CYCLE (%)

66

64

62

5.5 6.7 7.9 9.1 10.3 11.5 12.7 13.9 15.1 16.3

+125°C
+25°C
–40°C

VIN (V)

Figure 37. Maximum Duty Cycle vs. High Voltage Input (V

09347-036

)

IN

2.658

2.657

2.656

2.655

2.654

2.653

UVLO (V)

2.652

2.651

2.650

2.649

–40 120100806040200–20

TEMPERATURE (°C)

Figure 35. UVLO vs. Temperature

95

90

85

80

75

70

65

MAXIMUM DUTY CYCLE (%)

60

55

300 400 500 600 700 800 900 1000

FREQUENCY (kHz)

Figure 36. Maximum Duty Cycle vs. Frequency

+125°C
+25°C
–40°C

680

630

580

530

480

430

380

330

MINUMUM OFF-TIME (ns)

280

230

180

–40 120100806040200–20

09347-034

VREG = 2.7V
VREG = 3.6V
VREG = 5.5V

TEMPERATURE (° C)

09347-037

Figure 38. Minimum Off-Time vs. Temperature

680

630

580

530

480

430

380

330

MINUMUM OFF-TIME (ns)

280

230

180

2.7 5.55.14.74.33.93.53.1

09347-035

VREG (V)

+125°C
+25°C
–40°C

09347-038

Figure 39. Minimum Off-Time vs. VREG (Low Input Voltage)

Rev. 0 | Page 13 of 44

ADP1874/ADP1875

800

720

640

560

480

400

320

RECTIFIER DROP (mV)

240

160

80

300 400 500 600 700 800 900 1000

VREG = 2.7V
VREG = 3.6V
VREG = 5.5V

+125°C
+25°C
–40°C

FREQUENCY (kHz)

Figure 40. Internal Rectifier Drop vs. Frequency

09347-039

80

72

64

56

48

40

32

24

BODY DIODE CONDUCTION TIME (ns)

16

8

2.73.13.53.94.34.75.15.5

300kHz +125°C
1MHz

VREG (V)

+25°C
–40°C

Figure 43. Lower-Side MOSFET Body Diode Conduction Time vs. VREG

09347-042

1280
1200
1120
1040

960
880
800
720
640
560
480

RECTIFIER DROP (mV)

400
320
240
160

80

2.73.13.53.94.34.75.15.5

VIN = 5.5V
VIN = 13V
VIN = 16.5V

1MHz
300kHz

VREG (V)

TA = 25°C

Figure 41. Internal Boost Rectifier Drop vs. VREG (Low Input Voltage)

Variation

Over V

IN

720

640

560

480

400

300kHz +125°C
1MHz

+25°C
–40°C

OUTPUT VOLTAGE

1

2

3

4

CH1 50mV

09347-040

CH3 10V

B

CH2 5A 

W

B

CH4 5V

W

INDUCTOR CURRENT

SW NODE

LOW SIDE

M400ns A CH2 3.90A

T 35.8%

09347-043

Figure 44. Power Saving Mode (PSM) Operational Waveform, 100 mA

OUTPUT VOLTAGE

1

INDUCTOR CURRENT

2

320

RECTIFIER DROP (mV)

240

160

80

2.73.13.53.94.34.75.15.5
VREG (V)

Figure 42. Internal Boost Rectifier Drop vs. VREG

09347-041

Rev. 0 | Page 14 of 44

3

4

CH1 50mV
CH3 10V

B

CH2 5A 

W

B

CH4 5V

W

M4.0µs A CH2 3.90A

T 35.8%

Figure 45. PSM Waveform at Light Load, 500 mA

SW NODE

LOW SIDE

09347-044

ADP1874/ADP1875

OUTPUT VOLTAGE

4

INDUCTOR CURRENT

2

OUTPUT VOLTAGE

1

SW NODE

3

CH1 5A 
CH3 10V CH4 100mV

M400ns A CH3 2.20V

B

T 30.6%

W

Figure 46. CCM Operation at Heavy Load, 12 A

(See Figure 99 for Application Circuit)

OUTPUT VOLTAGE

2

12A STEP

1

3

4

CH1 10A  CH2 200mV
CH3 20V CH4 5V

B

M2ms A CH1 3.40A

W

T 75.6%

Figure 47. Load Transient Step—PSM Enabled, 12 A

(See Figure 99 Application Circuit)

SW NODE

LOW SIDE

1

3

4

CH1 10A  CH2 200mV

09347-045

CH3 20V CH4 5V

12A NEGATIVE STEP

SW NODE

LOW SIDE

B

M20µs A CH1 3.40A

W

T 48.2%

09347-048

Figure 49. Negative Step During Heavy Load Transient Behavior—PSM Enabled,

12 A (See Figure 99 Application Circuit)

4

OUTPUT VOLTAGE

12A STEP

1

2

3

CH1 10A  CH2 5V

09347-046

CH3 20V CH4 200mV

LOW SIDE

SW NODE

M2ms A CH1 6.20A

B

T 15.6%

W

09347-049

Figure 50. Load Transient Step—Forced PWM at Light Load, 12 A

(See Figure 99 Application Circuit)

2

12A POSITIVE STEP

1

3

LOW SIDE

4

CH1 10A  CH2 200mV
CH3 20V CH4 5V

OUTPUT VOLTAGE

SW NODE

B

M20µs A CH1 3.40A

W

T 30.6%

09347-047

Figure 48. Positiv e Step During Heavy Load Trans ient Behavior—PSM Enabled,

12 A, V

= 1.8 V (See Figure 99 Application Circuit)

OUT

Rev. 0 | Page 15 of 44

OUTPUT VOLTAGE

4

12A POSITIVE STEP

1

2

3

SW NODE

CH1 10A  CH2 5V
CH3 20V CH4 200mV

M20µs A CH1 6.20A

B

T 43.8%

W

LOW SIDE

09347-050

Figure 51. Positive Step During Heavy Load Transient Behavior—Forced PWM

at Light Load, 12 A, V

= 1.8 V (See Figure 99 Application Circuit)

OUT

ADP1874/ADP1875

2

OUTPUT VOLTAGE

12A NEGATIVE STEP

1

SW NODE

3

LOW

4

CH1 10A  CH2 200mV
CH3 20V CH4 5V

SIDE

B

M10µs A CH1 5.60A

W

T 23.8%

09347-051

Figure 52. Negative Step During Heavy Load Transient Behavior—Forced PWM

at Light Load, 12 A (See Figure 99 Application Circuit)

1

2

4

OUTPUT VOLTAGE

INDUCTOR CURRENT

LOW SIDE

OUTPUT VOLTAGE

1

INDUCTOR CURRENT

2

LOW SIDE

4

SW NODE

3

B

CH1 2V
CH3 10V CH4 5V

CH2 5A 

W

M2ms A CH1 720mV

T 32.8%

Figure 55. Start-Up Behavior at Heavy Load, 12 A, 300 kHz

(See Figure 99 Application Circuit)

1

2

4

OUTPUT VOLTAGE

INDUCTOR CURRENT

LOW SIDE

09347-054

SW NODE

3

B

CH1 2V
CH3 10V CH4 5V

CH2 5A 

W

M4ms A CH1 920mV

T 49.4%

Figure 53. Output Short-Circuit Behavior Leading to Hiccup Mode

1

OUTPUT VOLTAGE

INDUCTOR CURRENT

2

SW NODE

3

LOW SIDE

4

B

CH1 5V
CH3 10V CH4 5V

CH2 10A 

W

M10µs A CH2 8.20A

T 36.2%

Figure 54. Magnified Waveform During Hiccup Mode

SW NODE

3

B

CH1 2V

09347-052

CH3 10V CH4 5V

CH2 5A 

W

M4ms A CH1 720mV

T 41.6%

09347-055

Figure 56. Power-Down Waveform During Heavy Load

OUTPUT VOLTAGE

1

INDUCTOR CURRENT

2

SW NODE

3

LOW SIDE

4

B

B

W

W

CH2 5A 
CH4 5V

M2µs A CH2 3.90A

T 35.8%

09347-056

CH1 50mV

09347-053

CH3 10V

Figure 57. Output Voltage Ripple Waveform During PSM Operation

at Light Load, 2 A

Rev. 0 | Page 16 of 44

ADP1874/ADP1875

LOW SIDE

TA = 25°C

570

550

VREG = 5.5V
VREG = 3.6V
VREG = 2.7V

4

HIGH SIDE

SW NODE

3

2

M

HS MINUS
SW

CH3 5V
MATH 2V 40ns

CH2 5V
CH4 2V

M40ns A CH2 4.20V

T 29.0%

09347-058

Figure 58. Output Drivers and SW Node Waveforms

HIGH SIDE

t

r

,DRVH

TA = 25°C

)

09347-059

LOW SIDE

4

22ns (

SW NODE

3

2

HS MINUS

M

SW

CH3 5V
MATH 2V 40ns

t

pdh

DRVH

CH2 5V
CH4 2V

16ns (

t

)

f

,DRVL

)

25ns (

M40ns A CH2 4.20V

T 29.0%

Figure 59. Upper-Side Driver Rising and Lower-Side Falling Edge Waveforms

= 4.3 nF (Upper-/Lower-Side MOSFET),

(C

IN

= 27 nC (VGS = 4.4 V (Q1), VGS = 5 V (Q3))

Q

TOTAL

18ns (

t

4

HIGH SIDE

HS MINUS
SW

3

2

M

TA = 25°C

CH3 5V
MATH 2V 20ns

r

,DRVL

CH2 5V
CH4 2V

)

24ns (

t

pdh

11ns (

t

f

,DRVH

M20ns A CH2 4.20V

T 39.2%

,DRVL

)

LOW SIDE

)

SW NODE

09347-060

Figure 60. Upper-Side Driver Falling and Lower-Side Rising Edge Waveforms

= 4.3 nF (Upper-/Lower-Side MOSFET),

(C

IN

= 27 nC (VGS = 4.4 V (Q1), VGS = 5 V (Q3))

Q

TOTAL

530

510

490

470

TRANSCONDUCTANCE (µS)

450

430

–40 –20 120100806040200

TEMPERATURE (°C)

Figure 61. Transconductance (G

680

630

580

530

480

430

TRANSCONDUCTANCE (µs)

380

330

2.7 3.0 5.44.8 5.14.54.23.93.63.3

Figure 62. Transconductance (G

1.30

1.25

1.20

1.15

1.10

1.05

1.00

0.95

0.90

0.85

QUIESCENT CURRENT (mA)

0.80

0.75

0.70

2.7 5.55.14.74.3

Figure 63. Quiescent Current vs. VREG

VREG (V)

+125°C

+25°C

–40°C

3.93.53.1
VREG (V)

) vs. Temperature

m

) vs. VREG

m

+125°C
+25°C
–40°C

09347-061

09347-062

09347-163

Rev. 0 | Page 17 of 44

ADP1874/ADP1875

D

ADP1874/ADP1875 BLOCK DIGRAM

EN

VREG

VREG_IN

COMP

TRACK

SS

FB

ADP1874/ADP1875

PRECISION

ENABLE

EN_REF

I

SS

SS_REF

ERROR
AMP

LOWER

COMP

CLAMP

REF_ZERO

0.6V

REF_ZERO

SS
COMP

TO ENABLE
ALL BLOCKS

LDO

REF

BIAS BLOCK

AND REFERENCE

PSM

PWM

CS

AMP

IREV
COMP

CS GAIN SET

t

TIMER

ON

VREG

STATE

MACHINE

TON
BG_REF

IN_PSM
IN_SS

IN_HICC

PWM
IREV

ADC

SW

HS_O

LS_O

INFORMATION

690mV

FB

600mV

530mV

VREG

C

I

R (TRIMMED)

t

SW FILTER

0.4V

LEVEL
SHIFT

HS

SW

LS

RES DETECT AND
GAIN SET

= 2RC(V

ON

HS

LS

OUT/VIN

VREG

)

300k

8k

800k

PGOO

VIN

BST

DRVH

SW

DRVL

PGND

GND

RES

09347-063

Figure 64. ADP1874/ADP1875 Block Diagram

Rev. 0 | Page 18 of 44

ADP1874/ADP1875

V



THEORY OF OPERATION

The ADP1874/ADP1875 are versatile current mode, synchronous
step-down controllers that provide superior transient response,
optimal stability, and current limit protection by using a constant
on-time, pseudo-fixed frequency with a programmable current­sense gain, current-control scheme. In addition, these devices offer
optimum performance at low duty cycles by using a valley, current
mode control architecture. This allows the ADP1874/ADP1875
to drive all N-channel power stages to regulate output voltages
to as low as 0.6 V.

STARTUP

The ADP1874/ADP1875 have an internal regulator (VREG) for
biasing and supplying power for the integrated MOSFET drivers.
A bypass capacitor should be located directly across the VREG
(Pin 7) and PGND (Pin 13) pins. Included in the power-up
sequence is the biasing of the current-sense amplifier, the current­sense gain circuit (see the Programming Resistor (RES) Detect
Circuit section), the soft start circuit, and the error amplifier.

The current-sense blocks provide valley current information
(see the Programming Resistor (RES) Detect Circuit section)
and are a variable of the compensation equation for loop stability
(see the Compensation Network section). The valley current
information is extracted by forcing a voltage across the RES and
PGND pins, which generates a current depending on the resistor
value across RES and PGND. The current through the resistor is
used to set the current-sense amplifier gain. This process takes
approximately 800 µs, after which the drive signal pulses appear
at the DRVL and DRVH pins synchronously, and the output
voltage begins to rise in a controlled manner through the soft
start sequence.

The rise time of the output voltage is determined by the soft
start and error amplifier blocks (see the Soft Start section). At
the beginning of a soft start, the error amplifier charges the
external compensation capacitor, causing the COMP pin to
begin to rise (see Figure 66). Tying the VREG pin to the EN pin
via a pull-up resistor causes the voltage at this pin to rise above the
enable threshold of 630 mV to enable the ADP1874/ADP1875.

SOFT START

The ADP1874 employs externally programmable, soft start
circuitry that charges up a capacitor tied to the SS pin to GND.
This prevents input in-rush current through the external MOSFET
from the input supply (V
by producing PWM output pulses to the upper-side MOSFET.
The purpose is to limit the in-rush current from the high
voltage input supply (V

). The output tracks the ramping voltage

IN

) to the output (V

IN

OUT

).

PRECISION ENABLE CIRCUITRY

The ADP1874/ADP1875 have precision enable circuitry. The
precision enable threshold is 630 mV with 30 mV of hysteresis
(see Figure 65). Connecting the EN pin to GND disables the
ADP1874/ADP1875, reducing the supply current of the device
to approximately 140 µA.

REG

10k

EN

Figure 65. Connecting EN Pin to VREG via a Pull-Up Resistor to Enable the

COMP

2.4V

1.0V

500mV

0V

ADP1874/ADP1875

MAXIMUM CURRENT (UPPER CLAMP)

Figure 66. COMP Voltage Range

PRECISION
ENABLE COMP.

TO ENABLE

630mV

ZERO CURRENT

USABLE RANGE ONLY AFTER SOFT START
PERIOD I F CONTUNUO US CONDUCTION
MODE OF OPERATION IS SELECTED.

LOWER CLAMP

ALL BLOCKS

09347-064

09347-065

UNDERVOLTAGE LOCKOUT

The undervoltage lockout (UVLO) feature prevents the part from
operating both the upper- and lower-side MOSFETs at extremely
low or undefined input voltage (V
undefined bias voltage may result in the incorrect propagation
of signals to the high-side power switches. This, in turn, results
in invalid output behavior that can cause damage to the output
devices, ultimately destroying the device tied at the output. The
UVLO level is set at 2.65 V (nominal).

) ranges. Operation at an

IN

Rev. 0 | Page 19 of 44

ADP1874/ADP1875

ON-BOARD LOW DROPOUT REGULATOR

The ADP1874/ADP1875 use an on-board LDO to bias the
internal digital and analog circuitry. Connect the VREG and
VREG_IN pins together for normal LDO operation for low
voltage internal block biasing (see Figure 67).

ON-BOARD REGULATOR

VREG

VREG_IN

REF

Figure 67. Connecting VREG and VREG_IN Together

VIN

09347-168

With proper bypass capacitors connected to the VREG pin (output
of the internal LDO), this pin also provides power for the internal
MOSFET drivers. It is recommended to float VREG/VREG_IN
if VIN is used for greater than 5.5 V operation. The minimum
voltage where bias is guaranteed to operate is 2.75 V at VREG.

For applications where VIN is decoupled from VREG, the
minimum voltage at VIN must be 2.9 V. It is recommended to tie
VIN and VREG together if the VIN pin is subjected to a 2.75 V rail.

Table 5. Power Input and LDO Output Configurations

VIN VREG/VREG_IN Comments

>5.5 V Float Must use the LDO.
<5.5 V Connect to VIN

LDO drop voltage is not
realized (that is, if VIN = 2.75 V,
then VREG = 2.75 V).

<5.5 V Float LDO drop is realized.
VIN Ranging

Above and
Below 5.5 V

Float

LDO drop is realized,
minimum VIN
recommendation is 2.95 V.

THERMAL SHUTDOWN

The thermal shutdown is a self-protection feature to prevent the
IC from damage due to a very high operating junction temperature.
If the junction temperature of the device exceeds 155°C, the part
enters the thermal shutdown state. In this state, the device shuts off
both the upper- and lower-side MOSFETs and disables the entire
controller immediately, thus reducing the power consumption of
the IC. The part resumes operation after the junction temperature
of the part cools to less than 140°C.

PROGRAMMING RESISTOR (RES) DETECT CIRCUIT

Upon startup, one of the first blocks to become active is the RES
detect circuit. This block powers up before soft start begins. It
forces a 0.4 V reference value at the RES pin (see Figure 68) and is
programmed to identify four possible resistor values: 47 kΩ, 22 kΩ,
open, and 100 kΩ.

Rev. 0 | Page 20 of 44

The RES detect circuit digitizes the value of the resistor at the
RES pin (Pin 6). An internal ADC outputs a 2-bit digital code
that is used to program four separate gain configurations in the
current-sense amplifier (see Figure 69). Each configuration corre­sponds to a current-sense gain (A

) of 3 V/V, 6 V/V, 12 V/V, or

CS

24 V/V, respectively (see Ta bl e 6 and Ta ble 7). This variable is used
for the valley current-limit setting, which sets up the appropriate
current-sense gain for a given application and sets the compensation
necessary to achieve loop stability (see the Valley Current-Limit
Setting section and the Compensation Network section).

DRVH

SW

DRVL

RES

Figure 68. Programming Resistor Location

Figure 69. RES Detect Circuit for Current-Sense Gain Programming

CS

AMP

CS GAIN

SET

CS GAIN
PROGRAMMING

ADC

RES

0.4V

Q1

Q2

SW

PGND

09347-066

09347-067

Table 6. Current-Sense Gain Programming

Resistor ACS

47 kΩ 3 V/V
22 kΩ 6 V/V
Open 12 V/V
100 kΩ 24 V/V

VALLEY CURRENT-LIMIT SETTING

The architecture of the ADP1874/ADP1875 is based on valley
current-mode control. The current limit is determined by three
components: the R
sense amplifier output voltage swing, and the current-sense gain.
The CS output voltage range is internally fixed at 1.4 V. The
current-sense gain is programmable via an external resistor at
the RES pin (see the Programming Resistor (RES) Detect Circuit
section). The R
temperature and usually has a positive T
increases with temperature); therefore, it is recommended to
program the current-sense gain resistor based on the rated R
of the MOSFET at 125°C.

of the lower-side MOSFET, the current-

ON

of the lower-side MOSFET can vary over

ON

(meaning that it

C

ON

ADP1874/ADP1875

A

Because the ADP1874/ADP1875 are based on valley current
control, the relationship between I

K

⎛

II

⎜

LOADCLIM

⎝

⎞

I

−×=

1

⎟

2

⎠

CLIM

and I

LOAD

is

where:

K

is the ratio between the inductor ripple current and the

I

desired average load current (see Figure 70).

I

is the desired valley current limit.

CLIM

I

is the current load.

LOAD

Establishing K
Inductor Selection section), but in most cases K

helps to determine the inductor value (see the

I

= 0.33.

I

I

RIPPLE CURRENT =

LOAD CURRENT

VALLEY CURRENT LIMIT

LOAD

3

09347-068

Figure 70. Valley Current Limit to Average Current Relation

When the desired valley current limit (I

) has been determined,

CLIM

the current-sense gain can be calculated as follows:

V4.1

CLIM

=

RAI×

ONCS

where:

R

is the channel impedance of the lower-side MOSFET.

ON

is the current-sense gain multiplier (see Tab le 6 and Tab le 7 ).

A

CS

Although the ADP1874/ADP1875 have only four discrete current­sense gain settings for a given R

variable, Tab le 7 and Figure 71

ON

outline several available options for the valley current setpoint
based on various R

values.

ON

Table 7. Valley Current Limit Program (See Figure 71)

Valley Current Level

RON
(mΩ)

47 kΩ 22 kΩ Open 100 kΩ
A

= 3 V/V ACS = 6 V/V ACS = 12 V/V ACS = 24 V/V

CS

1.5 38.9
2 29.2

2.5 23.3
3 39.0 19.5

3.5 33.4 16.7

4.5 26.0 13
5 23.4 11.7

5.5 21.25 10.6
10 23.3 11.7 5.83
15 31.0 15.5 7.75 7.5
18 26.0 13.0 6.5 3.25

39
37
35
33
31
29
27
25
23
21
19
17
15
13

VALLEY CURRENT LIMIT (A)

11

RES = 100k

9

= 24V/V

A

7

CS

5
3

1234567891011121314151617181920

RES = NO RES

A

= 12V/V

CS

RON (m)

Figure 71. Valley Current-Limit Value vs. RON of the Lower-Side MOSFET

RES = 47k

A

= 3V/V

CS

RES = 22k

A

= 6V/V

CS

09347-069

for Each Programming Resistor (RES)

The valley current limit is programmed as outlined in Table 7
and Figure 71. The inductor chosen must be rated to handle the
peak current, which is equal to the valley current from Tab le 7
plus the peak-to-peak inductor ripple current (see the Inductor
Selection section). In addition, the peak current value must be
used to compute the worst-case power dissipation in the MOSFETs
(see Figure 72).

49

MAXIMUM DC LOAD

CURRENT

INDUCTOR

CURRENT

I = 33%

OF 30A

39.5A

35A

I = 45%

OF 32.25A

30A

VALLEY CURRENT-LIMIT
THRESHOLD (SET FOR 25A)

32.25A

I = 65%

OF 37A

37A

AMPLIFIER

OUTPUT

CS

SWING

CS

AMPLIFIER

OUTPUT

2.4V

1V0A

09347-070

Figu re 72. Valley Current-Limit Threshold in Relation to Inductor Ripple Current

Rev. 0 | Page 21 of 44

ADP1874/ADP1875

CLIM

ZERO

CURRENT

REPEATED CURRENT-LIMIT

VIOLATION DETECTED

HS

Figure 73. Idle Mode Entry Sequence Due to Current-Limit Violation

HICCUP MODE DURING SHORT CIRCUIT

A current-limit violation occurs when the current across the
source and drain of the lower-side MOSFET exceeds the current­limit setpoint. When 16 current-limit violations are detected,
the controller enters idle mode and turns off the MOSFETs for
6 ms, allowing the converter to cool down. Then, the controller
reestablishes soft start and begins to cause the output to ramp up
again (see Figure 73). While the output ramps up, CS amplifier
output is monitored to determine if the violation is still present.
If it is still present, the idle event occurs again, followed by the full
chip, power-down sequence. This cycle continues until the
violation no longer exists. If the violation disappears, the converter
is allowed to switch normally, maintaining regulation.

A PREDETERMINED NUMBER
OF PULSES IS COUNTED TO

ALLOW THE CONVERTER

TO COOL DOWN

SOFT START IS

REINITIALIZED TO

MONITOR IF THE

VIOLATION

STILL EXISTS

09347-071

ADP1875 POWER SAVING MODE (PSM)

A power saving mode is provided in the ADP1875. The ADP1875
operates in the discontinuous conduction mode (DCM) and
pulse skips at light load to medium load currents. The controller
outputs pulses as necessary to maintain output regulation. Unlike
the continuous conduction mode (CCM), DCM operation
prevents negative current, thus allowing improved system
efficiency at light loads. Current in the reverse direction through
this pathway, however, results in power dissipation and therefore
a decrease in efficiency.

HS

t

ON

SYNCHRONOUS RECTIFIER

The ADP1874/ADP1875 employ internal MOSFET drivers for
the external upper- and lower-side MOSFETs. The low-side
synchronous rectifier not only improves overall conduction
efficiency but it also ensures proper charging of the bootstrap
capacitor located at the upper-side driver input. This is beneficial
during startup to provide sufficient drive signal to the external
upper-side MOSFET and to attain fast turn-on response, which is
essential for minimizing switching losses. The integrated upper­and lower-side MOSFET drivers operate in complementary
fashion with built-in anti cross-conduction circuitry to prevent
unwanted shoot-through current that may potentially damage the
MOSFETs or reduce efficiency because of excessive power loss.

HS AND LS ARE OFF

OR IN IDLE MODE

AS THE INDUCTOR
CURRENT APPROACHES
ZERO CURRENT, THE STATE
MACHINE TURNS OFF THE
LOWER-SIDE MOSFET.

I

LOAD

LS

0A

Figure 74. Discontinuous Mode of Operation (DCM)

t

OFF

To minimize the chance of negative inductor current buildup,
an on-board zero-cross comparator turns off all upper- and
lower-side switching activities when the inductor current
approaches the zero current line, causing the system to enter
idle mode, where the upper- and lower-side MOSFETs are turned
off. To ensure idle mode entry, a 10 mV offset, connected in
series at the SW node, is implemented (see Figure 75).

ZERO-CROSS

COMPARATOR

LS

Figure 75. Zero-Cross Comparator with 10 mV of Offset

10mV

SW

Q2

I

Q2

09347-073

09347-072

Rev. 0 | Page 22 of 44

ADP1874/ADP1875

K

As soon as the forward current through the lower-side MOSFET
decreases to a level where

10 mV = I

Q2

× R

the zero-cross comparator (or I

ON(Q2)

comparator) emits a signal to

REV

turn off the lower-side MOSFET. From this point, the slope of the
inductor current ramping down becomes steeper (see Figure 76)
as the body diode of the lower-side MOSFET begins to conduct
current and continues conducting current until the remaining
energy stored in the inductor has been depleted.

ANOTHER
TRIGGERED WHEN V
FALLS BELOW REGULATION

SW

LS

I

LOAD

0A

Figure 76. 10 mV Offset to Ensure Prevention of Negative Inductor Current

t

EDGE IS

ON

OUT

HS AND LS

IN IDLE MODE

ZERO-CROSS COMPARATOR
DETECTS 10mV OFFSET AND
TURNS OFF LS

10mV = R

× I

ON

LOAD

t

ON

09347-074

The system remains in idle mode until the output voltage drops
below regulation. A PWM pulse is then produced, turning on the
upper-side MOSFET to maintain system regulation. The ADP1875
does not have an internal clock, so it switches purely as a hysteretic
controller as described in this section.

TIMER OPERATION

The ADP1874/ADP1875 employ a constant on-time architecture,
which provides a variety of benefits, including improved load
and line transient response when compared with a constant
(fixed) frequency current-mode control loop of comparable
loop design. The constant on-time timer, or t
the high-side input voltage (V

) and the output voltage (V

IN

using SW waveform information to produce an adjustable one­shot PWM pulse. The pulse varies the on-time of the upper-side
MOSFET in response to dynamic changes in input voltage,
output voltage, and load current conditions to maintain output
regulation. The timer generates an on-time (t
inversely proportional to V

V

OUT

Kt ×=

ON

K is a constant that is trimmed using an RC timer product

where

V

IN

.

IN

for the 300 kHz, 600 kHz, and 1.0 MHz frequency options.

timer, senses

ON

) pulse that is

ON

OUT

)

V

t

ON

C

SW

INFORMATI ON

Figure 77. Constant On-Time Time

VREG

I

R (TRIMMED)

IN

09347-075

The constant on-time (tON) is not strictly constant because it
varies with V

and V

IN

. However, this variation occurs in such

OUT

a way as to keep the switching frequency virtually independent
of V

and V

IN

The t

timer uses a feedforward technique, which when applied

ON

OUT

.

to the constant on-time control loop makes it a pseudo-fixed
frequency to a first-order approximation. Second-order effects,
such as dc losses in the external power MOSFETs (see the
Efficiency Consideration section), cause some variation in
frequency vs. load current and line voltage. These effects are
shown in Figure 23 to Figure 34. The variations in frequency
are much reduced compared with the variations generated if
the feedforward technique is not used.

The feedforward technique establishes the following relationship:

1

=

is the controller switching frequency (300 kHz,

SW

where f

f

SW

600 kHz, and 1.0 MHz).

timer senses VIN and V

The t

ON

to minimize frequency variation

OUT

as previously explained. This provides pseudo-fixed frequency
as explained in the Pseudo-Fixed Frequency section. To allow
headroom for V

and V

IN

sensing, adhere to the following

OUT

equations:

VREG ≥ V

VREG ≥ V

/8 + 1.5

IN

/4

OUT

For typical applications where VREG is 5 V, these equations are not
relevant; however, care may be required for lower VREG/VIN
inputs.

Rev. 0 | Page 23 of 44

ADP1874/ADP1875

−

V

PSEUDO-FIXED FREQUENCY

The ADP1874/ADP1875 employ a constant on-time control
scheme. During steady state operation, the switching frequency
stays relatively constant, or pseudo-fixed. This is due to the one-

timer that produces a high-side PWM pulse with a fixed

shot t

ON

duration, given that external conditions such as input voltage,
output voltage, and load current are also at steady state. During
load transients, the frequency momentarily changes for the
duration of the transient event so that the output comes back
within regulation more quickly than if the frequency were fixed
or if it were to remain unchanged. After the transient event is
complete, the frequency returns to a pseudo-fixed value.

To illustrate this feature more clearly, this section describes
one such load transient event—a positive load step—in detail.
During load transient events, the high-side driver output pulse­width stays relatively consistent from cycle to cycle; however,
the off-time (DRVL on-time) dynamically adjusts according to
the instantaneous changes in the external conditions mentioned.

When a positive load step occurs, the error amplifier (out of phase
with the output, V

) produces new voltage information at its

OUT

output (COMP). In addition, the current-sense amplifier senses
new inductor current information during this positive load
transient event. The error amplifier’s output voltage reaction is
compared with the new inductor current information that sets
the start of the next switching cycle. Because current information
is produced from valley current sensing, it is sensed at the down
ramp of the inductor current, whereas the voltage loop information
is sensed through the counter action upswing of the error
amplifier’s output (COMP).

The result is a convergence of these two signals (see Figure 78),
which allows an instantaneous increase in switching frequency
during the positive load transient event. In summary, a positive
load step causes V

to transient down, which causes COMP to

OUT

transient up and, therefore, shortens the off time. This resulting
increase in frequency during a positive load transient helps to
quickly bring V

back up in value and within the regulation

OUT

window.

Similarly, a negative load step causes the off time to lengthen in
response to V
demagnetizing phase, helping to bring V

rising. This effectively increases the inductor

OUT

within regulation.

OUT

In this case, the switching frequency decreases, or experiences a
foldback, to help facilitate output voltage recovery.

Because the ADP1874/ADP1875 have the ability to respond rapidly
to sudden changes in load demand, the recovery period in which
the output voltage settles back to its original steady state operating
point is much quicker than it would be for a fixed-frequency
equivalent. Therefore, using a pseudo-fixed frequency results in
significantly better load-transient performance compared to
using a fixed frequency.

PWM OUTPUT

POWER GOOD MONITORING

The ADP1874/ADP1875 power good circuitry monitors the
output voltage via the FB pin. The PGOOD pin is an open-drain
output that can be pulled up by an external resistor to a voltage
rail that does not necessarily have to be VREG. When the internal
NMOS switch is in high impedance (off state), this means that
the PGOOD pin is logic high, and the output voltage via the FB
pin is within the specified regulation window. When the internal
switch is turned on, PGOOD is internally pulled low when the
output voltage via the FB pin is outside this regulation window.

The power good window is defined with a typical upper
specification of +90 mV and a lower specification of −70 mV
below the FB voltage of 600 mV. When an overvoltage event occurs
at the output, there is a typical propagation delay of 12 µs prior
to the PGOOD pin deassertion (logic low). When the output
voltage re-enters the regulation window, there is a propagation
delay of 12 µs prior to PGOOD reasserting back to a logic high
state. When the output is outside the regulation window, the
PGOOD open drain switch is capable of sinking 1mA of current
and provides 140 mV of drop across this switch. The user is free
to tie the external pull-up resistor (R
20 V. The following equation provides the proper external pull-up
resistor value:

R

where:

is the PGOOD external resistor.

R

PGD

V

is a user-chosen voltage rail.

EXT

LOAD CURRENT

DEMAND

CS AMP

OUTPUT

ERROR AMP

OUTPUT

f

SW

Figure 78. Load Transient Response Operation

V

EXT

=

PGD

690mV

FB

600mV

530mV

Figure 79. Power Good, Output Voltage Monitoring Circuit

mV140

mA1

VALLEY
TRIP POINTS

>

f

SW

) to any voltage rail up to

RES

EXT

1mA

+

PGOOD
140mV
–

09347-076

R

PGD

09347-180

Rev. 0 | Page 24 of 44

ADP1874/ADP1875

690mV

640mV

FB

600mV

530mV

0V

PGOOD

0V

Figure 80. Power Good Timing Diagram, t

VREG

1.2V V

OUT2 (SLAVE)

R

TOP2

1k

R
1k

Figure 81. Coincident Tracking Circuit Implementation

VREG

1.2V V

OUT2 (SLAVE)

R

TOP2

1k

R
1k

SOFT-START

V

EXT

10k

BOT2

10k

BOT2

HYSTERESIS (50mV)

PGOOD
ASSERTIO N
AT POWER-UP

t

PGD

= 12 μs (Diagram May Look Disproportionate for Illustration Purposes.)

PGD

SLAVE

EN

PGOOD

FB

GND

TRACK

PGND

SLAVE

EN

PGOOD

FB

GND

TRACK

PGND

Figure 82. Ratiometric Tracking Circuit Implementation

VOLTAGE TRACKING

The ADP1874/ADP1875 feature a voltage-tracking function that
facilitates proper power-up sequencing in applications that require
tracking a master voltage. In this manner, the user is free to
impose a master voltage that typically comes with a selectable
or programmable ramp rate on slave or secondary power rails.
To impose any voltage tracking relationship, the master voltage
rise time must be longer than the slave voltage soft start period.
This is particularly important in applications such as I/O voltage
sequencing and core voltage applications where specific power
sequencing is required.

Tracking is made possible by four inputs to the error amplifier,
three of which are input pins to the IC. The TRACK and SS pins
are positive inputs, and the FB pin provides the negative feedback
from the output voltage via the divider network. The fourth input
to the amplifier is the reference voltage of 0.6 V. The negative
feedback pin (FB pin) regulates the output voltage to the lowest
of the three positive inputs (TRACK, SS, and 0.6 V reference).

In all tracking configurations, the slave output can be set to as
low as 0.6 V for a given operating condition. The master voltage
must have a longer rise time than the slaves programmed soft
start period; otherwise, the tracking relationship will not be
observed at the slave output.

Rev. 0 | Page 25 of 44

OUTPUT OVERVOLTAGE
PGOOD DEASSERT

PGOOD
REASSERT

PGOOD

DEASSERTI ON

AT POWER DOWN

t

PGD

t

PGD

t

PGD

09347-181

MASTER

R

SS

PGD

0.9V

R
1k

C

TRK1

SS

1.8V V

R

1k

EXT

OUT1 (MASTER)

TRK2

R

TOP1

R

10k

BOT1

EN

FB

GND

PGND

09347-182

VREG

V

MASTER

V

R

PGD

C

1.7V

R
1k

SS

TRK1

2.5V V

R

500

TRK2

SS

VREG

EXT

OUT1 (MASTER)

R

TOP1

R

10k

BOT1

EN

FB

GND

PGND

09347-184

Coincident and ratiometric tracking are two possible tracking
configuration options offered by the ADP1874/ADP1875.
Coincident tracking is the most commonly used tracking
technique. It is primarily used in core and I/O sequencing
applications. The ramp rate of the master voltage is fully
imposed onto the ramp rate of the slave output voltage until it
has reached its regulation setpoint. Connecting the TRACK pin,
by differentially tapping onto the master voltage via a resistive
divider of similar ratio to the slave feedback divider network,
is depicted in

Figure 83.

MASTER VOLTAGE

SLAVE VOLTAGE

OUTPUT VOLTAGE (V)

Figure 83. Coincident Tracking: Master Voltage—Slave Voltage Tracking

TIME (ms)

9347-083

Relationship

ADP1874/ADP1875

The slave output tracks the master output dv/dt until the slave
output regulation point is reached. Any influence by the master
voltage thereafter will no longer be in effect. Ensure that the voltage
forced on the slave TRACK pin is above 0.7 V at the end of TRACK
phase. Voltages imposed on the TRACK pin below 0.7 V, once
that tracking period has expired (steady state), may result in
regulation inaccuracies due to the internal offsets of the error
amplifier between TRACK and FB. Ratiometric tracking can be
achieved by assigning the slave output to rise more quickly than
the master voltage. The simplest way to perform ratiometric
tracking is to differentially connect the slave TRACK pin to the
FB pin of the master voltage IC. The slave output, however, must
be limited to a fraction of the master voltage. In this tracking
configuration, it is not recommended for the slave TRACK pin
to terminate at a voltage lower than 0.6 V due to inaccuracies
between the TRACK and FB inputs previously mentioned. It is

not recommended to force any voltage on the slave TRACK pin
lower than 0.6 V. Figure 84 illustrates a circuit with a ratiometric

> R

tracking configuration. Setting R

TRK1

ensures that the

TRK2

slave TRACK voltage will rise up more quickly (to the regulation
point) than the master voltage.

MASTER VOLTAGE

SLAVE VOLTAGE

OUTPUT VOLTAGE (V)

Figure 84. Ratiometric Tracking: Master Voltage—Slave Voltage Tracking

TIME (ms)

Relationship

9347-085

Rev. 0 | Page 26 of 44

ADP1874/ADP1875

I

APPLICATIONS INFORMATION

FEEDBACK RESISTOR DIVIDER

The required resistor divider network can be determined for a
given V
is fixed at 0.6 V. Selecting values for R

value because the internal band gap reference (V

OUT

and RB determines the

T

REF

minimum output load current of the converter. Therefore, for
a given value of R

, the RT value can be determined through the

B

following expression:

V

OUT

×=

RR

B

T

V)6.0( −

V6.0

INDUCTOR SELECTION

The inductor value is inversely proportional to the inductor
ripple current. The peak-to-peak ripple current is given by

LOAD

IKI ≈×=Δ

IL

LOAD

where K

is typically 0.33.

I

The equation for the inductor value is given by

VV

−

IN

L ×

=

L

)(

OUT

fI

×Δ

SW

where:

is the high voltage input.

V

IN

V

is the desired output voltage.

OUT

is the controller switching frequency (300 kHz, 600 kHz,

f

SW

or 1.0 MHz).

When selecting the inductor, choose an inductor saturation
rating that is above the peak current level, and then calculate
the inductor current ripple (see the Valley Current-Limit
Setting section and Figure 85).

52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18

PEAK INDUCTOR CURRENT (A)

16
14
12
10

8

6 8 10 12 14 16 18 20 22 24 26 28 30

Figure 85. Peak Inductor Current vs. Valley Current Limit for 33%, 40%, and

VALLEY CURRENT LIMIT (A)

50% of Inductor Ripple Current

3

V

OUT

V

IN

I = 50%

I = 40%

I = 33%

09347-077

)

Table 8. Recommended Inductors

L

DCR

I

Dimensions

(μH)

(mΩ)

0.12 0.33 55 10.2 × 7 Würth Elek. 744303012

0.22 0.33 30 10.2 × 7 Würth Elek. 744303022

0.47 0.8 50 14.2 × 12.8 Würth Elek. 744355147

0.72 1.65 35 10.5 × 10.2 Würth Elek. 744325072

0.9 1.6 32 14 × 12.8 Würth Elek. 744318120

1.2 1.8 25 10.5 × 10.2 Würth Elek. 744325120

1.0 3.8 16 10.2 × 10.2 Würth Elek. 7443552100

1.4 3.2 24 14 × 12.8 Würth Elek. 744318180

2.0 2.0 23 10.2 × 10.2 Würth Elek. 7443551200

0.8 27.5 Sumida CEP125U-0R8

SAT

(A)

(mm) Manufacturer

Model
Number

OUTPUT RIPPLE VOLTAGE (ΔVRR)

The output ripple voltage is the ac component of the dc output
voltage during steady state. For a ripple error of 1.0%, the output
capacitor value needed to achieve this tolerance can be determined
using the following equation. (Note that an accuracy of 1.0% is
only possible during steady state conditions, not during load
transients.)

= (0.01) × V

ΔV

RR

OUT

OUTPUT CAPACITOR SELECTION

The primary objective of the output capacitor is to facilitate the
reduction of the output voltage ripple; however, the output capacitor
also assists in the output voltage recovery during load transient
events. For a given load current step, the output voltage ripple
generated during this step event is inversely proportional to the
value chosen for the output capacitor. The speed at which the
output voltage settles during this recovery period depends on
where the crossover frequency (loop bandwidth) is set. This
crossover frequency is determined by the output capacitor, the
equivalent series resistance (ESR) of the capacitor, and the
compensation network.

To calculate the small signal voltage ripple (output ripple voltage) at
the steady state operating point, use the following equation:

OUT

⎛
⎜

×Δ=

IC

L

⎜

SW

⎝

1

[]

LRIPPLE

where ESR is the equivalent series resistance of the output
capacitors.

To calculate the output load step, use the following equation:

I

Δ

OUT

2

×=

is the amount that V

DROOP

C

where V
a given positive load current step (I

LOAD

ESRIVf

×Δ−Δ×

LOADDROOPSW

is allowed to deviate for

OUT

).

LOAD

⎞
⎟
⎟

×Δ−Δ××

)(8

ESRIVf

⎠

))((

Rev. 0 | Page 27 of 44

ADP1874/ADP1875

=

Ceramic capacitors are known to have low ESR. However, there
is a trade-off in using the popular X5R capacitor technology
because up to 80% of its capacitance may be lost due to derating
as the voltage applied across the capacitor is increased (see
Figure 86). Although X7R series capacitors can also be used, the
available selection is limited to 22 µF maximum.

20

10

0

–10

–20

–30

–40

–50

–60

–70

CAPACITANCE CHARGE (%)

–80

10µF TDK 25V, X7R, 1210 C3225X7R1E106M
22µF MURATA 25V, X7R, 1210 GRM32ER71E226KE15L

–90

–100

Figure 86. Capacitance vs. DC Voltage Characteristics for Ceramic Capacitors

47µF MURATA 16V, X5R, 1210 GRM32ER61C476KE15L

0 5 10 15 20 25 30

X5R (16V)

X7R (50V)

X5R (25V)

DC VOLTAGE (VDC)

09347-078

Electrolytic capacitors satisfy the bulk capacitance requirements
for most high current applications. However, because the ESR
of electrolytic capacitors is much higher than that of ceramic
capacitors, several MLCCs should be mounted in parallel with
the electrolytic capacitors to reduce the overall series resistance.

COMPENSATION NETWORK

Due to its current-mode architecture, the ADP1874/ADP1875
require Type II compensation. To determine the component
values needed for compensation (resistance and capacitance
values), it is necessary to examine the converter’s overall loop
gain (H) at the unity gain frequency (f

V

REF

GGH ××××== V/V1

M

CS

V

OUT

Examining each variable at high frequency enables the unity­gain transfer function to be simplified to provide expressions
for the R

COMP

and C

Output Filter Impedance (Z

component values.

COMP

FILT

Examining the filter’s transfer function at high frequencies
simplifies to

FILTER

1

RZ

×=

L

××+

++

L

at the crossover frequency (s = 2πf
series resistance of the output capacitors.

/10) when H = 1 V/V.

SW

ZZ

COMP

FILT

)

CESRs

OUT

CESRRs

)(1

OUT

). ESR is the equivalent

CROSS

Error Amplifier Output Impedance (Z

Assuming that CC2 is significantly smaller than C

COMP

)

COMP

, CC2 can
be omitted from the output impedance equation of the error
amplifier. The transfer function simplifies to

R

Z +×=

COMP

COMP

f

CROSS

CROSS

ff

ZERO

22

and

where f

1

12

, the zero frequency, is set to be 1/4 the crossover

ZERO

ff ×=

SWCROSS

frequency for the ADP1874.

Error Amplifier Gain (Gm)

The error amplifier gain (transconductance) is

G

= 500 µA/V (µs)

m

Current-Sense Loop Gain (GCS)

The current-sense loop-gain is

1

=

CS

(A/V)

RAG×

ONCS

where:

(V/V) is programmable for 3 V/V, 6 V/V, 12 V/V, and 24 V/V

A

CS

(see the Programming Resistor (RES) Detect Circuit and Val l e y
Current-Limit Setting sections).

R

is the channel impedance of the lower-side MOSFET.

ON

Crossover Frequency

The crossover frequency is the frequency at which the overall
loop (system) gain is 0 dB (H = 1 V/V). It is recommended for
current-mode converters, such as the ADP1874, that the user
set the crossover frequency between 1/10 and 1/15 the
switching frequency.

1

ff

=

SWCROSS

12

The relationship between C

COMP

and f

(zero frequency) is as

ZERO

follows:

ZERO

1

CRf××π=2

COMPCOMP

The zero frequency is set to 1/4 the crossover frequency.

Combining all of the above parameters results in

R

COMP

2

CESRRs

)(1

OUT

2

CESRs

OUT

V

OUT

R

L

11

×××

GGV

MREF

CS

CROSS

f

CROSS

2

()

++

×

22

+

ff

ZERO

L

2

()

1

××+

where ESR is the equivalent series resistance of the output
capacitors.

COMP

1

COMP

fRC××π×=2

ZERO

Rev. 0 | Page 28 of 44

ADP1874/ADP1875

EFFICIENCY CONSIDERATION

One of the important criteria to consider in constructing a dc-to-dc
converter is efficiency. By definition, efficiency is the ratio of the
output power to the input power. For high power applications at
load currents up to 20 A, the following are important MOSFET
parameters that aid in the selection process:

• V

• R

• Q

• C

• C

The following are the losses experienced through the external
component during normal switching operation:

• Channel conduction loss (both the MOSFETs)

• MOSFET driver loss

• MOSFET switching loss

• Body diode conduction loss (lower-side MOSFET)

• Inductor loss (copper and core loss)

Channel Conduction Loss

During normal operation, the bulk of the loss in efficiency is due
to the power dissipated through MOSFET channel conduction.
Power loss through the upper-side MOSFET is directly pro­portional to the duty-cycle (D) for each switching period, and
the power loss through the lower-side MOSFET is directly
proportional to 1 − D for each switching period. The selection
of MOSFETs is governed by the maximum dc load current that
the converter is expected to deliver. In particular, the selection
of the lower-side MOSFET is dictated by the maximum load
current because a typical high current application employs duty
cycles of less than 50%. Therefore, the lower-side MOSFET is
in the on state for most of the switching period.

is the MOSFET voltage applied between the gate

GS (TH)

and the source that starts channel conduction.

is the MOSFET on resistance during channel

DS (ON)

conduction.

is the total gate charge.

G

is the input capacitance of the upper-side switch.

N1

is the input capacitance of the lower-side switch.

N2

[ ]

()

1

N2(ON)N1(ON)N1,N2(CL)

IRDRDP ××−+×=

LOAD

2

MOSFET Driver Loss

Other dissipative elements are the MOSFET drivers. The con­tributing factors are the dc current flowing through a driver
during operation and the Q

[ ]

=

DR

)(

LOSSDR

[]

()

SW

lowerFET

parameter of the external MOSFETs.

GATE

( )

SW

upperFET

IVCfVREG

+×

IVCfVP

BIAS

++×

DR

BIASREG

where:

C

is the input gate capacitance of the upper-side MOSFET.

upperFET

is the input gate capacitance of the lower-side MOSFET.

C

lowerFET

I

is the dc current flowing into the upper- and lower-side drivers.

BIAS

is the driver bias voltage (that is, the low input voltage

V

DR

(VREG) minus the rectifier drop (see Figure 87)).
VREG is the bias voltage.

800

720

640

560

480

400

320

RECTIFIER DROP (mV)

240

160

80

300 1000900800700600500400

Figure 87. Internal Rectifier Voltage Drop vs. Switching Frequency

VREG = 2.7V
VREG = 3.6V
VREG = 5.5V

SWITCHING FREQUENCY (kHz)

+125°C
+25°C
–40°C

09347-079

Switching Loss

The SW node transitions due to the switching activities of the
upper- and lower-side MOSFETs. This causes removal and
replenishing of charge to and from the gate oxide layer of the
MOSFET, as well as to and from the parasitic capacitance
associated with the gate oxide edge overlap and the drain and
source terminals. The current that enters and exits these charge
paths presents additional loss during these transition times.
This can be approximately quantified by using the following
equation, which represents the time in which charge enters and
exits these capacitive regions:

t

SW-TRANS

= R

GATE

× C

TOTAL

where:

C

is the CGD + CGS of the external MOSFET.

TOTAL

R

is the gate input resistance of the external MOSFET.

GATE

The ratio of this time constant to the period of one switching cycle
is the multiplying factor to be used in the following expression:

t

-

P

LOSSSW

TRANSSW

)(

t

SW

LOAD

2

×××=

VI

IN

or

P

SW(LOSS)

= fSW × R

GATE

× C

TOTAL

× I

× VIN × 2

LOAD

Rev. 0 | Page 29 of 44

ADP1874/ADP1875

I

Diode Conduction Loss

The ADP1874/ADP1875 employ anti cross-conduction circuitry
that prevents the upper- and lower-side MOSFETs from conducting
current simultaneously. This overlap control is beneficial, avoiding
large current flow that may lead to irreparable damage to the
external components of the power stage. However, this blanking
period comes with the trade-off of a diode conduction loss
occurring immediately after the MOSFET change states and
continuing well into idle mode. The amount of loss through the
body diode of the lower-side MOSFET during the anti-overlap
state is given by the following expression:

t

LOSSBODY

P

LOSSBODY

)(

)(

t

SW

LOAD

2

×××=

VI

F

where:

t

BODY(LOSS)

is the body conduction time (see Figure 88 for dead

time periods).

t

is the period per switching cycle.

SW

is the forward drop of the body diode during conduction.

V

F

(See the selected external MOSFET data sheet for more
information about the V

80

72

64

56

48

40

32

24

BODY DIODE CONDUCTION TIME (ns)

16

8

2.7 5.54.84.13.4

Figure 88. Body Diode Conduction Time vs. Low Voltage Input (VREG)

parameter.)

F

1MHz
300kHz

VREG (V)

+125°C
+25°C
–40°C

09347-080

Inductor Loss

During normal conduction mode, further power loss is caused
by the conduction of current through the inductor windings,
which have dc resistance (DCR). Typically, larger sized inductors
have smaller DCR values.

The inductor core loss is a result of the eddy currents generated
within the core material. These eddy currents are induced by the
changing flux, which is produced by the current flowing through
the windings. The amount of inductor core loss depends on the
core material, the flux swing, the frequency, and the core volume.
Ferrite inductors have the lowest core losses, whereas powdered iron
inductors have higher core losses. It is recommended to use shielded
ferrite core material type inductors with the ADP1874/ADP1875
for a high current, dc-to-dc switching application to achieve
minimal loss and negligible electromagnetic interference (EMI).

2

+ Core Loss

IDCRP ×=

)(

LOSSDCR

LOAD

INPUT CAPACITOR SELECTION

The goal in selecting an input capacitor is to reduce or minimize
input voltage ripple and to reduce the high frequency source
impedance, which is essential for achieving predictable loop
stability and transient performance.

The problem with using bulk capacitors, other than their physical
geometries, is their large equivalent series resistance (ESR) and
large equivalent series inductance (ESL). Aluminum electrolytic
capacitors have such high ESR that they cause undesired input
voltage ripple magnitudes and are generally not effective at high
switching frequencies.

If bulk electrolytic capacitors are used, it is recommended to use
multilayered ceramic capacitors (MLCC) in parallel due to their
low ESR values. This dramatically reduces the input voltage ripple
amplitude as long as the MLCCs are mounted directly across the
drain of the upper-side MOSFET and the source terminal of the
lower-side MOSFET (see the Layout Considerations section).
Improper placement and mounting of these MLCCs may cancel
their effectiveness due to stray inductance and an increase in
trace impedance.

()

VVV

−×

IN

OUT

)1(

OUT

II

,,

MAXLOADRMSCIN

OUT

×=

V

The maximum input voltage ripple and maximum input capacitor
rms current occur at the end of the duration of 1 − D while the
upper-side MOSFET is in the off state. The input capacitor rms
current reaches its maximum at Time D. When calculating the
maximum input voltage ripple, account for the ESR of the input
capacitor as follows:

V

MAX,RIPPLE

= V

RIPP

+ (I

LOAD,MAX

× ESR)

where:

V

is usually 1% of the minimum voltage input.

RIPP

I

is the maximum load current.

LOAD,MAX

ESR is the equivalent series resistance rating of the input capacitor.

Inserting V

MAX,RIPPLE

into the charge balance equation to

calculate the minimum input capacitor requirement gives

−

C

IN,min

,

MAXLOAD

V

,

DD

×=

f

SWRIPPLEMAX

or

I

,

MAXLOAD

C

IN,min

=

Vf

4

RIPPLEMAXSW

,

where D = 50%.

Rev. 0 | Page 30 of 44

ADP1874/ADP1875

=

THERMAL CONSIDERATIONS

The ADP1874/ADP1875 are used for dc-to-dc, step down, high
current applications that have an on-board controller, an on-board
LDO, and on-board MOSFET drivers. Because applications may
require up to 20 A of load current and be subjected to high ambient
temperature, the selection of external upper- and lower-side
MOSFETs must be associated with careful thermal consideration
to not exceed the maximum allowable junction temperature of
125°C. To avoid permanent or irreparable damage, if the junction
temperature reaches or exceeds 155°C, the part enters thermal
shutdown, turning off both external MOSFETs and is not re­enabled until the junction temperature cools to 140°C (see the
On-Board Low Dropout Regulator section).

In addition, it is important to consider the thermal impedance
of the package. Because the ADP1874/ADP1875 employ an
on-board LDO, the ac current (fxCxV) consumed by the internal
drivers to drive the external MOSFETs, adds another element of
power dissipation across the internal LDO. Equation 3 shows the
power dissipation calculations for the integrated drivers and for
the internal LDO.

Tabl e 9 lists the thermal impedance for the ADP1874/ADP1875,
which are available in a 16-lead QSOP.

Table 9. Thermal Impedance for 16-lead QSOP

Parameter Thermal Impedance

16-Lead QSOP θJA

4-Layer Board 104°C/W

Figure 89 specifies the maximum allowable ambient temperature
that can surround the ADP1874/ADP1875 IC for a specified
high input voltage (V
derating conditions for each available switching frequency for
low, typical, and high output setpoints for the 16-lead QSOP
package. All temperature derating criteria are based on a
maximum IC junction temperature of 125°C.

150

140

130

120

110

100

90

80

70

TEMPERATURE (°C)

60

MAXIMUM ALLO WABLE AMBIENT

50

40

30

5.5 19.017.516.014. 513.011.510.08.57.0

4-Layer EVB, C

). Figure 89 illustrates the temperature

IN

V

600kHz
300kHz
1MHz

Figure 89. Ambient Temperature vs. V

= 4.3 nF (Upper-/Lower-Side MOSFET)

IN

= 0.8V

OUT

V

= 1.8V

OUT

V

= HIGH SETPOINT

OUT

VIN (V)

09347-183

,

IN

The maximum junction temperature allowed for the ADP1874/
ADP1875 ICs is 125°C. This means that the sum of the ambient
temperature (T

) and the rise in package temperature (TR), which is

A

caused by the thermal impedance of the package and the internal
power dissipation, should not exceed 125°C, as dictated by the
following expression:

T

= TR × TA (1)

J

where:

T

is the maximum junction temperature.

J

T

is the rise in package temperature due to the power

R

dissipated from within.

is the ambient temperature.

T

A

The rise in package temperature is directly proportional to its
thermal impedance characteristics. The following equation
represents this proportionality relationship:

= θJA × P

T

R

(2)

DR(LOSS)

where:

θ

is the thermal resistance of the package from the junction to

JA

the outside surface of the die, where it meets the surrounding air.

is the overall power dissipated by the IC.

P

DR(LOSS)

The bulk of the power dissipated is due to the gate capacitance of
the external MOSFETs and current running through the on-board
LDO. The power loss equations for the MOSFET drivers and
internal low dropout regulator (see the MOSFET Driver Loss
section and the Efficiency Consideration section) are

P

= [VDR × (fSWC

DR(LOSS)

[VREG × (f

SWClowerFET

upperFETVDR

VREG + I

+ I

)] +

BIAS

)] (3)

BIAS

where:

C

is the input gate capacitance of the upper-side MOSFET.

upperFET

is the input gate capacitance of the lower-side MOSFET.

C

lowerFET

I

is the dc current (2 mA) flowing into the upper- and lower-

BIAS

side drivers.

is the driver bias voltage (the low input voltage (VREG) minus

V

DR

the rectifier drop (see Figure 87)).

VREG is the LDO output/bias voltage.

P

)(

LDODISS

)()(

IVREGCfVREGVP

IN

)(

LOSSDR

SW

TOTAL

+×××−+

BIAS

where:

P

is the power dissipated through the pass device in the

DISS(LDO)

LDO block across VIN and VREG.

P

is the MOSFET driver loss.

DR(LOSS)

is the high voltage input.

V

IN

VREG is the LDO output voltage and bias voltage.
C

is the CGD + CGS of the external MOSFET.

TOTAL

I

is the dc input bias current.

BIAS

(4)

Rev. 0 | Page 31 of 44

ADP1874/ADP1875

(

)

[

]

PPP

I

−

Δ

For example, if the external MOSFET characteristics are θJA
(16-lead QSOP) = 104°C/W, f

3.3 nF, C

= 3.3 nF, VDR = 4.62 V, and VREG = 5.0 V, then the

lowerFET

= 300 kHz, I

SW

= 2 mA, C

BIAS

upperFET

=

power loss is

DR

SW

)(

LOSSDR

[

()

SW

lowerFET

upperFET

DR

BIAS

]

+×

IVREGCfVREG

BIAS

93

−

93

−

))002.00.5103.310300(0.5(

+×××××

))002.062.4103.310300(62.4(

++×××××=

++×=

IVCfVP

= 57.12 mW

)()(

+×××−=

LDODISS

IN

)(

SW

total

93

−

+×××××−=

IVREGCfVREGVP

BIAS

)002.05103.310300()V5V13(

= 55.6 mW

+=

+=

mW6.55mW13.77

)()()(

LOSSDRLDODISSTOTALDISS

= 132.73 mW

The rise in package temperature (for 16-lead QSOP) is

PT

×θ=

R

JA

×=

)(

LOSSDR

mW05.132°C104

= 13.7°C

Assuming a maximum ambient temperature environment of 85°C,

T

= TR × TA = 13.7°C + 85°C = 98.7°C

J

which is below the maximum junction temperature of 125°C.

DESIGN EXAMPLE

The ADP1874/ADP1875 are easy to use, requiring only a few
design criteria. For example, the example outlined in this section
uses only four design criteria: V

= 12 V (typical), and fSW = 300 kHz.

V

IN

= 1.8 V, I

OUT

Input Capacitor

The maximum input voltage ripple is usually 1% of the
minimum input voltage (11.8 V × 0.01 = 120 mV).

V

= 120 mV

RIPP

V

MAX,RIPPLE

= V

RIPP

− (I

LOAD,MAX

× ESR)

= 120 mV − (15 A × 0.001) = 45 mV

C

IN,min

,

4

Vf

==

RIPPLEMAXSW

,

I

MAXLOAD

= 120 µF

Choose five 22 µF ceramic capacitors. The overall ESR of five
22 µF ceramic capacitors is less than 1 m.

I

= I

RMS

P

CIN

/2 = 7.5 A

LOAD

= (I

)2 × ESR = (7.5 A)2 × 1 m = 56.25 mW

RMS

= 15 A (pulsing),

LOAD

A15

3

mV105103004

×××

Inductor

Determine inductor ripple current amplitude as follows:

LOAD

I ≈Δ

L

= 5 A

3

Therefore, calculating for the inductor value

)(

VV

IN,MAX

L

=

=

OUT

fI

×Δ

L

SW

−

3

10300V5

××

V

OUT

×

V

IN,MAX

V8.1

)V8.1V2.13(

×

V2.13

= 1.03 µH

The inductor peak current is approximately

15 A + (5 A × 0.5) = 17.5 A

Therefore, an appropriate inductor selection is 1.0 µH with
DCR = 3.3 m (Würth Elektronik 7443552100) from Tab l e 10
with peak current handling of 20 A.

2

)(LLOSSDCR

= 0.003 × (15 A)

IDCRP ×=

2

= 675 mW

Current Limit Programming

The valley current is approximately

15 A − (5 A × 0.5) = 12.5 A

Assuming a lower-side MOSFET R

of 4.5 m and 13 A as

ON

the valley current limit from Tab l e 7 and Figure 71 indicates, a
programming resistor (RES) of 100 k corresponds to an A

CS

of 24 V/V.

Choose a programmable resistor of R

= 100 kΩ for a current-

RES

sense gain of 24 V/V.

Output Capacitor

Assume that a load step of 15 A occurs at the output and no more
than 5% output deviation is allowed from the steady state
operating point. In this case, the ADP1874 advantage is that,
because the frequency is pseudo-fixed, the converter is able to
respond quickly because of the immediate, though temporary,
increase in switching frequency.

V



= 0.05 × 1.8 V = 90 mV

DROOP

Assuming that the overall ESR of the output capacitor ranges
from 5 m to 10 m,

I

2

C

OUT

2

×=

×=

LOAD

)(

Vf

Δ×

DROOPSW

A15

3

××

)mV90(10300

= 1.11 mF

Therefore, an appropriate inductor selection is five 270 µF
polymer capacitors with a combined ESR of 3.5 m.

Rev. 0 | Page 32 of 44

ADP1874/ADP1875

[

]

t

(

)

[

]

++×

=

+

×××−

=

Assuming an overshoot of 45 mV, determine if the output
capacitor that was calculated previously is adequate.

2

=

C

OUT

()

−

=

×

)A15(101

××

−−

)(

IL

LOAD

2

)(

−Δ−

26

22

)8.1()mV458.1(

2

()

VVV

OUTOVSHTOUT

= 1.4 mF

Choose five 270 µF polymer capacitors.

The rms current through the output capacitor is

VV

)(

I

RMS

1
2

×=

2

3

1

×=

3

1

1

−

MAXIN

,

−

OUT

fL

×

SW

)V8.1V2.13(

3

10300F1

××

V

OUT

×

V

MAXIN

,

V8.1

=×

V2.13

A49.1

The power loss dissipated through the ESR of the output
capacitor is

P

= (I

COUT

)2 × ESR = (1.5 A)2 × 1.4 m = 3.15 mW

RMS

Feedback Resistor Network Setup

Choosing R

= 1 k as an example, calculate RT as follows:

B

V)6.0V8.1(

k1 =

×=TR

−

V6.0

k2

Compensation Network

To calculate R

COMP

, C

COMP

, and C

, the transconductance

PAR

parameter and the current-sense gain variable are required. The
transconductance parameter (G

) is 500 µA/V, and the current-

m

sense loop gain is

11

=

G

CS

where A

and RON are taken from setting up the current limit

CS

=

×

RA

ONCS

005.024

×

A/V33.8

=

(see the Programming Resistor (RES) Detect Circuit section
and the Valley Current-Limit Setting section).

The crossover frequency is 1/12 the switching frequency.

300 kHz/12 = 25 kHz

The zero frequency is 1/4 the crossover frequency.

25 kHz/4 = 6.25 kHz

R

=

COMP

2

CESRRs

)(1

OUT

2

CESRs

OUT

V

OUT

R

L

11

×××

GGV

MREF

CROSS

f

CROSS

2

()

++

×

22

ff

+

ZERO

L

2

()

1

××+

2

R

COMP

8.1

6.0

()

K

25

=

+

1

×

6

−

××

×

22

kk

25.625

×

8.1153.810500

k

()

k

×+××π+

0011.0)0035.0)158.1((2521

22

×××π+

0011.00035.02521

= 60.25 k

COMP

=

= 423 pF

Loss Calculations

Duty cycle = 1.8/12 V = 0.15

R

= 5.4 m

ON (N2)

t

BODY(LOSS)

V

C

Q

R

= 20 ns (body conduction time)

= 0.84 V (MOSFET forward voltage)

F

= 3.3 nF (MOSFET gate input capacitance)

IN

= 17 nC (total MOSFET gate charge)

N1,N2

= 1.5  (MOSFET gate input resistance)

GATE

= (0.15 × 0.0054 + 0.85 × 0.0054) × (15 A)
= 1.215 W

P

LOSSBODY

= 20 ns × 300 × 10
= 151.2 mW

= fSW × R

P

SW(LOSS)

= 300 × 10
= 534.6 mW

LOSSDR

[]

= 57.12 mW

LDODISS

mW6.55

=

P

= (I

COUT

LOSSDCR

P

= (I

CIN

P

= P

LOSS

+ P

P

CS

2

×

COUT

= 1.215 W + 151.2 mW + 534.6 mW + 57.12 mW + 55.6 +

3.15 mW + 675 mW + 56.25 mW
= 2.655 W

1

COMP

)(

3

× 1.5 Ω × 3.3 × 10−9 × 15 A × 12 × 2

DR

)(

()

SW

lowerFET

IN

)(

)2 × ESR = (1.5 A)2 × 1.4 m = 3.15 mW

RMS

)(

)2 × ESR = (7.5 A)2 × 1 m = 56.25 mW

RMS

+ P

N1,N2

CIN

fRCπ=2

ZERO

1

()

1

LOSSBODY

)(

t

SW

3

× 15 A × 0.84 × 2

× C

GATE

BODY(LOSS)

TOTAL

SW

upperFET

93

−

2

= 0.003 × (15 A)2 = 675 mW

IDCRP ×=

LOAD

+ PSW + P

×××××

LOAD

× I

+×

−

93

SW

IVREGCfVREG

1025.61025.6014.32

BIAS

33

VI

LOAD

DR

+×××××

N2(ON)N1(ON)N1,N2(CL)

−

DCR

2

2

×××=

F

× VIN × 2

IVCfVP

BIAS

))002.00.5103.310300(0.5(

total

93

+×××××−=

+ PDR + P

2

IRDRDP ××−+×=

LOAD

))002.062.4103.310300(62.4(

++×××××=

)002.05103.310300()V5V13(

DISS(LDO)

)()(

IVREGCfVREGVP

BIAS

+

Rev. 0 | Page 33 of 44

ADP1874/ADP1875

EXTERNAL COMPONENT RECOMMENDATIONS

The configurations listed in Tabl e 1 0 are with f
VREG = 5 V (float), and a maximum load current of 14 A.

The ADP1875 models listed in Tabl e 1 0 are the PSM versions of the device.

Table 10. External Component Values

Marking Code

(First Line/Second Line)

SAP Model ADP1874 ADP1875

ADP1874ARQZ-0.3-R7/ 1874/0.3 1875/0.3 0.8 13 5 × 222 5 × 5603 0.72 56.9 620 62 0.3

ADP1875ARQZ-0.3-R7 1874/0.3 1875/0.3 1.2 13 5 × 222 4 × 5603 1.0 56.9 620 62 1.0
1874/0.3 1875/0.3 1.8 13 4 × 222 4 × 2704 1.2 56.9 470 47 2.0
1874/0.3 1875/0.3 2.5 13 4 × 222 3 × 2704 1.53 57.6 470 47 3.2
1874/0.3 1875/0.3 3.3 13 5 × 222 2 × 3305 2.0 56.9 470 47 4.5
1874/0.3 1875/0.3 5 13 4 × 222 3305 3.27 40.7 680 68 7.3
1874/0.3 1875/0.3 7 13 4 × 222 222 + ( 4 × 476) 3.44 40.7 680 68 10.7
1874/0.3 1875/0.3 1.2 16.5 4 × 222 4 × 5603 1.0 56.9 620 62 1.0
1874/0.3 1875/0.3 1.8 16.5 3 × 222 4 × 2704 1.0 56.9 470 47 2.0
1874/0.3 1875/0.3 2.5 16.5 3 × 222 4 × 2704 1.67 57.6 470 47 3.2
1874/0.3 1875/0.3 3.3 16.5 3 × 222 2 × 3305 2.00 56.9 510 51 4.5
1874/0.3 1875/0.3 5 16.5 3 × 222 2 × 1507 3.84 41.2 680 68 7.3
1874/0.3 1875/0.3 7 16.5 3 × 222 222 + 4 × 476 4.44 40.7 680 68 10.7
ADP1874ARQZ-0.6-R7/ 1874/0.6 1875/0.6 0.8 5.5 5 × 222 4 × 5603 0.22 56.2 300 300 0.3

ADP1875ARQZ-0.6-R7 1874/0.6 1875/0.6 1.2 5.5 5 × 222 4 × 2704 0.47 56.9 270 27 1.0
1874/0.6 1875/0.6 1.8 5.5 5 × 222 3 × 2704 0.47 56.9 220 22 2.0
1874/0.6 1875/0.6 2.5 5.5 5 × 222 3 × 1808 0.47 56.9 220 22 3.2
1874/0.6 1875/0.6 1.2 13 3 × 222 5 × 2704 0.47 56.9 360 36 1.0
1874/0.6 1875/0.6 1.8 13 5 × 109 3 × 3305 0.47 56.2 270 27 2.0
1874/0.6 1875/0.6 2.5 13 5 × 109 3 × 2704 0.90 57.6 240 24 3.2
1874/0.6 1875/0.6 3.3 13 5 × 109 2 × 2704 1.00 57.6 240 24 4.5
1874/0.6 1875/0.6 5 13 5 × 109 1507 1.76 40.7 360 36 7.3
1874/0.6 1875/0.6 1.2 16.5 3 × 109 4 × 2704 0.47 56.9 300 30 1.0
1874/0.6 1875/0.6 1.8 16.5 4 × 109 2 × 3305 0.72 53.6 270 27 2.0
1874/0.6 1875/0.6 2.5 16.5 4 × 109 3 × 2704 0.90 57.6 270 27 3.2
1874/0.6 1875/0.6 3.3 16.5 4 × 109 3305 1.0 53.0 270 27 4.5
1874/0.6 1875/0.6 5 16.5 4 × 109 4 × 476 2.0 41.2 360 36 7.3
1874/0.6 1875/0.6 7 16.5 4 × 109 3 × 476 2.0 40.7 300 30 10.7

= 1/12 × fSW, f

CROSS

V
(V)

OUT

ZERO

= ¼ × f

VIN
(V)

, R

CROSS

= 100 k, R

RES

CIN
(μF) C

OUT

(μF)

= 1 k, RON = 5.4 mΩ (BSC042N03MS G),

BOT

1

L
(μH)

RC
(kΩ)

C

COMP

(pF)

C

PAR

(pF)

R

TOP

(kΩ)

Rev. 0 | Page 34 of 44

ADP1874/ADP1875

Marking Code

SAP Model ADP1874 ADP1875

ADP1874ARQZ-1.0-R7/ 1874/1.0 1875/1.0 0.8 5.5 5 × 222 4 × 2704 0.22 54.9 200 20 0.3

ADP1875ARQZ-1.0-R7 1874/1.0 1875/1.0 1.2 5.5 5 × 222 2 × 3305 0.22 49.3 220 22 1.0
1874/1.0 1875/1.0 1.8 5.5 3 × 222 3 × 1808 0.22 56.9 130 13 2.0
1874/1.0 1875/1.0 2.5 5.5 3 × 222 2704 0.22 54.9 130 13 3.2
1874/1.0 1875/1.0 1.2 13 3 × 109 3 × 3305 0.22 53.6 200 20 1.0
1874/1.0 1875/1.0 1.8 13 4 × 109 3 × 2704 0.47 56.9 180 18 2.0
1874/1.0 1875/1.0 2.5 13 4 × 109 2704 0.47 54.9 180 18 3.2
1874/1.0 1875/1.0 3.3 13 5 × 109 2704 0.72 56.2 180 18 4.5
1874/1.0 1875/1.0 5 13 4 × 109 3 × 476 1.0 40.7 220 22 7.3
1874/1.0 1875/1.0 1.2 16.5 3 × 109 4 × 2704 0.47 56.9 270 27 1.0
1874/1.0 1875/1.0 1.8 16.5 3 × 109 3 × 2704 0.47 56.9 220 22 2.0
1874/1.0 1875/1.0 2.5 16.5 4 × 109 3 × 1808 0.72 56.9 200 20 3.2
1874/1.0 1875/1.0 3.3 16.5 4 × 109 2704 0.72 56.2 180 18 4.5
1874/1.0 1875/1.0 5 16.5 3 × 109 3 × 476 1.2 40.7 220 22 7.3
1874/1.0 1875/1.0 7 16.5 3 × 109 222 + 476 1.2 40.7 180 18 10.7

1

See the section and . Inductor Selection Table 11

2

22 μF Murata 25 V, X7R, 1210 GRM32ER71E226KE15L (3.2 mm × 2.5 mm × 2.5 mm).

3

560 μF Panasonic (SP-series) 2 V, 7 mΩ, 3.7 A EEFUE0D561LR (4.3 mm × 7.3 mm × 4.2 mm).

4

270 μF Panasonic (SP-series) 4 V, 7 mΩ, 3.7 A EEFUE0G271LR (4.3 mm × 7.3 mm × 4.2 mm).

5

330 μF Panasonic (SP-series) 4 V, 12 mΩ, 3.3 A EEFUE0G331R (4.3 mm × 7.3 mm × 4.2 mm).

6

47 μF Murata 16 V, X5R, 1210 GRM32ER61C476KE15L (3.2 mm × 2.5 mm × 2.5 mm).

7

150 μF Panasonic (SP-series) 6.3 V, 10 mΩ, 3.5 A EEFUE0J151XR (4.3 mm × 7.3 mm × 4.2 mm).

8

180 μF Panasonic (SP-series) 4 V, 10 mΩ, 3.5 A EEFUE0G181XR (4.3 mm × 7.3 mm × 4.2 mm).

9

10 μF TDK 25 V, X7R, 1210 C3225X7R1E106M.

(First Line/Second Line)

V
(V)

OUT

VIN

CIN

(V)

(μF)

(μF)

C

OUT

1

L
(μH)

RC
(kΩ)

C

COMP

(pF)

C

PAR

(pF)

R

TOP

(kΩ)

Table 11. Recommended Inductors

L (μH) DCR (mΩ) I

(A) Dimension (mm) Manufacturer Model Number

SAT

0.12 0.33 55 10.2 × 7 Würth Elektronik 744303012

0.22 0.33 30 10.2 × 7 Würth Elektronik 744303022

0.47 0.8 50 14.2 × 12.8 Würth Elektronik 744355147

0.72 1.65 35 10.5 × 10.2 Würth Elektronik 744325072

0.9 1.6 32 14 × 12.8 Würth Elektronik 744318120

1.2 1.8 25 10.5 × 10.2 Würth Elektronik 744325120

1.0 3.8 16 10.2 × 10.2 Würth Elektronik 7443552100

1.4 3.2 24 14 × 12.8 Würth Elektronik 744318180

2.0 2.6 23 10.2 × 10.2 Würth Elektronik 7443551200

0.8 27.5 Sumida CEP125U-0R8

Table 12. Recommended MOSFETs

VGS = 4.5 V RON (mΩ) ID (A) VDS (V) CIN (nF) Q

Upper-Side MOSFET

5.4 47 30 3.2 20 PG-TDSON8 Infineon BSC042N03MS G

(nC) Package Manufacturer Model Number

TOTAL

(Q1/Q2)

10.2 53 30 1.6 10 PG-TDSON8 Infineon BSC080N03MS G

6.0 19 30 35 SO-8 Vishay Si4842DY
9 14 30 2.4 25 SO-8 International Rectifier IRF7811
Lower-Side MOSFET

5.4 47 30 3.2 20 PG-TDSON8 Infineon BSC042N03MS G

(Q3/Q4)

10.2 82 30 1.6 10 PG-TDSON8 Infineon BSC080N03MS G

6.0 19 30 35 SO-8 Vishay Si4842DY

Rev. 0 | Page 35 of 44

ADP1874/ADP1875

V

LAYOUT CONSIDERATIONS

The performance of a dc-to-dc converter depends highly on how
the voltage and current paths are configured on the printed circuit
board (PCB). Optimizing the placement of sensitive analog and
power components is essential to minimize output ripple,
maintain tight regulation specifications, and reduce PWM jitter
and electromagnetic interference.

HIGH VOLTAGE INPUT

JP3

C

VIN

22µF

V

C

PAR

53pF

REG

OUT

R

0.1µF

R7 10k

2k

TOP

R

1k

C2

C

C

430pF
R

C

57k

BOT

R

RES

100k

1µF

C1

ADP1874/

ADP1875

1

VIN

2

COMP

3

EN

4

FB

5

GND

6

RES11PGOOD

7

VREG

8

VREG_IN9TRACK

BST

SW

DRVH

PGND

DRVL

SS

C

BST

100nF

16

15

14

13

12

5k

V

10

10k

Figure 90. ADP1874 High Current Evaluation Board Schematic (Blue Traces Indicate High Current Paths)

V

IN

Q1 Q2

Q3 Q4

REG

V

REG

Figure 90 shows the schematic of a typical ADP1874/ADP1875
used for a high current application. Blue traces denote high current
pathways. VIN, PGND, and V

traces should be wide and

OUT

possibly replicated, descending down into the multiple layers.
Vias should populate, mainly around the positive and negative
terminals of the input and output capacitors, alongside the source
of Q1/Q2, the drain of Q3/Q4, and the inductor.

= 12V

C3

22µFC422µFC522µFC622µFC722µFC8N/AC9N/A

1.0µH

R

SNB

2

C

SNB

1.5nF

MURATA: (HIGH VOLTAGE INPUT CAPACITORS)

C

SS

34nF

PANASONIC: (OUTPUT CAPACITORS)

INFINEON MOSFETs:

WÜRTH INDUCTORS:

C20

270µF

+

C25

C24

N/A

N/A

22µF, 25V, X7R, 1210 GRM32ER71E226KE15L

270µF, SP-SERIES, 4V, 7m EEFUE0G271LR

BSC042N03MS G (LOWER SIDE)
BSC080N03MS G (UPPER SIDE)

1µH, 3.8m, 16A 7443552100

+

270µF

C21

+

C26

N/A

V

+

= 1.8V, 15A

OUT

C22

270µF

+

C27

N/A

+

270µF

C23

+

C14 TO C19
N/A

+

09347-081

SENSITIVE ANALOG
COMPONENTS
LOCATED FAR
FROM NOISY
POWER SECTION

SEPARATE ANALOG
GROUND PLANE FOR
COMPENSATION AND
FEEDBACK RESISTORS

INPUT CAPACITORS
ARE MOUNTED CLOSE
TO DRAIN OF Q1/Q2
AND SOURCE OF Q3/Q4

OUTPUT
CAPACITORS
ARE MOUNTED
AT RIGHTMOST
AREA OF
EVALUATION
BOARD

09347-092

Figure 91. Overall Layout of the ADP1870 High Current Evaluation Board

Rev. 0 | Page 36 of 44

ADP1874/ADP1875

09347-093

Figure 92. Layer 2 of Evaluation Board

TOP RESISTOR
FEEDBACK TAP

VOUT SENSE TAP LINE
EXTENDING BACK TO THE
TOP RESISTOR IN THE
FEEDBACK DIVIDER
NETWORK. THIS OVERLAPS
WITH PGND SENSE TAP
LINE EXTENDING TO THE
ANALOG GROUND PLANE

9347-094

Figure 93. Layer 3 of Evaluation Board

Rev. 0 | Page 37 of 44

ADP1874/ADP1875

BOTTOM
RESISTOR TAP
TO ANALOG
GROUND PLANE

PGND SENSE TAP FROM
NEGATIVE TERMINALS OF
THE OUTPUT BULK
CAPACITORS. THIS
TRACK PLACEMENT
SHOULD BE DIRECTLY
BELOW THE VOUT SENSE
LINE OF LAYER 3.

Figure 94. Layer 4 (Bottom Layer) of Evaluation Board

IC SECTION (LEFT SIDE OF EVALUATION BOARD)

A dedicated plane for the analog ground plane (GND) should
be separate from the main power ground plane (PGND). With
the shortest path possible, connect the analog ground plane to
the GND pin (Pin 5). This plane should be on only the top layer
of the evaluation board. To avoid crosstalk interference, there
should not be any other voltage or current pathway directly below
this plane on Layer 2, Layer 3, or Layer 4. Connect the negative
terminals of all sensitive analog components to the analog ground
plane. Examples of such sensitive analog components include
the resistor divider’s bottom resistor, the high frequency bypass
capacitor for biasing (0.1 µF), and the compensation network.

Mount a 1 µF bypass capacitor directly across the VREG pin
(Pin 7) and the PGND pin (Pin 13). In addition, a 0.1 µF should
be tied across the VREG pin (Pin 7) and the GND pin (Pin 5).

POWER SECTION

As shown in Figure 91, an appropriate configuration to localize
large current transfer from the high voltage input (V
output (V

plane on the left, the output plane on the right, and the main

V

IN

) and then back to the power ground is to put the

OUT

power ground plane in between the two. Current transfers from
the input capacitors to the output capacitors, through Q1/Q2,
during the on state (see Figure 95). The direction of this current
(yellow arrow) is maintained as Q1/Q2 turns off and Q3/Q4 turns
on. When Q3/Q4 turns on, the current direction continues to be
maintained (yellow arrow) as it circles from the bulk capacitor
power ground terminal to the output capacitors, through
Q3/Q4. Arranging the power planes in this manner minimizes
the area in which changes in flux occur if the current through
Q1/Q2 stops abruptly. Sudden changes in flux, usually at the
source terminals of Q1/Q2 and the drain terminal of Q3/Q4,
cause large dv/dt at the SW node.

) to the

IN

Rev. 0 | Page 38 of 44

The SW node is near the top of the evaluation board. The SW
node should use the least amount of area possible and be away
from any sensitive analog circuitry and components. This is
because the SW node is where most sudden changes in flux
density occur. When possible, replicate this pad onto Layer 2
and Layer 3 for thermal relief and eliminate any other voltage and
current pathways directly beneath the SW node plane. Populate
the SW node plane with vias, mainly around the exposed pad of
the inductor terminal and around the perimeter of the source of
Q1/Q2 and the drain of Q3/Q4. The output voltage power plane

) is at the rightmost end of the evaluation board. This plane

(V

OUT

should be replicated, descending down to multiple layers with
vias surrounding the inductor terminal and the positive terminals
of the output bulk capacitors. Ensure that the negative terminals of
the output capacitors are placed close to the main power ground
(PGND), as previously mentioned. All of these points form a
tight circle (component geometry permitting) that minimizes
the area of flux change as the event switches between D and 1 − D.

Figure 95. Primary Current Pathways During the On State of the Upper-Side

MOSFET (Left Arrow) and the On State of the Lower-Side MOSFET (Right Arrow)

09347-095

09347-086

ADP1874/ADP1875

DIFFERENTIAL SENSING

Because the ADP1874/ADP1875 operate in valley current­mode control, a differential voltage reading is taken across the
drain and source of the lower-side MOSFET. The drain of the
lower-side MOSFET should be connected as close as possible to
the SW pin (Pin 15) of the IC. Likewise, the source should be
connected as close as possible to the PGND pin (Pin 13) of the
IC. When possible, both of these track lines should be narrow
and away from any other active device or voltage/current path.

SW

PGND

Differential sensing should also be employed between the
outermost output capacitor and the feedback resistor divider
(see Figure 93 and Figure 94). Connect the positive terminal of
the output capacitor to the top resistor (R

). Connect the negative

T

terminal of the output capacitor to the negative terminal of the
bottom resistor, which connects to the analog ground plane as
well. Both of these track lines, as previously mentioned, should
be narrow and away from any other active device or voltage/
current path.

LAYER 1: SENSE LINE FOR SW
(DRAIN OF LOWER MOSFET)

Figure 96. Drain/Source Tracking Tapping of the Lower-Side MOSFET for CS

Amp Differential Sensing (Yellow Sense Line on Layer 2).

LAYER 1: SENSE LINE FOR PGND
(SOURCE OF L OWER MOSFET)

09347-087

Rev. 0 | Page 39 of 44

ADP1874/ADP1875

TYPICAL APPLICATION CIRCUITS

12 A, 300 kHz HIGH CURRENT APPLICATION CIRCUIT

HIGH VOLTAGE INPUT

V

= 12V

IN

JP3

C

VIN

22µF

C

C

R7 10k

R

C2

0.1µF

TOP

2k

R

BOT

1k

560pF
R

C

49.3k

R

RES

100k

C1

1µF

C

PAR

56pF

V

REG

V

OUT

ADP1874/

ADP1875

1

VIN

2

COMP

3

EN

4

FB

5

GND

6

RES11PGOOD

7

VREG

8

VREG_IN9TRACK

BST

SW

DRVH

PGND

DRVL

SS

C

BST

100nF

16

15

14

13

12

5k

10

10k

Q1 Q2

Q3 Q4

V

REG

V

REG

Figure 97. Application Circuit for 12 V Input, 1.8 V Output, 12 A, 300 kHz (Q2/Q4 No Connect)

C3

22µFC422µFC522µFC622µFC722µFC8N/AC9N/A

1.2µH

R

SNB

2

C

SNB

1.5nF

MURATA: (HIGH VOLTAGE INPUT CAPACITORS)

C

SS

34nF

PANASONIC: (OUTPUT CAPACITORS)

INFINEON MOSFETs:

WÜRTH INDUCTORS:

C20

270µF

+

C25

C24

N/A

N/A

22µF, 25V, X7R, 1210 GRM32ER71E226KE15L

270µF, SP-SERIES, 4V, 7m EEFUE0G271LR

BSC042N03MS G (LOWER SIDE)
BSC080N03MS G (UPPER SIDE)

1.2µH, 2.00m, 20A 744325120

+

270µF

C21

+

C26

N/A

V

+

= 1.8V, 12A

OUT

C22

270µF

+

C27

N/A

+

270µF

C23

+

+

C14 TO C19
N/A

09347-088

5.5 V INPUT, 600 kHz APPLICATION CIRCUIT

JP3

C

VIN

22µF

C

C

220pF

C

22pF

V

REG

V

OUT

F

R

0.1µF

R7 10k

3.2k

TOP

R

BOT

1k

C2

R

C

56.9k

R

RES

100k

C1

1µF

Figure 98. Application Circuit for 5.5 V Input, 2.5 V Output, 12 A, 600 kHz (Q2/Q4 No Connect)

ADP1874/

ADP1875

1

VIN

2

COMP

3

EN

4

FB

5

GND

6

RES11PGOOD

7

VREG

8

VREG_IN9TRACK

BST

SW

DRVH

PGND

DRVL

SS

16

15

14

13

12

10

HIGH VOLTAGE INPUT

V

= 5.5V

IN

C

BST

100nF

Q1 Q2

Q3 Q4

5k

V

REG

10k

V

REG

C3

22µFC422µFC522µFC622µFC722µFC8N/AC9N/A

1.2µH

R

SNB

2

C

SNB

1.5nF

MURATA: (HIGH VOLTAGE INPUT CAPACITORS)

C

SS

34nF

PANASONIC: (OUTPUT CAPACITORS)

INFINEON MOSFETs:

WÜRTH INDUCTORS:

C20

180µF

+

C25

C24

N/A

N/A

22µF, 25V, X7R, 1210 GRM32ER71E226KE15L

180µF, SP-SERIES, 4V, 10m EEFUE0G181XR

BSC042N03MS G (LOWER SIDE)
BSC080N03MS G (UPPER SIDE)

0.47µH, 0.8m, 30A 744355147

+

C21

180µF

+

C26
N/A

V

OUT

+

= 2.5V, 12A

C22

180µF

+

C27
N/A

+

C23

N/A

+

+

C14 TO C19
N/A

09347-089

Rev. 0 | Page 40 of 44

ADP1874/ADP1875

300 kHz HIGH CURRENT APPLICATION CIRCUIT

HIGH VOLTAGE INPUT

V

= 13V

IN

JP3

C

VIN

22µF

C3

22µFC422µFC522µFC622µFC722µFC8N/AC9N/A

1.2µH

R

SNB

2

C

SNB

1.5nF

MURATA: (HIGH VOLTAGE INPUT CAPACITORS)

C

SS

34nF

PANASONIC: (OUTPUT CAPACITORS)

INFINEON MOSFETs:

WÜRTH INDUCTORS:

C20

270µF

+

C25

C24

N/A

N/A

22µF, 25V, X7R, 1210 GRM32ER71E226KE15L

270µF, SP-SERIES, 4V, 7m EEFUE0G271LR

BSC042N03MS G (LOWER SIDE)
BSC080N03MS G (UPPER SIDE)

1.2µH, 2.00m, 20A 744325120

+

C21

270µF

+

V

C26

N/A

OUT

+

= 1.8V, 12A

C22

270µF

+

C27
N/A

+

C23

270µF

+

+

C14 TO C19
N/A

09347-090

C

PAR

56pF

V

REG

V

OUT

R

0.1µF

C2

R7 10k

2k

TOP

R

BOT

1k

100k

C

C

560pF
R

C

49.3k

R

RES

C1

1µF

ADP1874/

ADP1875

1

VIN

2

COMP

3

EN

4

FB

5

GND

6

RES

7

VREG

8

VREG_IN9TRACK

BST

SW

DRVH

PGND

DRVL

PGOOD

SS

C

BST

100nF

16

15

14

13

12

5k

11

10

10k

Q1 Q2

Q3 Q4

V

REG

V

REG

Figure 99. Application Circuit for 13 V Input, 1.8 V Output, 12 A, 300 kHz (Q2/Q4 No Connect)

Rev. 0 | Page 41 of 44

ADP1874/ADP1875

OUTLINE DIMENSIONS

0.197 (5.00)

0.193 (4.90)

0.189 (4.80)

0.065 (1.65)

0.049 (1.25)

0.010 (0.25)

0.004 (0.10)

COPLANARITY

0.004 (0.10)

16

1

0.025 (0.64)
BSC

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRI ATE FOR USE IN DESIGN.

9

0.158 (4.01)

0.154 (3.91)

0.150 (3.81)

8

0.069 (1.75)

0.053 (1.35)

SEATING

0.012 (0.30)

0.008 (0.20)

COMPLIANT TO JEDEC STANDARDS MO-137-AB

PLANE

0.244 (6.20)

0.236 (5.99)

0.228 (5.79)

8°
0°

0.010 (0.25)

0.006 (0.15)

0.050 (1.27)

0.016 (0.41)

0.020 (0.51)

0.010 (0.25)

0.041 (1.04)
REF

012808-A

Figure 100. 16-Lead Shrink Small Outline Package [QSOP]

(RQ-16)

Dimensions shown in inches and (millimeters)

ORDERING GUIDE

Branding

Model1 Temperature Range Package Description Package Option

ADP1874ARQZ-0.3-R7 −40°C to +125°C 16-Lead Shrink Small Outline Package [QSOP] RQ-16 1874/0.3
ADP1874ARQZ-0.6-R7 −40°C to +125°C 16-Lead Shrink Small Outline Package [QSOP] RQ-16 1874/0.6
ADP1874ARQZ-1.0-R7 −40°C to +125°C 16-Lead Shrink Small Outline Package [QSOP] RQ-16 1874/1.0
ADP1874-0.3-EVALZ Evaluation Board
ADP1874-0.6-EVALZ Evaluation Board
ADP1874-1.0-EVALZ Evaluation Board
ADP1875ARQZ-0.3-R7 −40°C to +125°C 16-Lead Shrink Small Outline Package [QSOP] RQ-16 1875/0.3
ADP1875ARQZ-0.6-R7 −40°C to +125°C 16-Lead Shrink Small Outline Package [QSOP] RQ-16 1875/0.6
ADP1875ARQZ-1.0-R7 −40°C to +125°C 16-Lead Shrink Small Outline Package [QSOP] RQ-16 1875/1.0
ADP1875-0.3-EVALZ Evaluation Board
ADP1875-0.6-EVALZ Evaluation Board
ADP1875-1.0-EVALZ Evaluation Board

1

Z = RoHS Compliant Part.

(1st Line/2nd Line)

Rev. 0 | Page 42 of 44

ADP1874/ADP1875

NOTES

Rev. 0 | Page 43 of 44

ADP1874/ADP1875

NOTES

©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09347-0-2/11(0)

Rev. 0 | Page 44 of 44