Datasheet ADP1873 Datasheet (ANALOG DEVICES)

Synchronous Current-Mode with

V

V

Constant On-Time, PWM Buck Controller

FEATURES

Power input voltage as low as 2.75 V to 20 V
Bias supply voltage range: 2.75 V to 5.5 V
Minimum output voltage: 0.6 V

0.6 V reference voltage with ±1.0% accuracy
Supports all N-channel MOSFET power stages
Available in 300 kHz, 600 KHz, and 1.0 MHz options
No current-sense resistor required
Power saving mode (PSM) for light loads (ADP1873 only)
Resistor-programmable current-sense gain
Thermal overload protection
Short-circuit protection
Precision enable input
Integrated bootstrap diode for high-side drive
140 μA shutdown supply current
Starts into a precharged load
Small, 10-lead MSOP package

APPLICATIONS

Telecom and networking systems
Mid to high end servers
Set-top boxes
DSP core power supplies

ADP1872/ADP1873

TYPICAL APPLICATIONS CIRCUIT

C

C

C

C2

R

C

R

TOP

V

OUT

R

BOT

C

VDD2

VDD = 2.75V

TO 5.5V

C

VDD

100

= 5.5V, VIN = 5.5V (PSM)

V

DD

95

90

85

80

75

70

65

EFFICIENCY (%)

60

55

50

45

V

DD

100 1k 10k 100k

Figure 2. ADP1872 Efficiency vs. Load Current (V

VIN

ADP1872/

ADP1873

COMP/EN

FB DRVH

GND SW

VDD DRVL

BST

PGND

Figure 1.

= 5.5V, VIN = 13.0V (PS M)

V

DD

= 5.5V, VIN = 16.5V (PSM )

TA = 25°C
V

= 1.8V

OUT

f

= 300kHz

SW

WURTH INDUCTOR:
744325120, L = 1.2µH, DCR = 1.8m

INFINEON FETs:
BSC042N03MS G (UPPER/ LOWER)

LOAD CURRENT (mA)

= 2.75V TO 20

IN

C

IN

C

BST

R

RES

V

= 5.5V, VIN = 5.5V

DD

OUT

Q1

L

V

OUT

+

C

OUT

Q2

LOAD

5A

= 1.8 V, 300 kHz)

08297-001

08297-002

GENERAL DESCRIPTION

The ADP1872/ADP1873 are versatile current-mode, synchronous
step-down controllers that provide superior transient response,
optimal stability, and current limit protection by using a constant
on-time, pseudo-fixed frequency with a programmable current­sense gain, current-control scheme. In addition, these devices offer
optimum performance at low duty cycles by using valley current­mode control architecture. This allows the ADP1872/ADP1873
to drive all N-channel power stages to regulate output voltages
as low as 0.6 V.

The ADP1873 is the power saving mode (PSM) version of the
device and is capable of pulse skipping to maintain output
regulation while achieving improved system efficiency at light
loads (see the Power Saving Mode (PSM) Version (ADP1873)
section for more information).

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

Available in three frequency options (300 kHz, 600 kHz, and

1.0 MHz, plus the PSM option), the ADP1872/ADP1873 are
well suited for a wide range of applications. These ICs not only
operate from a 2.75 V to 5.5 V bias supply, but can also accept a
power input as high as 20 V.

In addition, an internally fixed, soft start period is included to limit
input in-rush current from the input supply during startup and
to provide reverse current protection during soft start for a pre­charged output. The low-side current-sense, current-gain scheme
and integration of a boost diode, along with the PSM/forced pulse­width modulation (PWM) option, reduce the external part count
and improve efficiency.

The ADP1872/ADP1873 operate over the −40°C to +125°C
junction temperature range and are available in a 10-lead MSOP.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2009–2010 Analog Devices, Inc. All rights reserved.

ADP1872/ADP1873

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

Typical Applications Circuit ............................................................ 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Absolute Maximum Ratings ............................................................ 5

Thermal Resistance ...................................................................... 5

Boundary Condition .................................................................... 5

ESD Caution .................................................................................. 5

Pin Configuration and Function Descriptions ............................. 6

Typical Performance Characteristics ............................................. 7

ADP1872/ADP1873 Block Digram .............................................. 17

Theory of Operation ...................................................................... 18

Startup .......................................................................................... 18

Soft Start ...................................................................................... 18

Precision Enable Circuitry ........................................................ 18

Undervoltage Lockout ............................................................... 18

Thermal Shutdown ..................................................................... 18

Programming Resistor (RES) Detect Circuit .......................... 19

Valley Current-Limit Setting .................................................... 19

Hiccup Mode During Short Circuit ......................................... 20

Synchronous Rectifier ................................................................ 21

Power Saving Mode (PSM) Version (ADP1873) .................... 21

Timer Operation ........................................................................ 21

Pseudo-Fixed Frequency ........................................................... 22

Applications Information .............................................................. 23

Feedback Resistor Divider ........................................................ 23

Inductor Selection ...................................................................... 23

Output Ripple Voltage (VRR) .................................................. 23

Output Capacitor Selection ....................................................... 23

Compensation Network ............................................................ 24

Efficiency Consideration ........................................................... 25

Input Capacitor Selection .......................................................... 26

Thermal Considerations ............................................................ 27

Design Example .......................................................................... 27

External Component Recommendations .................................... 30

Layout Considerations ................................................................... 32

IC Section (Left Side of Evaluation Board) ............................. 37

Power Section ............................................................................. 37

Differential Sensing .................................................................... 37

Typical Application Circuits ......................................................... 38

Dual-Input, 300 kHz High Current Application Circuit ...... 38

Single-Input, 600 kHz Application Circuit ............................. 38

Dual-Input, 300 kHz High Current Application Circuit ...... 39

Outline Dimensions ....................................................................... 40

Ordering Guide .......................................................................... 40

REVISION HISTORY

3/10—Rev. 0 to Rev. A

Changes to Figure 1 .......................................................................... 1

Changes to Table 1 ............................................................................ 3

Changes to Table 2 ............................................................................ 5

Changes to Figure 59 Caption and Figure 60 Caption .............. 16

Changes to Figure 64 ...................................................................... 17

Changes to Timer Operation Section .......................................... 22

Changes to Table 7 .......................................................................... 23

Changes to Inductor Section ......................................................... 28

Changes to Table 9 .......................................................................... 31

Changes to Figure 82 ...................................................................... 32

Rev. A | Page 2 of 40

Changes to Figure 83 ...................................................................... 33

Changes to Figure 84 ...................................................................... 34

Changes to Figure 85 ...................................................................... 35

Changes to Figure 86 ...................................................................... 36

Changes to Differential Sensing Section and Figure 88 ............ 37

Changes to Figure 89 and Figure 90............................................. 38

Changes to Figure 91 ...................................................................... 39

Updated Outline Dimensions ....................................................... 40

10/09—Revision 0: Initial Version

ADP1872/ADP1873

SPECIFICATIONS

All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). VDD = 5 V,
BST − SW = 5 V, VIN = 13 V. The specifications are valid for T

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

POWER SUPPLY CHARACTERISTICS

High Input Voltage Range VIN ADP1872ARMZ-0.3/ADP1873ARMZ-0.3 (300 kHz) 2.75 12 20 V
ADP1872ARMZ-0.6/ADP1873ARMZ-0.6 (600 kHz) 2.75 12 20 V
ADP1872ARMZ-1.0/ADP1873ARMZ-1.0 (1.0 MHz) 3.0 12 20 V
Low Input Voltage Range VDD CIN = 1 μF to PGND, CIN = 0.22 μF to GND
ADP1872ARMZ-0.3/ADP1873ARMZ-0.3 (300 kHz) 2.75 5 5.5 V
ADP1872ARMZ-0.6/ADP1873ARMZ-0.6 (600 kHz) 2.75 5 5.5 V
ADP1872ARMZ-1.0/ADP1873ARMZ-1.0 (1.0 MHz) 3.0 5 5.5 V
Quiescent Current I
Shutdown Current I

Q_DD

DD, SD

+ I

FB = 1.5 V, no switching 1.1 mA

Q_BST

+ I

COMP/EN < 285 mV 140 215 μA

BST, SD

Undervoltage Lockout UVLO Rising VDD (See Figure 34 for temperature variation) 2.65 V
UVLO Hysteresis Falling VDD from operational state 190 mV

SOFT START

Soft Start Period See Figure 57 3.0 ms

ERROR AMPLIFER

FB Regulation Voltage VFB T
T
T

= 25°C 600 mV

J

= −40°C to +85°C 595.5 600 605.4 mV

J

= −40°C to +125°C 594.2 600 606.5 mV

J

Transconductance GM 300 515 730 μs
FB Input Leakage Current I

FB = 0.6 V, COMP/EN = released 1 50 nA

FB, LEAK

CURRENT-SENSE AMPLIFIER GAIN

Programming Resistor (RES)

RES = 47 kΩ ± 1% 2.7 3 3.3 V/V

Value from DRVL to PGND
RES = 22 kΩ ± 1% 5.5 6 6.5 V/V
RES = none 11 12 13 V/V
RES = 100 kΩ ± 1% 22 24 26 V/V

SWITCHING FREQUENCY

Typical values measured at 50% time points with
0 nF at DRVH and DRVL; maximum values are
guaranteed by bench evaluation

ADP1872ARMZ-0.3/

300 kHz

ADP1873ARMZ-0.3 (300 kHz)

On-Time VIN = 5 V, V

Minimum On-Time VIN = 20 V 145 190 ns

Minimum Off-Time 84% duty cycle (maximum) 320 385 ns
ADP1872ARMZ-0.6/

600 kHz

ADP1873ARMZ-0.6 (600 kHz)

On-Time VIN = 5 V, V

Minimum On-Time VIN = 20 V, V

Minimum Off-Time 65% duty cycle (maximum) 320 385 ns
ADP1872ARMZ-1.0/

1.0 MHz

ADP1873ARMZ-1.0 (1.0 MHz)

On-Time VIN = 5 V, V

Minimum On-Time VIN = 20 V 60 85 ns

Minimum Off-Time 45% duty cycle (maximum) 320 385 ns

= −40°C to +125°C, unless otherwise specified.

J

1

= 2 V, TJ = 25°C 1120 1200 1280 ns

OUT

= 2 V, TJ = 25°C 500 520 580 ns

OUT

= 0.8 V 82 110 ns

OUT

= 2 V, TJ = 25°C 285 312 340 ns

OUT

Rev. A | Page 3 of 40

ADP1872/ADP1873

Parameter Symbol Conditions Min Typ Max Unit

OUTPUT DRIVER CHARACTERISTICS

High-Side Driver

Output Source Resistance I
Output Sink Resistance I
Rise Time2 t
Fall Time2 t

BST − SW = 4.4 V, CIN = 4.3 nF (see Figure 59) 25 ns

r, DR VH

BST − SW = 4.4 V, CIN = 4.3 nF (see Figure 60) 11 ns

f, DRV H

Low-Side Driver

Output Source Resistance I
Output Sink Resistance I
Rise Time2 t
Fall Time2 t

VDD = 5.0 V, CIN = 4.3 nF (see Figure 60) 18 ns

r, DR VL

VDD = 5.0 V, CIN = 4.3 nF (see Figure 59) 16 ns

f, DRV L

Propagation Delays

DRVL Fall to DRVH Rise2 t
DRVH Fall to DRVL Rise2 t

SW Leakage Current I

BST − SW = 4.4 V (see Figure 59) 22 ns

tpdh, DRVH

BST − SW = 4.4 V (see Figure 60) 24 ns

tpdh, DRVL

BST = 25 V, SW = 20 V, VDD = 5.5 V 110 μA

SW, LEAK

Integrated Rectifier

Channel Impedance I

PRECISION ENABLE THRESHOLD

Logic High Level VIN = 2.9 V to 20 V, VDD = 2.75 V to 5.5 V 235 285 330 mV
Enable Hysteresis VIN = 2.9 V to 20 V, VDD = 2.75 V to 5.5 V 35 mV

COMP VOLTAGE

COMP Clamp Low Voltage V

COMP Clamp High Voltage V
COMP Zero Current Threshold V

THERMAL SHUTDOWN T

COMP (LOW )

COMP (H IGH)

COMP_ZC T

TMSD

(2.75 V ≤ VDD ≤ 5.5 V) 2.55 V

(2.75 V ≤ VDD ≤ 5.5 V) 1.15 V

Thermal Shutdown Threshold Rising temperature 155 °C
Thermal Shutdown Hysteresis 15 °C
Hiccup Current Limit Timing 6 ms

1

The maximum specified values are with the closed loop measured at 10% to 90% time points (see Figure and Figure 60), C

MOSFETs being Infineon BSC042N03MS G.

2

Not automatic test equipment (ATE) tested.

= 1.5 A, 100 ns, positive pulse (0 V to 5 V) 2 3.5 Ω

SOURCE

= 1.5 A, 100 ns, negative pulse (5 V to 0 V) 0.8 2 Ω

SINK

= 1.5 A, 100 ns, positive pulse (0 V to 5 V) 1.7 3 Ω

SOURCE

= 1.5 A, 100 ns, negative pulse (5 V to 0 V) 0.75 2 Ω

SINK

= 10 mA 22 Ω

SINK

From disable state, release COMP/EN pin to enable

0.47 V

device (2.75 V ≤ VDD ≤ 5.5 V)

59

= 4.3 nF and upper- and lower-side

GATE

Rev. A | Page 4 of 40

ADP1872/ADP1873

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

VDD to GND −0.3 V to +6 V
VIN to PGND −0.3 V to +28 V
FB, COMP/EN to GND −0.3 V to (VDD + 0.3 V)
DRVL to PGND −0.3 V to (VDD + 0.3 V)
SW to PGND −0.3 V to +28 V
SW to PGND −2 V pulse (20 ns)
BST to SW −0.6 V to (VDD + 0.3 V)
BST to PGND −0.3 V to +28 V
DRVH to SW −0.3 V to VDD
PGND to GND ±0.3 V
Operating Junction Temperature

Range

Storage Temperature Range −65°C to +150°C
Soldering Conditions JEDEC J-STD-020
Maximum Soldering Lead

Temperature (10 sec)

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

−40°C to +125°C

300°C

Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all other voltages are
referenced to PGND.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 3. Thermal Resistance

Package Type θJA Unit

θJA (10-Lead MSOP)

2-Layer Board 213.1 °C/W
4-Layer Board 171.7 °C/W

BOUNDARY CONDITION

In determining the values given in Ta b l e 2 and Ta b le 3 , natural
convection was used to transfer heat to a 4-layer evaluation board.

ESD CAUTION

Rev. A | Page 5 of 40

ADP1872/ADP1873

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VIN

1

FB

GND

VDD

2

ADP1872

3

TOP VIEW

(Not to Scale)

4

5

COMP/EN

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 VIN High Input Voltage. Connect VIN to the drain of the upper-side MOSFET.
2 COMP/EN Output of the Internal Error Amplifier/IC Enable. When this pin functions as EN, applying 0 V to this pin disables the IC.
3 FB Noninverting Input of the Internal Error Amplifier. This is the node where the feedback resistor is connected.
4 GND

Analog Ground Reference Pin of the IC. All sensitive analog components should be connected to this ground
plane (see the Layout Considerations Section).

5 VDD

Bias Voltage Supply for the ADP1872/ADP1873 Controller (Includes the Output Gate Drivers). A bypass capacitor
of 1 μF directly from this pin to PGND and a 0.1 μF across VDD and GND are recommended.

6 DRVL

Drive Output for the External Lower Side, N-Channel MOSFET. This pin also serves as the current-sense gain

setting pin (see Figure 68).
7 PGND Power GND. Ground for the lower side gate driver and lower side, N-channel MOSFET.
8 DRVH Drive Output for the External Upper Side, N-Channel MOSFET.
9 SW Switch Node Connection.
10 BST

Bootstrap for the Upper Side MOSFET Gate Drive Circuitry. An internal boot rectifier (diode) is connected

between VDD and BST. A capacitor from BST to SW is required. An external Schottky diode can also be

connected between VDD and BST for increased gate drive capability.

BST

10

9

SW

8

DRVH

PGND

7

DRVL

6

08297-003

Rev. A | Page 6 of 40

ADP1872/ADP1873

TYPICAL PERFORMANCE CHARACTERISTICS

100

VDD = 5.5V, VIN = 13V (PSM)

95

V

= 5.5V,

DD

V

= 16.5V ( PSM)

IN

90

85

80

VDD = 5.5V,

75

V

= 5.5V

IN

(PSM)

70

65

60

55

EFFICIENCY (%)

50

45

40

35

30

100 100k10k1k

Figure 4. Efficiency—300 kHz, V

V

= 5.5V, VIN = 5.5V

DD

= 3.6V, VIN = 5.5V

V

DD

V

= 5.5V, VIN = 13V

DD

V

= 3.6V, VIN = 13V

DD

V

= 5.5V, VIN = 16.5V

DD

V

= 3.6V, VIN = 16.5V

DD

WURTH IND: 744355147, L = 0.47µH, DCR: 0.80m
INFINEON FETs: BSC042N03MS G (UPPER/LOWER)
TA = 25°C

LOAD CURRENT (mA)

= 0.8 V

OUT

08297-004

100

VDD = 5.5V, VIN = 13V (PSM)

95

V

= 5.5V, VIN = 5.5V (PSM)

DD

90
85
80
75

V

= 5.5V,

DD

70

V

= 16.5V

IN

(PSM)

65
60
55
50
45

EFFICIENCY (%)

40
35
30
25
20
15

100 100k10k1k

Figure 7. Efficiency—600 kHz, V

= 5.5V, VIN = 5.5V

V

DD

V

= 3.6V, VIN = 5.5V

V

= 5.5V, VIN = 13V

DD

V

= 5.5V, VIN = 16.5V

DD

WURTH IND: 744355147, L = 0.47µH, DCR: 0.80m
INFINEON FETs: BSC042N03MS G (UPPER/LOWER)
TA = 25°C

DD

LOAD CURRENT (mA)

= 0.8 V

OUT

08297-007

100

VDD = 5.5V, VIN = 5.5V (PSM)

95

90

85

80

75

70

65

60

55

EFFICIENCY (%)

50

45

40

35

30

25

100 100k10k1k

Figure 5. Efficiency—300 kHz, V

100

VDD = 5.5V, VIN = 16.5V (PSM)

95

90

85

80

= 5.5V,

V

DD

V

= 16V

IN

75

(PSM)

70

65

60

55

EFFICIENCY (%)

50

45

40

35

30

100 100k10k1k

Figure 6. Efficiency—300 kHz, V

V

= 5.5V, VIN = 16.5V ( PSM)

V

DD

V

= 5.5V, VIN = 16.5V

DD

V

= 5.5V, VIN = 13V (PSM)

DD

V

= 3.6V, VIN = 3.6V

DD

V

= 5.5V, VIN = 13V

DD

V

= 3.6V, VIN = 5.5V

DD

WURTH IND: 744325120, L = 1.2µH, DCR: 1.8m
INFINEON FETS: BSC042N03MS G ( UPPER/LOWER)
TA = 25°C

LOAD CURRENT (mA)

OUT

VDD = 2.7V

13V

16.5V

WURTH IND: 7443551200, L = 2µH, DCR: 2.6m
INFINEON FETs: BSC042N03MS G (UPPER/LOWER)
TA = 25°C

LOAD CURRENT (mA)

IN

IN

VDD = 3.6V

13V

16.5V

= 5.5V, VIN = 5.5V

DD

= 1.8 V

VDD = 5.5V

IN

IN

= 7 V

OUT

13V

16.5V

100

VDD = 5.5V, = VIN = 5.5(PSM)

95

VDD = 5.5V, VIN = 5.5V

90

85

80

75

70

VDD = 5.5V, VIN = 16.5V

V

= 5.5V, VIN = 16.5V (PSM)

DD

65

60

55

EFFICIENCY (%)

50

45

V

DD

40

35

30

25

100 100k10k1k

08297-005

= 5.5V, VIN = 13V (PSM)

V

DD

V

= 3.6V, VIN = 5.5V

DD

= 5.5V, VIN = 13V

WURTH IND: 744325120, L = 1.2µH, DCR: 1.8m
INFINEON FETS: BSC042N03MS G ( UPPER/LOWER)
TA = 25°C

LOAD CURRENT (mA)

Figure 8. Efficiency—600 kHz, V

OUT

08297-008

= 1.8 V

100

95

VDD = 5.5V,
V

= 13V (PSM)

IN

VDD = 3.6V,VIN = 13V

90

85

80

75

70

65

60

55

IN

IN

EFFICIENCY (%)

50

V

VDD = 5.5V, VIN = 13V

VDD = 5.5V, VIN = 16.5V (PSM)

VDD = 3.6V, VIN = 16.5V

= 5.5V, VIN = 16.5V

DD

45

40

35

30

100 100k10k1k

08297-006

Figure 9. Efficiency—600 kHz, V

WURTH IND: 7443551200, L = 2µH, DCR: 2.6m
INFINEON FETs: BSC042N03MS G (UPPER/LOWER)
TA = 25°C

LOAD CURRENT (mA)

= 5 V

OUT

08297-009

Rev. A | Page 7 of 40

ADP1872/ADP1873

100

= 5.5V, VIN = 13V (PSM )

V

DD

95

90

85

80

75

= 5.5V,

V

70

DD

V

= 16.5V

IN

65

(PSM)

60

55

50

EFFICIENCY (%)

45

40

35

30

25

20

100 100k10k1k

Figure 10. Efficiency—1.0 MHz, V

V

DD

= 5.5V, VIN = 13V

V

DD

= 3.6V, VIN = 5.5V

V

DD

VDD = 5.5V, VIN = 5.5V

= 5.5V, VIN = 16.5V

V

= 5.5V,

DD

V

= 5.5V (PSM)

IN

V

= 3.6V, VIN = 3.6V

DD

WURTH IND: 744303012, L = 0.12µH, DCR: 0.33m
INFINEON FETs: BSC042N03MS G (UPPER/LOWER)
TA = 25°C

LOAD CURRENT (mA)

OUT

08297-010

= 0.8 V

0.8030

0.8025

0.8020

0.8015

0.8010

0.8005

0.8000

0.7995

0.7990

0.7985

OUTPUT VOLTAGE (V)

0.7980

0.7975

0.7970

0.7965

0.7960

VIN = 5.5V

+125°C
+25°C
–40°C

0 2000 4000 6000 8000 10,000 12,000 14, 000 16,000

VIN = 13V

+125°C
+25°C
–40°C

LOAD CURRENT (mA)

Figure 13. Output Voltage Accuracy—300 kHz, V

VIN = 16.5V

+125°C
+25°C
–40°C

= 0.8 V

OUT

08297-013

100

95

90

VDD = 5.5V,
V

= 16.5V (PSM)

IN

= 5.5V, VIN = 5V (PSM )

V

DD

85

80

= 5.5V,

V

DD

75

V

= 13V

IN

(PSM)

70

65

60

55

50

EFFICIENCY (%)

45

40

35

30

25

20

100 100k10k1k

WURTH IND: 744303022, L = 0.22µH, DCR: 0.33m
INFINEON FETs: BSC042N03MS G (UPPER/LOWER)
TA = 25°C

Figure 11. Efficiency—1.0 MHz, V

100

VDD = 5.5V, VIN = 5V (PSM)

95

90

85

80

75

70

= 5V,

V

DD

V

= 13V

IN

65

60

55

50

EFFICIENCY (%)

45

40

35

30

25

20

100 10k1k

WURTH IND: 744325072, L = 0.72µH, DCR: 1.65m
INFINEON FETs: BSC042N03MS G (UPPER/LOWER)
TA = 25°C

Figure 12. Efficiency—1.0 MHz, V

= 5.5V, VIN = 16.5V

V

DD

VDD = 3.6V, VIN = 13V

V

= 3.6V, VIN = 16.5V

DD

V

= 5.5V, VIN = 13V

DD

LOAD CURRENT (mA)

= 5.5V, VIN = 16.5V (PSM)

V

DD

V

= 5V, VIN = 16.5V

DD

LOAD CURRENT (mA)

OUT

OUT

V

DD

V

IN

= 1.8 V

= 4 V

= 5.5V,

= 5V

1.821

1.816

1.811

1.806

1.801

OUTPUT VOLTAGE (V)

1.796

1.791

1.786

08297-011

VIN = 5.5V

+125°C
+25°C
–40°C

0 1500 3000 4500 6000 7500 9000 10,500 12,000 13,500 15,000

Figure 14. Output Voltage Accuracy—300 kHz, V

7.000

6.995

VIN = 13V

+125°C
+25°C
–40°C

LOAD CURRENT (mA)

VDD = 3.6V, VIN = 13V
VDD = 3.6V, VIN = 16.5V

VIN = 16.5V

+125°C
+25°C
–40°C

OUT

08297-014

= 1.8 V

6.990

6.985

6.980

6.975

6.970

OUTPUT VOLTAGE (V)

6.965

6.960

6.955

08297-012

Figure 15. Output Voltage Accuracy—300 kHz, V

+125°C
+25°C
–40°C

VDD = 5.5V, VIN = 13V
VDD = 5.5V, VIN = 16.5V

0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000

LOAD CURRENT (mA)

= 7 V

OUT

08297-015

Rev. A | Page 8 of 40

ADP1872/ADP1873

1.801

1.800

1.799

1.798

1.797

1.796

1.795

1.794

1.793

OUTPUT VOLTAGE (V)

1.792

1.791

1.790

1.789

VIN = 5.5V

+125°C
+25°C
–40°C

0 1500 3000 4500 6000 7500 9000 10,500 12,000 13,500 15,000

VIN = 13V

+125°C
+25°C
–40°C

LOAD CURRENT (mA)

VIN = 16.5V

Figure 16. Output Voltage Accuracy—600 kHz, V

+125°C
+25°C
–40°C

OUT

08297-016

= 1.8 V

1.810

1.809

1.808

1.807

1.806

1.805

1.804

1.803

1.802

1.801

OUTPUT VOLTAGE (V)

1.800

1.799

1.798

1.797

VIN = 5.5V

+125°C
+25°C
–40°C

0 1500 3000 4500 6000 7500 9000 10,500 12,000 13,500 15,000

VIN = 13V

+125°C
+25°C
–40°C

LOAD CURRENT (mA)

VIN = 16.5V

Figure 19. Output Voltage Accuracy—1.0 MHz, V

+125°C
+25°C
–40°C

OUT

= 1.8 V

08297-019

5.044

5.042

5.040

5.038

5.036

5.034

5.032

5.030

5.028

OUTPUT VOLTAGE (V)

5.026

5.024

5.022

5.020

+125°C
+25°C
–40°C

0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000

VDD = 5.5V, VIN = 13V
VDD = 5.5V, VIN = 16.5V

LOAD CURRENT (mA)

Figure 17. Output Voltage Accuracy—600 kHz, V

0.807
VIN = 5.5V

0.806

0.805

0.804

0.803

0.802

0.801

OUTPUT VOLTAGE (V)

0.800

0.799

0.798

+125°C
+25°C
–40°C

VIN = 13V

0 2000 4000 6000 8000 10,000 12,000 14,000 16,000

LOAD CURRENT (mA)

+125°C
+25°C
–40°C

VIN = 16.5V

+125°C
+25°C
–40°C

Figure 18. Output Voltage Accuracy—1 MHz, V

OUT

OUT

= 5 V

= 0.8 V

4.050

4.045

4.040

4.035

4.030

4.025

4.020

4.015

4.010

4.005

4.000

3.995

OUTPUT VOLTAGE (V)

3.990

3.985

3.980

3.975

3.970
0 800 1600 2400 3200 4000 4800 5600 6400 7200 8000

08297-017

Figure 20. Output Voltage Accuracy—1.0 MHz, V

0.6030

0.6025

0.6020

0.6015

0.6010

0.6005

0.6000

0.5995

0.5990

FEEDBACK VOLT AGE (V)

0.5985

0.5980

0.5975
–40.0 –7. 5 122.590.057.525.0

08297-018

VIN = 13V

+125°C
+25°C
–40°C

LOAD CURRENT (mA)

VDD = 2.7V, VIN = 2.7V, 3.6V
VDD = 3.6V, VIN = 3.6V TO 16.5V
VDD = 5.5V, VIN = 5.5V, 13V, 16.5V

TEMPERATURE (° C)

VIN = 16.5V

+125°C
+25°C
–40°C

OUT

08297-020

= 4 V

08297-021

Figure 21. Feedback Voltage vs. Temperature

Rev. A | Page 9 of 40

ADP1872/ADP1873

335

325

315

305

295

285

275

265

FREQUENCY (kHz)

255

245

235

225

10.8 11. 0 11.2 11.4 11.6 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2

VDD = 3.6V

+125°C
+25°C
–40°C

VIN (V)

NO LOADVDD = 5.5V

Figure 22. Switching Frequency vs. High Input Voltage,

300 kHz, ±10% of 12 V

08297-022

340

325

310

295

280

265

250

FREQUENCY (kHz)

235

220

205

190

0 1 6,00014,00012,00010,0008000600040002000

VIN = 5.5V
VIN = 13V
VIN = 16.5V

+125°C
+25°C
–40°C

LOAD CURRENT (mA)

Figure 25. Frequency vs. Load Current, 300 kHz, V

OUT

08297-025

= 0.8 V

650

600

550

500

FREQUENCY (kHz)

450

400

10.8 11. 0 11.2 11.4 11.6 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2

VDD = 5.5V
VDD = 3.6V

+125°C
+25°C
–40°C

VIN (V)

NO LOAD

Figure 23. Switching Frequency vs. High Input Voltage,

600 kHz, V

1000

950

900

850

800

750

700

FREQUENCY (kHz)

650

600

550

10.8 11. 0 11.2 11.4 11.6 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2

VDD = 5.5V
VDD = 3.6V

= 1.8 V, ±10% of 12 V

OUT

+125°C
+25°C
–40°C

VIN (V)

NO LOAD

Figure 24. Switching Frequency vs. High Input Voltage,

1.0 MHz, ±10% of 12 V

360

350

340

330

320

310

300

FREQUENCY (kHz)

290

280

270

260

08297-023

Figure 26. Frequency vs. Load Current, 300 kHz, V

358
354
350
346
342
338
334
330
326
322
318
314

FREQUENCY (kHz)

310
306
302
298
294
290

08297-024

Figure 27. Frequency vs. Load Current, 300 kHz, V

0 20,00016,000 18,00014,00012,00010,0008000600040002000

0 96006400 7200 8000 8800560048004000320024001600800

VIN = 5.5V
VIN = 13V
VIN = 16.5V

VIN = 13V
VIN = 16.5V

+125°C
+25°C
–40°C

LOAD CURRENT (mA)

+125°C
+25°C
–40°C

LOAD CURRENT (mA)

OUT

OUT

= 1.8 V

= 7 V

08297-026

08297-027

Rev. A | Page 10 of 40

ADP1872/ADP1873

700
670
640
610
580
550
520
490
460
430
400
370

FREQUENCY (kHz)

340
310
280
250
220
190

0 16,00014,00012,00010,0008000600040002000

VIN = 5.5V
VIN = 13V
VIN = 16.5V

+125°C
+25°C
–40°C

LOAD CURRENT (mA)

Figure 28. Frequency vs. Load Current, 600 kHz, V

= 0.8 V

OUT

08297-028

FREQUENCY (kHz)

1300

1125

1150

1075

1000

925

850

775

700

625

550

475

400

0 16,00014,00012,00010,0008000600040002000

VIN = 5.5V
VIN = 13V
VIN = 16.5V

+125°C
+25°C
–40°C

LOAD CURRENT (mA)

Figure 31. Frequency vs. Load Current, V

= 1.0 MHz, 0.8 V

OUT

08297-031

815

795

775

755

735

715

695

675

655

635

615

FREQUENCY (kHz)

595

575

555

535

515

495

0 20,00016,000 18,00014,00012,00010,0008000600040002000

VIN = 5.5V
VIN = 13V
VIN = 16.5V

LOAD CURRENT (mA)

Figure 29. Frequency vs. Load Current, 600 kHz, V

0 96008800800072006400560048004000320024001600800

VIN = 13V
VIN = 16.5V

705

698

691

684

677

670

663

656

649

642

FREQUENCY (kHz)

635

628

621

614

607

600

+125°C
+25°C
–40°C

LOAD CURRENT (mA)

Figure 30. Frequency vs. Load Current, 600 kHz, V

+125°C
+25°C
–40°C

= 1.8 V

OUT

OUT

=5 V

1450

1375

1300

1225

1150

1075

1000

925

FREQUENCY (kHz)

850

775

700

625

550

08297-029

Figure 32. Frequency vs. Load Current, 1.0 MHz, V

1450

1400

1350

1300

1250

1200

1150

FREQUENCY (kHz)

1100

1050

1000

08297-030

Figure 33. Frequency vs. Load Current, 1.0 MHz, V

VIN = 5.5V
VIN = 13V
VIN = 16.5V

MIN-OFF TIME
ENCROACHMENT

+125°C
+25°C
–40°C

0 20,00016,000 18,00014,00012,00010,0008000600040002000

VIN = 13V +125°C
VIN = 16.5V

0 8000800 1600 2400 3200 4000 4800 5600 6400 7200

LOAD CURRENT (mA)

+25°C
–40°C

LOAD CURRENT (mA)

OUT

OUT

= 1.8 V

= 4 V

08297-032

08297-033

Rev. A | Page 11 of 40

ADP1872/ADP1873

UVLO (V)

2.658

2.657

2.656

2.655

2.654

2.653

2.652

2.651

2.650

2.649
–40 120100806040200–20

TEMPERATURE ( °C)

Figure 34. UVLO vs. Temperature

08297-034

680

630

580

530

480

430

380

330

MINIMUM OFF-TIME (ns)

280

230

180

–40 120100806040200–20

VDD = 2.7V
VDD = 3.6V
VDD = 5.5V

TEMPERATURE (° C)

Figure 37. Minimum Off-Time vs. Temperature

08297-037

100

95

90

85

80

75

70

65

60

55

MAXIMUM DUTY CYCLE (%)

50

45

40

300 400 500 600 700 800 900 1000

FREQUENCY (kHz)

VDD = 2.7V
VDD = 3.6V
VDD = 5.5V

Figure 35. Maximum Duty Cycle vs. Frequency

84
82
80
78
76
74
72
70
68
66
64
62
60
58
56
54
52

MAXIMUM DUTY CYCLE (%)

50
48
46
44
42
40

3.6 4. 8 6. 0 7.2 8.4 9.6 10.8 12.0 13.2 14.4 15. 6

VDD = 3.6V +125°C
VDD = 5.5V

+25°C
–40°C

VIN (V)

Figure 36. Maximum Duty Cycle vs. High Voltage Input (VIN)

+125°C
+25°C
–40°C

680

630

580

530

480

430

380

330

MINIMUM OFF-TIME (ns)

280

230

180

2.7 5.55.14.74.33.93.53.1

08297-035

VDD (V)

+125°C
+25°C
–40°C

08297-038

Figure 38. Minimum Off-Time vs. VDD (Low Input Voltage)

800

720

640

560

480

400

320

RECTIFIER DROP (mV)

240

160

80

08297-036

300 400 500 600 700 800 900 1000

VDD = 2.7V
VDD = 3.6V
VDD = 5.5V

+125°C
+25°C
–40°C

FREQUENCY (kHz)

08297-039

Figure 39. Internal Rectifier Drop vs. Frequency

Rev. A | Page 12 of 40

ADP1872/ADP1873

1280

1200

1120

1040

960

880

800

720

640

560

480

RECTIFIER DROP (mV)

400

320

240

160

80

2.73.13.53.94.34.75.15.5

Figure 40. Internal Boost Rectifier Drop vs. VDD (Low Input Voltage)

VIN = 5.5V
VIN = 13V
VIN = 16.5V

1MHz
300kHz

VDD (V)

over VIN Variation

TA = 25°C

OUTPUT VOLTAGE

1

2

3

4

CH1 50mV

08297-040

CH3 10V

B

CH2 5A 

W

B

CH4 5V

W

INDUCTOR CURRENT

SW NODE

LOW SIDE

M400ns A CH2 3.90A

T 35.8%

08297-043

Figure 43. Power Saving Mode (PSM) Operational Waveform, 100 mA

720

640

560

480

400

320

RECTIFIER DROP (mV)

240

160

80

2.73.13.53.94.34.75.15.5

300kHz +125°C
1MHz

+25°C
–40°C

VDD (V)

08297-041

Figure 41. Internal Boost Rectifier Drop vs. VDD

80

72

64

56

48

40

32

24

BODY DIODE CONDUCT ION TIM E (ns)

16

8

2.73.13.53.94.34.75.15.5

300kHz +125°C
1MHz

VDD (V)

+25°C
–40°C

08297-042

Figure 42. Lower Side MOSFET Body Conduction Time vs. VDD (Low Input Voltage)

OUTPUT VOLTAGE

1

INDUCTOR CURRENT

2

3

4

CH1 50mV
CH3 10V

B

CH2 5A 

W

B

CH4 5V

W

M4.0µs A CH2 3.90A

T 35.8%

Figure 44. PSM Waveform at Light Load, 500 mA

OUTPUT VOLTAGE

4

INDUCTOR CURRENT

1

SW NODE

3

CH1 5A 
CH3 10V CH4 100mV

M400ns A CH3 2.20V

B

T 30.6%

W

Figure 45. CCM Operation at Heavy Load, 18 A

(See Figure 91 for Application Circuit)

SW NODE

LOW SIDE

08297-044

08297-045

Rev. A | Page 13 of 40

ADP1872/ADP1873

OUTPUT VOLTAGE

2

4

OUTPUT VO LTAGE

20A STEP

1

SW NODE

3

4

CH1 10A  CH2 200mV
CH3 20V CH4 5V

B

M2ms A CH1 3.40A

W

T 75.6%

LOW SIDE

08297-046

Figure 46. Load Transient Step—PSM Enabled, 20 A

(See Figure 91 Application Circuit)

2

20A POSITIVE STEP

1

3

LOW SIDE

4

CH1 10A  CH2 200mV
CH3 20V CH4 5V

OUTPUT VOLTAGE

SW NODE

B

M20µs A CH1 3. 40A

W

T 30.6%

08297-047

Figure 47. Positiv e Step During Heavy Load Trans ient Behavior—PSM Enabled,

= 1.8 V (See Figure 91 Application Circuit)

20 A, V

OUT

20A STEP

1

2

3

CH1 10A  CH2 5V
CH3 20V CH4 200mV

LOW SIDE

SW NODE

M2ms A CH1 6.20A

B

T 15.6%

W

08297-049

Figure 49. Load Transient Step—Forced PWM at Light Load, 20 A

(See Figure 91 Application Circuit)

OUTPUT VOLTAGE

4

20A POSITIVE STEP

1

2

3

SW NODE

CH1 10A  CH2 5V
CH3 20V CH4 200mV

M20µs A CH1 6. 20A

B

T 43.8%

W

LOW SIDE

08297-050

Figure 50. Positive Step During Heavy Load Transient Behavior—Forced PWM

at Light Load, 20 A, V

= 1.8 V (See Figure 91 Application Circuit)

OUT

2

OUTPUT VOLTAGE

20A NEGATIVE STEP

1

3

SW NODE

LOW SIDE

4

CH1 10A  CH2 200mV
CH3 20V CH4 5V

B

M20µs A CH1 3. 40A

W

T 48.2%

08297-048

Figure 48. Negative Step During Heavy Load Transient Behavior—PSM Enabled,

20 A (See Figure 91 Application Circuit)

Rev. A | Page 14 of 40

2

OUTPUT VO LTAGE

20A NEGATIVE STEP

1

SW NODE

3

LOW

4

CH1 10A  CH2 200mV
CH3 20V CH4 5V

SIDE

B

M10µs A CH1 5. 60A

W

T 23.8%

08297-051

Figure 51. Negative Step During Heavy Load Transient Behavior—Forced PWM

at Light Load, 20 A (See Figure 91 Application Circuit)

ADP1872/ADP1873

1

OUTPUT VOLTAGE

INDUCTOR CURRENT

2

LOW SIDE

4

SW NODE

3

B

CH1 2V
CH3 10V CH4 5V

CH2 5A 

W

M4ms A CH1 920mV

T 49.4%

Figure 52. Output Short-Circuit Behavior Leading to Hiccup Mode

1

OUTPUT VO LTAGE

INDUCTOR CURRENT

2

1

2

OUTPUT VOLTAGE

INDUCTOR CURRENT

LOW SIDE

4

SW NODE

3

B

CH1 2V

08297-052

CH3 10V CH4 5V

CH2 5A 

W

M4ms A CH1 720mV

T 41.6%

08297-055

Figure 55. Power-Down Waveform During Heavy Load

OUTPUT VOLTAGE

1

INDUCTOR CURRENT

2

SW NODE

SW NODE

3

LOW SIDE

4

B

CH1 5V
CH3 10V CH4 5V

CH2 10A 

W

M10µs A CH2 8. 20A

T 36.2%

Figure 53. Magnified Waveform During Hiccup Mode

OUTPUT VO LTAGE

1

INDUCTOR CURRENT

2

LOW SIDE

4

SW NODE

3

B

CH1 2V
CH3 10V CH4 5V

CH2 5A 

W

M2ms A CH1 720mV

T 32.8%

Figure 54. Start-Up Behavior at Heavy Load, 18 A, 300 kHz

(See Figure 91 Application Circuit)

3

LOW SIDE

4

B

B

W

W

CH2 5A 
CH4 5V

M2µs A CH2 3.90A

T 35.8%

08297-056

CH1 50mV

08297-053

CH3 10V

Figure 56. Output Voltage Ripple Waveform During PSM Operation

at Light Load, 2 A

OUTPUT VO LTAGE

1

LOW SIDE

4

SW NODE

3

INDUCTOR CURRENT

2

B

CH1 1V

08297-054

CH3 10V

W
B

W

CH2 5A 
CH4 2V

M1ms A CH1 1.56V

T 63.2%

08297-057

Figure 57. Soft Start and RES Detect Waveform

Rev. A | Page 15 of 40

ADP1872/ADP1873

LOW SIDE

TA = 25°C

570

550

VDD = 5.5V
VDD = 3.6V
VDD = 2.7V

4

HIGH SIDE

SW NODE

3

2

M

HS MINUS
SW

CH3 5V
MATH 2V 40ns

CH2 5V
CH4 2V

M40ns A CH2 4.20V

T 29.0%

08297-058

Figure 58. Output Drivers and SW Node Waveforms

HIGH SI DE

t

r

, DRVH

TA = 25°C

)

08297-059

LOW SIDE

4

22ns (

SW NODE

3

2

HS MINUS

M

SW

CH3 5V
MATH 2V 40ns

t

pdh

, DRVH

CH2 5V
CH4 2V

16ns (

t

)

f

, DRVL

)

25ns (

M40ns A CH2 4.20V

T 29.0%

Figure 59. Upper Side Driver Rising and Lower Side Falling Edge Waveforms

= 4.3 nF (Upper/Lower Side MOSFET),

(C

GATE

= 27 nC (VGS = 4.4 V (Q1), VGS = 5 V (Q3))

Q

TOTAL

530

510

490

470

TRANSCONDUCTANCE (µS )

450

430

–40 –20 120100806040200

Figure 61. Transconductance (G

680

630

580

530

480

430

TRANSCONDUCTANCE (µS )

380

330

2.7 3.0 5.44.8 5. 14.54.23.93.63.3

Figure 62. Transconductance (GM) vs. VDD

TEMPERATURE ( °C)

) vs. Temperature

M

VDD (V)

+125°C
+25°C
–40°C

08297-061

08297-062

18ns (

t

4

HIGH SIDE

HS MINUS
SW

3

2

M

TA = 25°C

CH3 5V
MATH 2V 20ns

r

, DRVL

CH2 5V
CH4 2V

)

24ns (

t

pdh

11ns (

t

f

, DRVH

M20ns A CH2 4.20V

T 39.2%

, DRVL

)

LOW SIDE

)

SW NODE

08297-060

Figure 60. Upper Side Driver Falling and Lower Side Rising Edge Waveforms

= 4.3 nF (Upper/Lower Side MOSFET),

(C

GATE

= 27 nC (VGS = 4.4 V (Q1), VGS = 5 V (Q3))

Q

TOTAL

Rev. A | Page 16 of 40

1.30

1.25

1.20

1.15

1.10

1.05

1.00

0.95

0.90

0.85

QUIESCENT CURRENT (mA)

0.80

0.75

0.70

2.7 5.55.14.74.3

Figure 63. Quiescent Current vs. VDD (VIN = 13 V)

+125°C

3.93.53.1

VDD (V)

+25°C

–40°C

08297-163

ADP1872/ADP1873

ADP1872/ADP1873 BLOCK DIGRAM

V

DD

DRIVERS

ADP1872/

ADP1873

300k

8k

800k

VIN

BST

DRVH

SW

DRVL

PGND

08297-063

COMP/EN

VDD

FB

SS_REF

LOWER

COMP

CLAMP

REF_ZERO

0.6V

V

REG

SS
COMP

ERROR
AMP

I

SS

C

SS

REF_ZERO CS GAIN SET

PRECISION E NABLE

BLOCK

BIAS

BLOCK

PFM

PWM

CS

AMP

I

REV

COMP

GND

t

ON

MACHINE

ADC

V

DD

STATE

TO ENABLE
ALL BLOCKS

FILTER

CS GAIN

PROGRAMMING

Figure 64. ADP1872/ADP1873 Block Diagram

Rev. A | Page 17 of 40

ADP1872/ADP1873

A

THEORY OF OPERATION

The ADP1872/ADP1873 are versatile current-mode, synchronous
step-down controllers that provide superior transient response,
optimal stability, and current limit protection by using a constant
on-time, pseudo-fixed frequency with a programmable current­sense gain, current-control scheme. In addition, these devices offer
optimum performance at low duty cycles by using valley current­mode control architecture. This allows the ADP1872/
ADP1873 to drive all N-channel power stages to regulate output
voltages as low as 0.6 V.

STARTUP

The ADP1872/ADP1873 have an input low voltage pin (VDD) for
biasing and supplying power for the integrated MOSFET drivers. A
bypass capacitor should be located directly across the VDD (Pin 5)
and PGND (Pin 7) pins. Included in the power-up sequence is
the biasing of the current-sense amplifier, the current-sense gain
circuit (see the Programming Resistor (RES) Detect Circuit
section), the soft start circuit, and the error amplifier.

The current-sense blocks provide valley current information
(see the Programming Resistor (RES) Detect Circuit section)
and are a variable of the compensation equation for loop stability
(see the Compensation Network section). The valley current
information is extracted by forcing 0.4 V across the DRVL output
and the PGND pin, which generates a current depending on the
resistor across DRVL and PGND in a process performed by the
RES detect circuit. The current through the resistor is used to set
the current-sense amplifier gain. This process takes approximately
800 µs, after which the drive signal pulses appear at the DRVL
and DRVH pins synchronously and the output voltage begins to
rise in a controlled manner through the soft start sequence.

The rise time of the output voltage is determined by the soft start
and error amplifier blocks (see the Soft Start section). At the
beginning of a soft start, the error amplifier charges the external
compensation capacitor, causing the COMP/EN pin to rise above the
enable threshold of 285 mV, thus enabling the ADP1872/ADP1873.

SOFT START

The ADP1872/ADP1873 have digital soft start circuitry, which
involves a counter that initiates an incremental increase in current,
by 1 µA, via a current source on every cycle through a fixed internal
capacitor. The output tracks the ramping voltage by producing
PWM output pulses to the upper side MOSFET. The purpose is to
limit the in-rush current from the high voltage input supply (VIN)
to the output (V

OUT

).

PRECISION ENABLE CIRCUITRY

The ADP1872/ADP1873 employ precision enable circuitry. The
enable threshold is 285 mV typical with 35 mV of hysteresis.
The devices are enabled when the COMP/EN pin is released,
allowing the error amplifier output to rise above the enable
threshold (see Figure 65). Grounding this pin disables the
ADP1872/ADP1873, reducing the supply current of the devices
to approximately 140 µA. For more information, see Figure 66.

Rev. A | Page 18 of 40

FB

COMP/EN

C

C

C

C2

R

C

Figure 65. Release COMP/EN Pin to Enable the ADP1872/ADP1873

COMP/EN

>2.4V

2.4V

1.0V

500mV

285mV

0V

Figure 66. COMP/EN Voltage Range

UNDERVOLTAGE LOCKOUT

The undervoltage lockout (UVLO) feature prevents the part
from operating both the upper side and lower side MOSFETs
at extremely low or undefined input voltage (VDD) ranges.
Operation at an undefined bias voltage may result in the incorrect
propagation of signals to the high-side power switches. This, in
turn, results in invalid output behavior that can cause damage
to the output devices, ultimately destroying the device tied at
the output. The UVLO level has been set at 2.65 V (nominal).

THERMAL SHUTDOWN

The thermal shutdown is a self-protection feature to prevent the IC
from damage due to a very high operating junction temperature.
If the junction temperature of the device exceeds 155°C, the
part enters the thermal shutdown state. In this state, the device
shuts off both the upper side and lower side MOSFETs and
disables the entire controller immediately, thus reducing the
power consumption of the IC. The part resumes operation after
the junction temperature of the part cools to less than 140°C.

DP1872/ADP1873

V

DD

SS

ERROR
AMPLIFIER

PRECISION
ENABLE

285mV

HICCUP MODE INI TIALI ZED
MAXIMUM CURRENT ( UPPER CLAMP)

ZERO CURRENT

USABLE RANGE ONLY AFTER SOFT START
PERIOD I F CONTUNUO US CONDUCTION
MODE OF OPERATION IS SELECTED.

LOWER CLAMP

PRECISION E NABLE THRESHOL D

35mV HYSTERESIS

0.6V

TO ENABLE
ALL BLOCKS

08297-064

08297-065

ADP1872/ADP1873

PROGRAMMING RESISTOR (RES) DETECT CIRCUIT

Upon startup, one of the first blocks to become active is the RES
detect circuit. This block powers up before soft start begins. It
forces a 0.4 V reference value at the DRVL output (see Figure 67)
and is programmed to identify four possible resistor values: 47 kΩ,
22 kΩ, open, and 100 kΩ.

The RES detect circuit digitizes the value of the resistor at the
DRVL pin (Pin 6). An internal ADC outputs a 2-bit digital code
that is used to program four separate gain configurations in the
current-sense amplifier (see Figure 68). Each configuration
corresponds to a current-sense gain (A
24 V/V, respectively (see Ta bl e 5 and Ta bl e 6). This variable is used
for the valley current-limit setting, which sets up the appropriate
current-sense gain for a given application and sets the compensation
necessary to achieve loop stability (see the Valley Current-Limit
Setting and Compensation Network sections).

ADP1872

DRVH

SW

DRVL

CS GAIN

PROGRAMMING

Figure 67. Programming Resistor Location

) of 3 V/V, 6 V/V, 12 V/V,

CS

Q1

Q2

R

RES

08297-066

VALLEY CURRENT-LIMIT SETTING

The architecture of the ADP1872/ADP1873 is based on valley
current-mode control. The current limit is determined by three
components: the R
output voltage swing (COMP), and the current-sense gain. The
COMP range is internally fixed at 1.4 V. The current-sense gain
is programmable via an external resistor at the DRVL pin (see
the Programming Resistor (RES) Detect Circuit section). The R
of the lower side MOSFET can vary over temperature and usually
has a positive T
therefore, it is recommended to program the current-sense gain
resistor based on the rated R

Because the ADP1872/ADP1873 are based on valley current
control, the relationship between I

where:

I

is the desired valley current limit.

CLIM

I

is the current load.

LOAD

K

is the ratio between the inductor ripple current and the

I

desired average load current (see Figure 10). Establishing K
helps to determine the inductor value (see the Inductor
Selection section), but in most cases, K

of the lower side MOSFET, the error amplifier

ON

(meaning that it increases with temperature);

C

of the MOSFET at 125°C.

ON

K

⎛

II

LOADCLIM

I

−×=

1

⎜

2

⎝

and I

CLIM

⎞
⎟
⎠

= 0.33.

I

LOAD

is

ON

I

CS

AMP

RES

ADC

0.4V

CS GAIN SET

DRVL

Figure 68. RES Detect Circuit for Current-Sense Gain Programming

SW

PGND

08297-067

Table 5. Current-Sense Gain Programming

Resistor ACS (V/V)

47 kΩ 3
22 kΩ 6
Open 12
100 kΩ 24

When the desired valley current limit (I
the current-sense gain can be calculated by

where:

A

CS

R

ON

Although the ADP1872/ADP1873 have only four discrete current­sense gain settings for a given R
outline several available options for the valley current setpoint
based on various R

Rev. A | Page 19 of 40

I

RIPPLE CURRENT =

LOAD CURRENT

VALLEY CURRENT LIMIT

Figure 69. Valley Current Limit to Average Current Relation

CLIM

V4.1

CLIM

=

RAI×

ONCS

LOAD

3

8297-068

) has been determined,

is the current-sense gain multiplier (see Tab le 5 and Tab l e 6 ).

is the channel impedance of the lower side MOSFET.

variable, Tab le 6 and Figure 70

ON

values.

ON

ADP1872/ADP1873

A

O

Table 6. Valley Current Limit Program1

Valley Current Level

R
(mΩ)

47 kΩ 22 kΩ Open 100 kΩ

ON

ACS = 3 V/V ACS = 6 V/V ACS = 12 V/V ACS = 24 V/V

1.5 38.9
2 29.2

2.5 23.3
3 39.0 19.5

3.5 33.4 16.7

4.5 26.0 13
5 23.4 11.7

5.5 21.25 10.6
10 23.3 11.7 5.83
15 31.0 15.5 7.75 7.5
18 26.0 13.0 6.5 3.25

1

Refer to Figure 70 for more information and a graphical representation.

39
37
35
33
31
29
27
25
23
21
19
17
15
13

VALLEY CURRENT LIMIT (A)

11

RES = 100k

9

= 24V/V

A

7

CS

5
3

1234567891011121314151617181920

Figure 70. Valley Current-Limit Value vs. R

RES = NO RES

A

= 12V/V

CS

RON (m)

ON

for Each Programming Resistor (RES)

RES = 47k

A

= 3V/V

CS

RES = 22k

A

= 6V/V

CS

of the Lower Side MOSFET

08297-069

The valley current limit is programmed as outlined in Table 6
and Figure 70. The inductor chosen must be rated to handle the
peak current, which is equal to the valley current from Tab l e 6
plus the peak-to-peak inductor ripple current (see the Inductor
Selection section). In addition, the peak current value must be
used to compute the worst-case power dissipation in the MOSFETs
(see Figure 71).

49

MAXIMUM DC LOAD

CURRENT

INDUCTOR

CURRENT

I = 33%

OF 30A

39.5A

35A

I = 45%

OF 32.25A

30A

VALLEY CURRENT LIMIT
THRESHOLD (SET FOR 25A)

32.25A

I = 65%

OF 37A

37A

OUTPUT

SWING

COMP

COMP

OUTPUT

2.4V

1V0A

Figu re 71. Valley Current-Limit Threshold in Relation to Inductor Ripple Current

HICCUP MODE DURING SHORT CIRCUIT

A current-limit violation occurs when the current across the
source and drain of the lower side MOSFET exceeds the current­limit setpoint. When 32 current-limit violations are detected,
the controller enters idle mode and turns off the MOSFETs for
6 ms, allowing the converter to cool down. Then, the controller
re-establishes soft start and begins to cause the output to ramp
up again (see Figure 72). While the output ramps up, COMP is
monitored to determine if the violation is still present. If it is still
present, the idle event occurs again, followed by the full-chip
power-down sequence. This cycle continues until the violation
no longer exists. If the violation disappears, the converter is
allowed to switch normally, maintaining regulation.

08297-070

REPEATED CURRENT L IMIT

VIOLATION DETECT ED

HS

CLIM

ZERO

CURRENT

A PREDETERMINED NUM BER
OF PULSES IS COUNTED TO
ALLOW THE CONVERTER

TO COOL DOWN

SOFT START IS

REINITIALIZED T

MONITOR IF THE

VIOLATION

STILL EXISTS

08297-071

Figure 72. Idle Mode Entry Sequence Due to Current-Limit Violations

Rev. A | Page 20 of 40

ADP1872/ADP1873

N

SYNCHRONOUS RECTIFIER

The ADP1872/ADP1873 employ an internal lower side MOSFET
driver to drive the external upper side and lower side MOSFETs.
The synchronous rectifier not only improves overall conduction
efficiency but also ensures proper charging to the bootstrap
capacitor located at the upper side driver input. This is beneficial
during startup to provide sufficient drive signal to the external
upper side MOSFET and attain fast turn-on response, which is
essential for minimizing switching losses. The integrated upper
and lower side MOSFET drivers operate in complementary
fashion with built-in anticross conduction circuitry to prevent
unwanted shoot-through current that may potentially damage the
MOSFETs or reduce efficiency as a result of excessive power loss.

POWER SAVING MODE (PSM) VERSION (ADP1873)

The power saving mode version of the ADP1872 is the ADP1873.
The ADP1873 operates in the discontinuous conduction mode
(DCM) and pulse skips at light load to midload currents. It
outputs pulses as necessary to maintain output regulation. Unlike
the continuous conduction mode (CCM), DCM operation
prevents negative current, thus allowing improved system
efficiency at light loads. Current in the reverse direction through
this pathway, however, results in power dissipation and therefore
a decrease in efficiency.

HS

t

ON

HS AND LS ARE OFF

OR IN IDLE MODE

AS THE INDUCTOR
CURRENT APPROACHES
ZERO CURRENT, THE STATE
MACHINE TURNS OF F THE
LOWER SIDE MOSFET.

SW

10mV

I

Q2

I

LOAD

LS

0A

t

OFF

Figure 73. Discontinuous Mode of Operation (DCM)

To minimize the chance of negative inductor current buildup,
an on-board, zero-cross comparator turns off all upper side
and lower side switching activities when the inductor current
approaches the zero current line, causing the system to enter
idle mode, where the upper side and lower side MOSFETs are
turned off. To ensure idle mode entry, a 10 mV offset, connected
in series at the SW node, is implemented (see Figure 74).

ZERO-CROSS

COMPARATOR

08297-072

As soon as the forward current through the lower side MOSFET
decreases to a level where

10 mV = I

the zero-cross comparator (or I

Q2

× R

ON(Q2)

comparator) emits a signal to

REV

turn off the lower side MOSFET. From this point, the slope of the
inductor current ramping down becomes steeper (see Figure 75)
as the body diode of the lower side MOSFET begins to conduct
current and continues conducting current until the remaining
energy stored in the inductor has been depleted.

ANOTHER
TRIGGERE D WHEN V
FALLS BELOW REGULATION

SW

LS

I

LOAD

0A

Figure 75. 10 mV Offset to Ensure Prevention of Negative Inductor Current

t

EDGE IS

ON

OUT

HS AND LS

IN IDLE MODE

ZERO-CROSS COMPARATOR
DETECTS 10mV O FFSET AND
TURNS OFF LS

10mV = R

× I

ON

LOAD

t

ON

08297-074

The system remains in idle mode until the output voltage drops
below regulation. A PWM pulse is then produced, turning on the
upper side MOSFET to maintain system regulation. The ADP1873
does not have an internal clock; therefore, it switches purely as a
hysteretic controller, as described in this section.

TIMER OPERATION

The ADP1872/ADP1873 employ a constant on-time architecture,
which provides a variety of benefits, including improved load
and line transient response when compared with a constant
(fixed) frequency current-mode control loop of comparable
loop design. The constant on-time timer, or t
the high input voltage (VIN) and the output voltage (V
SW waveform information to produce an adjustable one-shot
PWM pulse that varies the on-time of the upper side MOSFET in
response to dynamic changes in input voltage, output voltage, and
load current conditions to maintain regulation. It then generates
an on-time (t

ON

K is a constant that is trimmed using an RC timer product

where

) pulse that is inversely proportional to VIN.

ON

V

OUT

Kt

×=

VI

for the 300 kHz, 600 kHz, and 1.0 MHz frequency options.

timer, senses

ON

OUT

) using

LS

Q2

08297-073

Figure 74. Zero-Cross Comparator with 10 mV of Offset

Rev. A | Page 21 of 40

ADP1872/ADP1873

t

ON

INFORMATION

Figure 76. Constant On-Time Timer

VDD

C

I

SW

R (TRIMMED)

The constant on-time (tON) is not strictly constant because it varies
with VIN and V

. However, this variation occurs in such a

OUT

way as to keep the switching frequency virtually independent
of VIN and V

The t

timer uses a feedforward technique, applied to the constant

ON

OUT

.

on-time control loop, making it pseudo-fixed frequency to a first
order. Second-order effects, such as dc losses in the external power
MOSFETs (see the Efficiency Consideration section), cause some
variation in frequency vs. load current and line voltage. These
effects are shown in Figure 22 to Figure 33. The variations in
frequency are much reduced compared with the variations
generated when the feedforward technique is not used.

The feedforward technique establishes the following relationship:

f

= 1/K

SW

where f

is the controller switching frequency (300 kHz,

SW

600 kHz, and 1.0 MHz).

The t

timer senses VIN and V

ON

with VIN and V

as previously explained. This provides a

OUT

to minimize frequency variation

OUT

pseudo-fixed frequency, see the Pseudo-Fixed Frequency section
for additional information. To allow headroom for VIN/V
sensing, the following two equations must be adhered to. For
typical applications where V
relevant; however, for lower V

V

≥ VIN/8 + 1.5

DD

≥ V

V

DD

OUT

/4

is 5 V, these equations are not

DD

, care may be required.

DD

PSEUDO-FIXED FREQUENCY

The ADP1872/ADP1873 employ a constant on-time control
scheme. During steady state operation, the switching frequency
stays relatively constant, or pseudo-fixed. This is due to the one-

timer that produces a high-side PWM pulse with a fixed

shot t

ON

duration, given that external conditions such as input voltage,
output voltage, and load current are also at steady state. During
load transients, the frequency momentarily changes for the
duration of the transient event so that the output comes back
within regulation quicker than if the frequency were fixed or if
it were to remain unchanged. After the transient event is complete,
the frequency returns to a pseudo-fixed value to a first-order.

VIN

08297-075

OUT

To illustrate this feature more clearly, this section describes
one such load transient event—a positive load step—in detail.
During load transient events, the high-side driver output pulse
width stays relatively consistent from cycle to cycle; however,
the off-time (DRVL on-time) dynamically adjusts according to
the instantaneous changes in the external conditions mentioned.

When a positive load step occurs, the error amplifier (out of
phase of the output, V

) produces new voltage information

OUT

at its output (COMP). In addition, the current-sense amplifier
senses new inductor current information during this positive
load transient event. The error amplifier’s output voltage
reaction is compared to the new inductor current information
that sets the start of the next switching cycle. Because current
information is produced from valley current sensing, it is sensed
at the down ramp of the inductor current, whereas the voltage
loop information is sensed through the counter action upswing
of the error amplifier’s output (COMP).

The result is a convergence of these two signals (see Figure 77),
which allows an instantaneous increase in switching frequency
during the positive load transient event. In summary, a positive
load step causes V

to transient down, which causes COMP to

OUT

transient up and therefore shortens the off time. This resulting
increase in frequency during a positive load transient helps to
quickly bring V

back up in value and within the regulation

OUT

window.

Similarly, a negative load step causes the off time to lengthen in
response to V
demagnetizing phase, helping to bring V

rising. This effectively increases the inductor

OUT

to within regulation.

OUT

In this case, the switching frequency decreases, or experiences a
foldback, to help facilitate output voltage recovery.

Because the ADP1872/ADP1873 has the ability to respond
rapidly to sudden changes in load demand, the recovery period
in which the output voltage settles back to its original steady
state operating point is much quicker than it would be for a
fixed-frequency equivalent

. Therefore, using a pseudo-fixed

frequency, results in significantly better load transient
performance than using a fixed frequency.

LOAD CURRENT

DEMAND

CS AMP
OUTPUT

ERROR AMP

OUTPUT

PWM OUTPUT

f

SW

VALLEY
TRIP POINTS

>

f

SW

08297-076

Figure 77. Load Transient Response Operation

Rev. A | Page 22 of 40

ADP1872/ADP1873

I

I

APPLICATIONS INFORMATION

FEEDBACK RESISTOR DIVIDER

The required resistor divider network can be determine for a
given V
is fixed at 0.6 V. Selecting values for R

value because the internal band gap reference (V

OUT

and RB determines the

T

REF

minimum output load current of the converter. Therefore, for a
given value of R

T

, the RT value can be determined by

B

−

V

OUT

×=

RR

B

V)6.0(

V6.0

INDUCTOR SELECTION

The inductor value is inversely proportional to the inductor
ripple current. The peak-to-peak ripple current is given by

LOAD

V

VIN

3

OUT

I = 50%

I = 40%

I = 33%

08297-077

IKI ≈×=Δ

IL

LOAD

where K

is typically 0.33.

I

The equation for the inductor value is given by

−

)(

VVIN

OUT

=

L

×Δ

L

×

fI

SW

where:

VIN is the high voltage input.
V

is the desired output voltage.

OUT

f

is the controller switching frequency (300 kHz, 600 kHz,

SW

and 1.0 MHz).

When selecting the inductor, choose an inductor saturation rating
that is above the peak current level and then calculate the
inductor current ripple (see the Val le y Cu r re n t -L imi t Se tt i ng
section and Figure 78).

52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18

PEAK INDUCTOR CURRENT (A)

16
14
12
10

8

6 8 10 12 14 16 18 20 22 24 26 28 30

Figure 78. Peak Current vs. Valley Current Threshold for

33%, 40%, and 50% of Inductor Ripple Current

VALLEY CURRENT LIMIT (A)

)

Table 7. Recommended Inductors

L

DCR

I

Dimensions

(μH)

(mΩ)

0.12 0.33 55 10.2 × 7 Würth Elektronic 744303012

0.22 0.33 30 10.2 × 7 Würth Elektronic 744303022

0.47 0.8 50 14.2 × 12.8 Würth Elektronic 744355147

0.72 1.65 35 10.5 × 10.2 Würth Elektronic 744325072

0.9 1.6 28 13 × 12.8 Würth Elektronic 744355090

1.2 1.8 25 10.5 × 10.2 Würth Elektronic 744325120

1.0 3.3 20 10.5 × 10.2 Würth Elektronic 7443552100

1.4 3.2 24 14 × 12.8 Würth Elektronic 744318180

2.0 2.6 22 13.2 × 12.8 Würth Elektronic 7443551200

0.8 27.5 Sumida CEP125U-0R8

SAT

(A)

(mm) Manufacturer Model No.

OUTPUT RIPPLE VOLTAGE (ΔVRR)

The output ripple voltage is the ac component of the dc output
voltage during steady state. For a ripple error of 1.0%, the output
capacitor value needed to achieve this tolerance can be determined
using the following equation. (Note that an accuracy of 1.0% is
only possible during steady state conditions, not during load
transients.)

= (0.01) × V

V

RR

OUT

OUTPUT CAPACITOR SELECTION

The primary objective of the output capacitor is to facilitate
the reduction of the output voltage ripple; however, the output
capacitor also assists in the output voltage recovery during load
transient events. For a given load current step, the output voltage
ripple generated during this step event is inversely proportional
to the value chosen for the output capacitor. The speed at which
the output voltage settles during this recovery period depends
on where the crossover frequency (loop bandwidth) is set. This
crossover frequency is determined by the output capacitor, the
equivalent series resistance (ESR) of the capacitor, and the
compensation network.

To calculate the small signal voltage ripple (output ripple
voltage) at the steady state operating point, use the following
equation:

OUT

⎛
⎜

IC

×Δ=

L

⎜

SW

⎝

1

[]

LRIPPLE

where ESR is the equivalent series resistance of the output
capacitors.

To calculate the output load step, use the following equation:

Δ

C

2

×=

OUT

where V

is the amount that V

DROOP

a given positive load current step (I

LOAD

ESRIVf

×Δ−Δ×

LOADDROOPSW

is allowed to deviate for

OUT

).

LOAD

⎞
⎟
⎟

)(8

ESRIVf

×Δ−Δ××

⎠

))((

Rev. A | Page 23 of 40

ADP1872/ADP1873

+

Ceramic capacitors are known to have low ESR. However, the
trade-off of using X5R technology is that up to 80% of its capaci­tance may be lost due to derating because the voltage applied
across the capacitor is increased (see Figure 79). Although X7R
series capacitors can also be used, the available selection is
limited to only up to 22 µF.

20

10

0

–10

–20

–30

–40

–50

–60

–70

CAPACITANCE CHARGE (%)

–80

10µF TDK 25V, X7R, 1210 C3225X7R1E106M
22µF MURATA 25V, X7R, 1210 G RM32ER71E226KE15L

–90

47µF MURATA 16V , X5R, 1210 G RM32ER61C476KE15L

–100

0 5 10 15 20 25 30

Figure 79. Capacitance vs. DC Voltage Characteristics for Ceramic Capacitors

X5R (16V)

X7R (50V)

X5R (25V)

DC VOLTAGE (VDC)

08297-078

Electrolytic capacitors satisfy the bulk capacitance requirements
for most high current applications. Because the ESR of electrolytic
capacitors is much higher than that of ceramic capacitors, when
using electrolytic capacitors, several MLCCs should be mounted
in parallel to reduce the overall series resistance.

COMPENSATION NETWORK

Due to its current-mode architecture, the ADP1872/ADP1873
require Type II compensation. To determine the component
values needed for compensation (resistance and capacitance
values), it is necessary to examine the converter’s overall loop
gain (H) at the unity gain frequency (f

V

OUT

GGH ××××== V/V1

M

CS

V

REF

Examining each variable at high frequency enables the unity
gain transfer function to be simplified to provide expressions
for the R

Output Filter Impedance (Z

COMP

and C

component values.

COMP

FILT

Examining the filter’s transfer function at high frequencies
simplifies to

Z

FILTER

1

=

sC

OUT

at the crossover frequency (s = 2πf

/10) when H = 1 V/V.

SW

ZZ

COMP

)

).

CROSS

FILT

Rev. A | Page 24 of 40

Error Amplifier Output Impedance (Z

Assuming CC2 is significantly smaller than C

COMP

COMP

)

, CC2 can be
omitted from the output impedance equation of the error amplifier.
The transfer function simplifies to

ffR

Z

COMP

=

CROSSCOMP

f

CROSS

ZERO

)(

and

1

ff ×=

SWCROSS

12

where f

, the zero frequency, is set to be 1/4th of the crossover

ZERO

frequency for the ADP1872.

Error Amplifier Gain (GM)

The error amplifier gain (transconductance) is

G

= 500 µA/V

M

Current-Sense Loop Gain (GCS)

The current-sense loop gain is

1

=

CS

(A/V)

RAG×

ONCS

where:

(V/V) is programmable for 3 V/V, 6 V/V, 12 V/V, and 24 V/V

A

CS

(see the Programming Resistor (RES) Detect Circuit and Val l e y
Current-Limit Setting sections).

is the channel impedance of the lower side MOSFET.

R

ON

Crossover Frequency

The crossover frequency is the frequency at which the overall
loop (system) gain is 0 dB (H = 1 V/V). It is recommended for
current-mode converters, such as the ADP1872, that the user

th

set the crossover frequency between 1/10

and 1/15th of the

switching frequency.

1

ff

=

SWCROSS

12

The relationship between C

COMP

1

ZERO

CRf××=π2

COMPCOMP

The zero frequency is set to 1/4

and f

th

of the crossover frequency.

(zero frequency) is

ZERO

Combining all of the above parameters results in

V

Cf

fRC×××=π2

ZERO

π2

CROSS

M

OUT

OUT

GG

CS

V

REF

f

R ××

COMP

CROSS

=

CROSS

ff

+

ZERO

1

COMP

COMP

ADP1872/ADP1873

(

)

[

]

EFFICIENCY CONSIDERATION

One of the important criteria to consider in constructing a dc-to-dc
converter is efficiency. By definition, efficiency is the ratio of the
output power to the input power. For high power applications at
load currents up to 20 A, the following are important MOSFET
parameters that aid in the selection process:

• V

• R

• Q

• C

• C

The following are the losses experienced through the external
component during normal switching operation:

• Channel conduction loss (both the MOSFETs)

• MOSFET driver loss

• MOSFET switching loss

• Body diode conduction loss (lower side MOSFET)

• Inductor loss (copper and core loss)

Channel Conduction Loss

During normal operation, the bulk of the loss in efficiency is due
to the power dissipated through MOSFET channel conduction.
Power loss through the upper side MOSFET is directly proportional
to the duty cycle (D) for each switching period, and the power
loss through the lower side MOSFET is directly proportional to
1 − D for each switching period. The selection of MOSFETs is
governed by the amount of maximum dc load current that the
converter is expected to deliver. In particular, the selection of
the lower side MOSFET is dictated by the maximum load
current because a typical high current application employs duty
cycles of less than 50%. Therefore, the lower side MOSFET is in
the on state for most of the switching period.

MOSFET Driver Loss

Other dissipative elements are the MOSFET drivers. The
contributing factors are the dc current flowing through the
driver during operation and the Q
MOSFETs.

: the MOSFET support voltage applied between the

GS (TH)

gate and the source.

: the MOSFET on resistance during channel

DS (ON)

conduction.

: the total gate charge

G

: the input capacitance of the upper side switch

N1

: the input capacitance of the lower side switch

N2

2

P

[]

= [D × R

N1, N2 (CL)

DR

)(

LOSSDR

()

DD

SW

lowerFET

+ (1 − D) × R

N1 (ON)

SW

upperFET

+×

DD

N2 (ON)

parameter of the external

GATE

IVCfVP

DR

BIAS

IVCfV

BIAS

I

] ×

LOAD

++×=

800

720

640

560

480

400

320

RECTIFIER DROP (mV)

240

160

80

300 1000900800700600500400

Figure 80. Internal Rectifier Voltage Drop vs. Switching Frequency

MOSFET Switching Loss

The SW node transitions due to the switching activities of the
upper side and lower side MOSFETs. This causes removal and
replenishing of charge to and from the gate oxide layer of the
MOSFET, as well as to and from the parasitic capacitance
associated with the gate oxide edge overlap and the drain and
source terminals. The current that enters and exits these charge
paths presents additional loss during these transition times.
This can be approximately quantified by using the following
equation, which represents the time in which charge enters and
exits these capacitive regions.

t

SW-TRANS

where:

is the gate input resistance of the MOSFET.

R

GATE

C

is the CGD + CGS of the external MOSFET used.

TOTAL

The ratio of this time constant to the period of one switching cycle
is the multiplying factor to be used in the following expression:

P

LOSSSW

or

P

SW (LOSS)

where:

is the input gate capacitance of the upper-side MOSFET.

C

upperFET

is the input gate capacitance of the lower-side MOSFET.

C

lowerFET

V

is the driver bias voltage (that is, the low input voltage (VDD)

DR

minus the rectifier drop (see Figure 80)).

is the dc current flowing into the upper- and lower-side drivers.

I

BIAS

V

is the bias voltage.

DD

VDD = 2.7V
VDD = 3.6V
VDD = 5.5V

= R

× C

GATE

t

)(

t

= fSW × R

FREQUENCY (kHz)

TOTAL

-

TRANSSW

SW

× C

GATE

LOAD

TOTAL

× I

2

×××= VINI

× VIN × 2

LOAD

+125°C
+25°C
–40°C

08297-079

Rev. A | Page 25 of 40

ADP1872/ADP1873

Body Diode Conduction Loss

The ADP1872/ADP1873 employ anticross conduction circuitry
that prevents the upper side and lower side MOSFETs from
conducting current simultaneously. This overlap control is
beneficial, avoiding large current flow that may lead to
irreparable damage to the external components of the power
stage. However, this blanking period comes with the trade-off of
a diode conduction loss occurring immediately after the
MOSFETs change states and continuing well into idle mode.
The amount of loss through the body diode of the lower side
MOSFET during the antioverlap state is given by

t

LOSSBODY

P

LOSSBODY

)(

)(

t

SW

LOAD

2

×××=

VI

F

where:

t

BODY (LOSS)

is the body conduction time (refer to Figure 81 for

dead time periods).

t

is the period per switching cycle.

SW

is the forward drop of the body diode during conduction.

V

F

(Refer to the selected external MOSFET data sheet for more
information about the V

80

72

64

56

48

40

32

24

BODY DIODE CO NDUCTION TI ME (ns)

16

8

2.7 5.54.84.13.4

Figure 81. Body Diode Conduction Time vs. Low Voltage Input (V

parameter.)

F

1MHz
300kHz

VDD (V)

+125°C
+25°C
–40°C

08297-080

)

DD

Inductor Loss

During normal conduction mode, further power loss is caused
by the conduction of current through the inductor windings,
which have dc resistance (DCR). Typically, larger sized inductors
have smaller DCR values.

The inductor core loss is a result of the eddy currents generated
within the core material. These eddy currents are induced by the
changing flux, which is produced by the current flowing through
the windings. The amount of inductor core loss depends on the
core material, the flux swing, the frequency, and the core volume.
Ferrite inductors have the lowest core losses, whereas powdered iron
inductors have higher core losses. It is recommended to use shielded
ferrite core material type inductors with the ADP1872/ADP1873
for a high current, dc-to-dc switching application to achieve
minimal loss and negligible electromagnetic interference (EMI).

P

DCR (LOSS)

= DCR × + Core Loss

I

2

LOAD

Rev. A | Page 26 of 40

INPUT CAPACITOR SELECTION

The goal in selecting an input capacitor is to reduce or to minimize
input voltage ripple and to reduce the high frequency source
impedance, which is essential for achieving predictable loop
stability and transient performance.

The problem with using bulk capacitors, other than their physical
geometries, is their large equivalent series resistance (ESR) and
large equivalent series inductance (ESL). Aluminum electrolytic
capacitors have such high ESR that they cause undesired input
voltage ripple magnitudes and are generally not effective at high
switching frequencies.

If bulk capacitors are to be used, it is recommended to use multi­layered ceramic capacitors (MLCC) in parallel due to their low
ESR values. This dramatically reduces the input voltage ripple
amplitude as long as the MLCCs are mounted directly across
the drain of the upper side MOSFET and the source terminal of
the lower side MOSFET (see the Layout Considerations section).
Improper placement and mounting of these MLCCs may cancel
their effectiveness due to stray inductance and an increase in
trace impedance.

()

VVINV

−×

OUTOUT

II

×=

MAXLOADRMSCIN

,,

V

OUT

The maximum input voltage ripple and maximum input capacitor
rms current occur at the end of the duration of 1 − D while the
upper side MOSFET is in the off state. The input capacitor rms
current reaches its maximum at time D. When calculating the
maximum input voltage ripple, account for the ESR of the input
capacitor as follows:

V

MAX, RIPPLE

RIPP

+ (I

LOAD, MAX

× ESR)

= V

where:

is usually 1% of the minimum voltage input.

V

RIPP

I

is the maximum load current.

LOAD, MAX

ESR is the equivalent series resistance rating of the input

capacitor used.

Inserting V

MAX, RIPPLE

into the charge balance equation to calculate

the minimum input capacitor requirement gives

I

MAXLOAD

C

minIN,

,

V

,

−

DD

×=

)1(

f

SWRIPPLEMAX

or

I

MAXLOAD

=

C

minIN,

4

,

Vf

RIPPLEMAXSW

,

where D = 50%.

ADP1872/ADP1873

I

−

THERMAL CONSIDERATIONS

The ADP1872/ADP1873 are used for dc-to-dc, step down, high
current applications that have an on-board controller and on-board
MOSFET drivers. Because applications may require up to 20 A of
load current delivery and be subjected to high ambient temperature
surroundings, the selection of external upper side and lower side
MOSFETs must be associated with careful thermal consideration
to not exceed the maximum allowable junction temperature
of 125°C. To avoid permanent or irreparable damage if the
junction temperature reaches or exceeds 155°C, the part enters
thermal shutdown, turning off both external MOSFETs, and
does not re-enable until the junction temperature cools to 140°C
(see the Thermal Shutdown section).

The maximum junction temperature allowed for the ADP1872/
ADP1873 ICs is 125°C. This means that the sum of the ambient
temperature (T
is caused by the thermal impedance of the package and the internal
power dissipation, should not exceed 125°C, as dictated by

= TR × TA

T

J

where:

is the maximum junction temperature.

T

J

is the rise in package temperature due to the power

T

R

dissipated from within.

T

is the ambient temperature.

A

The rise in package temperature is directly proportional to its
thermal impedance characteristics. The following equation
represents this proportionality relationship:

= θJA × P

T

R

where:

is the thermal resistance of the package from the junction to

θ

JA

the outside surface of the die, where it meets the surrounding air.

P

DR (LOSS)

The bulk of the power dissipated is due to the gate capacitance
of the external MOSFETs. The power loss equation of the
MOSFET drivers (see the MOSFET Driver Loss section in the
Efficiency Consideration section) is

P

DR (LOSS)

(f

SWClowerFETVDD

where:

is the input gate capacitance of the upper side MOSFET.

C

upperFET

is the input gate capacitance of the lower side MOSFET.

C

lowerFET

I

is the dc current (2 mA) flowing into the upper side and

BIAS

lower side drivers.

V

is the driver bias voltage (that is, the low input voltage (VDD)

DR

minus the rectifier drop (see Figure 80)).

is the bias voltage

V

DD

) and the rise in package temperature (TR), which

A

DR (LOSS)

is the overall power dissipated by the IC.

= [VDR × (fSWC

+ I

BIAS

upperFETVDR

)]

+ I

)] + [VDD ×

BIAS

For example, if the external MOSFET characteristics are θ
(10-lead MSOP) = 171.2°C/W, f
C

upperFET

= 3.3 nF, C

= 3.3 nF, VDR = 5.12 V, and VDD = 5.5 V,

lowerFET

= 300 kHz, I

SW

= 2 mA,

BIAS

then the power loss is

= [VDR × (fSWC

P

DR (LOSS)

(f

SWClowerFETVDD

+ I

= [5.12 × (300 × 10

3

[5.5 × (300 × 10

×3.3 × 10−9 × 5.5 + 0.002)]

upperFETVDR

)]

BIAS

3

× 3.3 × 10−9 × 5.12 + 0.002)] +

+ I

)] + [VDD ×

BIAS

= 77.13 mW

The rise in package temperature is

T

= θJA × P

R

DR (LOSS)

= 171.2°C × 77.13 mW
= 13.2°C

Assuming a maximum ambient temperature environment of 85°C,
the junction temperature is

= TR × TA = 13.2°C + 85°C = 98.2°C

T

J

which is below the maximum junction temperature of 125°C.

DESIGN EXAMPLE

The ADP1872/ADP1873 are easy to use, requiring only a few
design criteria. For example, the example outlined in this section
uses only four design criteria: V
VIN = 12 V (typical), and f

Input Capacitor

The maximum input voltage ripple is usually 1% of the
minimum input voltage (11.8 V × 0.01 = 120 mV).

= 120 mV

V

RIPP

= V

V

MAX, RIPPLE

RIPP

− (I

= 120 mV − (15 A × 0.001) = 45 mV

I

,

C

minIN,

4

MAXLOAD

Vf

,

RIPPLEMAXSW

= 120 µF

Choose five 22 µF ceramic capacitors. The overall ESR of five
22 µF ceramic capacitors is less than 1 m.

= I

I

P

RMS

CIN

/2 = 7.5 A

LOAD

= (I

)2 × ESR = (7.5A)2 × 1 m = 56.25 mW

RMS

Inductor

Determining inductor ripple current amplitude:

LOAD

I ≈Δ

L

= 5 A

3

so calculating for the inductor value

VV

,

MAXIN

=

L

=

OUT

×Δ

fI

L

SW

−

)V8.1V2.13(

×

3

××

10300V5

= 1.03 µH

= 1.8 V, I

OUT

= 300 kHz.

SW

× ESR)

LOAD, MAX

==

)(

V

OUT

×

V

V8.1

V2.13

= 15 A (pulsing),

LOAD

A15

3

mV105103004

×××

MAXIN,

JA

Rev. A | Page 27 of 40

ADP1872/ADP1873

I

−

−

The inductor peak current is approximately

15 A + (5 A × 0.5) = 17.5 A

Therefore, an appropriate inductor selection is 1.0 µH with
DCR = 3.3 m (7443552100) from Tabl e 7 with peak current
handling of 20 A.

2

IDCRP ×=

)(

LOSSDCR

= 0.003 × (15 A)

LOAD

2

= 675 mW

Current Limit Programming

The valley current is approximately

15 A − (5 A × 0.5) = 12.5 A

Assuming a lower side MOSFET R

of 4.5 m, choosing 13 A

ON

as the valley current limit from Tabl e 6 and Figure 70 indicates
that a programming resistor (RES) of 100 k corresponds to an

of 24 V/V.

A

CS

Choose a programmable resistor of R

= 100 kΩ for a current-

RES

sense gain of 24 V/V.

Output Capacitor

Assume a load step of 15 A occurs at the output and no more
than 5% is allowed for the output to deviate from the steady
state operating point. The ADP1872’s advantage is, because the
frequency is pseudo-fixed, the converter is able to respond
quickly because of the immediate, though temporary, increase
in switching frequency.

V

= 0.05 × 1.8 V = 90 mV

DROOP

Assuming the overall ESR of the output capacitor ranges from
5 m to 10 m,

Δ

15

LOAD

Vf

Δ×

A

3

××

)(

DROOPSW

)mV90(10300

OUT

2

×=

2

×=

C

= 1.11 mF

Therefore, an appropriate inductor selection is five 270 µF
polymer capacitors with a combined ESR of 3.5 m.

Assuming an overshoot of 45 mV, determine if the output
capacitor that was calculated previously is adequate:

2

IL

)(

×

C

=

OUT

()

−

=

××

LOAD

2

)(

26

)A15(101

22

)8.1()mV458.1(

−−

2

()

VVV

−Δ−

OUTOVSHTOUT

= 1.4 mF

Choose five 270 µF polymer capacitors.

The rms current through the output capacitor is

)(

I

RMS

×=

2

3

1

1

×=

2

3

1

1

VV

MAXIN

,

×

fL

SW

)V8.1V2.13(

−

3

10300F1

××

OUT

V

OUT

×

V

MAXIN

,

V8.1

=×

V2.13

A49.1

The power loss dissipated through the ESR of the output
capacitor is

= (I

P

COUT

)2 × ESR = (1.5 A)2 × 1.4 m = 3.15 mW

RMS

Feedback Resistor Network Setup

It is recommended to use RB = 15 k. Calculate RT as

k15 =

×=TR

V)6.0V8.1(

V6.0

k30

Compensation Network

To calculate R

COMP

, C

COMP

, and C

, the transconductance

PAR

parameter and the current-sense gain variable are required. The
transconductance parameter (G

) is 500 µA/V, and the current-

M

sense loop gain is

G

where A

11

CS

and RON are taken from setting up the current limit

CS

==

RA

ONCS

×

=

005.024

A/V33.8

(see the Programming Resistor (RES) Detect Circuit and Va l le y
Current-Limit Setting sections).

The crossover frequency is 1/12

th

of the switching frequency:

300 kHz/12 = 25 kHz

The zero frequency is 1/4

th

of the crossover frequency:

25 kHz/4 = 6.25 kHz

R

=

COMP

2

f

CROSS

=

CROSS

×

1025

ff

+

ZERO

3

×+×

1025.61025

π

CROSS

×

×

33

GG

M

V

Cf

CS

OUT

OUT

×

V

REF

6

−

××

33

−

×××××

1011.11025141.32

3.810500

×

= 100 k

=

COMP

1

COMP

1

fRCπ=2

ZERO

33

1025.61010014.32

×××××

= 250 pF

8.1

6.0

Rev. A | Page 28 of 40

ADP1872/ADP1873

(

)

[

]

++×

=

[

]

P

Loss Calculations

Duty cycle = 1.8/12 V = 0.15

= 5.4 m

R

ON (N2)

t

BODY(LOSS)

V

C

Q

R

= 20 ns (body conduction time)

= 0.84 V (MOSFET forward voltage)

F

= 3.3 nF (MOSFET gate input capacitance)

IN

= 17 nC (total MOSFET gate charge)

N1, N2

= 1.5  (MOSFET gate input resistance)

GATE

()

1

= (0.15 × 0.0054 + 0.85 × 0.0054) × (15 A)
= 1.215 W

P

LOSSBODY

)(

= 20 ns × 300 × 10

)(

t

SW

3

× 15 A × 0.84 × 2

LOAD

VI

t

LOSSBODY

= 151.2 mW

= fSW × R

SW (LOSS)

= 300 × 10

3

× 1.5 Ω × 3.3 × 10−9 × 15 A × 12 × 2

= 534.6 mW

)(

LOSSDR

()

[]

DD

SW

lowerFET

= (5.12 × (300 × 10
(5.5 × (300 × 10
= 77.13 mW

P

= (I

COUT

2

IRDRDP ××−+×=

N2(ON)N1(ON)N2(CL)N1,

×××=

F

LOAD

2

2

P

= (I

CIN

P

LOSS

= 1.215 W + 151.2 mW + 534.6 mW + 77.13 mW +

3.15 mW + 675 mW + 56.25 mW

)2 × ESR = (1.5 A)2 × 1.4 m = 3.15 mW

RMS

)(

LOSSDCR

)2 × ESR = (7.5 A)2 × 1 m = 56.25 mW

RMS

= P

N1, N2

+ P

= 2.62 W

× C

GATE

DR

SW

DD

3

× 3.3 × 10−9 × 5.12 + 0.002)) +

3

×3.3 ×10−9 ×5.5 + 0.002))

2

IDCRP ×=

LOAD

BODY (LOSS)

× I

TOTAL

upperFET

+×

IVCfV

LOAD

DR

BIAS

= 0.003 × (15 A)2 = 675 mW

+ PSW + P

DCR

× VIN × 2

IVCfVP

BIAS

+ PDR + P

COUT

+ P

CIN

Rev. A | Page 29 of 40

ADP1872/ADP1873

EXTERNAL COMPONENT RECOMMENDATIONS

The configurations listed in Tabl e 8 are with f
V

= 5 V, and a maximum load current of 14 A.

DD

The ADP1873 models listed in Tabl e 8 are the PSM versions of the device.

Table 8. External Component Values

Marking Code

SAP Model ADP1872 ADP1873

ADP1872ARMZ-0.3-R7/

ADP1873ARMZ-0.3-R7

LDT LDF 0.8 13 5 × 22

LDT LDF 1.2 13 5 × 222 4 × 5603 1.0 47 740 74 15.0
LDT LDF 1.8 13 4 × 222 4 × 2704 1.0 47 571 57 30.0
LDT LDF 2.5 13 4 × 222 3 × 2704 1.53 47 571 57 47.5
LDT LDF 3.3 13 5 × 222 2 × 3305 2.0 47 571 57 67.5
LDT LDF 5 13 4 × 222 3305 3.27 34 800 80 110.0
LDT LDF 7 13 4 × 222 222 + (4 × 476) 3.44 34 800 80 160.0
LDT LDF 1.2 16.5 4 × 222 4 × 5603 1.0 47 740 74 15.0
LDT LDF 1.8 16.5 3 × 222 4 × 2704 1.0 47 592 59 30.0
LDT LDF 2.5 16.5 3 × 222 4 × 2704 1.67 47 592 59 47.5
LDT LDF 3.3 16.5 3 × 222 2 × 3305 2.00 47 592 59 67.5
LDT LDF 5 16.5 3 × 222 2 × 1507 3.84 34 829 83 110.0
LDT LDF 7 16.5 3 × 222 222 + 4 × 476 4.44 34 829 83 160.0
ADP1872ARMZ-0.6-R7/

ADP1873ARMZ-0.6-R7

LDU LDK

LDU LDK 1.2 5.5 5 × 222 4 × 2704 0.47 47 326 33 15.0
LDU LDK 1.8 5.5 5 × 222 3 × 2704 0.47 47 271 27 30.0
LDU LDK 2.5 5.5 5 × 222 3 × 1808 0.47 47 271 27 47.5
LDU LDK 1.2 13 3 × 222 5 × 2704 0.47 47 407 41 15.0
LDU LDK 1.8 13 5 × 109 3 × 3305 0.47 47 307 31 30.0
LDU LDK 2.5 13 5 × 109 3 × 2704 0.90 47 307 31 47.5
LDU LDK 3.3 13 5 × 109 2 × 2704 1.00 47 307 31 67.5
LDU LDK 5 13 5 × 109 1507 1.76 34 430 43 110.0
LDU LDK 1.2 16.5 3 × 109 4 × 2704 0.47 47 362 36 15.0
LDU LDK 1.8 16.5 4 × 109 2 × 3305 0.72 47 326 33 30.0
LDU LDK 2.5 16.5 4 × 109 3 × 2704 0.90 47 326 33 47.5
LDU LDK 3.3 16.5 4 × 109 3305 1.0 47 296 30 67.5
LDU LDK 5 16.5 4 × 109 4 × 476 2.0 34 415 41 110.0
LDU LDK 7 16.5 4 × 109 3 × 476 2.0 34 380 38 160.0
ADP1872ARMZ-1.0-R7/

ADP1873ARMZ-1.0-R7

LDV LDL

LDV LDL 1.2 5.5 5 × 222 2 × 3305 0.22 47 223 22 15.0
LDV LDL 1.8 5.5 3 × 222 3 × 1808 0.22 47 163 16 30.0
LDV LDL 2.5 5.5 3 × 222 2704 0.22 47 163 16 47.5
LDV LDL 1.2 13 3 × 109 3 × 3305 0.22 47 233 23 15.0
LDV LDL 1.8 13 4 × 109 3 × 2704 0.47 47 210 21 30.0
LDV LDL 2.5 13 4 × 109 2704 0.47 47 210 21 47.5
LDV LDL 3.3 13 5 × 109 2704 0.72 47 210 21 67.5
LDV LDL 5 13 4 × 109 3 × 476 1.0 34 268 27 110.0
LDV LDL 1.2 16.5 3 × 109 4 × 2704 0.47 47 326 33 15.0
LDV LDL 1.8 16.5 3 × 109 3 × 2704 0.47 47 261 26 30.0
LDV LDL 2.5 16.5 4 × 109 3 × 1808 0.72 47 233 23 47.5
LDV LDL 3.3 16.5 4 × 109 2704 0.72 47 217 22 67.5

= 1/12 × fSW, f

CROSS

V
(V)

0.8 5.5 5 × 22

0.8 5.5 5 × 22

OUT

ZERO

VIN
(V) C

= ¼ × f

, R

CROSS

IN

= 100 k, R

RES

(μF) C

2

5 × 5603 0.72 47 740 74 5.0

2

4 × 5603 0.22 47 339 34 5.0

2

4 × 2704 0.22 47 223 22 5.0

OUT

(μF)

= 15 k, RON = 5.4 mΩ (BSC042N03MS G),

BOT

1

L
(μH)

RC
(kΩ)

C

COMP

(pF)

C

PAR

(pF)

R

TOP

(kΩ)

Rev. A | Page 30 of 40

ADP1872/ADP1873

Marking Code

V

VIN

SAP Model ADP1872 ADP1873

OUT

(V)

(V) C

(μF) C

IN

OUT

(μF)

LDV LDL 5 16.5 3 × 109 3 × 476 1.0 34 268 27 110.0
LDV LDL 7 16.5 3 × 109 222 + 476 1.0 34 228 23 160.0

1

See the section (See Ta ). Inductor Selection ble 9

2

22 μF Murata 25 V, X7R, 1210 GRM32ER71E226KE15L (3.2 mm × 2.5 mm × 2.5 mm).

3

560 μF Panasonic (SP-series) 2 V, 7 mΩ, 3.7 A EEFUE0D561LR (4.3 mm × 7.3 mm × 4.2 mm).

4

270 μF Panasonic (SP-series) 4 V, 7 mΩ, 3.7 A EEFUE0G271LR (4.3 mm × 7.3 mm × 4.2 mm).

5

330 μF Panasonic (SP-series) 4 V, 12 mΩ, 3.3 A EEFUE0G331R (4.3 mm × 7.3 mm × 4.2 mm).

6

47 μF Murata 16 V, X5R, 1210 GRM32ER61C476KE15L (3.2 mm × 2.5 mm × 2.5 mm).

7

150 μF Panasonic (SP-series) 6.3 V, 10 mΩ, 3.5 A EEFUE0J151XR (4.3 mm × 7.3 mm × 4.2 mm).

8

180 μF Panasonic (SP-series) 4 V, 10 mΩ, 3.5 A EEFUE0G181XR (4.3 mm × 7.3 mm × 4.2 mm).

9

10 μF TDK 25 V, X7R, 1210 C3225X7R1E106M.

Table 9. Recommended Inductors

L (μH) DCR (mΩ) I

(A) Dimension (mm) Manufacturer Model Number

SAT

0.12 0.33 55 10.2 × 7 Würth Elektronik 744303012

0.22 0.33 30 10.2 × 7 Würth Elektronik 744303022

0.47 0.8 50 14.2 × 12.8 Würth Elektronik 744355147

0.72 1.65 35 10.5 × 10.2 Würth Elektronik 744325072

0.9 1.6 28 13 × 12.8 Würth Elektronic 744355090

1.2 1.8 25 10.5 × 10.2 Würth Elektronic 744325120

1.0 3.3 20 10.5 × 10.2 Würth Elektronic 7443552100

1.4 3.2 24 14 × 12.8 Würth Elektronic 744318180

2.0 2.6 22 13.2 × 12.8 Würth Elektronic 7443551200

0.8 27.5 Sumida CEP125U-0R8

1

L
(μH)

RC
(kΩ)

C

COMP

(pF)

C

R

TOP

(kΩ)

PAR

(pF)

Table 10. Recommended MOSFETs

R

ID

VDS

VGS = 4.5 V

Upper-Side MOSFET

ON

(mΩ)

(A)

(V)

CIN
(nF)

5.4 47 30 3.2 20 PG-TDSON8 Infineon BSC042N03MS G

Q

TOTAL

(nC) Package Manufacturer Model Number

(Q1/Q2)

10.2 53 30 1.6 10 PG-TDSON8 Infineon BSC080N03MS G

6.0 19 30 35 SO-8 Vishay Si4842DY
9 14 30 2.4 25 SO-8 International Rectifier IRF7811
Lower-Side MOSFET

5.4 47 30 3.2 20 PG-TDSON8 Infineon BSC042N03MS G

(Q3/Q4)

10.2 82 30 1.6 10 PG-TDSON8 Infineon BSC080N03MS G

6.0 19 30 35 SO-8 Vishay Si4842DY

Rev. A | Page 31 of 40

ADP1872/ADP1873

LAYOUT CONSIDERATIONS

The performance of a dc-to-dc converter depends highly on
how the voltage and current paths are configured on the printed
circuit board (PCB). Optimizing the placement of sensitive
analog and power components are essential to minimize output
ripple, maintain tight regulation specifications, and reduce
PWM jitter and electromagnetic interference.

LOW VOLTAGE INPUT

V

= 5.0V

DD

JP1

57pF

V

OUT

C

F

0.1µF

R1 30k

15k

C2

C

C

571pF
R

C

47k

R2

C1

1µF

ADP1872/

ADP1873

1

VIN

2

COMP/EN9SW

3

FB

4

GND

5

VDD

BST

DRVH

PGND

DRVL

10

8

7

6

100k

C12
100nF

Figure 82. ADP1872/ADP1873 High Current Evaluation Board Schematic (Blue Traces Indicate High Current Paths)

HIGH VOLT AGE INPUT

R5

Figure 82 shows the schematic of a typical ADP1872/ADP1873
used for a high power application. Blue traces denote high current
pathways. VIN, PGND, and V

traces should be wide and

OUT

possibly replicated, descending down into the multiple layers.
Vias should populate, mainly around the positive and negative
terminals of the input and output capacitors, alongside the source
of Q1/Q2, the drain of Q3/Q4, and the inductor.

VIN = 12V

C3

22µFC422µFC522µFC622µFC722µF

Q1 Q2

Q3 Q4

1.0µH

C20

R6

270µF

2

C13

1.5nF

MURATA: (HIGH VOLTAGE INPUT CAPACITORS)

22µF, 25V, X7R, 1210 GRM32ER71E226KE15 L

PANASONIC: (OUTPUT CAPACITORS)

270µF (SP- SERIES) 4 V, 7m EEFUE0G271LR

INFINEON MOSFETs:

BSC042N03MS G (L OWER-SIDE)
BSC080N03MS G (UPPER-SIDE)

WURTH INDUCTORS:

1µH, 3.3m, 20A 7 443552100

+

C21

270µF

V

OUT

+

270µF

= 1.8V, 15A

+

C22

270µF

C23

+

08297-081

Rev. A | Page 32 of 40

ADP1872/ADP1873

SENSITIV E ANALOG
COMPO NENTS
LOCATED FAR
FROM THE NOISY
POWER SECTION.

SW

SEPARATE ANALOG GROUND
PLANE FOR THE ANALOG
COMPONENTS (THAT IS,
COMPENSATION AND
FEEDBACK RESIST ORS).

OUTPUT CAPACI TORS
ARE MOUNTED ON T HE

BYPASS POWER CAPACITOR (C1)
FOR VREG BI AS DECOUPLING
AND HIGH FREQUENCY
CAPACITOR (C2) AS CLOSE AS
POSSIBLE TO THE IC.

INPUT CAPACITO RS
ARE MOUNTED CLO SE
TO DRAIN OF Q1/Q2
AND SOURCE OF Q 3/Q4.

RIGHTMOST AREA OF
THE EVB, WRAP PING
BACK AROUND TO THE
MAIN POWER GROUND
PLANE, WHERE IT MEETS
WITH THE NEGATIVE
TERMINALS O F THE
INPUT CAPACIT ORS

Figure 83. Overall Layout of the ADP1872 High Current Evaluation Board

08297-082

Rev. A | Page 33 of 40

ADP1872/ADP1873

Figure 84. Layer 2 of Evaluation Board

08297-083

Rev. A | Page 34 of 40

ADP1872/ADP1873

TOP RESISTO R
FEEDBACK TAP

VOUT SENSE TAP LINE EXTENDING BACK
TO THE T OP RESIST OR IN THE F EEDBACK
DIVIDER NETW ORK (SEE F IGURE 82). THIS
OVERLAPS WITH PGND SENSE TAP LINE
EXTENDING BACK TO THE ANALO G
PLANE (SEE F IGURE 86, L AYER 4 FOR
PGND TAP).

08297-084

Figure 85. Layer 3 of Evaluation Board

Rev. A | Page 35 of 40

ADP1872/ADP1873

BOTTOM RESISTOR
TAP TO T HE ANALOG
GROUND PLANE

PGND SENSE TAP FROM
NEGATIVE TERMINALS OF
OUTPUT BULK CAPACITORS.
THIS TRACK PLACEMENT
SHOULD BE DIRECTL Y
BELOW THE VOUT SENSE
LINE FROM FIGURE 84.

08297-085

Figure 86. Layer 4 (Bottom Layer) of Evaluation Board

Rev. A | Page 36 of 40

ADP1872/ADP1873

IC SECTION (LEFT SIDE OF EVALUATION BOARD)

A dedicated plane for the analog ground plane (GND) should
be separate from the main power ground plane (PGND). With
the shortest path possible, connect the analog ground plane to
the GND pin (Pin 4). This plane should only be on the top layer
of the evaluation board. To avoid crosstalk interference, there
should not be any other voltage or current pathway directly
below this plane on Layer 2, Layer 3, or Layer 4. Connect the
negative terminals of all sensitive analog components to the
analog ground plane. Examples of such sensitive analog com­ponents include the resistor divider’s bottom resistor, the high
frequency bypass capacitor for biasing (0.1 µF), and the
compensation network.

Mount a 1 µF bypass capacitor directly across the VDD pin
(Pin 5) and the PGND pin (Pin 7). In addition, a 0.1 µF should
be tied across the VDD pin (Pin 5) and the GND pin (Pin 4).

POWER SECTION

As shown in Figure 83, an appropriate configuration to localize
large current transfer from the high voltage input (VIN) to the
output (VOUT) and then back to the power ground is to put the
VIN plane on the left, the output plane on the right, and the main
power ground plane in between the two. Current transfers from
the input capacitors to the output capacitors, through Q1/Q2,
during the on state (see Figure 87). The direction of this current
(yellow arrow) is maintained as Q1/Q2 turns off and Q3/Q4
turns on. When Q3/Q4 turns on, the current direction continues to
be maintained (red arrow) as it circles from the bulk capacitor’s
power ground terminal to the output capacitors, through the
Q3/Q4. Arranging the power planes in this manner minimizes
the area in which changes in flux occur if the current through
Q1/Q2 stops abruptly. Sudden changes in flux, usually at source
terminals of Q1/Q2 and drain terminals of Q3/Q4, cause large
dV/dts at the SW node.

The SW node is near the top of the evaluation board. The SW
node should use the least amount of area possible and be away
from any sensitive analog circuitry and components because
this is where most sudden changes in flux density occur. When
possible, replicate this pad onto Layer 2 and Layer 3 for thermal
relief and eliminate any other voltage and current pathways directly
beneath the SW node plane. Populate the SW node plane with
vias, mainly around the exposed pad of the inductor terminal
and around the perimeter of the source of Q1/Q2 and the drain
of Q3/Q4. The output voltage power plane (VOUT) is at the right­most end of the evaluation board. This plane should be replicated,
descending down to multiple layers with vias surrounding the
inductor terminal and the positive terminals of the output bulk
capacitors. Ensure that the negative terminals of the output
capacitors are placed close to the main power ground (PGND),
as previously mentioned. All of these points form a tight circle
(component geometry permitting) that minimizes the area of
flux change as the event switches between D and 1 − D.

VIN PGND

Figure 87. Primary Current Pathways During the On State of the Upper-Side

MOSFET (Left Arrow) and the On State of the Lower-Side MOSFET (Right Arrow)

DIFFERENTIAL SENSING

Because the ADP1872/ADP1873 operate in valley current­mode control, a differential voltage reading is taken across the
drain and source of the lower-side MOSFET. The drain of the
lower-side MOSFET should be connected as close as possible to
the SW pin (Pin 9) of the IC. Likewise, the source should be
connected as close as possible to the PGND pin (Pin 7) of the
IC. When possible, both of these track lines should be narrow
and away from any other active device or voltage/current paths.

SW

LAYER 1: SENSE L INE FOR SW
(DRAIN OF LOWER MOSFET)

Figure 88. Drain/Source Tracking Tapping of the Lower-Side MOSFET for CS

Differential sensing should also be applied between the
outermost output capacitor to the feedback resistor divider (see
Figure 85 and Figure 86). Connect the positive terminal of the
output capacitor to the top resistor (R
terminal of the output capacitor to the negative terminal of the
bottom resistor, which connects to the analog ground plane as
well. Both of these track lines, as previously mentioned, should
be narrow and away from any other active device or voltage/
current paths.

Amp Differential Sensing (Yellow Sense Line on Layer 2)

SW

VOUT

PGND

LAYER 1: SENSE LINE FOR PGND
(SOURCE OF L OWER MO SFET)

). Connect the negative

T

08297-086

08297-087

Rev. A | Page 37 of 40

ADP1872/ADP1873

TYPICAL APPLICATION CIRCUITS

DUAL-INPUT, 300 kHz HIGH CURRENT APPLICATION CIRCUIT

LOW VOLTAGE INPUT

V

= 5.0V

DD

JP1

C

57pF

V

OUT

C

F

0.1µF

R1 30k

15k

C2

C

571pF
R

C

47k

R2

C1

1µF

ADP1872/

ADP1873

1

VIN

2

COMP/EN9SW

3

FB

4

GND

5

VDD

BST

DRVH

PGND

DRVL

Figure 89. Application Circuit for 12 V Input, 1.8 V Output, 15 A, 300 kHz (Q2/Q4 No Connect).

HIGH VOLT AGE INPUT

C12
100nF

10

8

7

6

R5

100k

VIN = 12V

Q1 Q2

Q3 Q4

C3

22µFC422µFC522µFC622µFC722µF

1.0µH

C20

R6

270µF

2

C13

1.5nF

MURATA: (HIGH VOLTAGE INPUT CAPACITORS)

22µF, 25V, X7R, 1210 GRM32ER71E226KE15 L

PANASONIC: (OUTPUT CAPACITORS)

270µF (SP- SERIES) 4 V, 7m EEFUE0G271LR

INFINEON MOSFETs:

BSC042N03MS G (L OWER-SIDE)
BSC080N03MS G (UPPER-SIDE)

WURTH INDUCTORS:

1µH, 3.3m, 20A 7 443552100

+

C21

270µF

V

OUT

+

270µF

= 1.8V, 15A

+

C22

270µF

C23

+

08297-088

SINGLE-INPUT, 600 kHz APPLICATION CIRCUIT

JP1

C

C

271pF

C

R

F

R1 47.5k

15k

C2

0.1µF

C

47k

R2

1µF

C1

27pF

V

OUT

Figure 90. Application Circuit for 5.5 V Input, 2.5 V Output, 15 A, 600 kHz (Q2/Q4 No Connect)

ADP1872/

ADP1873

1

VIN

2

COMP/EN9SW

3

FB

4

GND

5

VDD

BST

DRVH

PGND

DRVL

10

HIGH VOL TAGE INPUT

VIN = 5.5V

C12
100nF

8

7

6

100k

Q1 Q2

Q3 Q4

R5

C3

22µFC422µFC522µFC622µFC722µF

0.47µH

R6
2

C13

1.5nF

MURATA: (HIGH VOLTAGE INPUT CAPACITORS)

22µF, 25V, X7R, 1210 GRM32ER71E226KE15 L

PANASONIC: (OUTPUT CAPACITORS)

180µF (SP- SERIES) 4 V, 10m EEFUE0G181XR

INFINEON MOSFET s:

BSC042N03MS G (L OWER-SIDE)
BSC080N03MS G (UPP ER-SIDE)

WURTH INDUCTO RS:

0.47µH, 0. 8m, 50A 744355147

C20

180µF

V

OUT

+

180µF

= 2.5V, 15A

+

C21

180µF

C22

+

08297-089

Rev. A | Page 38 of 40

ADP1872/ADP1873

DUAL-INPUT, 300 kHz HIGH CURRENT APPLICATION CIRCUIT

LOW VOLTAGE INPUT

V

= 5V

DD

JP1

C

V

C

80pF

OUT

F

R1 30k

C2

0.1µF

800pF
R

33.5k

15k

C

C

R2

C1

1µF

ADP1872/

ADP1873

1

VIN

2

COMP/ EN9SW

3

FB

4

GND

5

VDD

BST

DRVH

PGND

DRVL

Figure 91. Application Circuit for 13 V Input, 1.8 V Output, 20 A, 300 kHz (Q2/Q4 No Connect)

HIGH VOLTAGE INPUT

C12
100nF

10

8

7

6

VIN = 13V

Q1 Q2

Q3 Q4

C3

22µFC422µFC522µFC622µFC722µF

0.8µH

C20

R6

270µF

2

C13

1.5nF

MURATA: (HIGH VOLTAGE INPUT CAPACITORS)

22µF, 25V, X7R, 1210 GRM32ER71E226KE15 L

PANASONIC: (OUTPUT CA PACITORS)

270µF (SP- SERIES) 4 V, 7m EEFUE0G271LR

INFINEON MOSFET s:

BSC042N03MS G (L OWER-SIDE)
BSC080N03MS G (UPPER-SIDE)

WURTH INDUCTO RS:

0.72µH, 1. 65m, 35A 744325072

+

270µF

C21

V

OUT

+

270µF

= 1.8V, 20A

+

C22

270µF

C23

+

08297-090

Rev. A | Page 39 of 40

ADP1872/ADP1873

OUTLINE DIMENSIONS

3.10

3.00

2.90

10

6

3.10

3.00

2.90

PIN 1

IDENTIFIER

0.95

0.85

0.75

0.15

0.05

COPLANARITY

1

0.50 BSC

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-BA

Figure 92. 10-Lead Mini Small Outline Package [MSOP]

5.15

4.90

4.65

5

15° MAX

6°
0°

0.23

0.13

0.30

0.15

1.10 MAX

(RM-10)

Dimensions shown in millimeters

0.70

0.55

0.40

091709-A

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option Branding

ADP1872ARMZ-0.3-R7 −40°C to +125°C 10-Lead Mini Small Outline Package [MSOP] RM-10 LDT
ADP1872ARMZ-0.6-R7 −40°C to +125°C 10-Lead Mini Small Outline Package [MSOP] RM-10 LDU
ADP1872ARMZ-1.0-R7 −40°C to +125°C 10-Lead Mini Small Outline Package [MSOP] RM-10 LDV
ADP1872ARMZ-0.3-EVALZ Forced PWM, 300 kHz Evaluation Board
ADP1872ARMZ-0.6-EVALZ Forced PWM, 600 kHz Evaluation Board
ADP1872ARMZ-1.0-EVALZ Forced PWM, 1 MHz Evaluation Board
ADP1873ARMZ-0.3-R7 −40°C to +125°C 10-Lead Mini Small Outline Package [MSOP] RM-10 LDF
ADP1873ARMZ-0.6-R7 −40°C to +125°C 10-Lead Mini Small Outline Package [MSOP] RM-10 LDK
ADP1873ARMZ-1.0-R7 −40°C to +125°C 10-Lead Mini Small Outline Package [MSOP] RM-10 LDL
ADP1873ARMZ-0.3-EVALZ Power Saving Mode, 300 kHz Evaluation Board
ADP1873ARMZ-0.6-EVALZ Power Saving Mode, 600 kHz Evaluation Board
ADP1873ARMZ-1.0-EVALZ Power Saving Mode, 1 MHz Evaluation Board

1

Z = RoHS Compliant Part.

©2009–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08297-0-3/10(A)

Rev. A | Page 40 of 40