Datasheet ADP1850 Datasheet (ANALOG DEVICES)

Wide Range Input, Dual/Two-Phase, DC-to-DC

V

Data Sheet

FEATURES

Wide range input: 2.75 V to 20 V
Power stage input voltage: 1 V to 20 V
Output voltage range: 0.6 V up to 90% V
Output current to more than 25 A per channel
Accurate current sharing between channels (interleaved)
Programmable frequency: 200 kHz to 1.5 MHz
180° phase shift between channels for reduced input

capacitance

±0.85% reference voltage accuracy from −40°C to +85°C
Integrated boost diodes
Power saving mode (PSM) at light loads
Accurate power good with internal pull-up resistor
Accurate voltage tracking capability
Independent channel precision enable
Overvoltage and overcurrent limit protection
Externally programmable soft start, slope compensation and

current sense gain
Synchronization input
Thermal overload protection
Input undervoltage lockout (UVLO)
Available in 32-lead 5 mm × 5 mm LFCSP

APPLICATIONS

High current single and dual output intermediate bus and

point of load converters requiring sequencing and

tracking capability, including converters for:

Point-of-load power supplies
Telecom base station and networking
Consumer
Industrial and instrumentation
Healthcare and medical

GENERAL DESCRIPTION

The ADP1850 is a configurable dual output or two-phase, single
output dc-to-dc synchronous buck controller capable of running
from commonly used 3.3 V to 12 V (up to 20 V) voltage inputs.
The device operates in current mode for improved transient
response and uses valley current sensing for enhanced noise
immunity.

The architecture enables accurate current sharing between
interleaved phases for high current outputs.

The ADP1850 is ideal in system applications requiring multiple
output voltages: the ADP1850 includes a synchronization fea­ture to eliminate beat frequencies between switching devices;
provides accurate tracking capability between supplies and
includes precision enable for simple, robust sequencing.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

IN

Synchronous Buck Controller

ADP1850

TYPICAL OPERATION CIRCUIT

R

RAMP2

R

R

CSG1

CSG2

IN

M1

L1

R11

M2

R12

V

IN

M3

L2

R21

M4

R22

R

RAMP1

RAMP1

VIN

ADP1850

EN1
EN2
VDL

VCCO
TRK1
TRK2

PGOOD1
PGOOD2

HI

LO

SYNC

FREQ

COMP1

COMP2

SS1
SS2

AGND

DH1

BST1

SW1

ILIM1

FB1

DL1

PGND1

RAMP2

DH2

BST2

SW2

ILIM2

FB2

DL2

PGND2

Figure 1. Single Phase Circuit

The ADP1850 provides high speed, high peak current drive
capability with dead-time optimization to enable energy
efficient power conversion. For low load operation, the device
can be configured to operate in power saving mode (PSM) by
skipping pulses and reducing switching losses to improve the
energy efficiency at light load and standby conditions.

The accurate current limit (±6%) allows the power architect to
design within a narrower range of tolerances and can reduce
overall converter size and cost.

The ADP1850 provides a configurable architecture capable
of wide range input operation to provide the designer with
maximum re-use opportunities and improved time to market.
Additional flexibility is provided by external programmability
of loop compensation, soft start, frequency setting, power
saving mode, current limit and current sense gain can all be
programmed using external components.

The ADP1850 includes a high level of integration in a small size
package. The start-up linear regulator and the boot-strap diode
for the high side drive are included. Protection features include:
undervoltage lock-out, overvoltage, overcurrent/short-circuit
and over temperature. The ADP1850 is available in a compact
32-lead LFCSP 5 mm × 5 mm thermally enhanced package.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2010-2012 Analog Devices, Inc. All rights reserved.

V

V

OUT1

OUT2

09440-001

ADP1850 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

General Description ......................................................................... 1

Typical Operation Circuit ................................................................ 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Absolute Maximum Ratings ............................................................ 5

ESD Caution .................................................................................. 5

Simplified Block Diagram ............................................................... 6

Pin Configuration and Function Descriptions ............................. 7

Typical Performance Characteristics ............................................. 9

Theory of Operation ...................................................................... 12

Control Architecture .................................................................. 12

Oscillator Fre quency .................................................................. 12

Modes of Operation ................................................................... 13

Synchronization .......................................................................... 13

Synchronous Rectifier and Dead Time ................................... 14

Input Undervoltage Lockout ..................................................... 14

Internal Linear Regulator .......................................................... 14

Overvoltage Protection .............................................................. 14

Power Good ................................................................................. 14

Short-Circuit and Current-Limit Protection .......................... 15

Shutdown Control ...................................................................... 15

Thermal Overload Protection ................................................... 15

Applications Information .............................................................. 16

Setting the Output Voltage ........................................................ 16

Soft Start ...................................................................................... 16

Setting the Current Limit .......................................................... 16

Accurate Current-Limit Sensing .............................................. 17

Setting the Slope Compensation .............................................. 17

Setting the Current Sense Gain ................................................ 17

Input Capacitor Selection .......................................................... 18

Input Filter ................................................................................... 18

Boost Capacitor Selection ......................................................... 18

Inductor Selection ...................................................................... 18

Output Capacitor Selection ....................................................... 19

MOSFET Selection ..................................................................... 19

Loop Compensation (Single Phase Operation) ..................... 21

Configuration and Loop Compensation (Dual-Phase

Operation) ................................................................................... 22

Switching Noise and Overshoot Reduction ............................ 22

Voltage Tracking ......................................................................... 23

Indepdendent Power Stage Input Voltage ............................... 24

PCB Layout Guidelines .................................................................. 25

MOSFETs, Input Bulk Capacitor, and Bypass Capacitor ...... 25

High Current and Current Sense Paths ................................... 25

Signal Paths ................................................................................. 25

PGND Plane ................................................................................ 25

Feedback and Current-Limit Sense Paths ............................... 25

Switch Node ................................................................................ 26

Gate Driver Paths ....................................................................... 26

Output Capacitors ...................................................................... 26

Typical Operating Circuits ............................................................ 27

Outline Dimensions ....................................................................... 31

Ordering Guide .......................................................................... 31



REVISION HISTORY

4/12—Rev. 0 to Rev. A

Changes to Setting the Current Sense Gain Section .................. 17

Updated Outline Dimensions ....................................................... 31

11/10—Revision 0: Initial Version

Rev. A | Page 2 of 32

Data Sheet ADP1850

SPECIFICATIONS

All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). VIN = 12 V. The
specifications are valid for T

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

POWER SUPPLY

Input Voltage VIN 2.75 20 V

Undervoltage Lockout Threshold IN

V

Undervoltage Lockout Hysteresis 0.1 V

Quiescent Current IIN

EN1 = EN2 = VIN = 12 V, VFB = V

Shutdown Current I

ERROR AMPLIFIER

FBx Input Bias Current IFB −100 +1 +100 nA

Transconductance Gm Sink or source 1 µA 385 550 715 µS

TRK1, TRK2 Input Bias Current I

CURRENT SENSE AMPLIFIER GAIN ACS

Default setting, R

OUTPUT CHARACTERICTISTICS

Feedback Accuracy Voltage VFB

Line Regulation of PWM ∆VFB/∆VIN ±0.015 %/V

Load Regulation of PWM ∆VFB/∆V

OSCILLATOR

Frequency fSW R

R

R

FREQ to AGND 235 300 345 kHz

FREQ to VCCO 475 600 690 kHz

SYNC Input Frequency Range f

SYNC Input Pulse Width t

SYNC Pin Capacitance to GND C

LINEAR REGULATOR

VCCO Output Voltage I

VCCO Load Regulation I

VCCO Line Regulation VIN = 5.5 V to 20 V, I

VCCO Current Limit1 VCCO drops to 4 V from 5 V 350 mA

VCCO Short-Circuit Current1 VCCO < 0.5 V 370 400 mA

VIN to VCCO Dropout Voltage2 V

LOGIC INPUTS

EN1, EN2 EN1/EN2 rising 0.57 0.63 0.68 V

EN1, EN2 Hysteresis 0.03 V

EN1, EN2 Input Leakage Current IEN V

SYNC Logic Input Low 1.3 V

SYNC Logic Input High 1.9 V

SYNC Input Pull-Down Resistance R

= −40°C to +125°C, unless otherwise specified. Typical values are at TA = 25°C.

J

V

UVLO

rising 2.45 2.6 2.75 V

IN

falling 2.4 2.5 2.6

IN

EN1 = EN2 = V

= 12 V, VFB = V

IN

in PWM mode

CCO

4.5 5.8

(no switching)

in PSM mode 2.8

CCO

EN1 = EN2 = GND, VIN = 5.5 V or 20 V 100 200

IN_SD

0 V ≤ V

TRK

TRK1/VTRK2

Gain resistor connected to DLx,

= 47 kΩ ± 5%

R

CSG

Gain resistor connected to DLx,

= 22 kΩ ± 5%

R

CSG

Gain resistor connected to DLx,

= 100 kΩ ± 5%

R

CSG

= −40°C to +85°C, VFB = 0.6 V

T

J

= −40°C to +125°C, VFB = 0.6 V

T

J

V

COMP

f

SYNC

100 ns

SYNCMIN

5 pF

SYNC

I

DROPOUT

1 MΩ

SYNC

range = 0.9 V to 2.2 V ±0.3 %

COMP

= 340 kΩ to AGND 170 200 235 kHz

FREQ

= 78.7 kΩ to AGND 720 800 880 kHz

FREQ

= 39.2 kΩ to AGND 1275 1500 1725 kHz

FREQ

= 2 × fSW 400 3000 kHz

SYNC

= 100 mA 4.7 5.0 5.3 V

VCCO

= 0 mA to 100 mA, 35 mV

VCCO

= 100 mA, VIN ≤ 5 V 0.33 V

VCCO

= 2.75 V to 20 V 1 200 nA

IN

≤ 5 V −100 +1 +100 nA

2.4 3 3.6 V/V

5.2 6 6.9 V/V

= open 10.5 12 13.5 V/V

CSG

20.5 24 26.5 V/V

−0.85% +0.6 +0.85% V

−1.5% +0.6 +1.5% V

= 20 mA 10 mV

VCCO

Rev. A | Page 3 of 32

mA

mA
µA

ADP1850 Data Sheet

Parameter Symbol Conditions Min Typ Max Unit

GATE DRIVERS

DHx Rise Time CDH = 3 nF, V
DHx Fall Time CDH = 3 nF, V
DLx Rise Time CDL = 3 nF 16 ns
DLx Fall Time CDL = 3 nF 14 ns
DHx to DLx Dead Time External 3 nF is connected to DHx and DLx 25 ns
DHx or DLx Driver RON, Sourcing

Current

1

R

Sourcing 2 A with a 100 ns pulse 2 Ω

ON_SOURCE

Sourcing 1 A with a 100 ns pulse, VIN = 3 V 2.3 Ω
DHx or DLx Driver RON, Tempco TC
DHx or DLx Driver RON, Sinking

Current

1

V

RON

R

Sinking 2 A with a 100 ns pulse 1.5 Ω

ON_SINK

= 3 V or 12 V 0.3 %/oC

IN

Sinking 1 A with a 100 ns pulse, VIN = 3 V 2 Ω

DHx Maximum Duty Cycle fSW = 300 kHz 90 %
DHx Maximum Duty Cycle fSW = 1500 kHz 50 %
Minimum DHx On Time fSW = 200 kHz to 1500 kHz 135 ns
Minimum DHx Off Time fSW = 200 kHz to 1500 kHz 335 ns
Minimum DLx On Time fSW = 200 kHz to 1500 kHz 285 ns

COMPx VOLTAGE RANGE

COMPx Pulse Skip Threshold V
COMPx Clamp High Voltage V

In pulse skip mode 0.9 V

COMP,THRES

2.25 V

COMP,HIGH

THERMAL SHUTDOWN

Thermal Shutdown Threshold T

155

TMSD

Thermal Shutdown Hysteresis 20

OVERVOLTAGE AND POWER GOOD

THRESHOLDS
FBx Overvoltage Threshold VOV V

rising 0.635 0.65 0.665 V

FB

FBx Overvoltage Hysteresis 30 mV
FBx Undervoltage Threshold VUV V

falling 0.525 0.55 0.578 V

FB

FBx Undervoltage Hysteresis 30 mV
TRKx INPUT VOLTAGE RANGE 0 5 V
FBx TO TRKx OFFSET VOLTAGE TRKx = 0.1 V to 0.57 V, offset = VFB − V
SOFT START

SSx Output Current ISS During start-up 4.6 6.5 8.4 µA

SSx Pull-Down Resistor During a fault condition 3 kΩ

FBx to SSx Offset VSS = 0.1 V to 0.6 V, offset = VFB − VSS −10 +10 mV
PGOODx

PGOODx Pull-up Resistor R

Internal pull-up resistor to VCCO 12.5 kΩ

PGOOD

PGOODx Delay 12 µs

Over Voltage or Under Voltage

This is the minimum duration required to trip

the PGOOD signal
Minimum Duration
ILIM1, ILIM2 Threshold Voltage1 Relative to PGNDx −5 0 +5 mV
ILIM1, ILIM2 Output Current ILIMx = PGNDx 47 50 53 µA
Current Sense Blanking Period

After DLx goes high, current limit is not sensed

during this period

INTEGRATED RECTIFIER

At 20 mA forward current 16 Ω

(BOOST DIODE) RESISTANCE

ZERO CURRENT CROSS OFFSET

(SWx TO PGNDx)

1

Guaranteed by design.

2

Connect VIN to VCCO when 2.75 V < VIN < 5.5 V.

1

In pulse skip mode only, f

− VSW = 5 V 16 ns

BST

− VSW = 5 V 14 ns

BST

−10 0 +10 mV

TRK

10 µs

100 ns

= 600 kHz 0 2 4 mV

SW

°C
°C

Rev. A | Page 4 of 32

Data Sheet ADP1850

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

VIN, EN1/EN2, RAMP1/RAMP2 21 V
FB1/FB2, COMP1/COMP2, SS1/SS2, TRK1/TRK2,

FREQ, SYNC, VCCO, VDL, PGOOD1/PGOOD2
ILIM1/ILIM2, SW1/SW2 to PGND1/PGND2 −0.3 V to +21 V
BST1/BST2, DH1/DH2 to PGND1/PGND2 −0.3 V to +28 V
DL1/DL2 to PGND1/PGND2 −0.3V to VCCO + 0.3 V
BST1/BST2 to SW1/SW2 −0.3 V to +6 V
BST1/BST2 to PGND1/PGND2

20 ns Transients
SW1/SW2 to PGND1/PGND2

20 ns Transients
DL1/DL2, SW1/SW2, ILIM1/ILIM2 to

PGND1/PGND2
20 ns Negative Transients

PGND1/PGND2 to AGND −0.3 V to +0.3 V
PGND1/PGND2 to AGND 20 ns Transients −8 V to +4 V

θJA on Multilayer PCB (Natural Convection)

Operating Junction Temperature Range3 −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Maximum Soldering Lead Temperature 260°C

1

Measured with exposed pad attached to PCB.

2

Junction-to-ambient thermal resistance (θJA) of the package was calculated
or simulated on multilayer PCB.

3

The junction temperature, TJ, of the device is dependent on the ambient
temperature, TA, the power dissipation of the device, PD, and the junction-to­ambient thermal resistance of the package, θJA. Maximum junction
temperature is calculated from the ambient temperature and power
dissipation using the formula: TJ = TA + PD × θJA.

1, 2

−0.3 V to +6 V

32 V

25 V

−8 V

32.6°C/W

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all other voltages are
referenced to GND.

ESD CAUTION

Rev. A | Page 5 of 32

ADP1850 Data Sheet

V

V

SIMPLIFIED BLOCK DIAGRAM

IN

CCO

THERMAL

SHUTDOWN

LDO

REF

OV

0.6V
UV

EN1

EN2

SYNC

FREQ

COMP1

FB1

TRK1

SS1

RAMP1

0.6V

1MΩ

1kΩ

+

–

+

–

ERROR
AMPLIFIER

–
+

G

m

+
+

V

=

0

.

6

V

R

F

E

6.5µA

LOGIC

FAULT

EN1

SLOPE COMP AND
RAMP GENERATOR

OSCILLAT OR

5V

OV1

OVER_LIM1

OVER_LIM1

UVLO

LOGIC

0.9V

COMPARATOR

CURRENT

CONTROL

PH1

PH2

0.6V

–

+

–

+

PWM

LIMIT

EN1_SW
EN2_SW

DUPLICATE FOR

CHANNEL 2

OV

FB1

UV

SYNC

EN1_SW

OVER_LIM1

OV1

PULSE SKIP

AV = 3, 6, 12, 24

+

–

+

–

DRIVER LOG IC
CONTROL AND

MACHINE

DCM

ZERO CROSS

DETECT

CS GAIN

–

+

+

–

OV1

UV1

VDL

STATE

+

–

CURRENT SENSE
AMPLIFIER

AGND

VCCO

LOGIC

12kΩ

PGOOD1

BST1

DH1

SW1

VDL

DL1

PGND1

VCCO

50µA

ILIM1

9440-003

Figure 2.

Rev. A | Page 6 of 32

Data Sheet ADP1850

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TRK1

FB1

COMP1

RAMP1

SS1

PGOOD1

ILIM1

SS2

BST1

25

24

SW1

23

DH1
PGND1

22

DL1

21
20

DL2

19

PGND2

18

DH2

17 SW2

ILIM2

BST2

PGOOD2

09440-004

32313029282726

1

EN1

2

SYNC

VIN

3
4
5
6
7
8

ADP1850

TOP VIEW

(Not to Scale)

9

10111213141516

FB2

TRK2

RAMP2

COMP2

VCCO

VDL

AGND

FREQ

EN2

NOTES

1. CONNECT THE BOTTOM EXPOSED PAD OF THE
LFCSP PACKAGE TO SYST EM AGND PLANE .

Figure 3. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1 EN1

Enable Input for Channel 1. Drive EN1 high to turn on the Channel 1 controller, and drive EN1 low to turn off the
Channel 1 controller. Tie EN1 to VIN for automatic startup. For a precision UVLO, put an appropriately sized
resistor divider from VIN to AGND and tie the midpoint to this pin.

2 SYNC

Frequency Synchronization Input. Accepts an external signal between 1× and 2.3× of the internal oscillator
frequency, f

, set by the FREQ pin. The controller operates in forced PWM when a signal is detected at SYNC or

SW

when SYNC is high. The resulting switching frequency is ½ of the SYNC frequency. When SYNC is low or left
floating, the controller operates in pulse skip mode. For dual-phase operation, connect SYNC to a logic high or an
external clock.

3 VIN

Connect to Main Power Supply. Bypass with a 1 µF or larger ceramic capacitor connected as close to this pin as
possible and PGNDx.

4 VCCO

Output of the Internal Low Dropout Regulator (LDO). Bypass VCCO to AGND with a 1 F or larger ceramic
capacitor. The VCCO output remains active even when EN1 and EN2 are low. For operation with VIN below 5 V,
VIN may be shorted to VCCO. Do not use the LDO to power other auxiliary system loads.

5 VDL

Power Supply for the Low-Side Driver. Bypass VDL to PGNDx with a 1 µF or greater ceramic capacitor. Connect

VCCO to VDL.
6 AGND Analog Ground.
7 FREQ

Sets the desired operating frequency between 200 kHz and 1.5 MHz with one resistor between FREQ and AGND.

Connect FREQ to AGND for a preprogrammed 300 kHz or FREQ to VCCO for 600 kHz operating frequency.
8 EN2

Enable Input for Channel 2. Drive EN2 high to turn on the Channel 2 controller, and drive EN2 low to turn off the

Channel 2 controller. Tie EN2 to VIN for automatic startup. For a precision UVLO, put an appropriately sized

resistor divider from VIN to AGND, and tie the midpoint to this pin.
9 TRK2 Tracking Input for Channel 2. Connect TRK2 to VCCO if tracking is not used.
10 FB2 Output Voltage Feedback for Channel 2. Connect to Output 2 via a resistor divider.
11 COMP2

Compensation Node for Channel 2. Output of Channel 2 error amplifier. Connect a series resistor-capacitor

network from COMP2 to AGND to compensate the regulation control loop.
12 RAMP2

Connect a resistor from RAMP2 to VIN to set up a ramp current for slope compensation in Channel 2. The voltage

at RAMP2 is 0.2 V. This pin is high impedance when the channel is disabled.
13 SS2

Soft Start Input for Channel 2. Connect a capacitor from SS2 to AGND to set the soft start period. The node is

internally pulled up to 5 V with a 6.5 µA current source.
14 PGOOD2

Power Good. Open-drain power-good indicator logic output with an internal 12 kΩ resistor connected between

PGOOD2 and VCCO. PGOOD2 is pulled to ground when the Channel 2 output is outside the regulation window.

An external pull-up resistor is not required.

Rev. A | Page 7 of 32

ADP1850 Data Sheet

Pin No. Mnemonic Description

15 ILIM2

16 BST2

17 SW2

18 DH2

19 PGND2

20 DL2

21 DL1

22 PGND1

23 DH1

24 SW1

25 BST1

26 ILIM1

27 PGOOD1

28 SS1

29 RAMP1

30 COMP1

31 FB1 Output Voltage Feedback for Channel 1. Connect to Output 1 via a resistor divider.
32 TRK1 Tracking Input for Channel 1. Connect TRK1 to VCCO if tracking is not used.
33

(EPAD)

Exposed Pad
(EPAD)

Current Limit Sense Comparator Inverting Input for Channel 2. Connect a resistor between ILIM2 and SW2 to set
the current limit offset. For accurate current limit sensing, connect ILIM2 to a current sense resistor at the source
of the low-side MOSFET.

Boot-Strapped Upper Rail of High Side Internal Driver for Channel 2. Connect a multilayer ceramic capacitor
(0.1 µF to 0.22 µF) between BST2 and SW2. There is an internal boost rectifier connected between VDL and BST2.

Switch Node for Channel 2. Connect to source of the high-side N-channel MOSFET and the drain of the low-side
N-channel MOSFET of Channel 2.

High-Side Switch Gate Driver Output for Channel 2. Capable of driving MOSFETs with total input capacitance up
to 20 nF.

Power Ground for Channel 2. Ground for internal Channel 2 driver. Differential current is sensed between SW2
and PGND2. Use the Kelvin sensing connection technique between PGND2 and source of the low-side MOSFET.

Low-Side Synchronous Rectifier Gate Driver Output for Channel 2. To set the gain of the current sense amplifier,
connect a resistor between DL2 and PGND2. Capable of driving MOSFETs with a total input capacitance up to 20 nF.

Low-Side Synchronous Rectifier Gate Driver Output for Channel 1. To set the gain of the current sense amplifier,
connect a resistor between DL1 and PGND1. Capable of driving MOSFETs with a total input capacitance up to 20 nF.

Power Ground for Channel 1. Ground for internal Channel 1 driver. Differential current is sensed between SW1
and PGND1. Use the Kelvin sensing connection technique between PGND1 and source of the low-side MOSFET.

High-Side Switch Gate Driver Output for Channel 1. Capable of driving MOSFETs with a total input capacitance
up to 20 nF.

Power Switch Node for Channel 1. Connect to source of the high-side N-channel MOSFET and the drain of the
low-side N-channel MOSFET of Channel 1.

Boot-Strapped Upper Rail of High Side Internal Driver for Channel 1. Connect a multilayer ceramic capacitor
(0.1 µF to 0.22 µF) between BST1 and SW1. There is an internal boost diode or rectifier connected between VDL
and BST1.

Current Limit Sense Comparator Inverting Input for Channel 1. Connect a resistor between ILIM1 and SW1 to set
the current limit offset. For accurate current limit sensing, connect ILIM1 to a current sense resistor at the source
of the low-side MOSFET.

Power Good. Open-drain power-good indicator logic output with an internal 12 kΩ resistor connected between
PGOOD1 and VCCO. PGOOD1 is pulled to ground when the Channel 1 output is outside the regulation window.
An external pull-up resistor is not required.

Soft Start Input for Channel 1. Connect a capacitor from SS1 to AGND to set the soft start period. This node is
internally pulled up to 5 V with a 6.5 µA current source.

Connect a resistor from RAMP1 to VIN to set up a ramp current for slope compensation in Channel 1. The voltage
at RAMP2 is 0.2 V. This pin is high impedance when the channel is disabled.

Compensation Node for Channel 1. Output of Channel 1 error amplifier. Connect a series resistor-capacitor
network from COMP1 to AGND to compensate the regulation control loop.

Connect the bottom exposed pad of the LFCSP package to the system AGND plane.

Rev. A | Page 8 of 32

Data Sheet ADP1850

TYPICAL PERFORMANCE CHARACTERISTICS

100

90

VO = 3.3V, PSM

80

70

60

50

= 1.8V, PSM

V

O

40

EFFICIENCY (%)

30

20

10

0

0.01 0.1 1 10 100

V

V

O

= 1.8V, PWM

O

LOAD (A)

= 3.3V, PWM

V

= 12V, 600kHz

IN

Figure 4. Efficiency Plot of Figure 44

100

90

80

VO = 5V, PSM

70

60

50

40

VO = 5V, PWM

EFFICIENCY (%)

30

20

10

0

0.01 0. 1 1 10

VO = 1.8V, PW M

LOAD (A)

VO = 1.8V, P SM

V

= 12V, 750kHz

IN

Figure 5. Efficiency Plot of Figure 45

0

09440-005

09440-006

5.10

5.05

5.00

4.95

4.90

4.85

VCCO (V)

4.80

4.75

4.70

4.65
5 7 9 11131517

NO LOAD O N LDO

100mA LOAD ON LDO

VIN (V)

Figure 7. LDO Line Regulation

6

5

4

3

VCCO (V)

2

1

0

0123456

VIN (V)

Figure 8. VCCO vs. V

IN

09440-008

09440-009

–0.05

–0.10

∆VCCO (V)

–0.15

–0.20

–0.25

50mA LOAD

100mA LOAD

2.5 3.0 3. 5 4. 0 4.5 5.0

VIN (V)

Figure 6. LDO Load Regulation

09440-007

Rev. A | Page 9 of 32

1

2

3

CH1 10V
CH3 5V

SW1

SW2

SYNC 600kHz

CH2 10V M1µs A CH1 5.60V

Figure 9. An Example of Synchronization, f

= 600 kHz

SYNC

09440-010

ADP1850 Data Sheet

OUTPUT RESPONSE

1

8A TO 13A STEP LOAD

4

VIN = 12V
V

= 3.3V

OUT

CH1 20mV

B

W

CH4 5A Ω

M200µs A CH4 11.5A

Figure 10. Step Load Transient of Figure 44

= 1.8V

DH1

DL1

IL1

CH2 5VCH1 5V

CH4 1A Ω

M1ms A CH1 2.4V

1

2

VOUT1

3

4

VIN = 12V
V

OUT

OUTPUT PRECHARGED TO 1V

CH3 1V

Figure 11. Soft Start into Precharged Output

SW1

1

PGOOD1

VCCO (CH3)

2

V

, PRELOADED (CH4)

CH2 2VCH1 10V

CH4 2V Ω

OUT

M10ms A CH2 3.76V

09440-014

3

4

09440-011

CH3 2V

Figure 13. Thermal Shutdown Waveform

0.5

0

–0.5

(%)

SW

f

–1.0

–1.5

CHANGE IN

–2.0

–2.5

09440-012

3 5 7 9 11 13 15 17 19 21

Figure 14. Change in f

REFERENCED AT VIN = 2.75V

600kHz

300kHz

850kHz

VIN (V)

vs. VIN

SW

09440-015

1

3
2
4

SW

EN

CH3 1V

V

(CH3)

OUT

SS (CH4)

CSS = 100nF

CH2 2VCH1 10V

CH4 1V

M10ms A CH2 1.52V

Figure 12. Enable Start-Up Function

09440-013

Rev. A | Page 10 of 32

2.0

1.5

1.0

0.5

(%)

SW

f

0

–0.5

–1.0

CHANGE IN

–1.5

–2.0

–2.5

–40 –15 10 35 60 85 110 135

Figure 15. f

VIN = 12V; REFERENCED AT 25° C

TEMPERATURE (° C)

vs. Temperature

SW

09440-016

Data Sheet ADP1850

350

300

250

200

TIME (ns)

150

100

50

2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0

DH MINIMUM OFF TIME

DH MINIMUM ON TIME

VIN (V)

Figure 16. Typical DH Minimum On Time and Off Time

4

3

2

1

0

–1

–2

–3

CHANGE IN MI NIMUM ON/OFF TIME (%)

–4

–40 –15 10 35 60 85 110 135

DH MINIMUM OFF TIME

DH MINIMUM ON TIME

TEMPERATURE (°C)

Figure 17. DH Minimum On Time and Off Time Over Temperature

35

VIN = 12V
OUTPUT IS LOADED

34

HS FET = BS C080N03LS
LS FET = BSC030N03LS

33

32

31

30

29

DEAD TIME (n s)

28

27

26

DEAD TIME BET WEEN SW FAL LING EDGE
AND DL RISING EDGE, I NCLUDING DI ODE RECOVE RY TIME

25

–40 –20 0 20 40 60 80 100 120 140

TEMPERATURE (°C)

Figure 18. Dead Time vs. Temperature

09440-017

09440-018

09440-019

45

43

41

39

37

35

33

DEAD TIME (n s)

31

29

27

DEAD TIME BETWEE N SW FAL LING EDGE
AND DL RISI NG EDGE, INCLUDI NG DIODE RECOVERY TIME

25

0215105

Figure 19. Dead Time vs. V

600

580

560

540

520

500

(µS)

m

G

480

460

440

420

400

–40 –15 10 35 60 85 110 135

TEMPERATURE (°C)

Figure 20. G

4.5

4.0

3.5

3.0

2.5

2.0

1.5

DRIVER RESISTANCE (Ω)

1.0

0.5

VIN = 2.75V, SO URCING

0

–40 –15 10 35 60 85 110 135

of Error Amplifier vs. Temperature

m

VIN = 12V, SOURCING

TEMPERATURE (°C)

TA = 25°C
OUTPUT IS LOADE D
HS FET = BSC080N03LS
LS FET = BSC030N03LS

VIN (V)

VIN = 2.75V, SI NKING

VIN = 12V, SINKING

IN

VIN = 2.75V TO 20V

Figure 21. Driver Resistance vs. Temperature

0

09440-020

09440-021

09440-022

Rev. A | Page 11 of 32

ADP1850 Data Sheet

THEORY OF OPERATION

The ADP1850 is a current mode, dual-channel, step-down
switching controller with integrated MOSFET drivers for external
N-channel synchronous power MOSFETs. The two outputs are
phase shifted 180°. This reduces the input RMS ripple current,
thus minimizing required input capacitance. In addition, the
two outputs can be combined for dual-phase PWM operation
that can deliver more than 50 A output current and the two
channels are optimized for current sharing.

The ADP1850 can be set to operate in pulse skip high efficiency
mode (power saving mode) under light load or in forced PWM.
The integrated boost diodes in the ADP1850 reduce the overall
system cost and component count. The ADP1850 includes
programmable soft start, output overvoltage protection, program­mable current limit, power good, and tracking function. The

ADP1850 can be set to operate in any switching frequency

between 200 kHz and 1.5 MHz with one external resistor.

CONTROL ARCHITECTURE

The ADP1850 is based on a fixed frequency, current mode,
PWM control architecture. The inductor current is sensed
by the voltage drop measured across the external low-side
MOSFET, R
(valley inductor current). The current sense signal is further
processed by the current sense amplifier. The output of the
current sense amplifier is held, and the emulated current ramp
is multiplexed and fed into the PWM comparator as shown in
Figure 22. The valley current information is captured at the end
of the off period, and the emulated current ramp is applied at
that point when the next on cycle begins. An error amplifier
integrates the error between the feedback voltage and the
generated error voltage from the COMPx pin (from error
amplifier in Figure 22).

V

I

RAMP

As shown in Figure 22, the emulated current ramp is generated
inside the IC but offers programmability through the RAMPx
pin. Selecting an appropriate value resistor from V
RAMPx pin programs a desired slope compensation value and,
at the same time, provides a feed forward feature. The benefits
realized by deploying this type of control scheme are that there
is no need to worry about the turn-on current spike corrupting
the current ramp. Also, the current signal is stable because the

, during the off period of the switching cycle

DSON

OSC Q

V

R

RAMP

IN

C

R

FROM
ERROR AMP

V

CS

IN

A

R

S

R

A

CS

Figure 22. Simplified Control Architecture

FF

Q

TO
DRIVERS

FROM
LOW-SIDE
MOSFET

to the

IN

09440-023

current signal is sampled at the end of the turn-off period,
which gives time for the switch node ringing to settle. Other
benefits of using current mode control scheme still apply, such
as simplicity of loop compensation. Control logic enforces
antishoot-through operation to limit cross conduction of the
internal drivers and external MOSFETs.

OSCILLATOR FREQUENCY

The internal oscillator frequency, which ranges from 200 kHz
to 1.5 MHz, is set by an external resistor, R
pin. Some popular f

values are shown in Tab l e 4, and a graph-

SW

ical relationship is shown in Figure 23. For instance, a 78.7 kΩ
resistor sets the oscillator frequency to 800 kHz. Furthermore,
connecting FREQ to AGND or FREQ to VCCO sets the oscil­lator frequency to 300 kHz or 600 kHz, respectively. For other
frequencies that are not listed in Ta bl e 4, the values of R
and f

can be obtained from Figure 23, or use the following

SW

empirical formula to calculate these values:

065.1

−

×=

fR

SWFEQ

)kHz(96568)k(

Table 4. Setting the Oscillator Frequency

R

fSW (Typical)

FREQ

332 kΩ 200 kHz

78.7 kΩ 800 kHz

60.4 kΩ 1000 kHz
51 kΩ 1200 kHz

40.2 kΩ 1500 kHz
FREQ to AGND 300 kHz
FREQ to VCCO 600 kHz

410

360

310

260

(kΩ)

210

FREQ

R

160

110

60

10

100 400 700 1000 1300 1600 19 00

Figure 23. R

R

f

FREQ

SW

(kHz)

(kΩ) = 96,568

vs. f

FREQ

FREQ

f

SW

, at the FREQ

FREQ

–1.065

(kHz)

SW

09440-024

Rev. A | Page 12 of 32

Data Sheet ADP1850

MODES OF OPERATION

The SYNC pin is a multifunctional pin. PWM mode is enabled
when SYNC is connected to VCCO or a high logic. With SYNC
connected to ground or left floating, the pulse skip mode is
enabled. Switching SYNC from low to high or high to low on
the fly causes the controller to transition from forced PWM
to pulse skip mode or pulse skip mode to forced PWM, respec­tively, in two clock cycles.

1

2

3

DH1

DL1

OUTPUT

RIPPLE

Table 5. Mode of Operation Truth Table

SYNC Pin Mode of Operation

Low Pulse skip mode
High Forced PWM or two-phase operation
No Connect Pulse skip mode

Clock Signal Forced PWM or two-phase operation

The ADP1850 has a pulse skip sensing circuitry that allows the
controller to skip PWM pulses, thus, reducing the switching
frequency at light loads and, therefore, maintaining high
efficiency during a light load operation. The switching
frequency is a fraction of the natural oscillator frequency and
is automatically adjusted to regulate the output voltage. The
resulting output ripple is larger than that of the fixed frequency
forced PWM. Figure 24 shows that the ADP1850 operates in
PSM under a very light load. Pulse skip frequency under light
load is dependent on the inductor, output capacitance, output
load, and input and output voltages.

SW1

1

COMP1 (CH2)

3

4

2

CH3 20mV

Figure 24. Example of Pulse Skip Mode Under Light Load

VOUT RIPPLE

INDUCTOR

CURRENT

CH2 200mVCH1 10V

CH4 2A Ω

M200µs A CH1 7.8V

09440-025

When the output load is greater than the pulse skip threshold
current, that is, V

reaches the threshold of 0.9 V, the

COMP

ADP1850 exits the pulse skip mode of operation and enters

the fixed frequency discontinuous conduction mode (DCM),
as shown in Figure 25. When the load increases further, the

ADP1850 enters CCM.

4

CH3 20mV

Figure 25. Example of Discontinuous Conduction Mode (DCM) Waveform

INDUCTOR CURRENT

CH2 5VCH1 10V

CH4 2A Ω

M1µs A CH1 13.4V

09440-026

In forced PWM, the ADP1850 always operates in CCM at any
load. The inductor current is always continuous, thus, efficiency
is poor at light loads.

SYNCHRONIZATION

The switching frequency of the ADP1850 can be synchronized
to an external clock by connecting SYNC to a clock signal. The
external clock should be between 1× and 2.3× of the internal
oscillator frequency, f
of the external SYNC frequency because the SYNC input is
divided by 2, and the resulting phases are used to clock the two
channels alternately. In synchronization, the ADP1850 operates
in PWM.

When an external clock is detected at the first SYNC edge, the
internal oscillator is reset, and the clock control shifts to SYNC.
The SYNC edges then trigger subsequent clocking of the PWM
outputs. The DH1/DH2 rising edges appear approximately 100 ns
after the corresponding SYNC edge, and the frequency is locked
to the external signal. Depending on the start-up conditions of
Channel 1 and Channel 2, either Channel 1 or Channel 2 can be
the first channel synchronized to the rising edge of the SYNC
clock. If the external SYNC signal disappears during operation,
the ADP1850 reverts to its internal oscillator. When the SYNC
function is used, it is recommended to connect a pull-up resistor
from SYNC to VCCO so that when the SYNC signal is lost, the

ADP1850 continues to operate in PWM.

. The resulting switching frequency is ½

SW

Rev. A | Page 13 of 32

ADP1850 Data Sheet

V

SYNCHRONOUS RECTIFIER AND DEAD TIME

The synchronous rectifier (low-side MOSFET) improves efficiency
by replacing the Schottky diode that is normally used in an
asynchronous buck regulator. In the ADP1850, the antishoot­through circuit monitors the SW and DL nodes and adjusts the
low-side and high-side drivers to ensure break-before-make
switching which prevents cross-conduction or shoot-through
between the high-side and low-side MOSFETs. This break­before-make switching is known as dead time, which is not
fixed and depends on how fast the MOSFETs are turned on
and off. In a typical application circuit that uses medium sized
MOSFETs with input capacitance of approximately 3 nF, the
typical dead time is approximately 30 ns. When small and fast
MOSFETs with fast diode recovery time are used, the dead time
can be as low as 13 ns.

INPUT UNDERVOLTAGE LOCKOUT

When the bias input voltage, VIN, is less than the undervoltage
lockout (UVLO) threshold, the switch drivers stay inactive.
When V

exceeds the UVLO threshold, the switchers start

IN

switching.

INTERNAL LINEAR REGULATOR

The internal linear regulator is low dropout (LDO) meaning it
can regulate its output voltage, VCCO. VCCO powers up the
internal control circuitry and provides power for the gate
drivers. It is guaranteed to have more than 200 mA of output
current capability, which is sufficient to handle the gate drive
requirements of typical logic threshold MOSFETs driven at up
to 1.5 MHz. VCCO is always active and cannot be shut down by
the EN1 and EN2 pins. Bypass VCCO to AGND with a 1 µF or
greater capacitor.

Because the LDO supplies the gate drive current, the output of
VCCO is subject to sharp transient currents as the drivers
switch and the boost capacitors recharge during each switching
cycle. The LDO has been optimized to handle these transients
without overload faults. Due to the gate drive loading, using the
VCCO output for other external auxiliary system loads is not
recommended.

The LDO includes a current limit well above the expected
maximum gate drive load. This current limit also includes a
short-circuit fold back to further limit the VCCO current in the
event of a short-circuit fault.

The VDL pin provides power to the low-side driver. Connect
VDL to VCCO. Bypass VDL to PGNDx with a 1 µF (minimum)
ceramic capacitor, which must be placed close to the VDL pin.

For an input voltage less than 5.5 V, it is recommended to
bypass the LDO by connecting VIN to VCCO, as shown in
Figure 26, thus eliminating the dropout voltage. However, if
the input range is 4 V to 7 V, the LDO cannot be bypassed by
shorting VIN to VCCO because the 7 V input has exceeded the
maximum voltage rating of the VCCO pin. In this case, use the
LDO to drive the internal drivers, but keep in mind that there is
a dropout when V

is less than 5 V.

IN

Rev. A | Page 14 of 32

= 2.75V TO 5. 5V

IN

VIN VCCO

ADP1850

09440-027

Figure 26. Configuration for V

< 5.5 V

IN

OVERVOLTAGE PROTECTION

The ADP1850 has a built-in circuit for detecting output over­voltage at the FB node. When the FB voltage, V

, rises above

FB

the overvoltage threshold, the low-side N-channel MOSFET
(NMOSFET) is immediately turned on, and the high-side
NMOSFET is turned off until the V

drops below the

FB

undervoltage threshold. This action is known as the crow­bar overvoltage protection. If the overvoltage condition is
not removed, the controller maintains the feedback voltage
between the overvoltage and undervoltage thresholds, and the
output is regulated to within typically +8% and −8% of the
regulation voltage. During an overvoltage event, the SS node
discharges toward zero through an internal 3 kΩ pull-down
resistor. When the voltage at FBx drops below the undervoltage
threshold, the soft start sequence restarts. Figure 27 shows the
overvoltage protection scheme in action in PSM.

1

2

3

4

CH1 20.0V CH2 5.00V
CH3 1.00V CH4 10.0V

DH1

PGOOD1

VO1 = 1.8V SHORTED T O 2V SOURCE

VIN

M100µs A CH1 10.0V

Figure 27. Overvoltage Protection in PSM

09440-028

POWER GOOD

The PGOODx pin is an open-drain NMOSFET with an internal
12 kΩ pull-up resistor connected between PGOODx and VCCO.
PGOODx is internally pulled up to VCCO during normal
operation and is active low when tripped. When the feedback
voltage, V
below the undervoltage threshold, the PGOODx output is
pulled to ground after a delay of 12 µs. The overvoltage or
undervoltage condition must exist for more than 10 µs for
PGOODx to become active. The PGOODx output also
becomes active if a thermal overload condition is detected.

, rises above the overvoltage threshold or drops

FB

Data Sheet ADP1850

SHORT-CIRCUIT AND CURRENT-LIMIT PROTECTION

When the output is shorted or the output current exceeds the
current limit set by the current limit setting resistor (between
ILIMx and SWx) for eight consecutive cycles, the ADP1850
shuts off both the high-side and low-side drivers and restarts
the soft start sequence every 10 ms, which is known as hiccup
mode. The SS node discharges to zero through an internal 1 kΩ
resistor during an overcurrent or short-circuit event. Figure 28
shows that the ADP1850 on a high current application circuit is
entering current limit hiccup mode when the output is shorted.

1

3

4

CH1 10V

CH3 500mV

Figure 28. Current Limit Hiccup Mode, 20 A Current Limit

CH4 10A Ω

SW1

SS1

INDUCTOR CURRENT

M2ms A CH1 11.2V

09440-029

SHUTDOWN CONTROL

The EN1 and EN2 pins are used to enable or disable Channel 1
and Channel 2 of the ADP1850. The precision enable (minimum)
threshold for EN1/EN2 is 0.57 V. When the voltage at EN1/EN2
rises above the threshold voltage, the ADP1850 is enabled and
starts normal operation after the soft start period. And when
the voltage at EN1/EN2 drops typically 30 mV (hysteresis)
below the threshold voltage, the switchers and the internal
circuits in the ADP1850 are turned off. Note that EN1/EN2
cannot shut down the LDO at VCCO, which is always active.

For the purpose of start-up power sequencing, the startup of the

ADP1850 can be programmed by connecting an appropriate

resistor divider from the master power supply to the EN1/EN2
pin, as shown in Figure 29. For instance, if the desired start-up
voltage from the master power supply is 10 V, R1 and R2 can be
set to 156 kΩ and 10 kΩ, respectively.

MASTER

SUPPLY VOLTAGE

R1

R2

Figure 29. Optional Power-Up Sequencing Circuit

ADP1850

EN1
OR
EN2

FB1

OR

FB2

V

OUT1

R

TOP

R

BOT

09440-030

THERMAL OVERLOAD PROTECTION

The ADP1850 has an internal temperature sensor that senses
the junction temperature of the chip. When the junction
temperature of the ADP1850 reaches approximately 155°C, the

ADP1850 goes into thermal shutdown, the converter is turned

off, and SS discharges toward zero through an internal 1 kΩ
resistor. At the same time, VCCO discharges to zero. When the
junction temperature drops below 135°C, the ADP1850 resumes
normal operation after the soft start sequence.

Rev. A | Page 15 of 32

ADP1850 Data Sheet

×

APPLICATIONS INFORMATION

SETTING THE OUTPUT VOLTAGE

The output voltage is set using a resistive voltage divider from
the output to FB. The voltage divider divides down the output
voltage to the 0.6 V FB regulation voltage to set the regulation
output voltage. The output voltage can be set to as low as 0.6 V
and as high as 90% of the power input voltage.

The maximum input bias current into FB is 100 nA. For a 0.15%
degradation in regulation voltage and with 100 nA bias current,
the low-side resistor, R
in 67 µA of divider current. For R

, must be less than 9 kΩ, which results

BOT

, use a 1 k to 20 k resistor.

BOT

A larger value resistor can be used but results in a reduction in
output voltage accuracy due to the input bias current at the FBx
pin, while lower values cause increased quiescent current
consumption. Choose R

to set the output voltage by using

TOP

the following equation:

⎛

OUT

⎜

RR

=

BOTTOP

⎜

V

⎝

⎞

VV

−

FB

⎟
⎟

FB

⎠

where:

R

is the high-side voltage divider resistance.

TOP

is the low-side voltage divider resistance.

R

BOT

is the regulated output voltage.

V

OUT

V

is the feedback regulation threshold, 0.6 V.

FB

The minimum output voltage is dependent on f
DH on time. The maximum output voltage is dependent on f

and minimum

SW

SW

the minimum DH off time, and the IR drop across the high-side
NMOSFET and the DCR of the inductor. For example, with f

SW

of
600 kHz (or 1.67 µs) and a minimum on time of 130 ns, the
minimum duty cycle is approximately 7.8% (130 ns/1.67 µs). If
V

is 12 V and the duty cycle is 7.8%, then the lowest output is

IN

0.94 V. As an example for the maximum output voltage, if V
5 V, f

is 600 kHz, and the minimum DH off time is 395 ns

SW

is

IN

(335 ns DH off time plus approximately 60 ns total dead time),
then the maximum duty cycle is 76%. Therefore, the maximum
output is approximately 3.8 V. If the IR drop across the high­side NMOSFET and the DCR of the inductor is 0.5 V, then the
absolute maximum output is 4.5 V (5 V − 0.5 V), independent of
f

and duty cycle.

SW

SOFT START

The soft start period is set by an external capacitor between
SS1/SS2 and AGND. The soft start function limits the input
inrush current and prevents output overshoot.

When EN1/EN2 is enabled, a current source of 6.5 µA starts
charging the capacitor, and the regulation voltage is reached
when the voltage at SS1/SS2 reaches 0.6 V.

The soft start period is approximated by

V6.0

=

Ct

SSSS

A5.6

,

The SSx pin reaches a final voltage equal to VCCO. If the output
voltage is precharged prior to turn-on, the ADP1850 prevents
reverse inductor current, which discharges the output capacitor.
Once the voltage at SSx exceeds the regulation voltage (typically

0.6 V), the reverse current is reenabled to allow the output
voltage regulation to be independent of load current.

Furthermore, in dual-phase operation, where SS1 is shorted to
SS2, the current source is doubled to 13 µA during the soft start
sequence.

When a controller is disabled, for instance, EN1/EN2 is pulled
low or experiences an overcurrent limit condition, the soft start
capacitor is discharged through an internal 3 kΩ pull-down
resistor.

SETTING THE CURRENT LIMIT

The current limit comparator measures the voltage across the
low-side MOSFET to determine the load current.

The current limit is set by an external current limit resistor,
R

, between ILIMx and SWx. The current sense pin, ILIMx,

ILIM

sources nominally 50 A to this external resistor. This creates an
offset voltage of R
across the low-side MOSFET, R
this offset voltage, the ADP1850 flags a current limit event.

Because the ILIMx current and the MOSFET, R
process and temperature, the minimum current limit should be
set to ensure that the system can handle the maximum desired
load current. To do this, use the peak current in the inductor,
which is the desired output current limit level plus ½ of the
ripple current, the maximum R
highest expected temperature, and the minimum ILIM current.
Keep in mind that the temperature coefficient of the MOSFET,
R

, is typically 0.4%/oC.

DSON

R

=

ILIM

where:

I

is the peak inductor current.

LPK

multiplied by 50 A. When the drop

ILIM

, is equal to or greater than

DSON

of the MOSFET at its

DSON

RI

LPK

MAXDSON

A47_μ

, vary over

DSON

Rev. A | Page 16 of 32

Data Sheet ADP1850

ACCURATE CURRENT-LIMIT SENSING

R

of the MOSFET can vary by more than 50% over the

DSON

temperature range. Accurate current limit sensing is achieved
by adding a current sense resistor from the source of the low­side MOSFET to PGNDx. Make sure that the power rating of the
current sense resistor is adequate for the application. Apply the
previous equation and calculate R
with R

. Figure 30 illustrates the implementation of accurate

SENSE

by replacing R

ILIM

DSON_MAX

current limit sensing.

V

IN

ADP1850

DHx

SWx

R

ILIM

ILIMx

DLx

R

SENSE

Figure 30. Accurate Current Limit Sensing

09440-031

SETTING THE SLOPE COMPENSATION

In a current-mode control topology, slope compensation is
needed to prevent subharmonic oscillations in the inductor
current and to maintain a stable output. The external slope
compensation is implemented by summing the amplified sense
signal and a scaled voltage at the RAMPx pin. To implement the
slope compensation, connect a resistor between RAMPx and
the input voltage. The resistor, R

9

107××

R

RAMP

=

L

RA

MAXDSONCS

_

where:

9

7 × 10

is an internal parameter.

L is the inductance (with units in H) of the inductor.
R
A

is the low-side MOSFET maximum on resistance.

DSON_MAX

is the gain, either 3 V/V, 6 V/V, 12 V/V, or 24 V/V, of the

CS

current sense amplifier (see the Setting the Current Sense Gain
section for more details).

R

is temperature dependent and can vary as much as

DSON

o

0.4%/

C. Choose R

at the maximum operating temperature.

DSON

The voltage at RAMPx is fixed at 0.2 V, and the current going
into RAMPx should be between 10 µA and 160 µA. Make sure
that the following condition is satisfied:

V

A10 μ≤

≤μ

V2.0

−

IN

R

RAMP

For instance, with an input voltage of 12 V, R
exceed 1.1 MΩ. If the calculated R
then select an R

value that produces between 10 µA and 15 µA.

RAMP

Figure 31 illustrates the connection of the slope compensation
resistor, R

, and the current sense gain resistor, R

RAMP

, is calculated by

RAMP

A160

should not

RAMP

produces less than 10 µA,

RAMP

CSG

.

Rev. A | Page 17 of 32

V

ILIM

IN

R

CSG

09440-032

R

RAMP

RAMP

ADP1850

DHx

SWx

R

ILIMx

DLx

Figure 31. Slope Compensation and CS Gain Connection

SETTING THE CURRENT SENSE GAIN

The voltage drop across the external low-side MOSFET is
sensed by a current sense amplifier by multiplying the peak
inductor current and the R
then amplified by a gain factor of either 3 V/V, 6 V/V, 12 V/V,
or 24 V/V, which is programmable by an external resistor, R
connected to the DLx pin. This gain is sensed only during
power-up and not during normal operation. The amplified
voltage is summed with the slope compensation ramp voltage
and fed into the PWM controller for a stable regulation voltage.

The voltage range of the internal node, V
and 2.2 V. Select the current sense gain such that the internal
minimum amplified voltage (V
maximum amplified voltage (V
or V

is not the same as V

CSMAX

to 2.25 V. Make sure that the maximum V
not exceed 2.2 V to account for temperature and part-to-part
variations. See the following equations for V
V

:

COMPMAX

CSMIN

V +

COMPMAX

V75.0

−

IN

=

pF100

where:

V

is the minimum amplified voltage of the internal current

CSMIN

sense amplifier at zero output current.

V

is the maximum amplified voltage of the internal current

CSMAX

sense amplifier at maximum output current.

R

is the low-side MOSFET minimum on resistance. The

DSON_MIN

zero-current level voltage of the current sense amplifier is 0.75 V.

I

is the peak-to-peak ripple current in the inductor.

LPP

I

is the maximum output dc load current.

LOADMAX

V

is the maximum voltage at the COMP pin.

COMPMAX

100 pF is an internal parameter.

t

is the high-side driver (DH) on time.

ON

of the MOSFET. The result is

DSON

, is between 0.4 V

CS

) is above 0.4 V and the

CSMIN

) is 2.1 V. Note that V

CSMAX

, which has a range of 0.85 V

COMP

COMP

1

LPP

2

(75.0

LOADMAXCSMAX

)V2.0(

R

×

RAMP

_

1

)

LPP

2

tV

ON

V

CSMAX

(V

CSMIN

ARIV ××−=

CSMINDSON

COMPMAX

, V

CSMAX

_

CSG

CSMIN

) does

, and

ARIIVV ××−+=

CSMAXDSON

,

ADP1850 Data Sheet

−

INPUT CAPACITOR SELECTION

The input current to a buck converter is a pulse waveform. It is
zero when the high-side switch is off and approximately equal
to the load current when it is on. The input capacitor carries the
input ripple current, allowing the input power source to supply
only the direct current. The input capacitor needs sufficient
ripple current rating to handle the input ripple, as well as an
ESR that is low enough to mitigate input voltage ripple. For the
usual current ranges for these converters, it is good practice to
use two parallel capacitors placed close to the drains of the
high-side switch MOSFETs (one bulk capacitor of sufficiently
high current rating and a 10 F ceramic decoupling capacitor,
typically).

Select an input bulk capacitor based on its ripple current rating.
First, determine the duty cycle of the output.

V

OUT

D =

The input capacitor RMS ripple current is given by

where:

I

is the output current.

O

D is the duty cycle

The minimum input capacitance required for a particular load is

C

where:

V

is the desired input ripple voltage.

PP

is the equivalent series resistance of the capacitor.

R

ESR

If an MLCC capacitor is used, the ESR is near 0, then the
equation is simplified to

The capacitance of MLCC is voltage dependent. The actual
capacitance of the selected capacitor must be derated according to
the manufacturer’s specification. In addition, add more bulk
capacitance, such as by using electrolytic or polymer capacitors,
as necessary for large step load transients. Make sure the
current ripple rating of the bulk capacitor exceeds the
maximum input current ripple of a particular design.

V

IN

)1( DDII

−=

ORMS

DDI

)1(

−×

MININ

IC

,

MININ

O

×−

PP

DD

−×=)1(

fV

×

PP

SW

O

=

,

fDRIV

)(

SWESRO

Rev. A | Page 18 of 32

INPUT FILTER

Normally a 0.1 µF or greater value bypass capacitor from the
input pin (VIN) to AGND is sufficient for filtering out any
unwanted switching noise. However, depending on the PCB
layout, some switching noise can enter the ADP1850 internal
circuitry; therefore, it is recommended to have a low pass filter
at the VIN pin. Connecting a resistor, between 2 Ω and 5 Ω, in
series with VIN and a 1 µF ceramic capacitor between VIN and
AGND creates a low pass filter that effectively filters out any
unwanted glitches caused by the switching regulator. Keep in
mind that the input current could be larger than 100 mA when
driving large MOSFETs. A 100 mA across a 5 Ω resistor creates
a 0.5 V drop, which is the same voltage drop in VCCO. In this
case, a lower resistor value is desirable.

2Ω TO 5Ω

V

IN

1µF

Figure 32. Input Filter Configuration

ADP1850

VIN

AGND

09440-033

BOOST CAPACITOR SELECTION

To lower system component count and cost, the ADP1850 has
an integrated rectifier (equivalent to the boost diode) between
VCCO and BSTx. Choose a boost ceramic capacitor with a
value between 0.1 µF and 0.22 µF; this capacitor provides the
current for the high-side driver during switching.

INDUCTOR SELECTION

The output LC filter smoothes the switched voltage at SWx. For
most applications, choose an inductor value such that the
inductor ripple current is between 20% and 40% of the
maximum dc output load current. Generally, a larger inductor
current ripple generates more power loss in the inductor and
larger voltage ripples at the output. Check the inductor data
sheet to make sure that the saturation current of the inductor is
well above the peak inductor current of a particular design.

Choose the inductor value by the following equation:

V

VV

IN

=

L ×

SW

Δ×

where:

L is the inductor value.
f

is the switching frequency.

SW

V

is the output voltage.

OUT

is the input voltage.

V

IN

ΔI

is the peak-to-peak inductor ripple current.

L

OUT

If

OUT

V

IN

L

Data Sheet ADP1850

Δ

××≅

OUTPUT CAPACITOR SELECTION

Choose the output bulk capacitor to set the desired output voltage
ripple. The impedance of the output capacitor at the switching
frequency multiplied by the ripple current gives the output
voltage ripple. The impedance is made up of the capacitive
impedance plus the nonideal parasitic characteristics, the
equivalent series resistance (ESR), and the equivalent series
inductance (ESL). The output voltage ripple can be
approximated by

⎞
⎟

×+

Lf

ESLSW

⎟
⎠

LfIRIVf

×Δ−Δ−Δ

ESLSW

OUT

⎛
⎜

RIV 4

L

ESR

⎜
⎝

1

+Δ≅Δ

×

Cf

8

SW

OUT

where:

ΔV

is the output ripple voltage.

OUT

ΔI

is the inductor ripple current.

L

R

is the equivalent series resistance of the output capacitor (or

ESR

the parallel combination of ESR of all output capacitors).

L

is the equivalent series inductance of the output capacitor

ESL

(or the parallel combination of ESL of all capacitors).

Solving C

in the previous equation yields

OUT

I

Δ

C

OUT

L

×

≅

8

SW

OUT

1

4

L

ESR

L

Usually the capacitor impedance is dominated by ESR. The
maximum ESR rating of the capacitor, such as in electrolytic or
polymer capacitors, is provided in the manufacturer’s data
sheet; therefore, output ripple reduces to

RIV ×Δ≅Δ

L

OUT

ESR

Electrolytic capacitors also have significant ESL, on the order of
5 nH to 20 nH, depending on type, size, and geometry. PCB
traces contribute some ESR and ESL, as well. However, using
the maximum ESR rating from the capacitor data sheet usually
provides some margin such that measuring the ESL is not
usually required.

In the case of output capacitors where the impedance of the
ESR and ESL are small at the switching frequency, for instance,
where the output capacitor is a bank of parallel MLCC capaci­tors, the capacitive impedance dominates and the output
capacitance equation reduces to

Δ

I

OUT

L

×Δ

fV

SW

≅

C

OUT

8

Make sure that the ripple current rating of the output capacitors
is greater than the maximum inductor ripple current.

During a load step transient on the output, for instance, when
the load is suddenly increased, the output capacitor supplies the
load until the control loop has a chance to ramp the inductor
current. This initial output voltage deviation results in a voltage
droop or undershoot. The output capacitance, assuming 0 Ω

SR, required to satisfy the voltage droop requirement is
approximated by

I

C

≅

OUT

STEP

×Δ

fV

SWDROOP

where:
∆I

is the step load.

STEP

∆V

is the voltage droop at the output.

DROOP

When a load is suddenly removed from the output, the energy
stored in the inductor rushes into the capacitor, causing the
output to overshoot. The output capacitance required to satisfy
the output overshoot requirement can be approximated by

2

LI

Δ

C

≅

OUT

STEP

2

)(

−Δ+

2

VVV

OUTOVERSHOOTOUT

where:
∆V

OVERSH OOT

is the overshoot voltage during the step load.

Select the largest output capacitance given by any of the
previous three equations.

MOSFET SELECTION

The choice of MOSFET directly affects the dc-to-dc converter
performance. A MOSFET with low on resistance reduces I
losses, and low gate charge reduces transition losses. The
MOSFET should have low thermal resistance to ensure that the
power dissipated in the MOSFET does not result in excessive
MOSFET die temperature.

The high-side MOSFET carries the load current during on time
and usually carries most of the transition losses of the converter.
Typically, the lower the on resistance of the MOSFET, the
higher the gate charge and vice versa. Therefore, it is important
to choose a high-side MOSFET that balances the two losses. The
conduction loss of the high-side MOSFET is determined by the
equation

⎛

⎞

2

×≅

)(

V

OUT

⎜

RIP

DSONLOADC

⎟
⎜
⎝

⎟

V

IN

⎠

where:

R

is the MOSFET on resistance.

DSON

The gate charging loss is approximated by the equation

PV

G

fQVP

SWG

where:

V

is the gate driver supply voltage.

PV

is the MOSFET total gate charge.

Q

G

Note that the gate charging power loss is not dissipated in the
MOSFET but rather in the ADP1850 internal drivers. This
power loss should be taken into consideration when calculating
the overall power efficiency.

2

R

Rev. A | Page 19 of 32

ADP1850 Data Sheet

+

≅

××=

+

=

The high-side MOSFET transition loss is approximated by the
equation

)(

fttIV

×+××

IN

P

≅

T

LOAD

FR

SW

2

where:

P

is the high-side MOSFET switching loss power.

T

is the rise time in charging the high-side MOSFET.

t

R

t

is the fall time in discharging the high-side MOSFET.

F

and tF can be estimated by

t

R

Q

GSW

GSW

RISEDRIVER

_

FALLDRIVER

_

t

≅

R

I

Q

t

≅

F

I

where:

Q

is the gate charge of the MOSFET during switching and is

GSW

given in the MOSFET data sheet.

I

DRIVER_RISE

and I

DRIVER_FALL

are the driver current put out by the

ADP1850 internal gate drivers.

If Q

is not given in the data sheet, it can be approximated by

GSW

Q

GS

QQ +≅

GDGSW

2

where:

and QGS are the gate-to-drain and gate-to-source charges

Q

GD

given in the MOSFET data sheet.

I

DRIVER_RISE

and I

DRIVER_FALL

I

RISEDRIVER

_

I

_

FALLDRIVER

can be estimated by

≅

≅

DD

_

SOURCEON

V

SP

_

SINKON

VV

−

SP

RR

+

GATE

RR

+

GATE

where:

V

is the input supply voltage to the driver and is between 2.75 V

DD

and 5 V, depending on the input voltage.

V

is the switching point where the MOSFET fully conducts;

SP

this voltage can be estimated by inspecting the gate charge
graph given in the MOSFET data sheet.

R

is the on resistance of the ADP1850 internal driver,

ON_SOURCE

given in Tab l e 1 when charging the MOSFET.

R

is the on resistance of the ADP1850 internal driver,

ON_SINK

given in Tab l e 1 when discharging the MOSFET.

R

is the on gate resistance of MOSFET given in the

GATE

MOSFET data sheet. If an external gate resistor is added, add
this external resistance to R

GATE

.

The total power dissipation of the high-side MOSFET is the
sum of conduction and transition losses:

PPP

CHS

T

The synchronous rectifier, or low-side MOSFET, carries the
inductor current when the high-side MOSFET is off. The low­side MOSFET transition loss is small and can be neglected in
the calculation. For high input voltage and low output voltage,
the low-side MOSFET carries the current most of the time.
Therefore, to achieve high efficiency, it is critical to optimize
the low-side MOSFET for low on resistance. In cases where the
power loss exceeds the MOSFET rating or lower resistance is
required than is available in a single MOSFET, connect multiple
low-side MOSFETs in parallel. The equation for low-side
MOSFET conduction power loss is

2

⎡

RIP 1)(

⎢

DSONLOADCLS

⎣

⎤

V

OUT

−×≅

⎥

V

IN

⎦

There is also additional power loss during the time, known as
dead time, between the turn-off of the high-side switch and the
turn-on of the low-side switch, when the body diode of the low­side MOSFET conducts the output current. The power loss in
the body diode is given by

IftVP ×

BODYDIODE

DF

OSW

where:

V

is the forward voltage drop of the body diode, typically 0.7 V.

F

is the dead time in the ADP1850, typically 30 ns when driving

t

D

some medium-size MOSFETs with input capacitance, C

, of

iss

approximately 3 nF. The dead time is not fixed. Its effective
value varies with gate drive resistance and C

, so P

iss

BODYDIODE

increases in high load current designs and low voltage designs.

Then the power loss in the low-side MOSFET is

PPP

BODYDIODECLSLS

Note that MOSFET, R
ture with a typical temperature coefficient of 0.4%/
MOSFET junction temperature (T

, increases with increasing tempera-

DSON

) rise over the ambient

J

o

C. The

temperature is

T

= TA + θJA × P

J

D

where:

θ

is the thermal resistance of the MOSFET package.

JA

is the ambient temperature.

T

A

P

is the total power dissipated in the MOSFET.

D

Rev. A | Page 20 of 32

Data Sheet ADP1850

LOOP COMPENSATION (SINGLE PHASE OPERATION)

As with most current mode step-down controller, a transcon­ductance error amplifier is used to stabilize the external voltage
loop. Compensating the ADP1850 is fairly easy; an RC compen­sator is needed between COMPx and AGND. Figure 33 shows
the configuration of the compensation components: R
C

, and CC2. Because CC2 is very small compared to C

COMP

to simplify calculation, C

is ignored for the stability

C2

compensation analysis.

ADP1850

COMPx

R

C

COMP

C2

C

COMP

AGND

Figure 33. Compensation Components

G

0.6V

m

FBx

09440-034

The open loop gain transfer function at angular frequency, s, is
given by

V

GGsH

m

REF

OUT

COMP

CS

V

××××=

FILTER

where:

G

is the transconductance of the error amplifier, 500 µS.

m

G

is the tranconductance of the power stage.

CS

is the impedance of the compensation network.

Z

COMP

Z

is the impedance of the output filter.

FILTER

V

= 0.6 V.

REF

with units of A/V is given by

G

CS

G

=

CS

1

RA

×

(2)

MINDSONCS

_

where:

A

is the current sense gain of either 3 V/V, 6 V/V, 12 V/V, or

CS

24 V/V set by the gain resistor between DLx and PGNDx.

R

If a sense resistor, R
then G

is the low-side MOSFET minimum on resistance.

DSON_MIN

, is added in series with the low-side FET,

S

becomes

CS

G+×=

CS

1

_ SMINDSONCS

)(

RRA

Because the zero produced by the ESR of the output capacitor is
not needed to stabilize the control loop, assuming ESR is small
the ESR is ignored for analysis. Then Z

1

Z

FILTER

Because C

=

is small relative to C

C2

RZ

(3)

sC

OUT

, Z

COMP

1

1

COMPCOMP

sC

=+=

COMP

is given by

FILTER

can be simplified to

COMP

×+

CsR

COMPCOMP

sC

COMP

,

COMP

,

COMP

)()()( sZsZ

(1)

(4)

At the crossover frequency, the open-loop transfer function is
unity or 0 dB, H (f
Equation 3, Z

COMP

fZ

CROSSCOMP

The zero produced by R

f

=

ZERO

2

) = 1. Combining Equation 1 and

CROSS

at the crossover frequency can be written as

f

CROSS

×

GG

CS

and C

⎞
⎟
⎟
⎠

COMP

×

VC

REF

⎞

OUTOUT

⎟

(5)

⎟
⎠

⎛
⎜
⎜

V

⎝

is

(6)

COMPCOMP

⎛

×π

2

⎜

=

)(

⎜

m

⎝

COMP

1

CR

×π

At the crossover frequency, Equation 4 can be shown as

2

ff

2

+

RfZ

)(

COMPCROSSCOMP

CROSS

×=

f

CROSS

ZERO

(7)

Combining Equation 5 and Equation 7 and solving for

gives

R

COMP

R

COMP

⎛

2

f

CROSS

CROSS

+

ff

ZERO

22

=

×π

⎜

×

⎜

m

⎝

f

×

CROSS

GG

CS

⎞

⎛

⎟

⎜

×

⎜

⎟

⎝

⎠

VC

×

⎞

OUTOUT

⎟

REF

⎟
⎠

V

Choose the crossover and zero frequencies as follows:

f

f

CROSS

f

ZERO

SW

=

(9)

12

ff

SWCROSS

==

(10)

484

Substituting Equation 2, Equation 9, and Equation 10 into
Equation 8 yields

×π

f

2

⎛
⎜

××=

97.0

RAR

DSONCSCOMP

⎜
⎝

G

CROSS

m

⎞
⎟

×

⎟
⎠

×

VC

REF

⎞

OUTOUT

⎟

(11)

⎟
⎠

⎛
⎜
⎜

V

⎝

where:

G

is the transconductance of the error amplifier, 500 µS.

m

A

is the current sense gain of 3 V/V, 6 V/V, 12 V/V, or 24 V/V.

CS

R

is on resistance of the low-side MOSFET.

DSON

V

= 0.6 V.

REF

And combining Equation 6 and Equation 10 yields

COMP

=

2

(12)

fRC×π

CROSSCOMP

Note that the previous simplified compensation equations for
R

COMP

and C

yield reasonable results in f

COMP

and phase

CROSS

margin assuming that the compensation ramp current is ideal.
Varying the ramp current or deviating the ramp current from
ideal can affect f

And lastly, set C

1

20

and phase margin.

CROSS

to

C2

1

2

10

(13)

CCC ×≤≤×

COMPCCOMP

(8)

Rev. A | Page 21 of 32

ADP1850 Data Sheet

V

≅

CONFIGURATION AND LOOP
(DUAL-PHASE OPERATION)

In dual-phase operation, the two outputs of the switching
regulators are shorted together and can source more than
50 A of output current depending on the selection of the
power components. Internal parameters in the ADP1850
are optimized and trimmed in the factory to minimize the
mismatch in output currents between the two channels. See
Figure 34 and Figure 47 for a configuration of a typical dual­phase application circuit. Note that FB1 shorts to FB2, SS1 to
SS2, and COMP1 to COMP2, where the outputs of the two
error amplifiers are shared. Furthermore, the controller needs
to be placed in forced PW
to VCCO or logic high.

The equations for calculating the loop compensation com
nents are identical to the single-phase operation, but the
combined value of G
gain and the effective f

RAMP1

ADP1850

EN1
EN2
VDL

VCCO
TRK1
TRK2
PGOOD1
PGOOD2

HI

LO

SYNC

FREQ

COMP1

COMP2

SS1
SS2

AGND

M operation by connecting SYNC

of the error amplifiers, t

m

are all doubled.

SW

R

RAMP1

VIN

DH1

BST1

SW1

ILIM1

FB1

DL1

PGND1

RAMP2

DH2

BST2

SW2

ILIM2

FB2

DL2

PGND2

Figure 34. Dual-Phase Circuit

COMPENSATION

he modulator

IN

M1

L1

M2

R

CSG1

R

RAMP2

R

CSG2

M3

M4

V

IN

L2

R1

R2

V

OUTx

po-

SWITCHING NOISE AND OVERSHOOT REDUCTION

In any high speed step-down regulator, high frequency noise
(generally in the range of 50 MHz to 100 MHz) and voltage
overshoot are always present at the gate, the switch node (SW),
and the drains of the external MOSFETs. The high frequency
noise and overshoot are caused by the parasitic capacitance,
C

, of the external MOSFET and the parasitic inductance of

GD

the gate trace and the packages of the MOSFETs. When the high
current is switched, electromagnetic interference (EMI) is

09440-002

generated, which can affect the operation of the surrounding
circuits. To reduce voltage ringing and noise, it is recommended
to add an RC snubber between SWx and PGNDx for high current
applications, as illustrated in Figure 35.

In most applications, R

is typically 2 Ω to 4 Ω, and C

SNUB

SNUB

typically 1.2 nF to 3 nF.

can be estimated by

R

SNUB

L

MOSFET

C

OSS

And C

≅

R 2

SNUB

can be estimated by

SNUB

CC

OSSSNUB

where:
L

is the total parasitic inductance of the high-side and

MOSFET

low-side MOSFETs, typically 3 nH, and is package dependent.

C

is the total output capacitance of the high-side and low-

OSS

side MOSFETs given in the MOSFET data sheet.

The size of the RC snubber components needs to be chosen
correctly to handle the power dissipation. The power dissipated
in R

is

SNUB

2

SNUB

IN

In most applications, a component size 0805 for R

fCVP ××=

SWSNUB

is sufficient.

SNUB

However, the use of an RC snubber reduces the overall efficiency,
generally by an amount in the range of 0.1% to 0.5%. The RC
snubber does not reduce the voltage overshoot. A resistor,
shown as R

in Figure 35, at the BSTx pin helps to reduce

RISE

overshoot and is generally between 2 Ω and 4 Ω. Adding a
resistor in series, typically between 2 Ω and 4 Ω, with the gate
driver also helps to reduce overshoot. If a gate resistor is added,
then R

is not needed.

RISE

VDL

ADP1850

(CHANNEL 1)

BST1

DH1

SW1

ILIM1

DL1

PGND1

V

R

R

RISE

ILIM1

IN

M1

L

V

OUTx

R

SNUB

C

M2

C

SNUB

OUT

09440-035

Figure 35. Application Circuit with a Snubber

Rev. A | Page 22 of 32

Data Sheet ADP1850

V

F

V

VOLTAGE TRACKING

The ADP1850 includes a tracking feature that tracks a master
voltage. This feature is especially important when the ADP1850
is providing separate power supply voltages to a single integrated
circuit, such as the core and I/O voltages of a DSP, FPGA, or
microcontroller. In these cases, improper sequencing can cause
damage to the load IC.

In all tracking configurations, the output can be set as low as 0.6 V
for a given operating condition. The soft start time setting of
the master voltage should be longer than the soft start of the
slave voltage. This forces the rise time of the master voltage to
be imposed on the slave voltage. If the soft start setting of the
slave voltage is longer, the slave comes up more slowly, and the
tracking relationship is not seen at the output.

Two tracking configurations are possible with the ADP1850:
coincident and ratiometric trackings.

Coincident Tracking

The most common application is coincident tracking, used in
core vs. I/O voltage sequencing and similar applications.
Coincident tracking forces the slave output voltage’s ramp rate
to be the same as the master’s until the slave output reaches its
regulation. Connect the slave TRKx input to a resistor divider
from the master voltage that is the same as the divider used on
the slave FBx pin. This forces the slave voltage to be the same as
the master voltage. For coincident tracking, use R
and R

= R

TRKB

, as shown in Figure 37.

BOT

MA STER VO LTAGE

SLA VE VOLTA GE

VOLTAGE (V)

TIME

Figure 36. Coincident Tracking

V

OUT1_MASTER

45.3kΩ

10kΩ

C

SS2

20nF

1.8V

3.3

C

100n

EN

VCCO

SS1

ADP1850

SS1

FB2

R

BOT

10kΩ

EN2EN1

FB1TRK1

TRK2

SS2

R

TOP

20kΩ

V

OUT2_SLAVE

Figure 37. Example of a Coincident Tracking Circuit

R
20kΩ

1.1V

R
10kΩ

The ratio of the slave output voltage to the master voltage is a
function of the two dividers.

TRKT

TRKB

= R

TOP

TRKT

09440-036

09440-037

⎛
⎜

1

V

SLAVEOUT

_

V

MASTEROUT

_

⎜
⎝

=

⎛
⎜

+

1

⎜
⎝

As the master voltage rises, the slave voltage rises identically.
Eventually, the slave voltage reaches its regulation voltage,
where the internal reference takes over the regulation while the
TRKx input continues to increase and thus removes itself from
influencing the output voltage.

To ensure that the output voltage accuracy is not compromised
by the TRKx pin being too close in voltage to the reference voltage
(V

, typically 0.6 V), make sure that the final value of the TRKx

FB

voltage of the slave channel is at least 30 mV above V

Ratiometric Tracking

Ratiometric tracking limits the output voltage to a fraction of
the master voltage, as illustrated in Figure 38 and Figure 39. The
final TRKx voltage of the slave channel should be set to at least
30 mV below the FB voltage of the master channel. When the
TRKx voltage of the slave channel drops to a level that’s below
the minimum on-time condition, the slave channel operates in
pulse skip mode while keeping the output regulated and tracked
to the master channel. Also, when TRKx or FBx drops below
the PGOOD undervoltage threshold, the PGOOD signal gets
tripped and becomes active low.

VOLTAGE (V)

Figure 38. Ratiometric Tracking

EN

ADP1850

VCCO

SS1

R

BOT

10kΩ

SS1

0.55V

C
37nF

Figure 39. Example of a Ratiometric Tracking Circuit

+

FB2

R

R

R

TRKT

R

TRKB

EN2EN1

TRK2

R

22.6kΩ

TOP

BOT

FB1TRK1

SS2

TOP

⎞
⎟
⎟
⎠

⎞
⎟
⎟
⎠

MA STER VOLT AGE

SLAVE VOLTAGE

TIME

3.3

V

OUT1_MASTER

45.3kΩ

0.6V

10kΩ

C

SS2

20nF

1.8V

V

OUT2_SLAVE

R

TRKT

49.9kΩ

0.55V
R

TRKB

10kΩ

.

FB

09440-038

09440-039

Rev. A | Page 23 of 32

ADP1850 Data Sheet

V

V

V

V

F

Another ratiometric tracking configuration is having the slave
channel rise more quickly than the master channel, as shown in
Figure 40 and Figure 41. The tracking circuits in Figure 39 and
Figure 41 are virtually identical with the exception that R
R

as shown in Figure 41.

TRKT

MASTER

VOLTAGE (V)

Figure 40. Ratiometric Tracking (Slave Channel Has a Faster Ramp Rate)

EN

EN2EN1

ADP1850

C

100n

VCCO

SS1

R
10kΩ

BOT

SS1

FB2

FB1TRK1

TRK2

SS2

R

TOP

20kΩ

Figure 41. Example of a Ratiometric Tracking Circuit (Slave Channel Has a

Faster Ramp Rate)

OLTAGE

SLAVE VOL TAGE

TIME

V

OUT1_MASTER

45.3kΩ

10kΩ

C

SS2

20nF

1.8V

V

OUT2_SLAVE

3.3

R

TRKT

5kΩ

2.2V

R

TRKB

10kΩ

09440-040

09440-041

TRKB

>

INDEPDENDENT POWER STAGE INPUT VOLTAGE

In addition to the single power supply configuration, the power
stage input voltage of the dc-to-dc converter can come from a
different voltage supply, as illustrated in Figure 42. The range of
the power stage input voltage (V
the bias input voltage (V

) is 5 V, V

IN

high as 20 V. The user needs to make sure that the minimum
or the maximum duty cycle is not violated in this operating
condition. Furthermore, note that R

VIN = 2.7V TO 20V

VIN

ADP1850

Figure 42. Independent Power Stage Input Voltage (Simplified Schematic)

R

RAMP1

DH1

SW1

FB1

DL1

PGND1

RAMP2

DH2

SW2

FB2

DL2

PGND2

RAMP1

) is 1 V to 20 V. For instance,

PIN

can be as low as 1 V or as

PIN

is connected to V

RAMP

= 1V TO 20

PIN

V

OUT1

R

RAMP2

V

= 1V TO 20V

PIN

V

OUT2

.

PIN

09440-042

Rev. A | Page 24 of 32

Data Sheet ADP1850

PCB LAYOUT GUIDELINES

In any switching converter, there are some circuit paths that
carry high dI/dt, which can create spikes and noise. Some
circuit paths are sensitive to noise, while other circuits carry
high dc current and can produce significant IR voltage drops.
The key to proper PCB layout of a switching converter is to
identify these critical paths and arrange the components and
the copper area accordingly. When designing PCB layouts,
be sure to keep high current loops small. In addition, keep
compensation and feedback components away from the switch
nodes and their associated components.

The following is a list of recommended layout practices for the
synchronous buck controller, arranged by decreasing order of
importance.

MOSFETS, INPUT BULK CAPACITOR, AND BYPASS CAPACITOR

The current waveform in the top and bottom FETs is a pulse
with very high dI/dt; therefore, the path to, through, and from
each individual FET should be as short as possible, and the two
paths should be commoned as much as possible. In designs that
use a pair of D-Pak, or a pair of SO-8 FETs, on one side of the
PCB, it is best to counter-rotate the two so that the switch node
is on one side of the pair. This allows the high-side FET’s drain
to be bypassed to the low-side FET’s source with a suitable
ceramic bypass capacitor placed as close as possible to the FETs.
Close proximity of the bypass capacitor minimizes the
inductance around the loop through the FETs and capacitor.
The recommended bypass ceramic capacitor values range from
1 µF to 22 µF, depending on the output current. The ceramic
bypass capacitor is usually connected to a larger value bulk filter
capacitor and should be grounded to the PGNDx plane.

HIGH CURRENT AND CURRENT SENSE PATHS

Part of the ADP1850 architecture is sensing the current across
the low-side FET between the SWx and PGNDx pins. The
switching GND currents of one channel creates noise and
can be picked up by the other channel. It is essential to have
Kelvin sensing connection between SWx and the drain of the
respective low-side MOSFET, and between PGNDx and the
source of the respective low-side MOSFET, as illustrated in
Figure 43. Place these Kelvin connections very close to the
FETs to achieve accurate current sensing. Figure 43 illustrates
the proper connection technique for the SW1/SW2, PGND1/
PGND2, and PGND plane.

V

IN

ADP1850

23

DH1

24

SW1

21

DL1

22

PGND1

19

PGND2

20

DL2

SW2

17

18

DH2

Figure 43. Grounding Technique for Two Channels

M1

M2

KELVIN

CONNECTIONS

M4

M3

L1

DECOUPLE1

C

DECOUPLE2

L2

C

V

IN

COUT1CIN1

COUT2CIN2

V

OUT1

AGND

PLANE

PGND PLANE

V

OUT2

09440-043

SIGNAL PATHS

The negative terminals of VIN bypass, compensation
components, soft start capacitor, and the bottom end of the
output feedback divider resistors should be tied to a small
AGND plane. These connections should attach from their
respective pins to the AGND plane and should be as short as
possible. No high current or high dI/dt signals should be
connected to this AGND plane. The AGND area should be
connected through one wide trace to the negative terminal of
the output filter capacitors.

PGND PLANE

The PGNDx pin handles a high dI/dt gate drive current returning
from the source of the low side MOSFET. The voltage at this pin
also establishes the 0 V reference for the overcurrent limit
protection function and the ILIMx pin. A PGND plane should
connect the PGNDx pin and the VDL bypass capacitor, 1 µF,
through a wide and direct path to the source of the low side
MOSFET. The placement of CIN is critical for controlling
ground bounce. The negative terminal of CIN must be placed
very close to the source of the low-side MOSFET.

FEEDBACK AND CURRENT-LIMIT SENSE PATHS

Avoid long traces or large copper areas at the FBx and ILIMx
pins, which are low-level signal inputs that are sensitive to
capacitive and inductive noise pickup. It is best to position
any series resistors and capacitors as close as possible to these
pins. Avoid running these traces close and/or parallel to high
dI/dt traces.

Rev. A | Page 25 of 32

ADP1850 Data Sheet

SWITCH NODE

The switch node is the noisiest place in the switcher circuit with
large ac and dc voltages and currents. This node should be wide
to minimize resistive voltage drop. To minimize capacitively
coupled noise, the total area should be small. Place the FETs
and inductor close together on a small copper plane to minimize
series resistance and keep the copper area small.

GATE DRIVER PATHS

Gate drive traces (DH and DL) handle high dI/dt and tend to
produce noise and ringing. They should be as short and direct
as possible. If vias are needed, it is best to use two relatively
large ones in parallel to reduce the peak current density and the
current in each via. If the overall PCB layout is less than

optimal, slowing down the gate drive slightly can be helpful to
reduce noise and ringing. It is occasionally helpful to place
small value resistors, such as between 2  and 4 , on the DHx
and DLx pins. These can be populated with 0  resistors if
resistance is not needed. Note that the added gate resistance
increases the switching rise and fall times, as well as increasing
switching power loss in the MOSFET.

OUTPUT CAPACITORS

The negative terminal of the output filter capacitors should be
tied close to the source of the low side FET. Doing this helps to
minimize voltage differences between AGND and PGNDx.

Rev. A | Page 26 of 32

Data Sheet ADP1850

TYPICAL OPERATING CIRCUITS

330pF

42.2kΩ

47pF

V

= 10V TO 18V

IN

1µF

45.3kΩ

10kΩ

1µF

2Ω

1µF

2Ω

560pF

47pF

23.2kΩ

1

2

3

4

5

6

7

8

187kΩ

VCCO

32 31 30 29 28 27 26 25

1

1

FB

TRK

EN1

SYNC

VIN

VCCO

VDL

AGND

FREQ

EN2

TRK2

9 10 11 12 13 14 15 16

VCCO

FB2

RAMP1

COMP1

ADP1850

COMP2

187kΩ

TO

VIN

RAMP2

100nF

SS1

SS2

100nF

22kΩ

M1

CIN

1

L1

COUT

11

M2

V

IN

M3

CIN

2

L2

M4

COUT

COUT

21

COUT

22

V

OUT1

3.3V
14A

12

V

OUT2

1.8V
14A

22pF

0.1µF

BST1

ILIM1

PGOOD1

PGOOD2

ILIM2

22pF

SW1

DH1

PGND1

DL1

DL2

PGND2

DH2

SW2

BST2

0.1µF

CIN

2.1kΩ

24

23

22

21

20

19

18

17

22kΩ

2.1kΩ

20kΩ10kΩ

f

= 600kHz

SW

CIN: 150µF/ 20V, OS-CON, 20SEP 150M, SANYO
L1, L2: 1. 2µH, WURTH ELEKTRO NIK, 744325120
M1, M3: BSC080N03L S
M2, M4: BSC030N03L S

CIN1, CIN2: 10µF/X7R/25V/1210 × 2, GRM32DR71E106KA12, MURATA
COUT

, COUT21: 330µF/6. 3V/POS CAP × 2, 6TPF330M9L, SANYO

11

COUT

, COUT22: 22µF/X5R/ 0805/6.3V × 3, GRM21BR60J226ME39, MURATA

12

09440-044

Figure 44. Typical 14 A Operating Circuit

Rev. A | Page 27 of 32

ADP1850 Data Sheet

73.2kΩ

10kΩ

2Ω

1µF

1µF

1µF

2Ω

84.5kΩ

1

2

3

4

5

6

7

8

560pF

28kΩ

33pF

150kΩ

VCCO

32 31 30 29 28 27 26 25

1

1

FB

TRK

EN1

SYNC

VIN

VCCO

VDL

AGND

FREQ

EN2

TRK2

9 10 11 12 13 14 15 16

FB2

RAMP1

COMP1

ADP1850

COMP2

RAMP2

100nF

SS1

SS2

= 10V TO 20V

V

IN

M1A

CIN

1

2.8kΩ

0.1µF

ILIM1

BST1

PGOOD1

ILIM2

BST2

PGOOD2

SW1

DH1

PGND1

DL1

DL2

PGND2

DH2

SW2

0.1µF

24

23

22

21

20

19

18

17

22kΩ

2.8kΩ

L1

M1B

V

IN

M2A

CIN

2

L2

M2B

COUT

COUT

2

V

OUT1

5V
5A

1

V

OUT2

1.8V
5A

150kΩ

VCCO

1.5nF

10kΩ

100pF

f

= 750kHz, PULS E SKIP MO DE

SW

L1: 2µH, W URTH ELEKTRONIK, 744310200
L2: 1.15µH, WURTH ELEKTRONIK, 744310115

20kΩ10kΩ

100nF

TO

VIN

CIN1, CIN2: 10µF/X5R/ 16V/1206 × 2, G RM31CR61C106KA88, MURATA
M1, M2: SI 944DY OR BSON03MD
COUT

, COUT2: 22µF/X R5/1210/6.3V × 3, GRM32DR60J226KA01, MURATA

1

22kΩ

09440-045

Figure 45. Typical Low Current Operating Circuit

Rev. A | Page 28 of 32

Data Sheet ADP1850

F

7.5kΩ

10kΩ

5Ω

1µF

1µF

1µF

78.7kΩ

1

2

3

4

5

6

7

8

1.8n

5.34kΩ

33pF

VCCO

32 31 30 29 28 27 26 25

1

1

FB

TRK

EN1

SYNC

VIN

VCCO

VDL

AGND

FREQ

EN2

TRK2

9 10 11 12 13 14 15 16

FB2

RAMP1

COMP1

ADP1850

COMP2

20kΩ

RAMP2

100nF

SS1

SS2

= 3V TO 5.5V

V

IN

M1

CIN

1

4.99kΩ

0.1µF

ILIM1

BST1

PGOOD1

PGOOD2

ILIM2

BST2

SW1

DH1

PGND1

DL1

DL2

PGND2

DH2

SW2

0.1µF

24

23

22

21

20

19

18

17

47kΩ

4.99kΩ

L1

M2

V

IN

M3

CIN

2

L2

M4

COUT

COUT

2

V

OUT1

1.05V

1.8A

1

V

OUT2

1.8V

1.8A

20kΩ

100nF

< 5.5 V

IN

47kΩ

TO

VIN

CIN1, CIN2: 4.7µF/ X5R/16V/0805 × 2, GRM219R60J475KE 19, MURATA
COUT

, COUT2: 22µF/X R5/0805/6.3V , GRM21BR60J226ME39, MURATA

1

09440-046

1nF

8.66kΩ

33pF

f

= 800kHz, PULS E SKIP MO DE

SW

L1, L2: 1µH, T OKO D62LCB1R0M
M1, M2, M3, M4: SI2302ADS, SOT23

VCCO

20kΩ10kΩ

Figure 46. Typical Low Current Application with V

Rev. A | Page 29 of 32

ADP1850 Data Sheet

F

3.3n

180pF

8.87kΩ

VIN = 10V TO 14V

CIN

CIN

12

L1

CIN

22

COUT11COUT

12

V

OUT1

1.09V
50A

L2

COUT21COUT

22

1µF

1µF

8.3kΩ

10kΩ

2Ω

1µF

CIN

1.74kΩ

22kΩ

CIN

1.74kΩ

22kΩ

11

21

SS1

SS2

22pF

0.1µF

ILIM1

BST1

PGOOD1

BST2

ILIM2

PGOOD2

SW1

DH1

PGND1

DL1

DL2

PGND2

DH2

SW2

24

23

22

21

20

19

18

17

0.1µF

22pF

137kΩ

COMP1

ADP1850

COMP2

11

12

137kΩ

TO

VIN

TO

100nF

RAMP1

RAMP2

13 14 15 16

TO

SS1

TO

VCCO

32 31 30 29 28 27 26 25

FB1

TRK1

1

EN1

2

SYNC

3

VIN

4

VCCO

2Ω

5

VDL

6

AGND

7

FREQ

8

EN2

K2
TR

FB2

9

10

TO

VCCO

TO

FB1

COMP1

M1 M2

M3 M4

VIN

M5 M6

M7 M8

f

= 300kHz

SW

CIN = 180µF/16V × 4, 16SEP180M, OS-CON, SANYO
M1, M2, M5, M6: BSC080N03IS
M3, M4, M7, M8: BSC030N03LS
L1, L2: SER1408-301, 300nH, COIL CRAFT; O R 744355147, 0.4µH, WURTH ELECTRO NIK

Figure 47. Dual-Phase Circuit, 50 A Output

CIN11, CIN12, CIN21, CIN22: 10µF/X7R/25V/1210, MURATA

, COUT21, 2SEPC560MZ × 3, 560µF, OSCON, SANYO

COUT

11

, COUT22: GRM31CR60J476ME19 × 2, 47µV/ 1206/6.3V, MURAT A

COUT

12

09440-047

Rev. A | Page 30 of 32

Data Sheet ADP1850

C

S

OUTLINE DIMENSIONS

INDI

EATING

PLANE

PIN 1

ATO R

0.80

0.75

0.70

5.10

5.00 SQ

4.90

0.05 MAX

0.02 NOM

0.20 REF

0.50

BSC

0.50

0.40

0.30

COPLANARITY

0.08

0.30

0.25

0.18

25

24

17

32

1

EXPOSED

PAD

8

BOTTOM VIEWTOP VIEW

3.50 REF

916

FOR PROPER CONNECTION O F
THE EXPOSE D PAD, REFER TO
THE PIN CONF IGURATIO N AND
FUNCTION DES CRIPTIONS
SECTION OF THIS DATA SHEET.

N

P

I

D

I

N

I

3.65

3.50 SQ

3.45

0.25 MIN

1

R

O

T

C

A

COMPLIANT TO JEDEC ST ANDARDS MO-220-W HHD.

04-02-2012-A

Figure 48. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

5 mm × 5 mm Body, Very Very Thin Quad

(CP-32-11)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

ADP1850ACPZ-R7 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-11
ADP1850SP-EVALZ Evaluation Board in Single-Phase Mode with 14 A Output
ADP1850DP-EVALZ Evaluation Board in Dual-Phase Mode with 50 A Output

1

Z = RoHS Compliant Part.

Rev. A | Page 31 of 32

ADP1850 Data Sheet

NOTES

©2010-2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09440-0-4/12(A)

Rev. A | Page 32 of 32