Datasheet ADP1752 Datasheet (ANALOG DEVICES)

0.8 A, Low VIN, Low Dropout

V

V

V

V

V

V

V

FEATURES

Maximum output current: 0.8 A
Input voltage range: 1.6 V to 3.6 V
Low shutdown current: <2 µA
Very low dropout voltage: 70 mV @ 0.8 A load
Initial accuracy: ±1%
Accuracy over line, load, and temperature: ±2%
7 fixed output voltage options with soft start

0.75 V to 2.5 V (ADP1752)

Adjustable output voltage option with soft start

0.75 V to 3.0 V (ADP1753)

High PSRR

65 dB @ 1 kHz
65 dB @ 10 kHz

54 dB @ 100 kHz
23 V rms at 0.75 V output
Stable with small 4.7 µF ceramic output capacitor
Excellent load and line transient response
Current-limit and thermal overload protection
Power-good indicator
Logic-controlled enable
Reverse current protection

APPLICATIONS

Server computers
Memory components
Telecommunications equipment
Network equipment
DSP/FPGA/microprocessor supplies
Instrumentation equipment/data acquisition systems

Linear Regulator

ADP1752/ADP1753

TYPICAL APPLICATION CIRCUITS

= 1.8

IN

4.7µF

100kΩ

PG

1

2

3

4

VIN

VIN

VIN

EN

16

VIN

VIN

ADP1752

TOP VIEW

(Not to Scale)

GND

PG

5

15

6

Figure 1. ADP1752 with Fixed Output Voltage, 1.5 V

= 1.8

IN

4.7µF

100kΩ

PG

1

2

3

4

VIN

VIN

VIN

EN

16

VIN

ADP1753

TOP VIEW

(Not to Scale)

GND

PG

5

15

VIN

6

Figure 2. ADP1753 with Adjustable Output Voltage, 0.75 V to 3.0 V

VOUT

14

VOUT

SS

7

14

SS

7

10nF

10nF

13

VOUT

VOUT

VOUT

VOUT

ADJ

NC

8

13

VOUT

VOUT

VOUT

VOUT

SENSE
NC

8

12

11

10

9

= 0.5V(1 + R1/R2)

OUT

12

11

10

9

R1

R2

OUT

4.7µF

= 1.5

4.7µF

07718-001

07718-002

GENERAL DESCRIPTION

The ADP1752/ADP1753 are low dropout (LDO) CMOS linear
regulators that operate from 1.6 V to 3.6 V and provide up to
800 mA of output current. These low V

IN/VOUT

LDOs are ideal

for regulation of nanometer FPGA geometries operating from

2.5 V down to 1.8 V I/O rails, and for powering core voltages
down to 0.75 V. Using an advanced proprietary architecture,
they provide high power supply rejection ratio (PSRR) and low
noise, and achieve excellent line and load transient response
with only a small 4.7 µF ceramic output capacitor.

The ADP1752 is available in seven fixed output voltage options.
The ADP1753 is the adjustable version, which allows output

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

voltages that range from 0.75 V to 3.0 V via an external divider.
The ADP1752/ADP1753 allow an external soft start capacitor
to be connected to program the startup. A digital power-good
output allows power system monitors to check the health of the
output voltage.

The ADP1752/ADP1753 are available in a 16-lead, 4 mm × 4 mm
LFCSP, making them not only very compact solutions, but also
providing excellent thermal performance for applications that
require up to 800 mA of output current in a small, low profile
footprint.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2008–2010 Analog Devices, Inc. All rights reserved.

ADP1752/ADP1753

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Typical Application Circuits ............................................................ 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Input and Output Capacitor, Recommended Specifications .. 4

Absolute Maximum Ratings ............................................................ 5

Thermal Data ................................................................................ 5

Thermal Resistance ...................................................................... 5

ESD Caution .................................................................................. 5

Pin Configurations and Function Descriptions ........................... 6

Typical Performance Characteristics ............................................. 7

Theory of Operation ...................................................................... 11

Soft Start Function (ADP1752/ADP1753) ............................. 11

Adjustable Output Voltage (ADP1753) ................................... 12

Enable Feature ............................................................................ 12

Power-Good Feature .................................................................. 12

Reverse Current Protection Feature ........................................ 13

Applications Information .............................................................. 14

Capacitor Selection .................................................................... 14

Undervoltage Lockout ............................................................... 15

Current-Limit and Thermal Overload Protection ................. 15

Thermal Considerations ............................................................ 15

PCB Layout Considerations ...................................................... 18

Outline Dimensions ....................................................................... 19

Ordering Guide .......................................................................... 19

REVISION HISTORY

2/10—Rev. A to Rev. B

Changes to Table 4 ............................................................................ 5

Changes to Ordering Guide .......................................................... 19

4/09—Rev. 0 to Rev. A

Changes to Adjustable Output Voltage Accuracy (ADP1753)

Parameter, Table 1 ............................................................................. 3

Changes to Table 3 ............................................................................ 5

10/08—Revision 0: Initial Version

Rev. B | Page 2 of 20

ADP1752/ADP1753

SPECIFICATIONS

VIN = (V

Table 1.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

INPUT VOLTAGE RANGE VIN T
OPERATING SUPPLY CURRENT1 I
I
I
I
I
SHUTDOWN CURRENT I

OUTPUT VOLTAGE ACCURACY

Fixed Output Voltage Accuracy

Adjustable Output Voltage Accuracy

LINE REGULATION V
LOAD REGULATION3 V
DROPOUT VOLTAGE4 V
I
I
I
START-UP TIME5 t
C
CURRENT-LIMIT THRESHOLD6 I
THERMAL SHUTDOWN

Thermal Shutdown Threshold TSSD T

Thermal Shutdown Hysteresis TS

PG OUTPUT LOGIC LEVEL

PG Output Logic High PG

PG Output Logic Low PG

PG Output Delay from EN Transition

PG OUTPUT THRESHOLD

Output Voltage Falling PG

Output Voltage Rising PG

EN INPUT

EN Input Logic High VIH 1.6 V ≤ VIN ≤ 3.6 V 1.2 V

EN Input Logic Low VIL 1.6 V ≤ VIN ≤ 3.6 V 0.4 V

EN Input Leakage Current V

UNDERVOLTAGE LOCKOUT UVLO

Input Voltage Rising UVLO

Input Voltage Falling UVLO

Hysteresis UVLO

SOFT START CURRENT ISS 1.6 V ≤ VIN ≤ 3.6 V 0.6 0.9 1.2 µA
ADJ INPUT BIAS CURRENT (ADP1753) ADJ
SENSE INPUT BIAS CURRENT SNS

+ 0.4 V) or 1.6 V (whichever is greater), I

OUT

(ADP1752)

2

(ADP1753)

Low to High

= 10 mA, CIN = C

OUT

= −40°C to +125°C 1.6 3.6 V

J

I

GND

EN = GND, V

GND-SD

= 500 A 90

OUT

= 100 mA 400

OUT

= 100 mA, TJ = −40°C to +125°C

OUT

= 0.8 A 0.9

OUT

= 0.8 A, TJ = −40°C to +125°C

OUT

= 1.6 V

IN

EN = GND, VIN = 1.6 V, TJ = −40°C to +85°C
EN = GND, VIN = 3.6 V, TJ = −40°C to +85°C

I

V

OUT

I
10 mA < I

I

V

ADJ

I
10 mA < I

/VIN VIN = (V

OUT

/I

OUT

OUT

I

DROPOUT

CSS = 0 nF, I

START-UP

1 1.4 5 A

LIMIT

15

SD-HYS

1.6 V ≤ VIN ≤ 3.6 V, IOH < 1 µA 1.0 V

HIGH

1.6 V ≤ VIN ≤ 3.6 V, IOL < 2 mA 0.4 V

LOW

1.6 V ≤ V

1.6 V ≤ VIN ≤ 3.6 V −10 %

FAL L

1.6 V ≤ VIN ≤ 3.6 V −6.5 %

RISE

EN = VIN or GND 0.1 1 µA

I-LEAKAGE

TJ = −40°C to +125°C

RISE

TJ = −40°C to +125°C 1.25

FAL L

TJ = 25°C

HYS

1.6 V ≤ VIN ≤ 3.6 V, TJ = −40°C to +125°C 10 150 nA

I-BIAS

1.6 V ≤ VIN ≤ 3.6 V 10 µA

I-BIAS

= 10 mA −1 +1 %

OUT

= 10 mA to 0.8 A −1.5 +1.5 %

OUT

< 0.8 A, TJ = −40°C to +125°C −2 +2 %

OUT

= 10 mA 0.495 0.5 0.505 V

OUT

= 10 mA to 0.8 A 0.492 0.508 V

OUT

< 0.8 A, TJ = −40°C to +125°C 0.490 0.510 V

OUT

+ 0.4 V) to 3.6 V, TJ = −40°C to +125°C −0.3 +0.3 %/V

OUT

I

= 10 mA to 0.8 A, TJ = −40°C to +125°C 0.8 %/A

OUT

= 100 mA, V

OUT

= 100 mA, V

OUT

= 0.8 A, V

OUT

= 0.8 A, V

OUT

= 10 nF, I

SS

rising 150

J

OUT

OUT

= 10 mA 200 µs

OUT

OUT

≤ 3.6 V, CSS = 10 nF 5.5 ms

IN

= 4.7 µF, TA = 25°C, unless otherwise noted.

OUT

800 µA

1.2 mA

≥ 1.8 V 10 mV

OUT

≥ 1.8 V, TJ = −40°C to +125°C 16 mV

OUT

2 6 µA

30 µA
100 µA

µA
µA

mA

≥ 1.8 V 70 mV
≥ 1.8 V, TJ = −40°C to +125°C 140 mV

= 10 mA 5.2 ms

°C
°C

1.58 V

100

V
mV

Rev. B | Page 3 of 20

ADP1752/ADP1753

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

OUTPUT NOISE OUT
10 Hz to 100 kHz, V
POWER SUPPLY REJECTION RATIO PSRR VIN = V

1

Minimum output load current is 500 A.

2

Accuracy when VOUT is connected directly to ADJ. When VOUT voltage is set by external feedback resistors, absolute accuracy in adjust mode depends on the

tolerances of resistors used.

3

Based on an end-point calculation using 10 mA and 0.8 A loads. See for typical load regulation performance. Figure 6

4

Dropout voltage is defined as the input to output voltage differential when the input voltage is set to the nominal output voltage. This applies only to output voltages

above 1.6 V.

5

Start-up time is defined as the time between the rising edge of EN to V

6

Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 1.0 V

output voltage is defined as the current that causes the output voltage to drop to 90% of 1.0 V, or 0.9 V.

INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS

Table 2.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

MINIMUM INPUT AND OUTPUT CAPACITANCE1 C
CAPACITOR ESR R

1

The minimum input and output capacitance should be greater than 3.3 µF over the full range of operating conditions. The full range of operating conditions in the

application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended;
Y5V and Z5U capacitors are not recommended for use with this LDO.

10 Hz to 100 kHz, V

NOISE

+ 1 V, I

OUT

1 kHz, V

OUT

1 kHz, V

OUT

10 kHz, V
10 kHz, V

OUT

OUT

100 kHz, V
100 kHz, V

being at 95% of its nominal value.

OUT

TA = −40°C to +125°C 3.3 µF

MIN

T

ESR

= 0.75 V 23 µV rms

OUT

= 2.5 V 65 µV rms

OUT

= 10 mA

OUT

= 0.75 V
= 2.5 V

= 0.75 V
= 2.5 V

= 0.75 V

OUT

= 2.5 V

OUT

= −40°C to +125°C 0.001 0.1 Ω

A

65
56
65
56
54
51

dB
dB
dB
dB
dB
dB

Rev. B | Page 4 of 20

ADP1752/ADP1753

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

VIN to GND −0.3 V to +3.6 V
VOUT to GND −0.3 V to +3.6 V
EN to GND −0.3 V to +3.6 V
SS to GND −0.3 V to +3.6 V
PG to GND −0.3 V to +3.6 V
SENSE/ADJ to GND −0.3 V to +3.6 V
Storage Temperature Range −65°C to +150°C
Operating Junction Temperature Range −40°C to +125°C
Soldering Conditions JEDEC J-STD-020

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL DATA

Absolute maximum ratings apply individually only, not in
combination. The ADP1752/ADP1753 may be damaged if the
junction temperature limits are exceeded. Monitoring ambient
temperature does not guarantee that T
temperature limits. In applications with high power dissipation
and poor thermal resistance, the maximum ambient tempera­ture may need to be derated. In applications with moderate
power dissipation and low PCB thermal resistance, the maximum
ambient temperature can exceed the maximum limit as long as
the junction temperature is within specification limits. The
junction temperature (T
ambient temperature (T
(P

), and the junction-to-ambient thermal resistance of the

D

package (θ

). TJ is calculated using the following formula:

JA

= TA + (PD × θJA).

T

J

) of the device is dependent on the

J

), the power dissipation of the device

A

is within the specified

J

Junction-to-ambient thermal resistance (θ
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on
the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θ
on PCB material, layout, and environmental conditions. The
specified values of θ
board. Refer to JEDEC JESD51-7 for detailed information about
board construction. For more information, see the AN-772
Application Note, A Design and Manufacturing Guide for the
Lead Frame Chip Scale Package (LFCSP) at www.analog.com.

Ψ

is the junction-to-board thermal characterization parameter

JB

with units of °C/W. Ψ
calculation using a 4-layer board. The JESD51-12 document,

Guidelines for Reporting and Using Electronic Package Thermal
Information, states that thermal characterization parameters are

not the same as thermal resistances. Ψ
power flowing through multiple thermal paths rather than
through a single path as in thermal resistance, θ

thermal paths include convection from the top of the package

Ψ

JB

as well as radiation from the package, factors that make Ψ
useful in real-world applications. Maximum junction temperature
(T

) is calculated from the board temperature (TB) and the power

J

dissipation (P

= TB + (PD × ΨJB)

T

J

Refer to the JEDEC JESD51-8 and JESD51-12 documents for more
detailed information about Ψ

THERMAL RESISTANCE

θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.

Table 4. Thermal Resistance

Package Type θJA ΨJB Unit

16-Lead LFCSP with Exposed Pad (CP-16-4) 42 25.5 °C/W

are based on a 4-layer, 4 in × 3 in circuit

JA

of the package is based on modeling and

JB

) using the following formula:

D

.

JB

) of the package is

JA

may vary, depending

JA

measures the component

JB

. Therefore,

JB

more

JB

ESD CAUTION

Rev. B | Page 5 of 20

ADP1752/ADP1753

T

T

2

T

T

2

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

VOU

VIN

VIN

VOU
14

13

15

16

PIN 1
INDICATOR

1VIN
2VIN

ADP1752

3VIN

TOP VIEW

(Not to S cale)

4EN

5

6

PG

NOTES

1. NC = NO CONNECT .
. THE EXPOSED PAD ON THE BO TTOM OF THE LFCS P E NHANCES

THERMAL PERF ORMANCE AND IS ELE CTRICALLY CONNECTED TO G ND
INSIDE THE PACKAGE. IT IS RECOMMENDED THAT THE EXP OSED PAD
BE CONNECTED TO THE GROUND PLANE ON THE BO ARD.

GND

7
SS

8
C

N

12 VOUT
11 VOUT
10 VOUT
9SENSE

1VIN
2VIN

ADP1753

3VIN

TOP VIEW

(Not to S cale)

4EN

NOTES

1. NC = NO CONNECT .
. THE EXPOSED PAD ON THE BO TTOM OF THE LFCS P E NHANCES

THERMAL PERF ORMANCE AND IS ELE CTRICALLY CONNECTED TO G ND
INSIDE THE PACKAGE. IT IS RECOMMENDED THAT THE EXP OSED PAD

07718-003

BE CONNECTED TO THE GROUND PLANE ON THE BO ARD.

VIN

VIN

15

16

PIN 1
INDICATOR

5

6

PG

GND

VOU

VOU
14

13

12 VOUT
11 VOUT
10 VOUT
9ADJ

8

7

C

SS

N

Figure 3. ADP1752 Pin Configuration Figure 4. ADP1753 Pin Configuration

Table 5. Pin Function Descriptions

ADP1752
Pin No.

1, 2, 3, 15, 16 1, 2, 3, 15, 16 VIN

ADP1753
Pin No. Mnemonic Description

Regulator Input Supply. Bypass VIN to GND with a 4.7 µF or greater capacitor. Note that all
five VIN pins must be connected to the source.

4 4 EN

Enable Input. Drive EN high to turn on the regulator; drive it low to turn off the regulator. For
automatic startup, connect EN to VIN.

5 5 PG

Power Good. This open-drain output requires an external pull-up resistor to VIN. If the part is
in shutdown mode, current-limit mode, thermal shutdown, or if it falls below 90% of the

nominal output voltage, PG immediately transitions low.
6 6 GND Ground.
7 7 SS Soft Start. A capacitor connected to this pin determines the soft start time.
8 8 NC Not Connected. No internal connection.
9 N/A SENSE

Sense. This pin measures the actual output voltage at the load and feeds it to the error

amplifier. Connect SENSE as close as possible to the load to minimize the effect of IR drop

between the regulator output and the load.
N/A 9 ADJ Adjust. A resistor divider from VOUT to ADJ sets the output voltage.
10, 11, 12,

13, 14

10, 11, 12,
13, 14

17 (EPAD) 17 (EPAD)

VOUT

Exposed
paddle
(EPAD)

Regulated Output Voltage. Bypass VOUT to GND with a 4.7 µF or greater capacitor. Note that

all five VOUT pins must be connected to the load.

The exposed pad on the bottom of the LFCSP package enhances thermal performance and

is electrically connected to GND inside the package. It is recommended that the exposed

pad be connected to the ground plane on the board.

07718-004

Rev. B | Page 6 of 20

ADP1752/ADP1753

TYPICAL PERFORMANCE CHARACTERISTICS

VIN = 1.9 V, V

1.520

1.515

1.510

1.505

1.500

1.495

OUTPUT VOLTAGE (V)

1.490

1.485

1.480

= 1.5 V, I

OUT

LOAD = 400mA

–40 –5 25 85 125

= 10 mA, CIN = 4.7 µF, C

OUT

LOAD = 10mA

LOAD = 100mA

LOAD = 800mA

JUNCTION TEM P ERATURE (°C)

Figure 5. Output Voltage vs. Junction Temperature

= 4.7 µF, TA = 25°C, unless otherwise noted.

OUT

1000

900

800

700

600

500

400

300

GROUND CURRENT (µA)

200

100

0

–40 –5 25 85 125

07718-105

Figure 8. Ground Current vs. Junction Temperature

LOAD = 800mA

LOAD = 400mA

LOAD = 100mA

LOAD = 10mA

JUNCTION TE M P ERATURE (°C)

07718-108

1.520

1.515

1.510

1.505

1.500

1.495

OUTPUT VOLTAGE (V)

1.490

1.485

1.480
10 100 1k

LOAD CURRENT (mA)

Figure 6. Output Voltage vs. Load Current

1.520

1.515

1.510

1.505

1.500

1.495

OUTPUT VOLTAGE (V)

1.490

1.485

1.480

1.8 3.63.43.23.02.82.62.42.22.0

LOAD = 10mA

LOAD = 400mA

INPUT VOLTAGE (V)

LOAD = 100mA

LOAD = 800mA

Figure 7. Output Voltage vs. Input Voltage

1000

900

800

700

600

500

400

300

GROUND CURRENT (µA)

200

100

0

10 100 1k

07718-106

LOAD CURRENT (mA)

07718-109

Figure 9. Ground Current vs. Load Current

1000

900

800

700

600

500

400

300

GROUND CURRENT (µA)

200

100

0

1.8 3.63.43.23.02.82.62.42.22.0

07718-107

LOAD = 800mA

LOAD = 400mA

LOAD = 100mA

LOAD = 10mA

INPUT VOLTAGE (V)

07718-110

Figure 10. Ground Current vs. Input Voltage

Rev. B | Page 7 of 20

ADP1752/ADP1753

100

90

80

70

60

50

40

30

SHUTDOWN CURRENT ( µA)

20

10

0

–40 85603510–15

TEMPERATURE (°C)

1.9V

2.0V

2.4V

2.6V

3.0V

3.6V

Figure 11. Shutdown Current vs. Temperature at Various Input Voltages

0.08

0.07

0.06

0.05

0.04

0.03

DROPOUT VO LTAGE (V )

0.02

0.01

0

1 10 100 1k

LOAD CURRENT (mA)

Figure 12. Dropout Voltage vs. Load Current, V

1.6V

2.5V

= 1.6 V, 2.5 V

OUT

07718-111

07718-112

4500

4000

3500

3000

2500

2000

1500

GROUND CURRENT (µA)

1000

500

0

2.3 2.4 2.5 2.6 2.7 2.8
INPUT VOLTAGE (V)

LOAD = 10mA
LOAD = 100mA
LOAD = 400mA
LOAD = 800mA

Figure 14. Ground Current vs. Input Voltage (in Dropout), V

T

1

1mA TO 800mA LOAD STEP, 2.5A/µs, 500mA/DIV

2

CH1 500mA Ω

B

W

Figure 15. Load Transient Response, C

CH2 50mV

I

LOAD

V

OUT

50mV/DIV

B

M10µs A CH1 380mA

W

T 10.20%

= 4.7 μF, C

IN

VIN = 3.6V
V

= 1.5V

OUT

OUT

= 2.5 V

OUT

= 4.7 μF

07718-114

07718-115

2.60

2.55

2.50

2.45

2.40

2.35

OUTPUT VOLTAGE (V)

2.30

2.25

2.20

2.3 2.4 2.5 2.6 2.7 2.8
INPUT VOLTAGE (V)

LOAD = 10mA
LOAD = 100mA
LOAD = 400mA
LOAD = 800mA

Figure 13. Output Voltage vs. Input Voltage (in Dropout), V

= 2.5 V

OUT

07718-113

Rev. B | Page 8 of 20

T

1

1mA TO 800mA LOAD STEP, 2.5A/µs, 500mA/DIV

2

CH1 500mA Ω

B

W

CH2 20mV

I

LOAD

V

OUT

20mV/DIV

B

W

Figure 16. Load Transient Response, C

VIN = 3.6V
V

= 1.5V

OUT

M10µs A CH1 530mA

T 10.20%

= 22 μF, C

IN

= 22 μF

OUT

07718-116

ADP1752/ADP1753

0

–10

–20

–30

–40

–50

PSRR (dB)

–60

–70

–80

–90

–100

10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 20. Power Supply Rejection Ratio vs. Frequency,

= 0.75 V, VIN = 1.75 V

V

OUT

800mA
400mA
100mA
10mA

07718-120

2

V

OUT

C

IN

1

CH1 500mV

T

3V TO 3.5V INPUT V OLTAGE STEP, 2V /µs

= 1.5V

= C

= 4.7µF

OUT

B

CH2 2.0mV

W

V

IN

V

OUT

2mV/DIV

B

M10µs A CH4 800mA

W

T 9.40%

Figure 17. Line Transient Response, Load Current = 800 mA

07718-117

70

60

50

40

30

NOISE (µV rms)

20

10

0

0.0001 0.001 0.01 0.1 1
LOAD CURRENT (A)

2.5V

1.5V

0.75V

Figure 18. Noise vs. Load Current and Output Voltage

10

1

1.5V

0.1

NOISE SPECTRAL DENSITY (µV/ Hz)

0.01
10 100 1k 10k 100k

FREQUENCY (Hz)

2.5V

0.75V

Figure 19. Noise Spectral Density vs. Output Voltage, I

LOAD

= 10 mA

0

–10

–20

–30

–40

–50

PSRR (dB)

–60

–70

–80

–90

–100

10 100 1k 10k 100k 1M 10M

07718-118

FREQUENCY (Hz)

LOAD = 800mA
LOAD = 400mA
LOAD = 100mA
LOAD = 10mA

07718-121

Figure 21. Power Supply Rejection Ratio vs. Frequency,

V

= 1.5 V, VIN = 2.5 V

OUT

0

–10

–20

–30

–40

–50

PSRR (dB)

–60

–70

–80

–90

–100

10 100 1k 10k 100k 1M 10M

07718-119

FREQUENCY (Hz)

LOAD = 800mA
LOAD = 400mA
LOAD = 100mA
LOAD = 10mA

07718-122

Figure 22. Power Supply Rejection Ratio vs. Frequency,

V

= 2.5 V, VIN = 3.5 V

OUT

Rev. B | Page 9 of 20

ADP1752/ADP1753

0

1.5V/800mA

–10

–20

–30

–40

–50

PSRR (dB)

–60

–70

–80

–90

2.5V/800mA

0.75V/800mA

10 100 1k 10k 100k 1M 10M

1.5V/10mA

2.5V/10mA

0.75V/10mA

FREQUENCY (Hz)

Figure 23. Power Supply Rejection Ratio vs. Frequency and Output Voltage

07718-123

Rev. B | Page 10 of 20

ADP1752/ADP1753

THEORY OF OPERATION

The ADP1752/ADP1753 are low dropout linear regulators that
use an advanced, proprietary architecture to provide high power
supply rejection ratio (PSRR) and excellent line and load transient
response with only a small 4.7 µF ceramic output capacitor.
Both devices operate from a 1.6 V to 3.6 V input rail and
provide up to 0.8 A of output current. Supply current in
shutdown mode is typically 2 µA.

REVERSE POLARI T Y

PROTECTION

0.5V
REF

REVERSE POLARITY

PROTECTION

0.5V
REF

R1

R2

0.9µA

0.9µA

VOUTVIN

SENSE

SS

VOUTVIN

ADJ

SS

7718-019

7718-020

GND

PG

GND

EN

PG

EN

ADP1752

UVLO

SHORT-CIRCUIT

AND THERMAL

PROTECTION

PG

DETECT

SHUTDOWN

Figure 24. ADP1752 Internal Block Diagram

ADP1753

UVLO

SHORT-CIRCUIT

AND THERMAL

PROTECTION

PG

DETECT

SHUTDOWN

Figure 25. ADP1753 Internal Block Diagram

Internally, the ADP1752/ADP1753 consist of a reference, an error
amplifier, a feedback voltage divider, and a PMOS pass transistor.
Output current is delivered via the PMOS pass transistor, which is
controlled by the error amplifier. The error amplifier compares the
reference voltage with the feedback voltage from the output and
amplifies the difference. If the feedback voltage is lower than the
reference voltage, the gate of the PMOS device is pulled lower,
allowing more current to pass and increasing the output voltage.
If the feedback voltage is higher than the reference voltage, the
gate of the PMOS device is pulled higher, allowing less current
to pass and decreasing the output voltage.

The ADP1752 is available in seven fixed output voltage options
between 0.75 V and 2.5 V. The ADP1752 allows for connection
of an external soft start capacitor that controls the output voltage
ramp during startup. The ADP1753 is the adjustable version
with an output voltage that can be set to a value between 0.75 V
and 3.0 V by an external voltage divider. Both devices are con­trolled by an enable pin (EN).

SOFT START FUNCTION (ADP1752/ADP1753)

For applications that require a controlled startup, the ADP1752/
ADP1753 provide a programmable soft start function. The
programmable soft start is useful for reducing inrush current
upon startup and for providing voltage sequencing. To implement
soft start, connect a small ceramic capacitor from SS to GND.
Upon startup, a 0.9 µA current source charges this capacitor.
The ADP1752/ADP1753 start-up output voltage is limited by
the voltage at SS, providing a smooth ramp-up to the nominal
output voltage. The soft start time is calculated as follows:

t

= V

SS

where:

t

is the soft start period.

SS

is the 0.5 V reference voltage.

V

REF

C

is the soft start capacitance from SS to GND.

SS

is the current sourced from SS (0.9 µA).

I

SS

When the ADP1752/ADP1753 are disabled (using EN), the soft
start capacitor is discharged to GND through an internal 100 Ω
resistor.

VOLTAGE (V)

× (CSS/ISS) (1)

REF

2.50

2.25

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0

024681

Figure 26. V

EN

1nF

4.7nF

10nF

TIME (ms)

Ramp-Up with External Soft Start Capacitor

OUT

0

07718-021

Rev. B | Page 11 of 20

ADP1752/ADP1753

1

2

CH1 2.0V

T

B

W

Figure 27. V

CH2 500mV

OUT

EN

V

OUT

V

= 1.5V

500mV/DIV

B

W

OUT

= C

C

M40µs A CH1 920mV

T 9.8%

= 4.7µF

IN

OUT

Ramp-Up with Internal Soft Start

07718-022

ADJUSTABLE OUTPUT VOLTAGE (ADP1753)

The output voltage of the ADP1753 can be set over a 0.75 V to

3.0 V range. The output voltage is set by connecting a resistive
voltage divider from VOUT to ADJ. The output voltage is calcu­lated using the following equation:

V

= 0.5 V × (1 + R1/R2) (2)

OUT

where:

R1 is the resistor from VOUT to ADJ.
R2 is the resistor from ADJ to GND.

The maximum bias current into ADJ is 150 nA. Therefore, to
achieve less than 0.5% error due to the bias current, use values
less than 60 kΩ for R2.

ENABLE FEATURE

The ADP1752/ADP1753 use the EN pin to enable and disable
the VOUT pin under normal operating conditions. As shown in
Figure 28, when a rising voltage on EN crosses the active
threshold, VOUT turns on. When a falling voltage on EN
crosses the inactive threshold, VOUT turns off.

T

EN

V

OUT

The EN pin active/inactive thresholds are derived from the VIN
voltage. Therefore, these thresholds vary with changing input
voltage. Figure 29 shows typical EN active/inactive thresholds
when the input voltage varies from 1.6 V to 3.6 V.

1.1

1.0

0.9

0.8

0.7

EN THRESHOLD ( V )

0.6

0.5

1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6

EN ACTIVE

EN INACTIVE

INPUT VOLTAG E ( V)

07718-024

Figure 29. Typical EN Pin Thresholds vs. Input Voltage

POWER-GOOD FEATURE

The ADP1752/ADP1753 provide a power-good pin, PG, to
indicate the status of the output. This open-drain output
requires an external pull-up resistor to V
shutdown, in current limit mode, in thermal shutdown, or if it
falls below 90% of the nominal output voltage, PG immediately
transitions low. During soft start, the rising threshold of the
power-good signal is 93.5% of the nominal output voltage.

The open-drain output is held low when the ADP1752/ADP1753
have sufficient input voltage to turn on the internal PG transistor.
An optional soft start delay can be detected. The PG transistor
is terminated via a pull-up resistor to V

Power-good accuracy is 93.5% of the nominal regulator output
voltage when this voltage is rising, with a 90% trip point when
this voltage is falling.

Regulator input voltage brownouts or glitches trigger a power
no-good if V

falls below 90%.

OUT

A normal power-down triggers a power no-good when V
drops below 90%.

. If the part is in

IN

or VIN.

OUT

OUT

1

2

V

= 1.5V

OUT

= C

C

M2.0ms A CH1 1.05V

T 29.6%

= 4.7µF

IN

OUT

07718-023

CH1 500mV

B

CH2 500mV

W

500mV/DIV

B

W

Figure 28. Typical EN Pin Operation

As shown in Figure 28, the EN pin has hysteresis built in. This
hysteresis prevents on/off oscillations that can occur due to
noise on the EN pin as it passes through the threshold points.

Rev. B | Page 12 of 20

ADP1752/ADP1753

V

IN

1V/DIV

1

2

2

B

CH1 1.0V
CH3 1.0V

W

B

W

Figure 30. Typical PG Behavior vs. V

V

IN

1V/DIV

1

CH2 500mV

V

OUT

500mV/DIV

T

V

OUT

500mV/DIV

PG

1V/DIV

V

= 1.5V

OUT

= C

C

IN

OUT

B

M40.0µs A CH3 900mV

W

T 50.40%

, VIN Rising (V

OUT

T

= 4.7µF

= 1.5 V)

OUT

07718-025

REVERSE CURRENT PROTECTION FEATURE

The ADP1752/ADP1753 have additional circuitry to protect
against reverse current flow from VOUT to VIN. For a typical
LDO with a PMOS pass device, there is an intrinsic body diode
between VIN and VOUT. When V
diode is reverse-biased. If V

OUT

diode becomes forward-biased and conducts current from VOUT
to VIN, potentially causing destructive power dissipation. The
reverse current protection circuitry detects when V
than V

and reverses the direction of the intrinsic diode connec-

IN

tion, reverse-biasing the diode. The gate of the PMOS pass
device is also connected to VOUT, keeping the device off.

Figure 32 shows a plot of the reverse current vs. the V
differential.

4000

3500

3000

2500

2000

1500

REVERSE CURRENT (µA)

1000

is greater than V

IN

OUT

, this

is greater than VIN, the intrinsic

is greater

OUT

to VIN

OUT

2

2

V

= 1.5V

OUT

= C

C

CH1 1.0V
CH3 1.0V

= 4.7µF

IN

OUT

B

W

B

W

Figure 31. Typical PG Behavior vs. V

CH2 500mV

PG

1V/DIV

B

M40.0µs A CH3 900mV

W

T 50.40%

, VIN Falling (V

OUT

= 1.5 V)

OUT

500

0

0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6

07718-026

Figure 32. Reverse Current vs. V

V

OUT

– VIN (V)

OUT

− VIN

07718-232

Rev. B | Page 13 of 20

ADP1752/ADP1753

APPLICATIONS INFORMATION

CAPACITOR SELECTION

Output Capacitor

The ADP1752/ADP1753 are designed for operation with small,
space-saving ceramic capacitors, but they can function with most
commonly used capacitors as long as care is taken with the
effective series resistance (ESR) value. The ESR of the output
capacitor affects the stability of the LDO control loop. A mini­mum of 3.3 µF capacitance with an ESR of 500 mΩ or less is
recommended to ensure the stability of the ADP1752/ADP1753.
Transient response to changes in load current is also affected by
output capacitance. Using a larger value of output capacitance
improves the transient response of the ADP1752/ADP1753 to
large changes in load current. Figure 33 and Figure 34 show the
transient responses for output capacitance values of 4.7 µF and
22 µF, respectively.

T

1

2

1mA TO 800mA LOAD STEP, 2V /µs, 500mA/DIV

CH1 500mA Ω

B

W

Figure 33. Output Transient Response, C

T

CH2 50mV

I

LOAD

V

OUT

50mV/DIV

VIN = 3.6V, V
C

IN

B

M1µs A CH1 380mA

W

T 11.6%

I

LOAD

= C

OUT

OUT

= 1.5V

OUT

= 4.7µF

= 4.7 μF

07718-132

Input Bypass Capacitor

Connecting a 4.7 µF capacitor from the VIN pin to GND reduces
the circuit sensitivity to printed circuit board (PCB) layout,
especially when long input traces or high source impedance
are encountered. If output capacitance greater than 4.7 µF is
required, it is recommended that the input capacitor be increased
to match it.

Input and Output Capacitor Properties

Any good quality ceramic capacitors can be used with the
ADP1752/ADP1753, as long as they meet the minimum
capacitance and maximum ESR requirements. Ceramic
capacitors are manufactured with a variety of dielectrics,
each with different behavior over temperature and applied
voltage. Capacitors must have a dielectric adequate to ensure
the minimum capacitance over the necessary temperature
range and dc bias conditions. X5R or X7R dielectrics with a
voltage rating of 6.3 V or 10 V are recommended. Y5V and
Z5U dielectrics are not recommended, due to their poor tempera­ture and dc bias characteristics.

Figure 35 shows the capacitance vs. voltage bias characteristics
of an 0805 case, 4.7 µF, 10 V, X5R capacitor. The voltage stability
of a capacitor is strongly influenced by the capacitor size and
voltage rating. In general, a capacitor in a larger package or with
a higher voltage rating exhibits better stability. The temperature
variation of the X5R dielectric is about ±15% over the −40°C to
+85°C temperature range and is not a function of package size
or voltage rating.

5

4

3

MURATA P/N GRM 2 19R61A475KE 34

1

2

1mA TO 800mA LOAD STEP, 2V /µs, 500mA/DIV

V

OUT

20mV/DIV

CH1 500mA Ω

B

CH2 20mV

W

B

M1µs A CH1 530mA

W

T 12.2%

Figure 34. Output Transient Response, C

VIN = 3.6V, V

= C

C

IN

OUT

OUT

= 1.5V

OUT

= 22µF

= 22 μF

07718-133

Rev. B | Page 14 of 20

2

CAPACITANCE (µF )

1

0

024681

VOLTAGE BIAS (V)

0

07718-029

Figure 35. Capacitance vs. Voltage Bias Characteristics

Equation 3 can be used to determine the worst-case capacitance
accounting for capacitor variation over temperature, component
tolerance, and voltage.

C

= C

EFF

× (1 − TEMPCO) × (1 − TOL) (3)

OUT

where:
C

is the effective capacitance at the operating voltage.

EFF

TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.

ADP1752/ADP1753

In this example, the worst-case temperature coefficient
(TEMPCO) over −40°C to +85°C is assumed to be 15% for an
X5R dielectric. The tolerance of the capacitor (TOL) is assumed
to be 10%, and C

= 4.46 F at 1.8 V, as shown in Figure 35.

OUT

Substituting these values in Equation 3 yields

C

= 4.46 F × (1 − 0.15) × (1 − 0.1) = 3.41 F

EFF

Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over temper­ature and tolerance at the chosen output voltage.

To guarantee the performance of the ADP1752/ADP1753, it is
imperative that the effects of dc bias, temperature, and toler­ances on the behavior of the capacitors be evaluated for each
application.

UNDERVOLTAGE LOCKOUT

The ADP1752/ADP1753 have an internal undervoltage lockout
circuit that disables all inputs and the output when the input
voltage is less than approximately 1.58 V. This ensures that the
ADP1753/ADP1753 inputs and the output behave in a predicta­ble manner during power-up.

CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION

The ADP1752/ADP1753 are protected against damage due to
excessive power dissipation by current-limit and thermal
overload protection circuits. The ADP1752/ADP1753 are
designed to reach current limit when the output load reaches

1.4 A (typical). When the output load exceeds 1.4 A, the output
voltage is reduced to maintain a constant current limit.

Thermal overload protection is included, which limits the
junction temperature to a maximum of 150°C (typical). Under
extreme conditions (that is, high ambient temperature and
power dissipation) when the junction temperature begins to
rise above 150°C, the output is turned off, reducing the output
current to zero. When the junction temperature drops below
135°C (typical), the output is turned on again and the output
current is restored to its nominal value.

Consider the case where a hard short from VOUT to ground
occurs. At first, the ADP1752/ADP1753 reach current limit so
that only 1.4 A is conducted into the short. If self-heating of
the junction becomes great enough to cause its temperature to
rise above 150°C, thermal shutdown activates, turning off the
output and reducing the output current to zero. As the junction
temperature cools and drops below 135°C, the output turns on
and conducts 1.4 A into the short, again causing the junction
temperature to rise above 150°C. This thermal oscillation between
135°C and 150°C causes a current oscillation between 1.4 A and
0 A that continues as long as the short remains at the output.

Current-limit and thermal overload protections are intended to
protect the device against accidental overload conditions. For
reliable operation, device power dissipation should be externally
limited so that junction temperatures do not exceed 125°C.

Rev. B | Page 15 of 20

THERMAL CONSIDERATIONS

To guarantee reliable operation, the junction temperature of the
ADP1752/ADP1753 must not exceed 125°C. To ensure that the
junction temperature stays below this maximum value, the user
needs to be aware of the parameters that contribute to junction
temperature changes. These parameters include ambient tempera­ture, power dissipation in the power device, and thermal resistance
between the junction and ambient air (θ
dent on the package assembly compounds used and the amount
of copper to which the GND pin and the exposed pad (EPAD)
of the package are soldered on the PCB. Tab le 6 shows typical
θ

values for the 16-lead LFCSP for various PCB copper sizes.

JA

Tabl e 7 shows typical Ψ

Table 6. Typical θ

values for the 16-lead LFCSP.

JB

Values

JA

Copper Size (mm2) θJA (°C/W), LFCSP

01 130
100 80
500 69
1000 54
6400 42

1

Device soldered to minimum size pin traces.

Table 7. Typical ΨJB Values

Copper Size (mm2) ΨJB (°C/W) @ 1 W

100 32.7
500 31.5
1000 25.5

The junction temperature of the ADP1752/ADP1753 can be
calculated from the following equation:

T

= TA + (PD × θJA) (4)

J

where:

T

is the ambient temperature.

A

P

is the power dissipation in the die, given by

D

= [(VIN − V

P

D

OUT

) × I

] + (VIN × I

LOAD

where:

V

and V

IN

I

is the load current.

LOAD

is the ground current.

I

GND

are the input and output voltages, respectively.

OUT

Power dissipation due to ground current is quite small and can
be ignored. Therefore, the junction temperature equation can
be simplified as follows:

T

= TA + {[(VIN − V

J

OUT

) × I

As shown in Equation 6, for a given ambient temperature, input­to-output voltage differential, and continuous load current, a
minimum copper size requirement exists for the PCB to ensure
that the junction temperature does not rise above 125°C. Figure 36
through Figure 41 show junction temperature calculations for
different ambient temperatures, load currents, V
differentials, and areas of PCB copper.

). The θJA value is depen-

JA

) (5)

GND

] × θJA} (6)

LOAD

IN

to V

OUT

ADP1752/ADP1753

T

T

T

T

T

T

140

120

(°C)

J

100

80

60

40

JUNCTION TEMPERATUR E ,

20

0

0.25 0.75 1.25 1.75 2.25 2.75

MAX JUNCTION
TEMPERATURE

LOAD = 800mA

LOAD = 10mA

VIN – V

OUT

(V)

LOAD = 400mA

LOAD = 200mA

LOAD = 100mA

LOAD = 50mA

Figure 36. 6400 mm2 of PCB Copper, TA = 25°C, LFCSP

07718-135

140

120

(°C)

J

100

80

60

40

JUNCTION TEMPERATUR E ,

20

0

0.25 0.75 1.25 1.75 2.25 2.75

MAX JUNCTION
TEMPERATURE

LOAD = 800mA

LOAD = 400mA

LOAD = 10mA

VIN – V

OUT

(V)

LOAD = 200mA

LOAD = 100mA

LOAD = 50mA

Figure 39. 6400 mm2 of PCB Copper, TA = 50°C, LFCSP

07718-138

140

120

(°C)

J

100

80

60

40

JUNCTION TEMPERATUR E ,

20

0

0.25 0.75 1.25 1.75 2.25 2.75

MAX JUNCTION
TEMPERATURE

LOAD = 800mA

LOAD = 10mA

VIN – V

LOAD = 400mA

LOAD = 50mA

(V)

OUT

LOAD = 200mA

LOAD = 100mA

Figure 37. 500 mm2 of PCB Copper, TA = 25°C, LFCSP

140

120

(°C)

J

100

80

60

40

JUNCTION TEMPERATUR E ,

20

0

0.25 0.75 1.25 1.75 2.25 2.75

MAX JUNCTION
TEMPERATURE

LOAD = 800mA

LOAD = 10mA

VIN – V

LOAD = 400mA

(V)

OUT

LOAD = 200mA

LOAD = 100mA

LOAD = 50mA

Figure 38. 0 mm2 of PCB Copper, TA = 25°C, LFCSP

140

120

(°C)

J

JUNCTION TEMPERATUR E ,

07718-136

LOAD = 800mA

100

80

60

40

20

0

0.25 0.75 1.25 1.75 2.25 2.75
VIN – V

MAX JUNCTION
TEMPERATURE

LOAD = 400mA

LOAD = 50mA

LOAD = 10mA

(V)

OUT

LOAD = 200mA

LOAD = 100mA

07718-139

Figure 40. 500 mm2 of PCB Copper, TA = 50°C, LFCSP

140

120

(°C)

J

100

80

60

40

JUNCTION TEMPERATUR E ,

20

0

0.25 0.75 1.25 1.75 2.25 2.75

07718-137

LOAD =
800mA

LOAD = 400mA

LOAD = 10mA

VIN – V

OUT

(V)

MAX JUNCTION
TEMPERATURE

LOAD = 200mA

LOAD = 100mA

LOAD = 50mA

07718-140

Figure 41. 0 mm2 of PCB Copper, TA = 50°C, LFCSP

Rev. B | Page 16 of 20

ADP1752/ADP1753

T

T

T

T

In cases where the board temperature is known, the thermal
characterization parameter, Ψ
junction temperature rise. Maximum junction temperature (T
is calculated from the board temperature (T
dissipation (P

T

= TB + (PD × ΨJB) (7)

J

) using the following formula:

D

, can be used to estimate the

JB

) and power

B

)

J

Figure 42 through Figure 45 show junction temperature calcula­tions for different board temperatures, load currents, V
V

differentials, and areas of PCB copper.

OUT

140

120

(°C)

J

100

80

60

40

JUNCTION TEMPERATUR E ,

20

0

0.25 0.75 1.25 1.75 2.25 2.75

Figure 42. 500 mm

140

120

(°C)

J

100

80

60

40

JUNCTION TE M PERATURE,

20

MAX JUNCTION
TEMPERATURE

LOAD = 800mA

LOAD = 400mA

LOAD = 200mA

LOAD = 100mA

LOAD = 50mA

LOAD = 10mA

VIN – V

(V)

OUT

2

of PCB Copper, TB = 25°C, LFCSP

MAX JUNCTION
TEMPERATURE

LOAD = 800mA

LOAD = 400mA

LOAD = 200mA

LOAD = 100mA

LOAD = 50mA

LOAD = 10mA

to

IN

07718-141

140

120

(°C)

J

100

80

60

40

JUNCTION TEMPERATUR E ,

20

0

0.25 0.75 1.25 1.75 2.25 2.75

Figure 44. 1000 mm

140

120

(°C)

J

100

80

60

40

JUNCTION TE M PERATURE,

20

0

0.25 0.75 1.25 1.75 2.25 2.75

Figure 45. 1000 mm

MAX JUNCTION
TEMPERATURE

LOAD = 800mA

LOAD = 400mA

LOAD = 200mA

LOAD = 100mA

LOAD = 50mA

LOAD = 10mA

VIN – V

2

of PCB Copper, TB = 25°C, LFCSP

MAX JUNCTION
TEMPERATURE

VIN – V

2

of PCB Copper, TB = 50°C, LFCSP

(V)

OUT

LOAD = 50mA

LOAD = 10mA

(V)

OUT

LOAD = 800mA

LOAD = 400mA

LOAD = 200mA

LOAD = 100mA

07718-143

07718-144

0

0.25 0.75 1.25 1.75 2.25 2.75

Figure 43. 500 mm

VIN – V

(V)

OUT

2

of PCB Copper, TB = 50°C, LFCSP

07718-142

Rev. B | Page 17 of 20

ADP1752/ADP1753

PCB LAYOUT CONSIDERATIONS

Heat dissipation from the package can be improved by increas­ing the amount of copper attached to the pins of the ADP1752/
ADP1753. However, as shown in Tab l e 6, a point of diminishing
returns is eventually reached, beyond which an increase in the
copper size does not yield significant heat dissipation benefits.

Here are a few general tips when designing PCBs:

• Place the input capacitor as close as possible to the VIN

and GND pins.

• Place the output capacitor as close as possible to the VOUT

and GND pins.

• Place the soft start capacitor as close as possible to the SS pin.

• Connect the load as close as possible to the VOUT and

SENSE pins (ADP1754) or to the VOUT and ADJ pins
(ADP1755).

Use of 0603 or 0805 size capacitors and resistors achieves the
smallest possible footprint solution on boards where area is
limited.

Figure 46. Evaluation Board

07718-145

Figure 47. Typical Board Layout—Top Side

Figure 48. Typical Board Layout—Bottom Side

7718-233

7718-146

Rev. B | Page 18 of 20

ADP1752/ADP1753

OUTLINE DIMENSIONS

PIN 1

INDICATOR

1.00

0.85

0.80

12° MAX

SEATING
PLANE

4.00

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

0.35

0.30

0.25

3.75

BSC SQ

0.20 REF

0.60 MAX

0.65 BSC

0.05 MAX

0.02 NOM

COPLANARITY

0.75

0.60

0.50

0.08

0.60 MAX

(BOTTOM VIEW)

16

13

12

9

8

5

1.95 BSC
FOR PROPER CONNECTION O F

THE EXPOSED PAD, REFER TO
THE PIN CONF IGURATION AND
FUNCTION DES CRI PTIONS
SECTION O F THIS DATA S HE E T.

PIN 1
INDICATOR

1

4

5

2

.

2

0

1

.

2

9

.

1

5

0.25 MIN

Q

S

COMPLIANT TO JEDEC STANDARDS MO-220-VGGC

072808-A

Figure 49. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm × 4 mm Body, Very Thin Quad

(CP-16-4)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Output Voltage (V) Package Description Package Option

ADP1752ACPZ-0.75R7 −40°C to +125°C 0.75 16-Lead LFCSP_VQ CP-16-4
ADP1752ACPZ-1.0-R7 −40°C to +125°C 1.0 16-Lead LFCSP_VQ CP-16-4
ADP1752ACPZ-1.1-R7 −40°C to +125°C 1.1 16-Lead LFCSP_VQ CP-16-4
ADP1752ACPZ-1.2-R7 −40°C to +125°C 1.2 16-Lead LFCSP_VQ CP-16-4
ADP1752ACPZ-1.5-R7 −40°C to +125°C 1.5 16-Lead LFCSP_VQ CP-16-4
ADP1752ACPZ-1.8-R7 −40°C to +125°C 1.8 16-Lead LFCSP_VQ CP-16-4
ADP1752ACPZ-2.5-R7 −40°C to +125°C 2.5 16-Lead LFCSP_VQ CP-16-4
ADP1753ACPZ-R7 −40°C to +125°C Adjustable from 0.75 to 3.0 16-Lead LFCSP_VQ CP-16-4
ADP1752-1.5-EVALZ 1.5 Evaluation Board
ADP1752-BL1-EVAL Blank Evaluation Board
ADP1753-EVALZ Adjustable Evaluation Board
ADP1753-BL1-EVAL Blank Evaluation Board

1

Z = RoHS Compliant Part.

Rev. B | Page 19 of 20

ADP1752/ADP1753

NOTES

©2008–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07718-0-2/10(B)

Rev. B | Page 20 of 20