Datasheet ADP1653 Datasheet (ANALOG DEVICES)

Compact, High Efficiency, High Power,

www.BDTIC.com/ADI

Flash/Torch LED Driver with Dual Interface

FEATURES

Small 6.4 mm × 7.2 mm solution

2.2 H power inductor
92% peak efficiency
Tx masking within 50 s

2.1 A, 12 V power switch
Pin-selectable interface: 2-bit logic or I
Programmable flash and torch current

Up to 200 mA in torch mode

Up to 500 mA in flash mode
Programmable indicator LED current up to 20 mA
Programmable timer register: up to 820 ms flash timeout

2.75 V to 5.5 V input voltage range
Low noise, 1.2 MHz PWM operation
Safety features

Interrupt output pin

Fault condition register

S

hort-circuit protection
Output overvoltage protection
Thermal overload protection
Integrated current limit and soft start

Small 3 mm × 3 mm, 16-lead LFCSP footprint

APPLICATIONS

Camera-enabled cellular phones, smart phones
Digital still cameras, camcorders, PDAs

2

C

ADP1653

GENERAL DESCRIPTION

The ADP1653 is a very compact, high efficiency, high power,
camera flash LED driver optimized for cellular phones. The
high efficiency and dynamic LED current control of the device
improve flash brightness and picture quality in dimly lit
environments. Efficiency peaks at 92% and is higher than
charge pump solutions over the Li-Ion battery range.

The device has a dual-mode interface that is configurable to 2-bit
log

ic or an I

currents are programmable with external resistors or through the

2

I

C interface. To maximize overall flash brightness, the ADP1653
offers an input to reduce flash LED current in less than 50 µs,
referred to as the Tx mask. Tx masking reduces battery stress by
scaling back flash LED current during an RF transmission.

The ADP1653 solution requires only four external components

2

in I
grates multiple safety features such as soft start, flash timeout,
output current limit, thermal protection, and overvoltage
protection.

The ADP1653 operates over the −40°C to +125°C junction
t

emperature range.

2

C® interface. The indicator and high power LED

C mode and fits in a 6.4 mm × 7.2 mm space. The part inte-

TYPICAL OPERATING CIRCUIT

INPUT VOLTAGE = 2.75V TO 5.5V

4.7µF

ON

16 15 14 13

STR

EN

V

ADP1653

OUT

ILED

SETI

5 6 7 8

OPTIONAL

TxMASK

OFFONOFF

1

SETT

2

SETF

3

CTRL1/SCL

4

CTRL0/SDA

V

DD

Figure 1.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

2.2µH

UP TO 10.2V

4.7µF

LX

DD

PGND

INT

INTF

HPLED

GND

12

ONE

OR

TWO

11

LEDs

10

9

06180-001

PCB LAYOUT

LI-ION +

INDUCTOR

L1

7.2mm

R5

INPUT CAPACIT OR

C1

SCHOTTKY DI ODE

PGND

ADP1653

R4

OPTIO NAL (Tx MAS K ONLY)

6.4mm

FROM WHITE
LEDs

Figure 2.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2007 Analog Devices, Inc. All rights reserved.

GND

D1

C2

OUTPUT CAPACI TOR

L = FDSE0312- 2R2
CIN = GRM219R61A475K
D1 = BAT20J
COUT = GRM21BR61C475K

TO WHITE
LEDs

6180-036

ADP1653

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TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description......................................................................... 1

Typical O p erating Ci rc u it ................................................................ 1

PCB Layout........................................................................................ 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

2

I

C Timing Specifications............................................................ 5

Absolute Maximum Ratings............................................................ 6

Thermal Resistance ...................................................................... 6

Boundary Condition .................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

REVISION HISTORY

9/07—Rev. A to Rev. B

Changes to Table 1............................................................................ 3

Changes to Table 5............................................................................ 7

Changes to I

Changes to Safety Features Section .............................................. 16

Inserted Table 9 and Table 10........................................................ 18

Inserted Table 11 and Table 12...................................................... 19

1/07—Revision A: Initial Version

2

C Interface Mode (INTF = 0) Section .................. 14

Typical Perfor m an c e Charac t e r istics ..............................................9

Theory of Operation ...................................................................... 13

White LED Driver...................................................................... 13

2-Bit Logic Interface Mode (INTF = 1)................................... 14

2

I

C Interface Mode (INTF = 0)................................................. 14

Turning on the Flash and Watchdog Timer ........................... 15

Safety Features ............................................................................ 16

Applications Information.............................................................. 17

Flash Current Foldback During Transmit Pulse.................... 17

External Component Selection ................................................ 18

PCB Layout ................................................................................. 20

Outline Dimensions ....................................................................... 22

Ordering Guide .......................................................................... 22

Rev. B | Page 2 of 24

ADP1653

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SPECIFICATIONS

VDD = 3.0 V to 5.5 V, TJ = −40°C to +125°C, unless otherwise noted.

Table 1.

Parameter Conditions Min Typ Max Unit

SUPPLY

Input Voltage Range

2

3.0 5.5 V
Undervoltage Lockout Threshold VDD rising 2.80 2.9 2.95 V
V

falling 2.58 2.7 2.75 V

DD

Shutdown Current EN = GND, TJ = −40°C to +85°C 0.1 1 μA
Soft Power-Down Current

INTF = 0, EN = VDD, ILED register = 0,
HPLED register = 0, T

INTF = 1, EN = V

= −40°C to +85°C

T

J

INTF = 0, EN = VDD, ILED register = 001,

Operating Current

3

HPLED register = 0
INTF = 1, (CTRL1, CTRL0) = (0, 1), R
INTF = 0, EN = VDD, HPLED register = 00001 1.6 3 mA

INTF = 1, (CTRL1, CTRL0) = (1, x) 1.6 3 mA
LX Leakage TJ = −40°C to +85°C 0.05 0.5 μA
HPLED Leakage TJ = −40°C to +85°C 0.03 0.5 μA

THERMAL SHUTDOWN

Thermal Shutdown Threshold TJ rising 155 °C

INPUTS

EN, STR, CTRL1/SCL, CTRL0/SDA

Input Logic Low Voltage TJ = −40°C to +85°C 0.54 V
T

= −40°C to +125°C 0.48 V

J

Input Logic High Voltage TJ = −40°C to +85°C 1.26 V
T

= −40°C to +125°C 1.27 V

J

SETI, SETT, SETF

Input Logic High Voltage 1.4 V

INTF

Input Logic Low Voltage
Input Logic High Voltage

INT OUTPUT

Logic Low Output Voltage I

4

4

V

V

= −3 mA 0.4 V

SINK

Logic High Leakage Current 0.05 0.5 μA

SETI, SETT, SETF REFERENCE VOLTAGE 1.19 1.22 1.24 V
INDICATOR LED

Current Sink Headroom V

R

R

= VDD − VF (ILED) 1 V

HEADROOM

= 25 kΩ 14.5 17.5 21.5 mA INTF = 1, SETI Current Source

SETI

= 200 kΩ 2.0 2.5 3.0 mA

SETI

ILED register = 1 (001 binary), SETI = V

ILED register = 7 (111 binary), SETI = V

WHITE LED DRIVER

LX

Switching Frequency 1.1 1.2 1.3 MHz
Current Limit 1.8 2.1 2.45 A
On Resistance 250 420 mΩ

OUT

Soft Start Ramp 18 V/ms
Overvoltage Threshold VDD rising 9.8 10.15 10.5 V
Bias Current

5

V

= 10 V 12 μA

OUT

1

= −40°C to +85°C

J

, (CTRL1, CTRL0) = (0, 0),

DD

= 200 kΩ 500 700 μA

SETI

19 45 μA

19 45 μA

500 700 μA

/2 − 0.6 V

DD

/2 + 0.6 V

DD

DD

DD

2.0 2.5 3.0 mA INTF = 0

14.5 17.5 21.5 mA

Rev. B | Page 3 of 24

ADP1653

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Conditions Min Typ Max Unit Parameter

HPLED

Regulation Voltage

Regulation Current

INTF = 1, Torch Mode RSETT = 50 kΩ or SETT = V
RSETT = 125 kΩ 35 50 60 mA
Flash Mode RSETF = 50 kΩ 460 500 550 mA
RSETF = 500 kΩ 35 50 60 mA
INTF = 0, Flash Mode HPLED register = 11111 (binary), SETF = V
HPLED register = 11000 (binary), SETF = V
Torch Mode HPLED register = 00110 (binary), SETF = V

HPLED register = 00001 (binary), SETF = V

Step Size for HPLED LSB Change SETF = V

Maximum Flash Timeout INTF = 0 or 1, 983,040 × oscillator cycles 820 ms
SETF RESPONSE (TRANSMIT MASKING FUNCTION)7
HPLED current = 335 mA to 140 mA 22 μs
HPLED current = 140 mA to 335 mA 24 μs

1

All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). Typical values are at TA = 25°C, VDD = 3.6 V.

2

This is the VDD input voltage range over which the rest of the specifications are valid. The part operates as expected until VDD goes below the UVLO threshold.

3

This is the current into the VDD pin. Additional current can flow into the indicator LED or HPLED, depending on the mode selected.

4

INTF should be tied to GND (INTF = 0) for I2C interface or to VDD (INTF = 1) for hardwire interface. All other digital inputs are 1.8 V compatible.

5

This bias current is active only when the high power LED and/or indicator LED functions are enabled.

6

This specification is not valid during minimum on-time operation of the boost converter (one LED case) when excess voltage is dropped across the HPLED pin.

7

This specification is not production tested but is based on bench evaluation. It is based on the typical two-LED application circuit using a 100 kΩ resistor from SETF to GND,

and a 160 kΩ resistor to a 1.8 V Tx mask logic signal with <1 μs rise/fall time. HPLED register = 11001 (binary). The inductor current has settled to within ±5% of final value.

6

Boost active, two high power LEDs (HPLEDs)

0.23 0.32 0.42 V

in series

DD

DD

110 125 145 mA

460 500 550 mA

DD

365 395 435 mA

DD

110 125 145 mA

DD

38 50 60 mA

DD

15 mA

Rev. B | Page 4 of 24

ADP1653

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I2C TIMING SPECIFICATIONS

Table 2.

Parameter Min Max Unit Description

f

SCL

t

HIGH

t

LOW

t

SU, DAT

1

t

HD, DAT

t

SU, STA

t

HD, STA

t

BUF

t

SU, STO

t

R

t

F

t

SP

2

C

B

1

A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH minimum of the SCL signal) to bridge the undefined region of the

SCL falling edge.

2

CB is the total capacitance of one bus line in picofarads.

400 kHz SCL clock frequency

0.6 μs SCL high time

1.3 μs SCL low time
100 ns Data setup time
0 0.9 μs Data hold time T

0.6 μs Setup time for repeated start

0.6 μs Hold time for start/repeated start

1.3 μs Bus free time between a stop and a start condition

0.6 μs Setup time for stop condition
20 + 0.1 C
20 + 0.1 C

B 300 ns Rise time of SCL and SDA

B

B 300 ns Fall time of SCL and SDA

B

0 50 ns Pulse width of suppressed spike
400 pF Capacitive load for each bus line

SDA

t

t

LOW

SCL

S

S = START CONDI TION
Sr = REPEATED START CONDITION
P = STOP CO NDITION

t

R

t

HD, DAT

t

SU, DAT

t

HIGH

Figure 3. I

t

F

t

F

t

SU, STA

2

C Interface Timing Diagram

Sr P S

t

HD, STA

t

SP

t

SU, STO

BUF

t

R

06180-002

Rev. B | Page 5 of 24

ADP1653

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ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

VDD, CTRL0/SDA, CTRL1/SCL, INTF, EN,

−0.3 V to +6 V

SETI, SETT, SETF, STR, HPLED to GND
INT, ILED to GND

−0.3 V to + (V

+ 0.3 V)

DD

LX, OUT to GND −0.3 V to +12 V
PGND to GND −0.3 V to +0.3 V
Operating Ambient Temperature Range −40°C to +125°C

1

Operating Junction Temperature 125°C
Storage Temperature Range −65°C to +150°C
Soldering Conditions JEDEC J-STD-020

1

In applications where high power dissipation and poor thermal resistance

are present, the maximum ambient temperature may have to be derated.
Maximum ambient temperature (T
operating junction temperature (T
dissipation of the device (P
resistance of the part/package in the application (θJA), using the following
equation: T

A(MAX)

= T

J(MAXOP)

D(MAX)

− (θJA × P

) is dependent on the maximum

A(MAX)

= 125°C), the maximum power

J(MAXOP)

), and the junction-to-ambient thermal

).

D(MAX)

Stresses above those listed under Absolute Maximum Ratings
ma

y cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Absolute maximum ratings apply individually only, not in

mbination. Unless otherwise specified, all other voltages

co
are referenced to GND.

THERMAL RESISTANCE

Junction-to-ambient thermal resistance (θJA) of the package is
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is dependent on the
application and board layout. In applications where high maximum
power dissipation exists, attention to thermal board design is
required. The value of θ

may vary, depending on PCB material,

JA

layout, and environmental conditions. For more information,
see the AN-772 Application Note, A Design and Manufacturing
Guide for the Lead Frame Chip Scale Package (LFCSP).

Table 4. Thermal Resistance

Parameter Value Unit

θ

JA

44 °C/W

Maximum Power Dissipation 1 W

BOUNDARY CONDITION

Natural convection, 4-layer board, exposed pad soldered to
the PCB.

ESD CAUTION

Rev. B | Page 6 of 24

ADP1653

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DD

LX

EN

STR

V

13

14

15

16

PIN 1
INDICATO R

1SETT

2SETF

ADP1653

3CTRL1/SCL

TOP VIEW

(Not to Scale)

4CTRL0/SDA

5

6

SETI

ILED

Figure 4. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 SETT

2 SETF

Set Torch Input (2-Bit Logic Interface Only). SETT prog
external resistor connected between SETT and ground sets the torch current. When SETT is tied high, the current
is internally set to 125 mA. In I

2

C mode, this pin is regarded as a no connect.

Set Flash Input. SETF programs the high power LED (HP
blanking of the LED. In 2-bit logic interface mode, an external resistor connected between SETF and ground sets
the flash current. If SETF is tied high, the current is set internally to 500 mA. In I
with both the external resistor and the internal HPLED bits in the output select register. If SETF is tied high, an
internal 50 kΩ resistor combined with the HPLED bits set the HPLED current.

3 CTRL1/SCL

4 CTRL0/SDA

5 SETI

6 ILED

Serial Interface Clock Input. In 2-bit logic interface mode, C

2

In I

C mode, SCL is the clock input of the I2C-compatible serial interface.

Serial Interface Data Input. In 2-bit logic interface mode, CTRL0 is the first input bit of the digital interface.

2

C mode, SDA is the data input/output of the I2C-compatible serial interface.

I

In
Set Indicator Input (2-Bit Logic Interface Only). SETI programs t

between SETI and ground sets the indicator LED (ILED) current. If SETI is tied high, the current is internally set to
10 mA. In I

2

C mode, this pin is regarded as a no connect.

Indicator LED Input. Connect the cathode of the indicator LED t
or to a voltage rail greater than the LED forward voltage.

7 OUT

White LED Output Voltage. OUT senses the output voltage of the white LED step-up converter. At startup, the
ADP1653 limits the r

ate of increase of the voltage at OUT (soft start) to prevent excessive input inrush current.
The OUT pin features a comparator to detect an overvoltage condition if the LED string is open circuited. Connect
the anode of the white LED(s) to OUT. Connect a 3.3 μF or greater capacitor between OUT and PGND.

8 GND Analog/Digital Ground. Connect GND to PGND at the LFCSP paddle.
9 HPLED

10 INTF

11

INT

High Power LED Current Regulator. HPLED regulates the current of the high power LED(s). Connect the cathode of
the whit

e LED string to HPLED.

Interface Input. INTF selects the 2-pin interface mode. INTF is driven high to enable CTRL1 and CTRL0 for 2-bit

ic interface mode. INTF is driven low to enable SDA and SCL for I

log
Active Low Interrupt Output. INT is an open-drain output that transitions from high to low to signal that a fault
condition has occurred. INT

supply rail and directly to the system processor. When an interrupt is detected, the system processor can read the
FAULT register, using the I

should be connected via a pull-up resistor (for example, 10 kΩ to 100 kΩ) to the I/O

2

C interface for details on the fault condition.
12 PGND Power Ground for Internal Switching FET.
13 LX

14 V

DD

15 EN

White LED Switch Node. LX drives the inductor of the white LED step-up converter. An inductor and diode

onnected to LX powers the white LEDs.

c
Supply Input. Connect the battery between VDD and PGND. Bypass VDD to PGND with a 4.7 μF or greater capacitor.
Enable Input. CMOS input. Driving EN high turns on the ADP1653. Dr

reduces the input current to less than 1 μA. When EN is high, disabling the LEDs puts the part into sleep mode,
dropping the input current to less than 45 μA.

16 STR

Strobe Control Input (I

2

C Interface Only). CMOS input. Driving STR high enables the flash function of the white

LED. STR also enables the watchdog timer to prevent overstressing the white LEDs.

12 PGND

11 INT

10 INTF

9 HPLED

8

7

OUT

GND

06180-003

rams the high power LED current in torch mode. An

LED) current in flash mode and allows for transmit

2

C mode, the flash current scales

TRL1 is the second input bit of the digital interface.

he indicator LED current. An external resistor connected

o the ILED pin. Connect the anode to the battery

2

C interfacing.

iving EN low disables the ADP1653 and

Rev. B | Page 7 of 24

ADP1653

www.BDTIC.com/ADI

Table 6. Mode Selection

Pin Mnemonic Value INTF = 0 (I2C Interface) INTF = 1 (2-Bit Logic Interface)

CTRL0/SDA SDA CTRL1, CTRL0 = 0, 0 (ADP1653 disabled)
CTRL1/SCL SCL CTRL1, CTRL0 = 0, 1 (ADP1653 indicator LED)
CTRL1, CTRL0 = 1, 0 (ADP1653 torch mode)
CTRL1, CTRL0 = 1, 1 (ADP1653 flash mode)

Low ADP1653 disabled ADP1653 disabled EN
High ADP1653 enabled ADP1653 enabled
Low Flash disabled Ignored STR
High Flash enabled Ignored

INT

SETI

SETT

SETF

1

If a resistor is present on SETI or SETT in I2C mode, it is ignored. Both pins should be tied high when operating in I2C mode.

2

If a resistor is present, the current is set by this resistor. If a resistor is not present, the pin must be tied high and a default internal current set.

3

If a resistor is present on SETF in I2C mode, the output current scales with both the I2C setting and the external reference current. The SETF resistor scales both the flash

mode and torch mode currents.

Low Fault condition Fault condition
High Normal operation Normal operation
Resistor Ignored
High I
Resistor Ignored
High I
Resistor SETF resistor(s) and I2C set flash current and torch current
High I

1

2

C sets ILED current ILED current = 10 mA

1

2

C sets torch current Torch current = 125 mA

2

C sets flash current Flash current = 500 mA

3

SETI resistor sets indicator LED current

SETT resistor sets torch current

SETF resistor(s) set flash current

2

2

2

Rev. B | Page 8 of 24

ADP1653

Δ

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TYPICAL PERFORMANCE CHARACTERISTICS

L = D2812C-2R0

Δ: 138µs

L = D2812C-2R0

: 132µs

1

2

3

4

CHANNEL 1 (IL) 0.5A/DIV
CHANNEL 2 (I

Figure 5. Startup, Two LEDs Flash Mode,

L = D2812C-2R0

1

2

3

4

CHANNEL 1 (IL) 0.5A/DIV
CHANNEL 2 (I

Figure 6. Startup, Two LEDs Flash Mode,

) 0.2A/DIV

HPLED

LED C

urrent = 335 mA, V

Δ: 175µs

) 0.2A/DIV

HPLED

urrent = 335 mA, V

LED C

40µs/DIV

CHANNEL 3 (V
CHANNEL 4 (STR) 5V/DIV

DD

40µs/DIV

CHANNEL 3 (V
CHANNEL 4 (STR) 5V/DIV

DD

= 3.2 V

= 3.6 V

OUT

OUT

) 5V/DIV

) 5V/DIV

1

2

3

4

CHANNEL 1 (IL) 0.5A/DIV

06180-011

CHANNEL 2 (I

HPLED

) 0.2A/DIV

40µs/DIV

CHANNEL 3 (V
CHANNEL 4 (SCL) 5V /DIV

OUT

) 5V/DIV

06180-014

Figure 8. Startup, Two LEDs Torch Mode,

LED C

urrent = 130 mA, V

L = D2812C-2R0

1

2

3

4

CHANNEL 1 (IL) 0.5A/DIV

06180-012

CHANNEL 2 (I

HPLED

400ns/DIV

) 0.2A/DIV

= 3.6 V

DD

CHANNEL 3 (LX) 5V/DIV
CHANNEL 4 (HPLED NODE)
1V/DIV

06180-015

Figure 9. Inductor Current, Two LEDs Flash Mode,

LED C

urrent = 335 mA, V

= 3.6 V

DD

HPLED

Δ: 153µs

) 0.2A/DIV

40µs/DIV

CHANNEL 3 (V
CHANNEL 4 (SCL) 5V/ DIV

OUT

) 5V/DIV

06180-013

L = D2812C-2R0

1

2

3

4

CHANNEL 1 (IL) 0.5A/DIV
CHANNEL 2 (I

Figure 7. Startup, Two LEDs Torch Mode,

LED C

urrent = 130 mA, V

= 3.2 V

DD

Rev. B | Page 9 of 24

L = D2812C-2R0

1

2

3

4

CHANNEL 1 (IL) 0.5A/DIV
CHANNEL 2 (I

HPLED

400ns/DIV

) 0.2A/DIV

CHANNEL 3 (LX) 5V /DIV
CHANNEL 4 (HPLED NO DE)

1V/DIV

Figure 10. Inductor Current, Two LEDs Torch Mode,

urrent = 130 mA, V

LED C

= 3.6 V

DD

06180-016

ADP1653

www.BDTIC.com/ADI

) 0.2A/DIV

Δ: 22.4µs

40µs/DIV

CHANNEL 3 (V
CHANNEL 4 (Tx MASK)
5V/DIV

= 3.2 V

DD

OUT

) 5V/DIV

06180-021

500

450

400

350

300

(mA)

250

HPLED

200

I

150

100

50

0

0 5 10 15 20 25 30

HPLED CODE

2

Figure 11. HPLED Current vs. HPLED Code, I

C Mode, SETF = V

1

2

3

4

06180-037

DD

CHANNEL 1 (IBAT) 0.5A/DIV
CHANNEL 2 (I

HPLED

Figure 14. Tx Masking Response, Tx Mask 0 V to 1.8 V,

IHPLE

D = 335 mA to 140 mA, V

86

84

82

80

78

76

EFFI CIENCY (%)

74

L = D2812C-2R0

72

DS = BAT20J
D1, D2 = PWF- 3

70

100 400

150 200 250 300 350

Figure 12. Efficiency P

85

80

75

VDD = 4.2V

VDD = 3.6V

VDD = 3V

LED CURRENT (mA)

, Two High Power White LEDs in Series

LED/PIN

VDD = 3.2V

VDD = 3.6V

VDD = 3.2V

Δ: 23.2µs

1

2

3

4

06180-018

CHANNEL 1 (IBAT) 0.5A/DIV
CHANNEL 2 (I

HPLED

) 0.2A/DIV

40µs/DIV

CHANNEL 3 (V
CHANNEL 4 (Tx MASK)

5V/DIV

OUT

) 5V/DIV

06180-022

Figure 15. Tx Masking Response, Tx Mask 0 V to 1.8 V,

= 140 mA to 335 mA, VDD = 3.2 V

I

HPLED

1

70

EFFICIENCY (%)

65

L = LQM31P-2R2
DS = BAT20J
D1 = PWF-3

60

0500

Figure 13. Efficiency P

100 200 300 400

HPLED CURRENT (mA)

, One High Power White LED

LED/PIN

VDD = 3V

VDD = 4.2V

06180-020

Rev. B | Page 10 of 24

2

3

4

CHANNEL 1 (IL) 0.5A/DIV
CHANNEL 2 (I

HPLED

100ms/DIV

) 0.2A/DIV

CHANNEL 3 (INT) 5V/DIV

L 4 (STR) 5V/DIV

CHANNE

Figure 16. Flash Timed Mode, Two LEDs, Timer = 820 ms,

= 380 mA, VDD = 3.6 V

I

HPLED

06180-023

ADP1653

www.BDTIC.com/ADI

35

1

2

3

4

CHANNEL 1 (IL) 0.5A/DIV
CHANNEL 2 (I

HPLED

100ms/DIV

) 0.2A/DIV

CHANNEL 3 (INT) 5V/DIV
CHANNEL 4 (STR) 5V/DIV

Figure 17. Flash Untimed Mode, Two LEDs, Timer = 300 ms,

= 380 mA, VDD = 3.6 V

I

HPLED

2.5

HIGH

2.3

MEDIUM

2.1

1.9

LOW

LX CURRENT LI MIT (A)

1.7

1.5
–40 10 60 110

TEMPERATURE ( °C)

Figure 18. Typical Current Limit vs. Temperature;

ow, Medium, and High Current Limit Parts

L

30

25

20

(µA)

Q

I

15

10

5

0

–50 125

06180-024

050100

Figure 20. Quiescent Current vs. Temperature,

EN =

V

DD

1.6

1.4

1.2

1.0

0.8

(mA)

Q

I

0.6

0.4

0.2

0

06

06180-040

IQ = 21.5μA

12345

Figure 21. Quiescent Current vs. V

ILED Active at 2.5 mA Until UVLO Threshold

VDD = 5.5V

VDD = 3.6V

VDD = 3V

TEMPERATURE ( °C)

, LED Functions Disabled

ILED ENABLED

V

(V)

DD

, VDD Swept from 5.5 V to 0 V,

DD

06180-027

06180-028

0.20

0.18

0.16

0.14

0.12

0.10

0.08

0.06

SHUTDOWN CURRENT (µA)

0.04

0.02

VDD = 3.6V

VDD = 3V

0

–40 125

10 60 110

TEMPERATURE ( °C)

VDD = 5.5V

06180-026

Figure 19. Shutdown Current vs. Temperature, EN = 0 V

Rev. B | Page 11 of 24

1.220

1.215

1.210

1.205

1.200

5.5V

1.195

1.190

FREQUENCY (MHz )

1.185

1.180

1.175

1.170
–40 –15 10 35 60 85 110

3V

3.6V

TEMPERATURE ( °C)

Figure 22. Oscillator Frequency vs. Temperature vs. V

06180-029

DD

ADP1653

www.BDTIC.com/ADI

(mA)

HPLED

I

127.5

127.0

126.5

126.0

125.5

125.0

124.5

124.0

123.5

123.0

122.5
–40

3V

3.6V

10 60 110

TEMPERATURE (° C)

Figure 23. HPLED Regulation, Set at 125 mA,

PLED Register = 00110 (Binary), SETF = V

H

5.5V

06180-031

DD

353

352

351

(mA)

350

3.6V

HPLED

I

3V

349

348

347

–40

10 60 110

TEMPERATURE (°C)

5.5V

06180-032

Figure 24. HPLED Regulation, Set at 350 mA,

PLED Register = 10101 (Binary), SETF = V

H

DD

Rev. B | Page 12 of 24

ADP1653

V

www.BDTIC.com/ADI

THEORY OF OPERATION

The ADP1653 is a high power, white LED driver ideal for
driving white LEDs for use as a camera flash. The ADP1653
includes a step-up converter and a current regulator suitable for
powering one, or up to three, high power, white LEDs. A second
lower current sink allows an indicator LED to be driven with

2.5 mA to 17.5 mA current.

The ADP1653 responds to a 2-pin control interface that can
o

perate in two separate pin-selectable modes. Tying the INTF
pin high enables a 2-bit logic hardwire interface. Tying the
INTF pin low enables the I

2

C interface.

WHITE LED DRIVER

The ADP1653 drives a step-up converter to power typically one
or two series-connected, high power LEDs. The white LED driver
regulates the high power LED current for accurate brightness
control. The ADP1653 uses an integrated NFET current regulator
that drops the voltage when the power LED forward voltage is
less than the battery voltage.

DD

= 2.75VTO 5.5V

When the required LED voltage is greater than the battery voltage,

he NFET current regulator voltage at the HPLED pin is approxi-

t
mately 320 mV, and the step-up converter applies the appropriate
voltage to OUT, allowing the LED to conduct the regulated current.

When the white LED is turned on, the step-up converter output
v

oltage slew is limited to 18 V/ms to prevent excessive battery
current while charging the output capacitor. The output voltage
of the step-up converter is sensed at OUT. If the output voltage
exceeds the 10.15 V (typical) limit, the white LED converter
turns off to indicate that a fault condition has occurred through

INT

the

output and system registers. This feature prevents damage
due to an overvoltage if the white LED string fails with an open­circuit condition.

Setting the LED regulation currents depends on the 2-pin
co

ntrol interface used, as described in the following sections.

CTRL0/SDA

CTRL1/SCL

I/O V

DD

STR

EN

INT

INTF

L1

ILED OUT

6 7 14

ILED

CONTRO L

16

15

4

3

11

10

VDD/2

INTERFACE/

CONTROL

× 400
= ILED

10.15V

OVP UVLO

FAULT

REGISTER

THERMAL

PROTECTION

V

DD

2.7V

WATCHDOG

TIMER

× 5200
= TORCH

BIAS

OSCILLATOR

PWM

CONTRO LLER

LED CONTROL

–

+

0.32V

HIGH POWER

× 20800
= FLASH

13

CIN

PGND

D1

LX

9

12

COUT

PGND

HPLED

PGND

7

OUT

1.22V1.22V

I

REF

(ILED)

I

(TORCH)

1.22V1.22V

1 25

SETTSETI

Figure 25. Detailed Block Diagram

Rev. B | Page 13 of 24

REF

1.22V

I

REF

(FLASH)

1.22V

SETF

1.22V/RF1.22V/RT1.22V/RI RFRTRI

8

GND

Tx MASK (OPTIONAL)

6180-004

ADP1653

www.BDTIC.com/ADI

2-BIT LOGIC INTERFACE MODE (INTF = 1)

In 2-bit logic interface mode, the two control pins, CTRL1 and
CTRL0, select whether the part is disabled or operating in indicator
LED mode, torch mode, or flash mode, as outlined in Ta b le 7 .

Table 7. 2-Bit Logic Interface Mode Selection

LED Current

INTF = 1 CTRL1 CTRL0

S

etting Pin

Disabled 0 0 — —
ILED 0 1 SETI ILED = 10 mA
Torch 1 0 SETT HPLED = 125 mA
Flash 1 1 SETF HPLED = 500 mA

The LED current levels for indicator LED mode, torch mode,
and flash mode operation are set with separate external resistors
tied between ground and the SETI, SETT, and SETF pins,
respectively. The resulting reference current into each SETx pin
is equal to 1.22 V/R

. The reference current multiplied by a

SETx

fixed ratio sets the relevant LED current.

Table 8. Reference Current to

LED Current Scaling

INTF = 1 CTRL1 CTRL0 LED Current

Disabled 0 0 —
ILED 0 1 I
Torch 1 0 I
Flash 1 1 I

Alternatively, a default internal current setting is used by tying
the SETx pin high. The default current for each mode of operation
approximately equals the current obtained with a 50 kΩ resistor
tied from the SETx pin to ground.

ST0110000 0 0 0SP

Default Current
(SETx = H)

(SETI) × 400

REF

(SETT) × 5200

REF

(SETF) × 20,800

REF

0=WRITE

0

SUBADDRESSCHIP ADDRESS

Consequently, the LED current resulting from an external

sistor R

re

where I

is given by the following equation:

SETx

k50

LED

DEFAULT

II

×=

DEFAULT

is the LED current resulting from tying the SETx

(1)

R

SETx

pin high.

The values of I

are given in Ta b le 7 for indicator LED mode

DEFAULT

(SETI), torch mode (SETT), and flash mode (SETF) operation.
For accurate LED current settings, the minimum SETx resistor
values should be 25 kΩ (SETI, SETT) or 50 kΩ (SETF).

The flash current can be quickly reduced with an external
log

ic signal (typically 1.8 V logic) by adding a second external
resistor from the SETF pin to the logic signal. Bringing this
digital input from low to high toggles the flash from normal
to reduced current mode by reducing the reference current
supplied to the ADP1653 via the SETF pin (see the

formation section).

In

Applications

I2C INTERFACE MODE (INTF = 0)

The ADP1653 includes an I2C-compatible serial interface for
control of LED current, as well as for readback of system status
registers. The I
write mode). The default value of all four registers is 0x00.
Registers values are reset to the default values when enable is
brought low, or the VDD supply falls below the undervoltage
(UVLO) level.

Figure 26 illustrates the I
content selects which of the four ADP1653 registers is written
to.

Figure 27 shows the I
the data from the register denoted by the subaddress. In this
case, the fault register is read (REG3).

The register definitions are shown in Figure 28. The lowest bit

umber (0) represents the least significant bit, and the highest

n
bit number (7) represents the most significant bit.

2

C chip address is 0x60 (0110 0000 (binary) in

2

C write sequence. The subaddress

2

C read sequence. The ADP1653 sends

ADP1653 RECEIVES DATA

ADP1653 ACK

Figure 26. I

2

C Write Sequence

0=WRITE

ST0110000 0000000110ST0110000 0 1SP

0 1

SUBADDRESSCHIP ADDRESS CHIP ADDRESS

ADP1653 ACK

Figure 27. I

ADP1653 ACK

2

C Read Sequence

Rev. B | Page 14 of 24

ADP1653 ACK

ADP1653 ACK

1=READ

ADP1653 SENDS DAT A

ADP1653 ACK

06180-038

ADP1653 NO ACK

06180-039

ADP1653

www.BDTIC.com/ADI

OUT_SEL

OUTPUT SELECT

CONFIG

CONFIGURAT ION

SOFTW ARE STROBE

TIMER

SW_STROBE

FAULT

FAU LT

CONDITIONS

D7 D6 D5 D4 D3 D2 D1 D0

HPLED<4:0>

HIGH POWER

LED CURRENT

D7 D6 D5 D4 D3 D2 D1 D0

UNUSED

CONFIGURATION

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

UNUSED

Figure 28. I

The LED regulation current levels are controlled by writing to
t

he ILED and HPLED registers. If the ILED register is set to 0,
the ILED regulator is turned off and no current flows through
the indicator LED. If the ILED register is programmed from
1 (001 binary) to 7 (111 binary), the indicator LED is continuously
on, with a current scaled to the register setting given by

I

= 2.5 mA × Code (2)

ILED

where Cod

e is the ILED register setting. Therefore, the ILED

current can be programmed between 2.5 mA and 17.5 mA,
using the full range of codes.

If the HPLED register is set to 0, the HPLED regulator is turned

ff, and no current flows through the high power LED(s). If the

o
HPLED register is programmed from 1 (00001 binary) to 11
(01011 binary), the regulator is in torch mode, and the HPLED
remains continuously on, independent of the state of STR. If the
HPLED register is programmed between 12 (01100 binary) and
31 (11111 binary), the HPLED regulator remains off until enabled
through the strobe input (STR) or a software strobe command.
To program a desired HPLED current with SETF tied high, use
the following equation:

I

= 35 mA + Code × 15 mA (3)

HPLED

where Cod

e is the HPLED register setting.

TMR_SET<3:0>

TMR_CFG

TIMER

UNUSED

FLT_SCP

SHORT-CIRCUIT

FAULT

OVERTEMPERATURE

2

C Register Assignments

TIMER PERI OD

FLT_OT

FAULT

Therefore, the HPLED torch current can be programmed between
50 mA a
current can be programmed between 215 mA and 500 mA for
Code 12 to Code 31.

Additionally, the HPLED current can be adjusted with an external
r

esistor. This feature is primarily intended for limiting the LED
flash current in handset applications when the phone’s power
amplifier transmits, but it can also be used to modify the HPLED
current settings. If an external SETF resistor is present, the HPLED
current is given by

TURNING ON THE FLASH AND WATCHDOG TIMER

A watchdog timer is always active in flash mode to prevent
overstress of the HPLED.

In 2-bit logic interface mode, users select flash operation by
s

etting the CTRL1 pin and the CTRL0 pin high. The watchdog
timer in this mode is fixed at 0.82 sec. Bringing the CTRLx pins
to another state terminates the flash. If the state of the CTRLx
pins remains high for longer than 0.82 sec, flash is automatically
disabled by the watchdog timer, and the interrupt pin (
goes low to indicate a fault.

REG0

ILED<2:0>

INDICATOR LED

CURRENT

REG1

SETTING

REG2

SW_STROBE

SOFTWARE STROBE

ENABLE

REG3

FLT_OV

OVERVOLTAGE

FLT_TMR

TIMEOUT FAULT

FAULT

06180-005

nd 200 mA for Code 1 to Code 11, and the HPLED flash

k50

HPLED

CodeI

mA)15mA35( ××+=

(4)

R

SETF

INT

)

Rev. B | Page 15 of 24

ADP1653

www.BDTIC.com/ADI

In I2C mode, users select flash operation by programming the
HPLED register between 12 (01100 binary) and 31 (11111 binary).
The flash does not turn on until a strobe command is given by
either pulling the STR pin high or by writing a software strobe
command to the appropriate I

There are additional settings for the watchdog timer in I

2

C register.

2

C mode.
The strobe command operates in one of two watchdog timer
modes, timed flash and user-controlled flash, which are
controlled via the state of the timeout configuration
(TMR_CFG) bit of the CONFIG register. If TMR_CFG is set
(1), the flash operates in timed mode. In timed flash, a rising
edge on STR turns on the flash. The flash remains on until the
internal timeout occurs, which is set by the TMR_SET bits of the
CONFIG register, according to the following equation:

t

= 820 ms − Code × 54.6 ms (5)

FLASH

where Cod

e ranges from 0 (0000 binary) to 15 (1111 binary),

allowing for flash periods ranging from 54 ms to 820 ms.

If TMR_CFG is not set (0), the flash operates in user-controlled
tim

er mode. In user-controlled timer mode, the flash remains
on as long as STR is held high. If STR remains high longer than
T

(if TMR_SET = 0, t

FLASH

= 820 ms), the flash is turned off

FLASH

and a fault is set in the watchdog timeout (FLT_TMR) bit of the
FAULT register.

The ADP1653 also offers a software strobe option, allowing the

er to turn on the flash directly through the I

us

2

C interface without
pulling the STR pin high. Setting the SW_STROBE register bit
to 1 initiates a flash cycle. The strobe can operate in either timed
or user-controlled mode, as previously described.

SAFETY FEATURES

Interrupts

For critical system conditions, such as output overvoltage,
watchdog timeout, and overtemperature conditions, the ADP1653
indicates that an interrupt event has occurred by asserting the

INT

active low interrupt output
and should be pulled up to the I/O voltage rail by using a resistor.

2

C interface mode, the system baseband processor can read

In I
the fault register through the I
of the fault condition after sensing that
can clear a fault by writing 0x00 to the OUT_SEL register. This

INT

brings

high and clears the FAULT register.

In 2-bit logic interface mode,
conditions, but I

2

C register readback is not available. To clear

a fault, set CTRL1 and CTRL0 low.

Overvoltage Fault

The ADP1653 contains a comparator at the OUT pin that monitors
the voltage from the high power LED(s) to PGND. If the voltage
exceeds 10.15 V (typical), the ADP1653 shuts down (I

INT

and

goes low. In I2C mode, Bit D0 in the FAULT register
(FLT_OV) is read back as high. The ADP1653 is disabled, and
INT

remains low until the fault is cleared.

INT

.

is an open-drain output

2

C interface to determine the nature

INT

has gone low. Users

INT

goes low for the same fault

< 45 µA)

Q

Timeout Fault

If the 2-bit logic interface is used, the maximum duration for
flash being enabled (CTRL1/CTRL0 =1) is preset to 820 ms.
If CTRL1 and CTRL0 remain high for longer than 820 ms,

INT

goes low and the ADP1653 is disabled.

2

In I

C mode, if TMR_CFG is not set (0), and STR remains high

for longer than t

(see Equation 5),

FLASH

INT

goes low and the

FLT_TMR bit in the FAULT register is read back as high. The

INT

ADP1653 is disabled, and

remains low until the fault is

cleared.

Overtemperature Fault

If the junction temperature of the ADP1653 rises above 155°C,
a thermal protection circuit shuts down the LED driver and

INT

brings
register is read back as high. The ADP1653 is disabled, and

low. In I2C mode, Bit D2 (FLT_OT) of the FAULT

INT

remains low until the fault is cleared.

Short-Circuit Fault

The HPLED pin features short-circuit protection that disables
the ADP1653 if it detects a short circuit to ground at the cathode
of the LED(s). The ADP1653 monitors the HPLED voltage once
the part is enabled in torch mode. If after 820 ms the HPLED
pin remains grounded, a short circuit is detected.

INT

goes low,
and Bit D3 (FLT_SCP) of the FAULT register is read back as high.
Avoid false triggering of the Short Circuit Fault by not changing
the torch current level while the short-circuit detection circuit is
making a measurement of HPLED pin voltage. Do not change
torch setting directly between two non-zero torch levels 750 ms
to 900 ms after the torch has been enabled. To change torch
mode current level between two non-zero torch levels 750 ms to
900 ms after enabling torch mode, use the following sequence:
Torch Current Setting #1
Torc h Cur rent Se t ti n g = 0
Torch Current Setting #2
Torch mode and flash modes can be enabled or disabled at
any time.

Input Undervoltage

The ADP1653 includes an input undervoltage lockout circuit.
If the battery voltage drops below the 2.7 V (typical) input UVLO
threshold, the ADP1653 shuts down and the input current drops to
less than 45 µA to prevent deep discharge of the battery. In this
case, the system register information is lost, and when power is
reapplied, a power-on reset circuit resets the registers to their
default conditions.

Current Limit

The internal LX switch limits battery current by ensuring that
the peak inductor current does not exceed 2.1 A (typical). If the
SETI, SETT, or SETF pins accidentally connect to ground, the
reference current is limited to a maximum of 1 mA.

Rev. B | Page 16 of 24

ADP1653

V

V

×

www.BDTIC.com/ADI

APPLICATIONS INFORMATION

FLASH CURRENT FOLDBACK DURING TRANSMIT PULSE

The ADP1653 allows a fast, 1.8 V logic-enabled foldback of the
flash current, typically enabled shortly before an RF transmit
pulse. This feature extends the life of the battery by preventing
overstress of the battery cell. It also extends the life of the phone
by reducing the maximum instantaneous system current that
can occur, allowing a lower battery operating voltage limit.

2-Bit Logic Interface Mode (INTF = 1)

In 2-bit logic interface mode, the flash current is set with an
external resistor. The 1.22 V reference voltage is buffered to the
SETF pin, generating a reference current across an external SETF
resistor. This reference current is multiplied by a fixed gain to
set the flash current in the HPLED.

A 1.8 V compatible logic signal selects normal or reduced flash

urrent by adjusting the reference current, as shown in Figure 29

c
and Figure 30.

CURRENT
MIRRORS

1.22V

R2

DIGITAL
OUTPUT

TxMASK = 0V

(Nor

mal Operation with R2 Grounded Through Digital Control Signal)

Figure 29. Flash Mode Current Foldback

1.22V/R2

Full current flash mode has a reference current of

V22.1

I

0REF

_

==

R2R1

||

The reference current is multiplied by a fixed gain to give the
ac

tual flash current (see Tabl e 8).

IREF

1.22V

SETF

1.22V/R1

R1

06180-006

R2R1

+×

)(V22.1

R2R1

×

(6)

A logic high to R2 changes the direction of the current in R2.

= IR1 − I

I

REF

I

REF

I

HPLED

R2

V22.1

V22.1

−=

R1

= I

× 20,800 (9)

REF

−

maskTx

R2

(8)

(7)

The ratio of full flash current to reduced flash current for
a 1.8 V log

ic signal is approximately

FlashFull

=

FlashReduced

R2

R1R2

+

(10)

R1

−

2

If R1 = R2 = 100 kΩ, the maximum flash current is 500 mA,

nd the reduced flash current is 125 mA.

a

I2C Mode (INTF = 0)

To allow flash current foldback in I2C mode, the user should
connect a resistor between SETF and ground, and another
resistor from SETF to the logic input, as shown in Figure 29 and
Figure 30. Operation is the same as for the 2-bit logic interface
m

ode, except the flash current is additionally scaled by setting

the HPLED bits in the OUT_SEL register.

Full current flash mode (Tx mask = 0 V) has a flash current of

k50

HPLED

CodeI

mA)15mA35( ××+=

(11)

R

SETF

where:

R

is a parallel combination of R1 and R2.

SETF

Code is the HPLED register setting.

Bring the Tx mask voltage high for reduced reference current.
Ther

efore, the reduced LED current is I

V22.1

I

REF

HPLED

R1

V22.1

−=

−

maskTx

R2

CodeI

mA)15mA35(

(see Equation 13).

HPLED

(12)

I

k50

××+=

REF

(13)

V22.1

CURRENT

MIRRORS

1.22V

1.8V

DIGITAL
OUTPUT

TxMASK = 1.8V

Figure 30. Flash Mode Current Fol

R2

0.6V/R2

dback with 1.8 V Signal Applied to R2

IREF

1.22V

SETF

1.22V/R1

R1

06180-007

Rev. B | Page 17 of 24

ADP1653

V

VVVVVV

www.BDTIC.com/ADI

EXTERNAL COMPONENT SELECTION

Selecting the Inductor

The ADP1653 step-up converter increases the battery voltage to
allow driving one, two, or three LEDs, whose combined voltage
drop is higher than the battery voltage plus the 0.32 V (typical)
current source headroom voltage. This allows the converter to
regulate the HPLED current over the entire battery voltage range
and with a wide variation of LED forward voltage.

Users should choose an inductor value such that the inductor
r

ipple current is approximately 2/5th of the maximum dc input
load current. In general, lower inductance values have higher
saturation current and lower series resistance for a given physical
size. For most applications, an inductor in the range of 1.5 µH
to 3.3 µH works well.

To determine the inductor ripple current, users should first

ulate the switch duty cycle for the step-up converter, which

calc
is determined by the input voltage (V
and Schottky forward voltage (V

), output voltage (V

IN

). V

equals the LED voltage

F

OUT

drop plus 320 mV (typical) overhead for the HPLED current
regulator.

OUT

IN

VV

+

F

(14)

D

−=

1

Solving for D

−+

D

1

IN

−=
+

OUT

OUT

=

F

OUT

INF

VV

+

F

The HPLED (output) current is regulated as low as 50 mA

orch mode) and as high as 500 mA (flash mode). The

(t
maximum dc input current is related to the maximum dc
output current by the following equation:

⎞

⎛

where η i

V

II

⎜

×=

)()(

MAXOUTMAXIN

⎜
⎝

s efficiency (assume η ≈ 0.80 in the two-LED case).

OUT

IN

1

⎟

(15)

×

⎟

ηV

⎠

Choose the initial inductor value by using the equation

⎛

V

IN

=

L

×Δ

L

OUT

⎜
⎜

fI

SW

⎝

OUT

+

⎞

−+

VVV

INF

⎟

(16)

⎟

VV

F

⎠

where:

he inductor value (reduce L to reduce solution size).

L is t

is the switching frequency.

f

SW

ΔI

is the inductor ripple current, typically 2/5th of the

L

maximum dc input current.

is the forward voltage of the Schottky diode.

V

F

OUT

),

The inductor saturation current should be greater than the sum
o

f the dc input current and half the inductor ripple current.
A reduction in the effective inductance due to saturation increases
the inductor current ripple but improves loop stability, reducing
the amount of output capacitance required. Ensure that the peak
inductor current (dc + 1/2 of inductor ripple) is less than the
LX minimum current limit (1.8 A).

Table 9. Recommended Inductors

Value

Vendo r

Toko 2.2 FDSE0312 145 3.1 3 × 3 × 1.2
Toko 2.0 DE2812C 67 1.8 2.8 × 2.8 × 1.2
Toko 3.3 FDSE0312 199 2.6 3 × 3 × 1.2
Coilcraft 2.2 LPS3010 220 1.4 3 × 3 × 1.0
Coilcraft 2.2 LPS3314 100 1.5 3 × 3 × 1.4

(µH)

Part No.

DCR
(mΩ)

ISAT
(A)

Dimensions
L × W × H (mm)

Selecting the Input Capacitor

The ADP1653 requires an input bypass capacitor to supply
transient currents while maintaining constant input and output
voltage. The input capacitor carries the input ripple current,
allowing the input power source to supply only the dc current.
Use an input capacitor with sufficient ripple current rating to
handle the inductor ripple. A 4.7 µF X5R/X7R ceramic capacitor
rated for 6.3 V is the minimum recommended input capacitor.
Increased input capacitance reduces the amplitude of the switching
frequency ripple on the battery. Because of the dc bias charac­teristics of ceramic capacitors, a 0603, 6.3 V X5R/X7R, 10 µF
ceramic capacitor is preferable.

Table 10. Recommended Input Capacitors

Dimensions

W × H

L ×

Vendor Value Par t No.

Murata 10 μF, 6.3 V GRM188R60J106ME47 1.6 × 0.8 × 0.8
TDK 10 μF, 6.3 V C1608JB0J106K 1.6 × 0.8 × 0.8

(mm)

Selecting the Diode

The ADP1653 is a nonsynchronous boost and, as such, requires
an external Schottky rectifier to conduct the inductor current to
the output capacitor and HPLEDs when the LX switch is off.
Ensure that the Schottky peak current rating is greater than the
maximum inductor current. Choose a diode with an average
current rating that is significantly larger than the maximum
LED current. To prevent thermal runaway, derate the Schottky
rectifier to ensure reliable operation at high junction temperatures.
To achieve the best efficiency, select a Schottky diode with a low V

F

.

Rev. B | Page 18 of 24

ADP1653

www.BDTIC.com/ADI

Table 11. Recommended Schottky Diodes

I

I

Vendo r

PEAK

(A)

AVE

(A)

VR
(V)

Part No.

Dimensions
L × W × H (mm)

ST 2 1 23 BAT20J 1.65 × 1.25 × 1.0
Rohm 5 1 20 RB161VA-20 1.9 × 1.3 × 0.6
ON Semi 2 1 20 MBR120LSFT1 2.7 × 1.65 × 0.95
Philips 2 2 20 PMEG2020EJ 1.7 × 1.25 × 0.72

Selecting the Output Capacitor

The output capacitor maintains the output voltage and supplies
the HPLED current when the LX switch is on. It also stabilizes
the loop. A 4.7 µF, 16 V X5R/X7R ceramic capacitor is generally
recommended. The minimum required capacitance for loop
stability for the two-LED and one-LED cases is shown in

Figure 31

and Figure 32, respectively. Choose a capacitor with a capacitance

eater than the minimum shown in Figure 31 and Figure 32

gr
fo

r the worst-case dc bias voltage and temperature condition.

Note that dc bias characterization data is available from

pacitor manufacturers and should be taken into account

ca
when selecting input and output capacitors. 16 V capacitors are
recommended for most two-LED designs. Designs with 1 mm
height restrictions can also use 0603 case size, 16 V capacitors
in parallel.

Table 12. Recommended Output Capacitors

Dimensions

Vendor Value Part No.

L

× W × H (mm)

Murata 4.7 μF, 16 V GRM21BR61C475KA88 2 × 1.25 × 1.25
TDK 4.7 μF, 16 V C2012X5R1C475K 2 × 1.25 × 1.25
Murata 4.7 μF, 10 V GRM219R61A475KE34 2 × 1.25 × 0.95
TDK 4.7 μF, 10 V C1608X5R1A475K 1.6 × 0.8 × 0.8

4.5
OUT = 6.3V, VDD=3.2V

OUT = 6.3V, VDD=4.2V

4.0
OUT = 8.3V, VDD=3.2V
OUT = 8.3V, VDD=4.2V

3.5

3.0

2.5

2.0

1.5

1.0

MINIMUM CAPACI TANCE (µF)

0.5

0

05

100 200 300 400

HPLED CURRENT, 2 LED CASE ( mA)

3.3μH + 20%

2.2μH+20%

OUT = 6.3V, VDD=3.2V
OUT = 6.3V, VDD=4.2V
OUT = 8.3V, VDD=3.2V
OUT = 8.3V, VDD=4.2V

Figure 31. Minimum Output Capacitance for L = 3.3 µH + 20% and

2.2 µH + 20% for Two-LED Designs

L =

4.0

3.5

3.0

2.5

2.0

1.5

1.0

MINIMUM CAPACITANCE (µF)

0.5

OUT = 4.3V, VDD=4.2V

OUT = 4.3V, VDD=3.2V

0

0 500

50 100 150 200 250 300 350 400 450

HPLED CURRENT, 1 LED CASE (mA)

OUT = 3.3V, VDD=3.2V

2.2μH + 20%

Figure 32. Minimum Output Capacitance for L = 2.2 µH + 20%

for One-LED Design

5.0

4.5

4.0

3.5

3.0

2.5

2.0

CAPACITANCE (µF)

1.5

1.0

0.5

0

01

Figure 33. DC Bias Characteristic of a 10 V, 4.7 F Ceramic Capacitor

–40°C (10V)

+85°C (10V)

246810

DC BIAS (V)

00

6180-033

06180-030

2

6180-008

Rev. B | Page 19 of 24

ADP1653

www.BDTIC.com/ADI

PCB LAYOUT

Good PCB layout is important to maximize efficiency and to
minimize noise and electromagnetic interference (EMI). An
example PCB layout is shown in Figure 34. Refer to the

lowing guidelines for adjustments to the suggested layout.

fol

The high current paths are shown in Figure 35. Place components

hat are on high current paths first. To minimize large current

t
loops, place the input capacitor, inductor, Schottky diode, and
output capacitor as close as possible to each other and to the
ADP1653 using wide tracks (use shapes where possible).

Use separate analog and power ground planes. The analog ground
p

lane is used to ground the SETI, SETT, and SETF resistors and

for any digital connections (that is, INTF = 0 = AGND).

Use the power ground plane to ground the power components.

onnect the input capacitor, output capacitor, and the PGND pin

C
(Pin 12) to the PGND plane. If it is not possible to make the PGND
plane continuous, use a number of low inductance vias to connect

V

IN

INPUT CAPACITO R

the planes. Connect the AGND and PGND planes at the paddle
or close to the paddle of the ADP1653.

The SETI, SETT, and SETF resistors set a small reference current
t

hat generates the LED current. To minimize noise and current
error, connect the SETI, SETT, and SETF resistors as close as
possible to the ADP1653. Connect the other end of the resistors
directly to the AGND plane.

Connect the output capacitor to the high power LED(s), using

wide, low resistance trace. Connect the bottom of the LED string

a
back to the HPLED pin (Pin 9) with a wide trace. The GND pin
(Pin 8) is connected to the source of the current regulator NFET.
Ensure that there is a low impedance back to the battery for the
high power LED current by connecting the GND pin to the PGND
plane with a low impedance via(s) close to the GND pin.

The OUT pin is used for soft start and contains a comparator

r overvoltage protection. Connect the output capacitor back

fo
to the OUT pin (Pin 7) with a direct trace. The trace does not
need to be wide.

GND

PGND PLANE

AGND PLANE

SETT RESISTOR

R6

SETF RESISTOR

R5

R4

Tx MASK RESISTOR

SETI RESISTOR

R7

INDUCTOR

ADP1653

C1

L1

SCHOTTKY DI ODE

D1

OUTPUT CAPACIT OR

C2

PGND

SEE
NOTE 1

HIGH POWER

LED

D3

INDICATOR LED

D4

HIGH POWER

LED

D2

PGND

NOTES

1. CONNECT THE AGND AND PGND PLANES CLOSE TO PADDLE. T HIS IS THE GND RETURN PATH F OR HPLED CURRENT ,
SO A REASONABLY LARGE VIA SHOULD BE USED T O CONNECT THE AGND AND PGND PLANES .

Figure 34. Example Layout of ADP1653 Driving Two White LEDs, Pink = GND

Rev. B | Page 20 of 24

06180-034

Layer, Gray/Green = Top Layer (a One-LED Layout Is Similar)

ADP1653

A

www.BDTIC.com/ADI

16 15 14 13

TR

N

S

E

1

OPTIONAL

Tx MASK

SETT

2

SETF

ADP1653

3

CTRL1/SCL

4

CTRL0/SDA

ILED

SETI

5 6 7 8

V

DD

Figure 35. Typical Applications Circuit (

V

OUT

DD

INPUT VOLT

X

L

PGND

INT

INTF

HPLED

GND

2.2µH

12

11

10

9

GE = 2.75V TO 5.5V

4.7µF

4.7µF

ONE

OR
TWO
LEDs

High Current Lines Are Shown in Bold)

06180-035

Rev. B | Page 21 of 24

ADP1653

R

R

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

0.50

0.40

PIN 1

INDICATO

0.90

0.85

0.80

SEATING

PLANE

12° MAX

3.00

BSC SQ

TOP

VIEW

0.30

0.23

0.18

*

COMPLIANT
EXCEPT FOR EXPOSED PAD DIMENSION.

2.75

BSC SQ

0.80 MAX

0.65 TYP

0.05 MAX

0.02 NOM

0.20 REF

TO

JEDEC STANDARDS MO-220-VEED-2

0.45

0.50

BSC

1.50 REF

0.60 MAX

12

9

13

(BOTTOM VIEW)

8

Figure 36. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

3 mm × 3 mm Body, Very Thin Quad (CP-16-3)

Dimensions shown in millimeters

EXPOSED

PAD

0.30

16

1

4

5

N

P

I

D

N

I

*

1.65

1.50 SQ

1.35

0.25 MIN

1

O

C

I

A

T

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

ADP1653ACPZ-R71−40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-3 L3H
ADP1653-EVALZ

1

Z = RoHS Compliant Part.

1

Evaluation Board

Rev. B | Page 22 of 24

ADP1653

www.BDTIC.com/ADI

NOTES

Rev. B | Page 23 of 24

ADP1653

www.BDTIC.com/ADI

NOTES

©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06180-0-9/07(B)

Rev. B | Page 24 of 24