Datasheet ADP124, ADP125 Datasheet (ANALOG DEVICES)

Current, CMOS Linear Regulators

ADP124/ADP125

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

Trademarks and registered trademarks are the property of their respective owners.

Fax: [phone] ©2009–2012 Analog Devices, Inc. All rights reserved.

2

4

1

5

8

V

OUT

= 3.3V V

IN

= 5.5V

VOUT

VOUT VIN

VOUT
SENSE

NC

GND

VIN

EN

C2 C1

ADP124

OFF

ON

7

3

6

08476-001

2

4

1

5

8

V

OUT

= 3.3V

V

IN

= 5.5V

VOUT

VOUT VIN

ADJ

NC

GND

VIN

EN

C2 R1

R2

C1

ADP125

7

3 6

08476-002

OFF

ON

Data Sheet

FEATURES

Input voltage supply range: 2.3 V to 5.5 V
500 mA maximum output current
Fixed and adjustable output voltage versions
1% initial accuracy
Up to 31 fixed-output voltage options available

from 1.75 V to 3.3 V
Adjustable-output voltage range from 0.8 V to 5.0 V
Very low dropout voltage: 130 mV
Low quiescent current: 45 µA
Low shutdown current: <1 µA
Excellent PSRR performance: 60 dB at 100 kHz
Excellent load/line transient response
Optimized for small 1.0 μF ceramic capacitors
Current limit and thermal overload protection
Logic controlled enable
Compact 8-lead exposed paddle MSOP and LFCSP packages

APPLICATIONS

Digital camera and audio devices
Portable and battery-powered equipment
Automatic meter reading (AMR) meters
GPS and location management units
Medical instrumentation
Point of load power

5.5 V Input, 500 mA, Low Quiescent

TYPICAL APPLICATION CIRCUITS

Figure 1. ADP124 with Fixed Output Voltage

Figure 2. ADP 125 with Adjustable Output Voltage

GENERAL DESCRIPTION

The ADP124/ADP125 are low quiescent current, low dropout
linear regulators. They are designed to operate from an input
voltage between 2.3 V and 5.5 V and to provide up to 500 mA
of output current. The low 130 mV dropout voltage at a 500 mA
load improves efficiency and allows operation over a wide input
voltage range.

The low 210 μA of quiescent current with a 500 mA load makes the
ADP124/ADP125 ideal for battery-operated portable equipment.

The ADP124 is capable of 31 fixed-output voltages from 1.75 V
to 3.3 V. The ADP125 is the adjustable version of the device and
allows the output voltage to be set between 0.8 V and 5.0 V by
an external voltage divider.

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or othe r
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

The ADP124/ADP125 are specifically designed for stable operation
with tiny 1 µF ceramic input and output capacitors to meet the
requirements of high performance, space constrained applications.

The ADP124/ADP125 have an internal soft start that gives a
constant start-up time of 350 µs. Short-circuit protection and
thermal overload protection circuits prevent damage in adverse
conditions. The ADP124/ADP125 are available in 8-lead
exposed paddle MSOP and LFCSP packages. When compared
with the standard MSOP and LFCSP packages, the exposed
paddle MSOP and LFCSP packages have lower thermal resistance
(θ

). The lower thermal resistance package allows the ADP124/

JA

ADP125 to meet the needs of a variety of portable applications
while minimizing the rise in junction temperature.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]

www.analog.com

ADP124/ADP125 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Typical Application Circuits ............................................................ 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Recommended Capacitor Specifications ................................... 4

Absolute Maximum Ratings ............................................................ 5

Thermal Data ................................................................................ 5

Thermal Resistance ...................................................................... 5

ESD Caution .................................................................................. 5

Pin Configurations and Function Descriptions ........................... 6

REVISION HISTORY

6/12—Rev. B to Rev. C

Changes to Table 3 ............................................................................. 5

Updated Outline Dimensions ........................................................ 17

4/12—Rev. A to Rev. B

Updated Outline Dimensions ........................................................ 17

Changes to Ordering Guide ........................................................... 18

9/10—Rev. 0 to Rev. A

Added 8-Lead LFCSP Package ..................................... Throughout

Added Figure 4 and Figure 6 (Renumbered Sequentially) ......... 6

Changes to Thermal Conditions Section and Table 6 ............... 14

Added Table 7 .................................................................................. 14

Changes to Junction Temperature Calculations Section ........... 15

Added Figure 44 .............................................................................. 16

Updated Outline Dimensions ....................................................... 17

Changes to Ordering Guide .......................................................... 18

12/09—Revision 0: Initial Version

Typical Performance Characteristics ..............................................7

Theory of Operation ...................................................................... 11

Applications Information .............................................................. 12

Capacitor Selection .................................................................... 12

Undervoltage Lockout ............................................................... 13

Enable Feature ............................................................................ 13

Current Limit and Thermal Overload Protection ................. 14

Thermal Considerations ............................................................ 14

Junction Temperature Calculations ......................................... 15

Printed Circuit Board Layout Considerations........................ 16

Outline Dimensions ....................................................................... 17

Ordering Guide .......................................................................... 18

Rev. C | Page 2 of 20

Data Sheet ADP124/ADP125

GND

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

J

OUT

J

OUT

OUT

OUT

OUT

I

OUT

= 1 mA to 500 mA, TJ = −40°C to +125°C

0.001

%/mA

I-BIAS

DROPOUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

STA RT-UP

OUT

LIMIT

I-LEAKAGE

RISE

FAL L

HYS

SPECIFICATIONS

Unless otherwise noted, VIN = (V
C

= 1.0 µF; TA = 25°C.

OUT

Table 1.

Parameter Symbol Test Conditions Min Typ Max Unit

INPUT VOLTAGE RANGE VIN 2.3 5.5 V
OPERATING SUPPLY CURRENT1 I

I

I

I

I

I

I

I

SHUTDOWN CURRENT ISD EN = GND 0.1 µA

EN = GND, TJ = −40°C to +125°C 1 µA

OUTPUT VOLTAGE ACCURACY2 V

Fixed Output I

100 µA < I

Adjustable Output

I

100 µA < I

LINE REGULATION ∆V
LOAD REGULATION3 ∆V

+ 0.5 V) or 2.3 V, whichever is greater; ADJ connected to VOUT; I

OUT

I

= 0 µA 45 µA
= 0 µA, TJ = −40°C to +125°C 105 µA
= 1 mA 60 µA
= 1 mA, TJ = −40°C to +125°C 120 µA
= 250 mA 160 µA
= 250 mA, TJ = −40°C to +125°C 210 µA
= 500 mA 210 µA
= 500 mA, TJ = −40°C to +125°C 280 µA

= 10 mA −1 +1 %

< 500 mA, VIN = (V

T

OUT

= −40°C to +125°C

+ 0.5 V) to 5.5 V,

OUT

= 10 mA 0.495 0.500 0.505 V

< 500 mA, VIN = 2.3 V to 5.5 V,

T

= −40°C to +125°C

OUT

/∆VIN VIN = VIN = 2.3 V to 5.5 V, TJ = −40°C to +125°C −0.05 +0.05 %/V
/∆I

I

= 1 mA to 500 mA 0.0005 %/mA

= 10 mA; CIN = 1.0 µF;

OUT

−2 +1.5 %

0.485 0.500 0.515 V

ADJ INPUT BIAS CURRENT ADJ
DROPOUT VOLTAGE4 V

I

I

I

I

I

I

START-UP TIME5 t
CURRENT LIMIT THRESHOLD6 I

2.3 V ≤ VIN ≤ 5.5 V, ADJ connected to VOUT 15 nA

= 10 mA, V

> 2.3 V 3 mV
= 10 mA, TJ = −40°C to +125°C 5 mV
= 250 mA, V

> 2.3 V

65 mV
= 250 mA, TJ = −40°C to +125°C 120 mV
= 500 mA, V

> 2.3V

130 mV
= 500 mA, TJ = −40°C to +125°C 230 mV

V

= 3.0 V 350 µs

550 750 1000 mA

THERMAL SHUTDOWN

Thermal Shutdown Threshold TSSD TJ rising 150
Thermal Shutdown Hysteresis TS

15

SD-HYS

EN INPUT

EN Input Logic High VIH 2.3 V ≤ VIN ≤ 5.5 V 1.2 V
EN Input Logic Low VIL 2.3 V ≤ VIN ≤ 5.5 V 0.4 V
EN Input Leakage Current V

EN = VIN or GND 0.1 µA

EN = VIN or GND, TJ = −40°C to +125°C 1 µA

UNDERVOLTAGE LOCKOUT UVLO

Input Voltage Rising UVLO
Input Voltage Falling UVLO
Hysteresis UVLO

TJ = −40°C to +125°C 2.1 V

TJ = −40°C to +125°C 1.5 V

TA = 25°C 125 mV

°C
°C

Rev. C | Page 3 of 20

ADP124/ADP125 Data Sheet

NOISE

OUT

OUT

OUT

OUT

10 Hz to 100 kHz, VIN = 5.5 V, V

OUT

= 4.2V

65 µV rms

IN

OUT

Capacitor ESR

R

ESR

TA = −40°C to +125°C

0.001

1 Ω

Parameter Symbol Test Conditions Min Typ Max Unit

OUTPUT NOISE OUT
10 Hz to 100 kHz, VIN = 5.5 V, V

10 Hz to 100 kHz, VIN = 5.5 V, V
10 Hz to 100 kHz, VIN = 5.5 V, V

10 Hz to 100 kHz, VIN = 5.5 V, V

= 1.2 V 25 µV rms
= 1.8 V 35 µV rms
= 2.5 V 45 µV rms
= 3.3 V 55 µV rms

POWER SUPPLY REJECTION RATIO

(V

= V

+1V)

1

The current from the external resistor divider network in the case of adjustable voltage output (as with the ADP125) should be subtracted from the ground current measured.

2

Accuracy when VOUT is connected directly to ADJ. When VOUT voltage is set by external feedback resistors, absolute accuracy in adjust mode depends on the tolerances of

the resistors used.

3

Based on an endpoint calculation using 1 mA and 500 mA loads.

4

Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output voltages

greater than 2.3 V.

5

Start-up time is defined as the time between the rising edge of EN to VOUT being at 90% of its nominal value.

6

Current limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.3 V

output voltage is defined as the current that causes the output voltage to drop to 90% of 3.3 V, or 2.97 V.

PSRR 10 kHz to 100 kHz, V

= 1.8 V, 2.5 V, 3.3 V 60 dB

OUT

RECOMMENDED CAPACITOR SPECIFICATIONS

Table 2.

Parameter Symbol Test Conditions Min Typ Max Unit

Minimum Input and Output

Capacitance

1

The minimum input and output capacitance should be greater than 0.70 µF over the full range of operating conditions. The full range of operating conditions in the

application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended;
Y5V and Z5U capacitors are not recommended for use with this LDO.

1

TA = −40°C to +125°C 0.70 µF

CAP

MIN

Rev. C | Page 4 of 20

Data Sheet ADP124/ADP125

ADJ to GND

−0.3 V to +6.5 V

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

VIN to GND −0.3 V to +6.5 V

EN to GND −0.3 V to +6.5 V
VOUT to GND −0.3 V to VIN
Storage Temperature Range −65°C to +150°C
Operating Ambient Temperature Range −40°C to +85°C
Operating Junction Temperature Range −40°C to +125°C
Soldering Conditions JEDEC J-STD-020

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL DATA

Absolute maximum ratings apply individually only, not in
combination. The ADP124/ADP125 can be damaged when the
junction temperature limits are exceeded. Monitoring ambient
temperature does not guarantee that T
specified temperature limits. In applications with high power
dissipation and poor thermal resistance, the maximum ambient
temperature may have to be limited.

In applications with moderate power dissipation and low PCB
thermal resistance, the maximum ambient temperature can
exceed the maximum limit as long as the junction temperature
is within specification limits. The junction temperature (T
the device is dependent on the ambient temperature (T
power dissipation of the device (P
thermal resistance of the package (θ

Maximum junction temperature (T
ambient temperature (T

) and power dissipation (PD) using the

A

formula

T

= TA + (PD × θJA)

J

The junction-to-ambient thermal resistance (θ
is based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on the

will remain within the

J

J

), the

A

), and the junction-to-ambient

D

).

JA

) is calculated from the

J

) of the package

JA

) of

application and board layout. In applications in which high maxi­mum power dissipation exists, close attention to thermal board
design is required. The value of θ

may vary, depending on PCB

JA

material, layout, and environmental conditions. The specified
values of θ

are based on a 4-layer, 4 inch × 3 inch circuit board.

JA

Refer to JESD 51-7 for detailed information on the board
construction.

Ψ

is the junction-to-board thermal characterization parameter

JB

and is measured in °C/ W. The Ψ

of the package is based on

JB

modeling and calculation using a 4-layer board. The Guidelines for
Reporting and Using Package Thermal Information: JESD51-12
states that thermal characterization parameters are not the same
as thermal resistances. Ψ

measures the component power flowing

JB

through multiple thermal paths rather than a single path as in
thermal resistance, θ

. Therefore, ΨJB thermal paths include

JB

convection from the top of the package as well as radiation from
the package—factors that make Ψ
applications. Maximum junction temperature (T
from the board temperature (T

more useful in real-world

JB

) is calculated

J

) and power dissipation (PD)

B

using the formula

T

= TB + (PD × ΨJB)

J

Refer to JESD51-8 and JESD51-12 for more detailed information
about Ψ

.

JB

THERMAL RESISTANCE

θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.

Table 4. Thermal Resistance

Package Type θJA ΨJB Unit

8-Lead MSOP 102.8 31.8 °C/W
8-Lead LFCSP 68.9 44.1 °C/W

ESD CAUTION

Rev. C | Page 5 of 20

ADP124/ADP125 Data Sheet

VOUT

1

VOUT

2

VOUT SENSE

3

GND

4

VIN

8

VIN

7

NC

6

EN

5

NOTES

1. NC = NO CONNEC T.

2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND.

ADP124

TOP VIEW

(Not to Scale)

08476-003

TOP VIEW

(Not to Scale)

ADP124

3VOUT SENSE

4GND

1VOUT

2VOUT

6 NC
5 EN

8 VIN
7 VIN

08476-105

NOTES

1. NC = NO CONNEC T.

2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND.

VOUT

1

VOUT

2

ADJ

3

GND

4

VIN

8

VIN

7

NC

6

EN

5

ADP125

TOP VIEW

(Not to Scale)

08476-004

NOTES

1. NC = NO CONNEC T.

2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND.

TOP VIEW

(Not to Scale)

ADP125

3ADJ

4GND

1VOUT

2VOUT

6 NC
5 EN

8 VIN
7 VIN

08476-106

NOTES

1. NC = NO CONNEC T.

2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND.

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 3. ADP124 Fixed Output MSOP Pin Configuration

Figure 4. ADP124 Fixed Output LFCSP Pin Configuration

Figure 5. ADP125 Adjustable Output MSOP Pin Configuration

Figure 6. ADP125 Adjustable Output LFCSP Pin Configuration

Table 5. Pin Function Descriptions

Mnemonic
Pin No. ADP124 ADP125 Description

1 VOUT VOUT Regulated Output Voltage. Bypass VOUT to GND with a 1 µF or greater capacitor.
2 VOUT VOUT Regulated Output Voltage. Bypass VOUT to GND with a 1 µF or greater capacitor.
3 VOUT SENSE N/A Feedback Node for the Error Amplifier. Connect to VOUT.
N/A ADJ Feedback Node for the Error Amplifier. Connect the midpoint of an external divider from VOUT to GND

to this pin to set the output voltage.
4 GND GND Ground.
5 EN EN Enable Input. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For

automatic startup, connect EN to VIN.
6 NC NC No Connect. This pin is not connected internally.
7 VIN VIN Regulator Input Supply. Bypass VIN to GND with a 1 µF or greater capacitor.
8 VIN VIN Regulator Input Supply. Bypass VIN to GND with a 1 µF or greater capacitor.
EPAD EPAD The exposed pad must be connected to ground.

Rev. C | Page 6 of 20

Data Sheet ADP124/ADP125

3.270

3.275

3.280

3.285

3.290

3.295

3.300

3.305

3.310

–40 –5 +25 +85 +125

JUNCTION T E M P E R ATURE (°C)

V

OUT

(V)

I

OUT

= 100µA

I

OUT

= 1mA

I

OUT

= 10mA

I

OUT

= 100mA

I

OUT

= 300mA

I

OUT

= 500mA

08476-005

3.303

3.304

3.305

3.306

3.307

3.308

3.309

0.1 1 10 100 1000
I

OUT

(mA)

V

OUT

(V)

08476-006

3.292

3.294

3.296

3.298

3.300

3.302

3.304

3.306

3.308

3.310

3.50 4.00 4.50 5.00 5.50

V

IN

(V)

V

OUT

(V)

I

OUT

= 100µA

I

OUT

= 1mA

I

OUT

= 10mA

I

OUT

= 100mA

I

OUT

= 300mA

I

OUT

= 500mA

08476-007

50

100

150

200

250

300

GROUND CURRENT ( µ A)

–40 –5 +25 +85 +125

JUNCTION T E M P E R ATURE (°C)

I

OUT

= 100µA

I

OUT

= 1mA

I

OUT

= 10mA

I

OUT

= 100mA

I

OUT

= 300mA

I

OUT

= 500mA

08476-008

0

50

100

150

200

250

0.1 1 10 100 1000
I

LOAD

(mA)

GROUND CURRENT ( µ A)

08476-009

50

70

90

110

130

150

170

190

210

230

250

3.50 4.00 4.50 5.00 5.50
VIN (V)

GROUND CURRENT ( µ A)

I

OUT

= 100µA

I

OUT

= 1mA

I

OUT

= 10mA

I

OUT

= 100mA

I

OUT

= 300mA

I

OUT

= 500mA

08476-010

TYPICAL PERFORMANCE CHARACTERISTICS

VIN = 3.8 V, V

= 3.3V, I

OUT

= 10 mA, CIN = 1.0 µF, C

OUT

= 1.0 µF, TA = 25°C, unless otherwise noted.

OUT

Figure 7. Output Voltage vs. Junction Temperature

Figure 8. Output Voltage vs. Load Current

Figure 10. Ground Current vs. Junction Temperature

Figure 11. Ground Current vs. Load Current

Figure 9. Output Voltage vs. Input Voltage

Figure 12. Ground Current vs. Input Voltage

Rev. C | Page 7 of 20

ADP124/ADP125 Data Sheet

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

–50 –25 0 25 50 75 100 125

TEMPERATURE (°C)

SHUTDOWN CURRE NT (µA)

V

IN

= 3.80

VIN = 4.20

V

IN

= 4.40

VIN = 5.00

VIN = 5.20

VIN = 5.40

VIN = 5.50

08476-011

0

20

40

60

80

100

120

1 10 100 1000

I

OUT

(mA)

DROPOUT ( mV )

08476-012

0

50

100

150

200

250

300

350

400

450

3.00 3.10 3.20 3.30 3.40 3.50 3.60 3.70
V

IN

(V)

I

GND

(µA)

I

OUT

= 100mA

I

OUT

= 300mA

I

OUT

= 500mA

I

OUT

= 10mA

08476-013

2.95

3.00

3.05

3.10

3.15

3.20

3.25

3.30

3.35

3.00 3.10 3.20 3.30 3.40 3.50 3.60
V

IN

(V)

V

OUT

(V)

I

OUT

= 100mA

I

OUT

= 300mA

I

OUT

= 500mA

I

OUT

= 10mA

08476-014

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

10

100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

PSRR (dB)

I

OUT

= 100µA

V

IN

= V

OUT

+1V

V

RIPPLE

= 50mV

C

IN

= C

OUT

= 1µF

I

OUT

= 1mA

I

OUT

= 10mA

I

OUT

= 100mA

I

OUT

= 300mA

I

OUT

= 500mA

08476-015

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

PSRR (dB)

I

OUT

= 100µA

V

IN

= V

OUT

+1V

V

RIPPLE

= 50mV

C

IN

= C

OUT

= 1µF

I

OUT

= 1mA

I

OUT

= 10mA

I

OUT

= 100mA

I

OUT

= 300mA

I

OUT

= 500mA

08476-016

Figure 13. Shutdown Current vs. Temperature at Various Input Voltages

Figure 14. Dropout Voltage vs. Load Current

Figure 16. Output Voltage vs. Input Voltage (in Dropout)

Figure 17. Power Supply Rejection Ratio v s. Frequency, V

= 2.8 V, VIN = 3.8 V

OUT

Figure 15. Ground Current vs. Input Voltage (in Dropout)

Figure 18. Power Supply Rejection Ratio v s. Frequency, V

= 3.3 V, VIN = 4.3 V

OUT

Rev. C | Page 8 of 20

Data Sheet ADP124/ADP125

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

PSRR (dB)

I

OUT

= 100µA

V

IN

= V

OUT

+ 1V

V

RIPPLE

= 50mV

C

IN

= C

OUT

= 1µF

I

OUT

= 1mA

I

OUT

= 10mA

I

OUT

= 100mA

I

OUT

= 300mA

I

OUT

= 500mA

08476-017

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

PSRR (dB)

V

OUT

= 2.8V, I

OUT

= 10mA

V

IN

= V

OUT

+ 1V

V

RIPPLE

= 50mV

C

IN

= C

OUT

= 1µF

V

OUT

= 3.3V, I

OUT

= 10mA

V

OUT

= 4.2V, I

OUT

= 10mA

V

OUT

= 2.8V, I

OUT

= 500mA

V

OUT

= 3.3V, I

OUT

= 500mA

V

OUT

= 4.2V, I

OUT

= 500mA

08476-018

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

10 100 1k 10k 100k 1M 10M

PSRR (dB)

FREQUENCY (Hz)

V

IN

= 3.1V, I

OUT

= 10mA

V

IN

= 3.3V, I

OUT

= 10mA

VIN = 3.8V, I

OUT

= 10mA

VIN = 4.8V, I

OUT

= 10mA

V

IN

= 3.1V, I

OUT

= 500mA

VIN = 3.3V, I

OUT

= 500mA

VIN = 3.8V, I

OUT

= 500mA

VIN = 4.8V, I

OUT

= 500mA

08476-019

0

1

2

3

4

5

10 100 1k 10k 100k

FREQUENCY ( Hz )

NOISE (µv/√Hz)

08476-020

V

OUT

= 2.8V

V

OUT

= 3.3V

V

OUT

= 4.2V

20

25

30

35

40

45

50

55

60

65

70

0.001 0.01 0.1 1 10 100 1k
I

LOAD

(mA)

RMS NOISE (µV)

V

OUT

= 2.8V

V

OUT

= 3.3V

V

OUT

= 4.2V

08476-021

08476-022

M40.0µs A CH1 200mA

1

2

T 9.800%

VIN = 4V
V

OUT

= 3.3V

V

OUT

1mA TO 500mA LO AD S TEP

CH1 500mA Ω

B

W

CH2 50.0mV

B

W

I

OUT

Figure 19. Power Supply Rejection Ratio v s. Frequency, V

= 4.2 V, VIN = 5.2 V

OUT

Figure 22. Output Noise Spectrum, V

= 5 V

IN

Figure 20. Power Supply Rejection Ratio vs. Frequency,

Various Output Voltages and Load Currents

Figure 21. Power Supply Rejection Ratio vs. Headroom Voltage (VIN − V

V

OUT

= 2.8 V

Figure 23. Output Noise vs. Load Current and Output Voltage, VIN = 5 V

OUT

),

Figure 24. Load Transient Response, C

OUT

= 1 μF

Rev. C | Page 9 of 20

ADP124/ADP125 Data Sheet

08476-023

M40.0µs A CH1 200mA

1

2

T 9.800%

VIN = 4V
V

OUT

= 3.3V

V

OUT

I

OUT

1mA TO 500mA LO AD S TEP

CH1 500mA Ω

B

W

CH2 50.0mV

B

W

08476-024

M10.0µs A CH3 2. 36V

2

1

T 9.600%

V

OUT

4V TO 4.5V VOLTAGE STEP

CH1 1.00V

B

W

CH2 2.00mV

B

W

V

IN

08476-025

M10.0µs A CH3 200mA

2

1

T 9.800%

V

OUT

V

IN

4V TO 4.5V VOLTAGE STEP

CH1 1.00V

B

W

CH2 2.00mV

B

W

Figure 25. Load Transient Response, C

= 4.7 μF

OUT

Figure 27. Line Transient Response, Load Current = 500 mA

Figure 26. Line Transient Response, Load Current = 1 mA

Rev. C | Page 10 of 20

Data Sheet ADP124/ADP125

SHORT CIRCUIT,

UVLO,AND

THERMAL
PROTECT

0.5V REFERE NCE

ADP124

SHUTDOWN

VIN VOUT

R1

R2

GND

NOTES

1. R1 AND R2 ARE INTERNAL RESISTORS, AVAILABLE ON
THE ADP 124 ONLY.

EN

VOUT SENSE

08476-121

SHORT CIRCUIT,

UVLO,AND

THERMAL
PROTECT

0.5V REFERE NCE

SHUTDOWN

VIN VOUT

GND

EN

08476-122

ADP125

ADJ

THEORY OF OPERATION

The ADP124/ADP125 are low quiescent current, low dropout
linear regulators that operate from 2.3 V to 5.5 V and can provide
up to 500 mA of output current. Drawing a low 210 µA of quies­cent current (typical) at full load makes the ADP124/ADP125
ideal for battery-operated portable equipment. Shutdown current
consumption is typically 100 nA.

Optimized for use with small 1 µF ceramic capacitors, the
ADP124/ADP125 provide excellent transient performance.

Internally, the ADP124/ADP125 consist of a reference, an error
amplifier, a feedback voltage divider, and a PMOS pass transistor.
Output current is delivered via the PMOS pass device, which is
controlled by the error amplifier. The error amplifier compares
the reference voltage with the feedback voltage from the output
and amplifies the difference. If the feedback voltage is lower than
the reference voltage, the gate of the PMOS device is pulled lower,
allowing more current to pass and increasing the output voltage.
If the feedback voltage is higher than the reference voltage, the
gate of the PMOS device is pulled higher, allowing less current
to pass and decreasing the output voltage.

The adjustable ADP125 has an output voltage range of 0.8 V to

5.0 V. The output voltage is set by the ratio of two external resistors,
as shown in Figure 2. The device servos the output to maintain
the voltage at the ADJ pin at 0.5 V referenced to ground. The
current in R1 is then equal to 0.5 V/R2 and the current in R1 is
the current in R2 plus the ADJ pin bias current. The ADJ pin
bias current, 15 nA at 25°C, flows through R1 into the ADJ pin.

The output voltage can be calculated using the equation:

V

= 0.5 V(1 + R1/R2) + (ADJ

OUT

I-BIAS

)(R1)

The value of R1 should be less than 200 kΩ to minimize errors
in the output voltage caused by the ADJ pin bias current. For
example, when R1 and R2 each equal 200 kΩ, the output voltage
is 1.0 V. The output voltage error introduced by the ADJ pin
bias current is 3 mV or 0.3%, assuming a typical ADJ pin bias
current of 15 nA at 25°C.

Note that in shutdown, the output is turned off and the divider
current is 0.

The ADP124/ADP125 use the EN pin to enable and disable the
VOUT pin under normal operating conditions. When EN is high,
VOUT turns on; when EN is low, VOUT turns off. For automatic
startup, EN can be tied to VIN.

Figure 28. ADP124 Internal Block Diagram (Fixed Output)

Figure 29. ADP125 Internal Block Diagram (Adjustable Output)

Rev. C | Page 11 of 20

ADP124/ADP125 Data Sheet

08476-028

M400ns A CH1 200mA

1

2

T 13.20%

VIN = 4V
V

OUT

= 3.3V

V

OUT

I

OUT

1mA TO 500mA LO AD S TEP

CH1 500mA Ω

B

W

CH2 50.0mV

B

W

08476-029

M400ns A CH1 200mA

1

2

T 13.60%

V

IN

= 4V

V

OUT

= 3.3V

V

OUT

I

OUT

1mA TO 500mA LO AD S TEP

CH1 500mA Ω

B

W

CH2 50.0mV

B

W

0.70

0.75

0.80

0.85

0.90

0.95

1.00

1.05

1.10

0 1 2 3 4 5 6 7

BIAS VOLTAGE (V)

CAPACITANCE (µF)

08476-030

APPLICATIONS INFORMATION

CAPACITOR SELECTION

Output Capacitor

The ADP124/ADP125 are designed for operation with small,
space-saving ceramic capacitors, but these devices can function
with most commonly used capacitors as long as care is taken to
ensure an appropriate effective series resistance (ESR) value. The
ESR of the output capacitor affects the stability of the LDO control
loop. A minimum of 0.70 µF capacitance with an ESR of 1 Ω or
less is recommended to ensure stability of the ADP124/ADP125.
The transient response to changes in load current is also affected by
the output capacitance. Using a larger value of output capacitance
improves the transient response of the ADP124/ADP125 to
dynamic changes in load current. Figure 30 and Figure 31 show
the transient responses for output capacitance values of 1 µF and

4.7 µF, respectively.

Input Bypass Capacitor

Connecting a 1 µF capacitor from VIN to GND reduces the circuit
sensitivity to the printed circuit board (PCB) layout, especially
when a long input trace or high source impedance is encountered.
If greater than 1 µF of output capacitance is required, the input
capacitor should be increased to match it.

Input and Output Capacitor Properties

Any good quality ceramic capacitors can be used with the
ADP124/ADP125, as long as the capacitor meets the minimum
capacitance and maximum ESR requirements. Ceramic capacitors
are manufactured with a variety of dielectrics, each with different
behavior over temperature and applied voltage. Capacitors must
have an adequate dielectric to ensure the minimum capacitance
over the necessary temperature range and dc bias conditions.
Using an X5R or X7R dielectric with a voltage rating of 6.3 V or
10 V is recommended. However, using Y5V and Z5U dielectrics
are not recommended for any LDO, due to their poor temperature
and dc bias characteristics.

Figure 32 depicts the capacitance vs. capacitor voltage bias charac­teristics of an 0402, 1 µF, 1 0 V X5R capacitor. The voltage stability
of a capacitor is strongly influenced by the capacitor size and the
voltage rating. In general, a capacitor in a larger package or of a
higher voltage rating exhibits better stability. The temperature
variation of the X5R dielectric is about ±15% over the −40°C to
+85°C temperature range and is not a function of package or
voltage rating.

Figure 30. Output Transient Response, C

Figure 31. Output Transient Response, C

= 1 µF

OUT

Figure 32. Capacitance vs. Capacitor Voltage Bias Characteristics

Equation 1 can be used to determine the worst-case capacitance,
accounting for capacitor variation over temperature, component
tolerance, and voltage.

C

= C × (1 − TEMPCO) × (1 − TOL) (1)

EFF

= 4.7 µF

OUT

where:
C

is the effective capacitance at the operating voltage.

EFF

C is the rated capacitance value.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.

Rev. C | Page 12 of 20

Data Sheet ADP124/ADP125

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

V

EN

V

OUT

08476-230

0.60

0.65

0.70

0.75

0.80

0.85

0.90

0.95

1.00

1.05

2.2 2.7 3.2 3.7 4.2 4.7 5.2
V

IN

(V)

ENABLE (EN) TRESHOLDS (V)

FALLING

RISING

08476-032

08476-033

CH1 1.00V CH2 1.00V

B

W

M100µs A CH1 2.00V

2

1

T 296.800µs

V

OUT

= 2.8V

V

OUT

= 3.3V

V

OUT

= 4.2V

VIN = 5V

In this example, the worst-case temperature coefficient (TEMPCO)
over −40°C to +85°C is assumed to be 15% for an X5R dielectric.
The tolerance of the capacitor (TOL) is assumed to be 10%, and
C is 0.94 μF at 4.2 V from the graph in Figure 32.

Substituting these values in Equation 1 yields

C

= 0.94 μF × (1 − 0.15) × (1 − 0.1) = 0.719 μF

EFF

Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over tem­perature and tolerance at the chosen output voltage.

To guarantee the performance of the ADP124/ADP125, it is
imperative that the effects of dc bias, temperature, and tolerances
on the behavior of the capacitors are evaluated for each application.

UNDERVOLTAGE LOCKOUT

The ADP124/ADP125 have an internal undervoltage lockout
circuit that disables all inputs and the output when the input
voltage is less than approximately 2 V. This ensures that the
ADP124/ADP125 inputs and the output behave in a predictable
manner during power-up.

ENABLE FEATURE

The ADP124/ADP125 uses the EN pin to enable and disable the
VOUT pin under normal operating conditions. As shown in
Figure 33, when a rising voltage on EN crosses the active threshold,
VOUT turns on. Conversely, when a falling voltage on EN crosses
the inactive threshold, VOUT turns off.

The active and inactive thresholds of the EN pin are derived from
the VIN voltage. Therefore, these thresholds vary as the input
voltage changes. Figure 34 shows typical EN active and inactive
thresholds when the VIN voltage varies from 2.3 V to 5.5 V.

Figure 34. Typical EN Pin Thresholds vs. Input Voltage

The ADP124/ADP125 use an internal soft start to limit the
inrush current when the output is enabled. The start-up time
for the 2.8 V option is approximately 350 µs from the time the
EN active threshold is crossed to when the output reaches 90%
of its final value. As shown in Figure 35, the start-up time is
dependent on the output voltage setting and increases slightly
as the output voltage increases.

Figure 33. Typical EN Pin Operation

As shown in Figure 33, the EN pin has built-in hysteresis. This
prevents on/off oscillations that may occur due to noise on the
EN pin as it passes through the threshold points.

Figure 35. Typical Start-Up Time

Rev. C | Page 13 of 20

ADP124/ADP125 Data Sheet

JA

1000

34.7

67.8

CURRENT LIMIT AND THERMAL OVERLOAD PROTECTION

The ADP124/ADP125 are protected from damage due to excessive
power dissipation by current and thermal overload protection
circuits. The ADP124/ADP125 are designed to limit the current
when the output load reaches 750 mA (typical). When the output
load exceeds 750 mA, the output voltage is reduced to maintain
a constant current limit.

Thermal overload protection is included, which limits the junction
temperature to a maximum of 150°C typical. Under extreme con­ditions (that is, high ambient temperature and power dissipation),
when the junction temperature starts to rise above 150°C, the
output is turned off, reducing output current to zero. When the
junction temperature cools to less than 135°C, the output is turned
on again and the output current is restored to its nominal value.

Consider the case where a hard short from VOUT to GND occurs.
At first, the ADP124/ADP125 limit the current so that only 750 mA
is conducted into the short. If self-heating causes the junction
temperature to rise above 150°C, thermal shutdown activates,
turning off the output and reducing the output current to zero.
When the junction temperature cools to less than 135°C, the
output turns on and conducts 750 mA into the short, again
causing the junction temperature to rise above 150°C. This
thermal oscillation between 135°C and 150°C results in a current
oscillation between 750 mA and 0 mA that continues as long
as the short remains at the output.

Current and thermal limit protections are intended to protect the
device from damage due to accidental overload conditions. For
reliable operation, the device power dissipation must be externally
limited so that the junction temperature does not exceed 125°C.

THERMAL CONSIDERATIONS

To guarantee reliable operation, the junction temperature of the
ADP124/ADP125 must not exceed 125°C. To ensure that the
junction temperature is less than this maximum value, the user
needs to be aware of the parameters that contribute to junction
temperature changes. These parameters include ambient tem­perature, power dissipation in the power device, and thermal
resistances between the junction and ambient air (θ
of θ

is dependent on the package assembly compounds used

JA

and the amount of copper to which the GND pins of the package
are soldered on the PCB. Table 6 shows typical θ
8-lead MSOP package for various PCB copper sizes. Tabl e 7
shows typical Ψ

values of the 8-lead MSOP and 8-lead 3 mm ×

JB

3 mm LFCSP package.

). The value

JA

values of the

JA

Table 6. Typical θ

Copper
Size (mm

2

) MSOP LFCSP

25 108.6 177.8
100 75.5 138.2
500 42.5 79.8

6400 26.1 53.5

Table 7. Typical ΨJB Values

MSOP LFCSP

31.7 44.1

The junction temperature of the ADP124/ADP125 can be
calculated from the following equation:

T

= TA + (PD × θJA) (2)

J

where:

T

is the ambient temperature.

A

P

is the power dissipation in the die, given by

D

P

= [(VIN − V

D

where:

I

is the load current.

LOAD

I

is the ground current.

GND

V

and V

IN

OUT

The power dissipation due to ground current is quite small and
can be ignored. Therefore, the junction temperature equation
can be simplified as follows:

T

= TA + {[(VIN − V

J

As shown in Equation 4, for a given ambient temperature, input­to-output voltage differential, and continuous load current, there
exists a minimum copper size requirement for the PCB to ensure
that the junction temperature does not rise above 125°C. Figure 36
through Figure 41 show junction temperature calculations for
different ambient temperatures, load currents, V
differentials, and areas of PCB copper.

In cases where the board temperature is known, the thermal
characterization parameter, Ψ
ction temperature rise. The maximum junction temperature (T
calculated from the board temperature (T
(P

) using the formula

D

T

= TB + (PD × ΨJB) (5)

J

Values for Specified PCB Copper Sizes

JA

θ

(°C/W)

ΨJB (°C/W)

OUT

) × I

] + (VIN × I

LOAD

) (3)

GND

are input and output voltages, respectively.

OUT

) × I

] × θJA} (4)

LOAD

to V

IN

, can be used to estimate the jun-

JB

) and power dissipation

B

OUT

) is

J

Rev. C | Page 14 of 20

Data Sheet ADP124/ADP125

08476-034

25

35

45

55

65

75

85

95

105

115

125

135

145

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

4.0

JUNCTION T E M P E R ATURE (°C)

TOTAL POWER DISSIPATION (W)

6400 mm

2

500 mm

2

25 mm

2

T

J

MAX

08476-035

25

35

45

55

65

75

85

95

105

115

125

135

145

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

JUNCTION T E M P E R ATURE (°C)

TOTAL POWER DISSIPATION (W)

6400 mm

2

500 mm

2

25 mm

2

TJ MAX

50

60

70

80

90

100

110

120

130

140

0 0.2

0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0

JUNCTION T E M P E R ATURE (°C)

TOTAL POWER DISSIPATION (W)

08476-036

6400 mm

2

500 mm

2

25 mm

2

TJ MAX

50

60

70

80

90

100

110

120

130

140

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

JUNCTION T E M P E R ATURE (°C)

TOTAL POWER DISSIPATION (W)

08476-037

6400 mm

2

500 mm

2

25 mm

2

TJ MAX

08476-038

JUNCTION T E M P E R ATURE (°C)

TOTAL POWER DISSIPATION (W)

0

20

40

60

80

100

120

140

0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50

T

B

= 25°C
TB = 50°C
TB = 65°C
T

B

= 85°C
TJ MAX

08476-039

JUNCTION T E M P E R

ATURE (°C)

TOT

AL POWER DISSIPATION (W)

0

20

40

60

80

100

120

140

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

4.5

TB = 25°C
TB = 50°C
TB = 65°C
T

B

= 85°C
TJ MAX

JUNCTION TEMPERATURE CALCULATIONS

Figure 36. Junction Temperature vs. Power Dissipation and copper area,

= 25°C

MSOP, T

A

Figure 37. Junction Temperature vs. Power Dissipation and copper area,

LFCSP, T

= 25°C

A

Figure 39. Junction Temperature vs. Power Dissipation and copper area,

= 50°C

LFCSP, T

A

Figure 40. Junction Temperature vs. Power Dissipation, MSOP package

at various Board Temperatures

Figure 38. Junction Temperature vs. Power Dissipation and copper area,

MSOP, T

= 50°C

A

Figure 41. Junction Temperature vs. Power Dissipation, LFCSP package

at various Board Temperatures

Rev. C | Page 15 of 20

ADP124/ADP125 Data Sheet

08476-041

08476-042

08476-045

PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS

Heat dissipation from the package can be improved by increasing
the amount of copper attached to the pins of the ADP124/ADP125.
Howeve r, as shown in Ta bl e 6, a point of diminishing returns
eventually is reached, beyond which an increase in the copper
size does not yield significant heat dissipation benefits.

The input capacitor should be placed as close as possible to the
VIN and GND pins, and the output capacitor should be placed
as close as possible to the VOUT and GND pins. Use of 0402 or
0603 size capacitors and resistors achieves the smallest possible
footprint solution on boards where the area is limited.

Figure 43. Example ADP125 MSOP PCB Layout

Figure 42. Example ADP124 MSOP PCB Layout

Figure 44. Example ADP124/ADP125 LFCSP PCB Layout

Rev. C | Page 16 of 20

Data Sheet ADP124/ADP125

071008-A

COMPLIANT TO JEDEC STANDARDS MO-187-AA- T

0.70

0.55

0.40

8°
0°

0.94

0.86

0.78

SEATING
PLANE

1.10 MAX

0.15

0.10

0.05

0.40

0.33

0.25

5.05

4.90

4.75

2.26

2.16

2.06

1.83

1.73

1.63

3.10

3.00

2.90

3.10

3.00

2.90

8

5

4

1

0.65 BSC

0.525 BSC

PIN 1

INDICATOR

COPLANARITY

0.10

0.23

0.18

0.13

TOP

VIEW

BOTTOM VIEW

EXPOSED

PAD

FOR PROP E R CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CO NFIGURATI ON AND
FUNCTIO N DE S CRIPTIONS
SECTION OF THIS DATA SHEET.

TOP VIEW

8

1

5

4

BOTTOM VIEW

(WITHEXPOSEDPAD)

PIN 1 INDEX

AREA

2.00

BSC SQ

SEATING

PLANE

0.60

0.55

0.50

0.20 REF

0.20 MIN

0.05 MAX

0.02 NOM

0.30

0.25

0.20

1.10

1.00

0.90

1.70

1.60

1.50

0.50
BSC

PIN 1
INDICATOR
(R 0.10)

FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.

0.30

0.25

0.18

06-24-2009-A

COPLANARITY

0.05

OUTLINE DIMENSIONS

Figure 45. 8-Lead Mini Small Outline Package with Exposed Pad [MINI_SO_EP]

(RH-8-1)

Dimensions shown in millimeters

Figure 46. 8-Lead Lead Frame Chip Scale Package [LFCSP_UD]

2 mm × 2 mm Body, Ultra Thin, Dual Lead

(CP-8-8)

Dimensions shown in millimeters

Rev. C | Page 17 of 20

ADP124/ADP125 Data Sheet

Model1

Temperature Range (TJ)

Output Voltage (V)2

Package Description

Package Option

Branding

ADP124ACPZ-3.3-R7

–40°C to +125°C

3.3

8-Lead LFCSP_UD

CP-8-8

LHL

ORDERING GUIDE

ADP124ARHZ-1.8-R7 –40°C to +125°C 1.8 8-Lead MINI_SO_EP RH-8-1 37
ADP124ARHZ-2.5-R7 –40°C to +125°C 2.5 8-Lead MINI_SO_EP RH-8-1 3T
ADP124ARHZ-2.7-R7 –40°C to +125°C 2.7 8-Lead MINI_SO_EP RH-8-1 3U
ADP124ARHZ-2.8-R7 –40°C to +125°C 2.8 8-Lead MINI_SO_EP RH-8-1 3Z
ADP124ARHZ-2.85-R7 –40°C to +125°C 2.85 8-Lead MINI_SO_EP RH-8-1 40
ADP124ARHZ-2.9-R7 –40°C to +125°C 2.9 8-Lead MINI_SO_EP RH-8-1 41
ADP124ARHZ-3.0-R7 –40°C to +125°C 3.0 8-Lead MINI_SO_EP RH-8-1 49
ADP124ARHZ-3.3-R7 –40°C to +125°C 3.3 8-Lead MINI_SO_EP RH-8-1 4F
ADP124ACPZ-1.8-R7 –40°C to +125°C 1.8 8-Lead LFCSP_UD CP-8-8 LHH
ADP124ACPZ-2.8-R7 –40°C to +125°C 2.8 8-Lead LFCSP_UD CP-8-8 LHJ
ADP124ACPZ-2.9-R7 –40°C to +125°C 2.9 8-Lead LFCSP_UD CP-8-8 LM2
ADP124ACPZ-3.0-R7 –40°C to +125°C 3.0 8-Lead LFCSP_UD CP-8-8 LHK

ADP125ACPZ-R7 –40°C to +125°C 0.8 to 5.0 (Adjustable) 8-Lead LFCSP_UD CP-8-8 LHM
ADP125ARHZ-R7 –40°C to +125°C 0.8 to 5.0 (Adjustable) 8-Lead MINI_SO_EP RH-8-1 38
ADP125ARHZ –40°C to +125°C 0.8 to 5.0 (Adjustable) 8-Lead MINI_SO_EP RH-8-1 38
ADP124-3.3-EVALZ 3.3 MSOP Evaluation Board
ADP125-EVALZ Adjustable MSOP Evaluation Board
ADP124CP-3.3-EVA LZ 3.3 LFCSP Evaluation Board
ADP125CP-EVALZ Adjustable LFCSP Evaluation Board
ADP124RHZ-REDYKIT REDYKIT
ADP124CPZ-REDYKIT REDYKIT

1

Z = RoHS Compliant Part.

2

Up to 31 fixed-output voltage options from 1.75 V to 3.3 V are available. For additional voltage options, contact a local Analog Devices, Inc., sales or distribution

representative.

Rev. C | Page 18 of 20

Data Sheet ADP124/ADP125

NOTES

Rev. C | Page 19 of 20

ADP124/ADP125 Data Sheet

©2009–2012 Analog Devices, Inc. All rights reserved. Trademarks and

NOTES

registered trademarks are the property of their respective owners.
D08476-0-6/12(C)

Rev. C | Page 20 of 20