Datasheet ADP120 Datasheet (ANALOG DEVICES)

100 mA, Low Quiescent Current,

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FEATURES

Input voltage range: 2.3 V to 5.5 V
Output voltage range: 1.2 V to 3.3 V
Output current: 100 mA
Low quiescent current

I

= 11 μA with zero load

GND

I

= 22 μA with 100 mA load

GND

Low shutdown current: <1 μA
Low dropout voltage

60 mV @ 100 mA load

High PSRR

73 dB @ 1 kHz at V

70 dB @ 10 kHz at V
Low noise: 40 μV rms at V
No noise bypass capacitor required
Initial accuracy: ±1%
Stable with small 1 μF ceramic output capacitor
16 fixed output voltage options
Current-limit and thermal overload protection
Logic controlled enable
5-lead TSOT package
4-ball 0.4 mm pitch WLCSP

= 1.2 V

OUT

OUT

= 1.2 V

= 1.2 V

OUT

CMOS Linear Regulator

ADP120

TYPICAL APPLICATIONS CIRCUITS

NC

V

= 1.8V

OUT

5

+

1µF

4

07589-001

V

= 1.8V

OUT

+

1µF

07589-002

V

= 2.3V

IN

Figure 1. ADP120 TSOT with Fixed Output Voltage, 1.8 V

V

= 2.3V

IN

+

1µF

Figure 2. ADP120 WLCSP with Fixed Output Voltage, 1.8 V

+

1µF

1

2

3

NC = NO CONNECT

VIN VOUT

EN GND

VIN

GND

EN

VOUT

APPLICATIONS

Mobile phones
Digital camera and audio devices
Portable and battery-powered equipment
Post regulation

GENERAL DESCRIPTION

The ADP120 is a low quiescent current, low dropout, linear
regulator that operates from 2.3 V to 5.5 V and provides up to
100 mA of output current. The low 60 mV dropout voltage at
100 mA load improves efficiency and allows operation over a
wide input voltage range. The low 25 A of quiescent current at
full load makes the ADP120 ideal for battery-operated portable
equipment.

The ADP120 is available in 16 fixed output voltage options,
ranging from 1.2 V to 3.3 V. The part is optimized for stable
operation with small 1 µF ceramic output capacitors. The
ADP120 delivers good transient performance with minimal
board area.

Short-circuit protection and thermal overload protection circuits
prevent damage in adverse conditions. The ADP120 is available
in a tiny 5-lead TSOT and a 4-ball 0.4 mm pitch WLCSP for the
smallest footprint solution for use in a variety of portable
applications.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2008 Analog Devices, Inc. All rights reserved.

ADP120

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TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Typical Application Circuits ............................................................ 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Recommended Specifications: Input and Output Capacitors 4

Absolute Maximum Ratings ............................................................ 5

Thermal Data ................................................................................ 5

Thermal Resistance ...................................................................... 5

ESD Caution .................................................................................. 5

Pin Configurations and Function Descriptions ........................... 6

REVISION HISTORY

7/08—Rev. 0 to Rev. A

Deleted ADP120-1.............................................................. Universal

Changes to General Description .................................................... 1

Changes to Dropout Voltage Parameter, Table 1 .......................... 3

Changes to Thermal Data Section .................................................. 5

Changes to Figure 12 and Figure 14 ............................................... 8

Changes to Figure 22 ........................................................................ 9

Changes to Table 6 and Table 7 ..................................................... 14

Changes to Figure 46 and Figure 47 Captions ............................ 17

Changes to Ordering Guide .......................................................... 18

6/08—Revision 0: Initial Version

Typical Performance Characteristics ..............................................7

Theory of Operation ...................................................................... 11

Applications Information .............................................................. 12

Capacitor Selection .................................................................... 12

Undervoltage Lockout ............................................................... 13

Enable Feature ............................................................................ 13

Current Limit and Thermal Overload Protection ................. 14

Thermal Considerations ............................................................ 14

PCB Layout Considerations ...................................................... 17

Outline Dimensions ....................................................................... 18

Ordering Guide .......................................................................... 19

Rev. A | Page 2 of 20

ADP120

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SPECIFICATIONS

VIN = (V

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

INPUT VOLTAGE RANGE VIN T
OPERATING SUPPLY CURRENT I
I
I
I
I
I
SHUTDOWN CURRENT I
EN = GND, TJ = −40°C to +125°C 1.5 µA
FIXED OUTPUT VOLTAGE ACCURACY V
100 µA < I

REGULATION

Line Regulation V

Load Regulation

I

DROPOUT VOLTAGE

TSOT I

I

I

I

WLCSP I

I

I

I

START-UP TIME
CURRENT LIMIT THRESHOLD
THERMAL SHUTDOWN

Thermal Shutdown Threshold TSSD T

Thermal Shutdown Hysteresis TS

EN INPUT

EN Input Logic High VIH 2.3 V ≤ VIN ≤ 5.5 V 1.2 V

EN Input Logic Low VIL 2.3 V ≤ VIN ≤ 5.5 V 0.4 V

EN Input Leakage Current V

EN = VIN or GND, TJ = −40°C to +125°C 1 µA

UNDERVOLTAGE LOCKOUT UVLO

Input Voltage Rising UVLO

Input Voltage Falling UVLO

Hysteresis UVLO

OUTPUT NOISE OUT
10 Hz to 100 kHz, VIN = 5 V, V
10 Hz to 100 kHz, VIN = 5 V, V

+ 0.4 V) or 2.3 V, whichever is greater; EN = VIN, I

OUT

= −40°C to +125°C 2.3 5.5 V

J

I

GND

EN = GND 0.1 µA

GND-SD

I

OUT

= 0 µA 11 µA

OUT

= 0 µA, TJ = −40°C to +125°C 21 µA

OUT

= 10 mA 15 µA

OUT

= 10 mA, TJ = −40°C to +125°C 29 µA

OUT

= 100 mA 22 µA

OUT

= 100 mA, TJ = −40°C to +125°C 35 µA

OUT

= 10 mA −1 +1 %

OUT

100 µA < I

= −40°C to +125°C

T

J

1

2

V

3

t

4

I

/VIN

OUT

V

/I

OUT

OUT

V

DROPOUT

V

START-UP

110 180 350 mA

LIMIT

15 °C

SD-HYS

EN = VIN or GND 0.05 µA

I-LEAKAGE

TJ = −40°C to +125°C 2.25 V

RISE

FAL L

120 mV

HYS

10 Hz to 100 kHz, VIN = 5 V, V

NOISE

= (V

V

IN

= −40°C to +125°C

T

J

I

= 1 mA to 100 mA 0.001 %/mA

OUT

= 1 mA to 100 mA, TJ = −40°C to +125°C 0.005 %/mA

OUT

OUT

= 10 mA 8 mV

OUT

= 10 mA, TJ = −40°C to +125°C 12 mV

OUT

= 100 mA 80 mV

OUT

= 100 mA, TJ = −40°C to +125°C 120 mV

OUT

= 10 mA 6 mV

OUT

= 10 mA, TJ = −40°C to +125°C 9 mV

OUT

= 100 mA 60 mV

OUT

= 100 mA, TJ = −40°C to +125°C 90 mV

OUT

OUT

rising 150 °C

J

TJ = −40°C to +125°C 1.5 V

= 10 mA, CIN = C

OUT

< 100 mA, VIN = (V

OUT

< 100 mA, VIN = (V

OUT

+ 0.4 V) to 5.5 V, I

OUT

OUT

= 1 µF, TA = 25°C, unless otherwise noted.

OUT

+ 0.4 V) to 5.5 V −2 +2 %

OUT

+ 0.4 V) to 5.5 V,

OUT

= 1 mA,

−2.5 +2.5 %

−0.03 +0.03 %/ V

= 3.3 V

= 3.3 V 120 µs

= 3.3 V 65 µV rms

OUT

= 2.5 V 52 µV rms

OUT

= 1.2 V 40 µV rms

OUT

Rev. A | Page 3 of 20

ADP120

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Parameter Symbol Conditions Min Typ Max Unit

POWER SUPPLY REJECTION RATIO PSRR 10 kHz, VIN = 5 V, V
10 kHz, VIN = 5 V, V
10 kHz, VIN = 5 V, V

1

Based on an endpoint calculation using 1 mA and 100 mA loads. See Figure 6 for typical load regulation performance for loads less than 1 mA.

2

Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output

voltages above 2.3 V.

3

Start-up time is defined as the time between the rising edge of EN to V

4

Current limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V

output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.

being at 90% of its nominal value.

OUT

RECOMMENDED SPECIFICATIONS: INPUT AND OUTPUT CAPACITORS

Table 2.

Parameter Symbol Conditions Min Typ Max Unit

MINIMUM INPUT AND OUTPUT CAPACITANCE1 C
CAPACITOR ESR R

1

The minimum input and output capacitance should be greater than 0.70 F over the full range of operating conditions. The full range of operating conditions in the

application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R- and X5R-type capacitors are recommended,
Y5V and Z5U capacitors are not recommended for use with any LDO.

MIN

ESR

= 3.3 V 60 dB

OUT

= 2.5 V 66 dB

OUT

= 1.2 V 70 dB

OUT

TJ = −40°C to +125°C 0.70 µF

T

= −40°C to +125°C 0.001 1 Ω

J

Rev. A | Page 4 of 20

ADP120

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ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

VIN to GND Pins −0.3 V to +6 V
VOUT to GND Pins −0.3 V to VIN
EN to GND Pins −0.3 V to +6 V
Storage Temperature Range −65°C to +150°C
Operating Junction Temperature Range −40°C to +125°C
Soldering Conditions JEDEC J-STD-020

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL DATA

Absolute maximum ratings apply individually only, not in
combination. The ADP120 can be damaged when the junction
temperature limits are exceeded. Monitoring ambient temperature
does not guarantee that T
limits. In applications with high power dissipation and poor
thermal resistance, the maximum ambient temperature may
have to be derated.

In applications with moderate power dissipation and low PCB
thermal resistance, the maximum ambient temperature can
exceed the maximum limit as long as the junction temperature
is within specification limits. The junction temperature (T
the device is dependent on the ambient temperature (T
power dissipation of the device (P
thermal resistance of the package (θ

Maximum junction temperature (T
ambient temperature (T
formula

T

= TA + (PD × θJA)

J

is within the specified temperature

J

) of

J

), the

A

), and the junction-to-ambient

D

).

JA

) is calculated from the

J

) and power dissipation (PD) using the

A

Junction-to-ambient thermal resistance (θ
based on modeling and calculation using a four-layer board.
The junction-to-ambient thermal resistance is highly dependent
on the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θ
PCB material, layout, and environmental conditions. The speci­fied values of θ
Refer to JESD 51-7 and JESD 51-9 for detailed information
regarding board construction. For additional information, see
Application Note AN-617, MicroCSP
Package.

Ψ

is the junction-to-board thermal characterization parameter

JB

with units of °C/W. Ψ
calculation using a four-layer board. JESD51-12, Guidelines for
Reporting and Using Package Thermal Information, states that
thermal characterization parameters are not the same as
thermal resistances. Ψ
through multiple thermal paths rather than a single path as in
thermal resistance, θ
convection from the top of the package as well as radiation from
the package, factors that make Ψ
applications. Maximum junction temperature (T
from the board temperature (T
using the formula

T

= TB + (PD × ΨJB)

J

Refer to JESD51-8, JESD51-9, and JESD51-12 for more detailed
information about Ψ

THERMAL RESISTANCE

θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.

Table 4. Thermal Resistance

Package Type θJA ΨJB Unit

5-Lead TSOT 170 43 °C/W
4-Ball, 0.4 mm Pitch WLCSP 260 58 °C/W

are based on a four-layer, 4 in. × 3 in. PCB.

JA

of the package is based on modeling and

JB

measures the component power flowing

JB

. Therefore, ΨJB thermal paths include

JB

more useful in real-world

JB

) and power dissipation (PD)

B

.

JB

) of the package is

JA

may vary, depending on

JA

TM

Wafer Le v el Chip S cal e

) is calculated

J

Rev. A | Page 5 of 20

ESD CAUTION

ADP120

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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

VIN

2

GND

Figure 3. 5-Lead TSOT Pin Configuration

TOP VIEW

(Not to Scale)

3

EN

NC = NO CONNECT

5

4

VOUT

NC

07589-033

Figure 4. 4-Ball WLCSP Pin Configuration

12

VIN VOUT

A

TOP VIEW

(Not to Scale)

ENB

GND

Table 5. Pin Function Descriptions

Pin No.

TSOT WLCSP

Mnemonic Description

1 A1 VIN Regulator Input Supply. Bypass VIN to GND with a 1 µF or greater capacitor.
2 B2 GND Ground.
3 B1 EN

Enable Input. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic

startup, connect EN to VIN.
4 N/A NC No Connect. Not connected internally. Not applicable (N/A) for the WLCSP.
5 A2 VOUT Regulated Output Voltage. Bypass VOUT to GND with a 1 µF or greater capacitor.

4

07589-03

Rev. A | Page 6 of 20

ADP120

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TYPICAL PERFORMANCE CHARACTERISTICS

VIN = 2.3 V, V

1.804

1.802

1.800

1.798

(V)

OUT

V

1.796

= 1.8 V, I

OUT

= 10 mA, CIN = C

OUT

= 1 µF, TA = 25°C, unless otherwise noted.

OUT

LOAD = 10µA
LOAD = 100µA
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA

35

30

25

20

15

1.794

1.792

1.790
–40°C –5°C 25°C 85°C 125°C

TJ (°C)

Figure 5. Output Voltage vs. Junction Temperature

1.805

1.803

1.801

(V)

OUT

V

1.799

1.797

1.795

0.01 0.1 1 10 100
I

LOAD

(mA)

Figure 6. Output Voltage vs. Load Current

(V)

OUT

V

1.805

1.803

1.801

1.799

1.797

1.795

2.3 5.55.34.94.54.13.73.1 3.32.7 5.14.74.33.93.52.92.5
VIN (V)

LOAD = 10µA
LOAD = 100µA
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA

Figure 7. Output Voltage vs. Input Voltage

10

GROUND CURRENT (µA)

5

0

–40°C –5°C 25°C 85°C 125°C

07589-005

TJ (°C)

LOAD = 10µA
LOAD = 100µ A
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA

07589-008

Figure 8. Ground Current vs. Junction Temperature

30

25

20

15

10

GROUND CURRENT (µA)

5

0

0.01 0.1 1 10 100

07589-006

I

LOAD

(mA)

07589-009

Figure 9. Ground Current vs. Load Current

30

25

20

15

10

GROUND CURRENT (µA)

5

0

2.3 5.55.34.94.54.13.73.1 3.32.7 5.14.74.33.93.52.92.5

07589-007

VIN (V)

LOAD = 10µA
LOAD = 100µA
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA

07589-010

Figure 10. Ground Current vs. Input Voltage

Rev. A | Page 7 of 20

ADP120

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0.35

0.30

0.25

0.20

0.15

0.10

SHUTDOWN CURRENT (µ A)

0.05

Figure 11. Shutdown Current vs. Temperature at Various Input Voltages

2.30V

2.50V

3.00V

3.50V

4.20V

5.50V

0

–50 –25 0 25 50 75 100 125

TEMPERATURE (°C)

90

TA = 25°C

80

70

60

50

40

30

DROPOUT VO LTAGE (mV)

20

10

0

1 10 100

07589-011

I

LOAD

Figure 14. Dropout Voltage vs. Load Current, WLCSP, V

(mA)

V

= 2.5V

OUT

V

= 3.3V

OUT

07589-014

= 2.5 V and 3.3 V

OUT

120

TA = 25°C

100

80

60

40

DROPOUT VOLTAGE (mV)

20

0

1 10 100

Figure 12. Dropout Voltage vs. Load Current, TSOT, V

3.35

3.30

3.25

(V)

3.20

OUT

V

3.15

3.10

3.05

3.20 3.403.353.303.25 3.603.553.503.45

I

LOAD

VIN (V)

V

(mA)

OUT

= 2.5V

V

OUT

= 3.3V

= 2.5 V and 3.3 V

OUT

V

@ 1mA

OUT

V

@ 10mA

OUT

V

@ 20mA

OUT

V

@ 50mA

OUT

V

@ 100mA

OUT

Figure 13. Output Voltage vs. Input Voltage (in Dropout), TSOT, V

OUT

07589-012

07589-013

= 3.3 V

3.35

3.30

3.25

(V)

3.20

OUT

V

3.15
V

@ 1mA

OUT

V

@ 10mA

3.10

3.05

3.20 3.403.353.303.25 3.603.553.503.45
VIN (V)

OUT

V

OUT

V

OUT

V

OUT

@ 20mA
@ 50mA
@ 100mA

Figure 15. Output Voltage vs. Input Voltage (in Dropout), WLCSP, V

60

50

40

30

20

GROUND CURRENT (µA)

10

0

3.20 3.403.353.303.25 3.603.553.503.45
VIN (V)

I

LOAD

I

LOAD

I

LOAD

I

LOAD

I

LOAD

@ 1mA
@ 10mA
@ 20mA
@ 50mA
@ 100mA

Figure 16. Ground Current vs. Input Voltage (in Dropout)

OUT

07589-015

= 3.3 V

07589-016

Rev. A | Page 8 of 20

ADP120

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0

100mA V

–10

–20

–30

–40

–50

PSRR (dB)

–60

–70

–80

–90

–100

10mA
1mA
100µA
NO LOAD

10 100k10k1k100 10M1M

FREQUENCY (Hz)

Figure 17. Power Supply Rejection Ratio vs. Frequency

RIPPLE

V

IN

V

OUT

C

OUT

= 5V

= 1.2V
= 1µF

= 50mV

07589-017

0

3.3V/100mA

3.3V/100µA

10 100k10k1k100 10M1M

PSRR (dB)

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

1.2V/100mA

1.2V/100µA

FREQUENCY (Hz)

Figure 20. Power Supply Rejection Ratio vs. Frequency,

1.8V/100mA

1.8V/100µA

07589-020

Various Output Voltages and Load Currents

0

100mA V

–10

–20

–30

–40

–50

PSRR (dB)

–60

–70

–80

–90

–100

10mA
1mA
100µA
NO LOAD

10 100k10k1k100 10M1M

FREQUENCY (Hz)

Figure 18. Power Supply Rejection Ratio vs. Frequency

RIPPLE

V

IN

V

OUT

C

OUT

= 5V

= 1.8V
= 1µF

= 50mV

07589-018

10

3.3V

1

NOISE (µV/ Hz)

0.1

0.01
10 10k1k100 100k

Figure 21. Output Noise Spectrum, V

1.8V

1.2V

FREQUENCY (Hz)

= 5 V, I

IN

= 10 mA, C

LOAD

OUT

= 1 F

07589-021

0

100mA V

–10

–20

–30

–40

–50

PSRR (dB)

–60

–70

–80

–90

–100

10mA
1mA
100µA
NO LOAD

10 100k10k1k100 10M1M

FREQUENCY (Hz)

Figure 19. Power Supply Rejection Ratio vs. Frequency

RIPPLE

V

IN

V

OUT

C

OUT

= 5V

= 3.3V
= 1µF

= 50mV

07589-019

Rev. A | Page 9 of 20

70

60

50

40

30

NOISE ( µV rms)

20

10

0

0.001 0.01 0.1 1 10 100

3.3V

2.5V

1.8V

1.5V

1.2V

I

LOAD

(mA)

Figure 22. Output Noise vs. Load Current and Output Voltage

V

= 5 V, C

IN

OUT

= 1 F

07589-022

ADP120

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I

LOAD

1mA TO 100mA LO AD STEP,

2.5A/µs

(100mA/DIV)(50mV/DIV)

V

OUT

(40µs/DIV)

Figure 23. Load Transient Response, CIN and C

I

LOAD

1mA TO 100mA LO AD STEP,

2.5A/µs

(100mA/DIV)(50mV/DIV)

V

OUT

VIN = 5V
V

= 1.8V

OUT

= 1 F

OUT

I

LOAD

4V TO 5V INPUT VOLTAGE STEP,

(1V/DIV)(10mV/DIV)

V

= 1.8V,

OUT

C

= C

IN

OUT

07589-023

= 1µF

2V/µs

V

OUT

(4µs/DIV)

07589-125

Figure 25. Line Transient Response, Load Current = 100 mA

I

LOAD

(1V/DIV)(10mV/DIV)

4V TO 5V INPUT VOLTAGE STEP,

2V/µs

V

OUT

(40µs/DIV)

Figure 24. Load Transient Response, CIN and C

VIN = 5V
V

= 1.8V

OUT

= 4.7 F

OUT

07589-024

V

= 1.8V,

OUT

C

= C

= 1µF

IN

OUT

(10µs/DIV)

Figure 26. Line Transient Response, Load Current = 1 mA

07589-026

Rev. A | Page 10 of 20

ADP120

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THEORY OF OPERATION

The ADP120 is a low quiescent current, low dropout linear
regulator that operates from 2.3 V to 5.5 V and provides up
to 100 mA of output current. Drawing a low 22 A of quies-
cent current (typical) at full load makes the ADP120 ideal
for battery-operated portable equipment. Shutdown current
consumption is typically 100 nA.

Optimized for use with small 1 µF ceramic capacitors, the
ADP120 provides excellent transient performance.

VIN VOUT

R1

R2

GND

EN

SHORT CIRCUIT ,

UVLO, AND

THERMAL
PROTECT

0.8V REFERE NCESHUTDOWN

Figure 27. Internal Block Diagram

7589-127

Internally, the ADP120 consists of a reference, an error amplifier,
a feedback voltage divider, and a PMOS pass transistor. Output
current is delivered via the PMOS pass device, which is controlled
by the error amplifier. The error amplifier compares the reference
voltage with the feedback voltage from the output and amplifies
the difference. If the feedback voltage is lower than the reference
voltage, the gate of the PMOS device is pulled lower, allowing
more current to pass and increasing the output voltage. If the
feedback voltage is higher than the reference voltage, the gate of
the PMOS device is pulled higher, allowing less current to pass
and decreasing the output voltage.

The ADP120 is available in 16 output voltage options, ranging
from 1.2 V to 3.3 V. The ADP120 uses the EN pin to enable and
disable the VOUT pin under normal operating conditions. When
EN is high, VOUT turns on; when EN is low, VOUT turns off.
For automatic startup, EN can be tied to VIN.

Rev. A | Page 11 of 20

ADP120

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APPLICATIONS INFORMATION

CAPACITOR SELECTION

Output Capacitor

The ADP120 is designed for operation with small, space-saving
ceramic capacitors, but functions with most commonly used
capacitors as long as care is taken with regard to the effective
series resistance (ESR) value. The ESR of the output capacitor
affects stability of the LDO control loop. A minimum of 0.70 µF
capacitance with an ESR of 1 Ω or less is recommended to ensure
stability of the ADP120. Transient response to changes in load
current is also affected by output capacitance. Using a larger
value of output capacitance improves the transient response of
the ADP120 to large changes in load current. Figure 28 and
Figure 29 show the transient responses for output capacitance
values of 1 µF and 4.7 µF, respectively.

I

LOAD

1mA TO 100mA LOAD ST E P,

(100mA/DIV)(50mV/DIV)

2.5A/µs

Input and Output Capacitor Properties

Use any good quality ceramic capacitors with the ADP120, as
long as they meet the minimum capacitance and maximum ESR
requirements. Ceramic capacitors are manufactured with a variety
of dielectrics, each with different behavior over temperature and
applied voltage. Capacitors must have a dielectric adequate to
ensure the minimum capacitance over the necessary tempera­ture range and dc bias conditions. X5R or X7R dielectrics with
a voltage rating of 6.3 V or 10 V are recommended for best
performance. Y5V and Z5U dielectrics are not recommended
for use with any LDO because of their poor temperature and dc
bias characteristics.

Figure 30 depicts the capacitance vs. voltage bias characteristic
of a 0402 1 µF, 10 V, X5R capacitor. The voltage stability of a capa­citor is strongly influenced by the capacitor size and voltage rating.
In general, a capacitor in a larger package or higher voltage rating
exhibits better stability. The temperature variation of the X5R
dielectric is about ±15% over the −40°C to +85°C temperature
range and is not a function of package or voltage rating.

1.2

1.0

MURATA PART NUMBER:

GRM155R61A105KE15

V

OUT

V

= 1.8V,

OUT

= C

C

(100mA/DIV)(50mV/DIV)

V
C

= 1µF

IN

OUT

(400ns/DIV)

Figure 28. Output Transient Response, C

I

LOAD

1mA TO 100mA LOAD ST E P,

= 1.8V,

OUT

= C

= 4.7µF

IN

OUT

Figure 29. Output Transient Response, C

2.5A/µs

V

OUT

(400ns/DIV)

= 1 µF

OUT

= 4.7 µF

OUT

07589-128

07589-129

Input Bypass Capacitor

Connecting a 1 µF capacitor from VIN to GND reduces the cir­cuit sensitivity to printed circuit board (PCB) layout, especially
when long input traces or high source impedance are encountered.
If greater than 1 µF of output capacitance is required, increase
the input capacitor to match it.

0.8

0.6

0.4

CAPACITANCE (µF)

0.2

0

024681

Figure 30. Capacitance vs. Voltage Characteristic

VOLTAGE (V)

0

07589-126

Use Equation 1 to determine the worst-case capacitance accounting
for capacitor variation over temperature, component tolerance,
and voltage.

C

= C

EFF

× (1 − TEMPCO) × (1 − TOL) (1)

BIAS

where:
C

is the effective capacitance at the operating voltage.

BIAS

TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.

In this example, the worst-case temperature coefficient (TEMPCO)
over −40°C to +85°C is assumed to be 15% for an X5R dielec­tric. The tolerance of the capacitor (TOL) is assumed to be 10%,
and C

is 0.94 F at 1.8 V, as shown in Figure 30.

BIAS

Substituting these values in Equation 1 yields

C

= 0.94 F × (1 − 0.15) × (1 − 0.1) = 0.719 F

EFF

Rev. A | Page 12 of 20

ADP120

www.BDTIC.com/ADI

Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over temper­ature and tolerance at the chosen output voltage.

To guarantee the performance of the ADP120, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.

UNDERVOLTAGE LOCKOUT

The ADP120 has an internal undervoltage lockout circuit that
disables all inputs and the output when the input voltage is less
than approximately 2.2 V. This ensures that the inputs and the
output of the ADP120 behave in a predictable manner during
power-up.

ENABLE FEATURE

The ADP120 uses the EN pin to enable and disable the VOUT
pin under normal operating conditions. As shown in Figure 31,
when a rising voltage on EN crosses the active threshold, VOUT
turns on. When a falling voltage on EN crosses the inactive
threshold, VOUT turns off.

V

OUT

EN

(500mV/DIV)

VIN = 5V

= 1.8V

V

OUT

= C

IN

LOAD

= 1µF

OUT

= 100mA

07589-124

C
I

(40ms/DIV)

Figure 31. Typical EN Pin Operation

As shown in Figure 31, the EN pin has hysteresis built-in. This
prevents on/off oscillations that can occur due to noise on the
EN pin as it passes through the threshold points.

The EN pin active/inactive thresholds are derived from the VIN
voltage; therefore, these thresholds vary with changing input
voltage. Figure 32 shows typical EN active/inactive thresholds
when the input voltage varies from 2.3 V to 5.5 V.

1.10

1.05

1.00

0.95

0.90

0.85

0.80

TYPICAL EN THRESHOLDS (V)

0.75

0.70

2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25 5.50

EN ACTIVE

VIN (V)

EN INACTIVE

07589-025

Figure 32. Typical EN Pin Thresholds vs. Input Voltage

The ADP120 utilizes an internal soft start to limit the inrush
current when the output is enabled. The start-up time for the

1.8 V option is approximately 120 µs from the time the EN
active threshold is crossed to when the output reaches 90% of its
final value. The start-up time is somewhat dependent on the
output voltage setting and increases slightly as the output
voltage increases.

6

5

4

3

CURRENT (V)

2

1

0

0218016014012010080604020

TIME (µs)

Figure 33. Typical Start-Up Time

EN

3.3V

1.8V

1.2V

00

07589-133

Rev. A | Page 13 of 20

ADP120

www.BDTIC.com/ADI

CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION

The ADP120 is protected against damage due to excessive
power dissipation by current and thermal overload protection
circuits. The ADP120 is designed to current limit when the
output load reaches 150 mA (typical). When the output load
exceeds 150 mA, the output voltage reduces to maintain a
constant current limit.

Thermal overload protection is built-in, limiting the junction
temperature to a maximum of 150°C (typical). Under extreme
conditions (that is, high ambient temperature and power dissi­pation) when the junction temperature starts to rise above 150°C,
the output turns off, reducing the output current to zero. When
the junction temperature drops below 135°C, the output turns
on again thereby restoring output current to its nominal value.

Consider the case where a hard short from VOUT to GND
occurs. At first, the ADP120 current limits, conducting only
150 mA into the short. If self-heating of the junction is great
enough to cause its temperature to rise above 150°C, thermal
shutdown activates, turning off the output and reducing the
output current to zero. As the junction temperature cools and
drops below 135°C, the output turns on and conducts 150 mA
into the short, again causing the junction temperature to rise
above 150°C. This thermal oscillation between 135°C and 150°C
causes a current oscillation between 150 mA and 0 mA that
continues as long as the short remains at the output.

Current- and thermal-limit protections are intended to protect
the device against accidental overload conditions. For reliable
operation, device power dissipation must be externally limited
to prevent junction temperatures from exceeding 125°C.

THERMAL CONSIDERATIONS

In most applications, the ADP120 does not dissipate much heat
due to its high efficiency. However, in applications with high
ambient temperature and high supply voltage-to-output voltage
differential, the heat dissipated in the package is large enough to
cause the junction temperature of the die to exceed the maximum
junction temperature of 125°C.

When the junction temperature exceeds 150°C, the converter
enters thermal shutdown. It recovers only after the junction
temperature has decreased below 135°C to prevent any permanent
damage. Therefore, thermal analysis for the chosen application
is very important to guarantee reliable performance over all
conditions. The junction temperature of the die is the sum of
the ambient temperature of the environment and the tempera­ture rise of the package due to the power dissipation, as shown
in Equation 2.

To guarantee reliable operation, the junction temperature of
the ADP120 must not exceed 125°C. To ensure the junction
temperature stays below this maximum value, the user needs to
be aware of the parameters that contribute to junction

temperature changes. These parameters include ambient temper­ature, power dissipation in the power device, and thermal
resistances between the junction and ambient air (θ

). The θJA

JA

number is dependent on the package assembly compounds that
are used and the amount of copper used to solder the package
GND pins to the PCB. Table 6 shows typical θ

values of the

JA

5-lead TSOT and 4-ball WLCSP packages for various PCB
copper sizes. Tabl e 7 shows the typical Ψ

value of the 5-lead

JB

TSOT and 4-ball WLCSP.

Table 6. Typical θ

Copper Size (mm2)

01 170 260
50 152 159
100 146 157
300 134 153
500 131 151

1

Device soldered to minimum size pin traces.

Values

JA

θ

(°C/W)

JA

TSOT WLCSP

Table 7. Typical ΨJB Values

ΨJB (°C/W)

TSOT WLCSP

42.8 58.4

The junction temperature of the ADP120 can be calculated
from the following equation:

T

= TA + (PD × θJA) (2)

J

where:

T

is the ambient temperature.

A

is the power dissipation in the die, given by

P

D

P

= [(VIN − V

D

OUT

) × I

] + (VIN × I

LOAD

) (3)

GND

where:

I

is the load current.

LOAD

is the ground current.

I

GND

V

and V

IN

are input and output voltages, respectively.

OUT

Power dissipation due to ground current is quite small and
can be ignored. Therefore, the junction temperature equation
simplifies to the following:

T

= TA + {[(VIN − V

J

OUT

) × I

] × θJA} (4)

LOAD

As shown in Equation 4, for a given ambient temperature, input­to-output voltage differential, and continuous load current, there
exists a minimum copper size requirement for the PCB to ensure
the junction temperature does not rise above 125°C. The following
figures show junction temperature calculations for different
ambient temperatures, load currents, V

-to-V

IN

differentials,

OUT

and areas of PCB copper.

Rev. A | Page 14 of 20

ADP120

T

T

T

T

T

T

www.BDTIC.com/ADI

140

MAX JUNCTION TEMPERATURE

120

(°C)

J

100

80

60

40

JUNCTION TEMPERATURE,

20

0

0.5 4.54.03.53.02.52.01.51.0
VIN – V

OUT

(V)

Figure 34. TSOT, 500 mm2 of PCB Copper, TA = 25°C

= 10mA

I

L

= 100mA

I

L

= 75mA

I

L

= 50mA

I

L

= 25mA

I

L

I

L

= 1mA

07589-134

140

MAX JUNCTION TEMPERATURE

120

(°C)

J

100

80

60

40

JUNCTION TEMPERATURE,

20

0

0.5 4.54.03.53.02.52.01.51.0
VIN – V

OUT

(V)

Figure 37. TSOT, 500 mm2 of PCB Copper, TA = 50°C

= 10mA

I

L

= 100mA

I

L

= 75mA

I

L

= 50mA

I

L

= 25mA

I

L

I

L

= 1mA

07589-137

140

MAX JUNCTION TEMPERATURE

120

(°C)

J

100

80

60

40

JUNCTION TEMPERATURE,

20

0

0.5 4.54.03.53.02.52.01.51.0
VIN – V

OUT

(V)

Figure 35. TSOT, 100 mm2 of PCB Copper, TA = 25°C

140

120

(°C)

J

100

80

60

40

JUNCTION TEMPERATURE,

20

0

MAX JUNCTION TEMPERATURE

0.5 4.54.03.53.02.52.01.51.0
VIN – V

OUT

(V)

Figure 36. TSOT, 0 mm2 of PCB Copper, TA = 25°C

= 10mA

I

L

= 10mA

I

L

= 100mA

I

L

= 75mA

I

L

= 50mA

I

L

= 25mA

I

L

I

L

= 100mA

I

L

= 75mA

I

L

= 50mA

I

L

= 25mA

I

L

I

L

= 1mA

= 1mA

140

MAX JUNCTION TEMPERATURE

120

(°C)

J

100

80

= 100mA

I

L

= 75mA

I

L

= 50mA

I

L

= 25mA

I

L

60

40

JUNCTION TEMPERATURE,

20

0

0.5 4.54.03.53.02.52.01.51.0

07589-027

VIN – V

OUT

(V)

= 10mA

I

L

I

= 1mA

L

07589-030

Figure 38. TSOT, 100 mm2 of PCB Copper, TA = 50°C

140

120

(°C)

J

100

80

60

40

JUNCTION TEMPERATURE,

20

07589-028

MAX JUNCTION TEMPERATURE

0

0.5 4.54.03.53.02.52.01.51.0
VIN – V

OUT

I

L

= 100mA

(V)

= 10mA

I

L

= 75mA

I

L

= 50mA

I

L

= 25mA

I

L

I

= 1mA

L

07589-031

Figure 39. TSOT, 0 mm2 of PCB Copper, TA = 50°C

Rev. A | Page 15 of 20

ADP120

T

T

T

T

T

T

www.BDTIC.com/ADI

140

120

(°C)

J

100

80

60

40

JUNCTION TEMPERATURE,

20

0

0.5 4.54.03.53.02.52.01.51.0

Figure 40. WLCSP, 500 mm2 of PCB Copper, TA = 25°C

140

120

(°C)

J

100

80

60

40

JUNCTION TEMPERATURE,

20

0

0.5 4.54.03.53.02.52.01.51.0

Figure 41. WLCSP, 100 mm2 of PCB Copper, TA = 25°C

140

120

(°C)

J

100

80

60

40

JUNCTION TE M PE RATURE,

20

0

0.5 4.54.03.53.02.52.01.51.0

Figure 42. WLCSP, 0 mm2 of PCB Copper, TA = 25°C

MAX JUNCTION TEMPERATURE

VIN – V

OUT

(V)

MAX JUNCTION TEMPERATURE

VIN – V

OUT

(V)

MAX JUNCTION TEMPERATURE

I

= 100mA

L

VIN – V

OUT

(V)

= 10mA

I

L

= 10mA

I

L

= 10mA

I

L

= 100mA

I

L

= 75mA

I

L

= 50mA

I

L

= 25mA

I

L

I

L

= 100mA

I

L

= 75mA

I

L

= 50mA

I

L

= 25mA

I

L

I

L

= 75mA

I

L

= 50mA

I

L

I

= 25mA

L

I

L

= 1mA

= 1mA

= 1mA

140

MAX JUNCTION TEMPERATURE

120

(°C)

J

100

80

I

= 100mA

L

I

= 75mA

L

= 50mA

I

L

I

= 25mA

L

60

40

JUNCTION TEMPERATUR E ,

20

0

0.5 4.54.03.53.02.52.01.51.0

07589-140

VIN – V

OUT

= 10mA

I

L

(V)

I

= 1mA

L

07589-143

Figure 43. WLCSP, 500 mm2 of PCB Copper, TA = 50°C

140

120

(°C)

J

100

80

60

40

JUNCTION TEMPERATUR E ,

20

0

07589-141

MAX JUNCTION TEMPERATURE

0.5 4.54.03.53.02.52.01.51.0
VIN – V

OUT

I

= 10mA

I

L

(V)

= 100mA

L

I

= 75mA

L

= 50mA

I

L

I

= 25mA

L

I

= 1mA

L

07589-144

Figure 44. WLCSP, 100 mm2 of PCB Copper, TA = 50°C

140

MAX JUNCTION TEMPERATURE

120

(°C)

J

100

80

60

40

JUNCTION TE M PE RATURE,

20

0

0.5 4.54.03.53.02.52.01.51.0

07589-142

= 100mA

I

L

VIN – V

OUT

= 10mA

I

L

(V)

I

= 75mA

L

I

= 50mA

L

= 25mA

I

L

I

= 1mA

L

07589-145

Figure 45. WLCSP, 0 mm2 of PCB Copper, TA = 50°C

Rev. A | Page 16 of 20

ADP120

T

T

www.BDTIC.com/ADI

In cases where the board temperature is known, use the thermal
characterization parameter, Ψ
temperature rise. Maximum junction temperature (T
calculated from the board temperature (T
dissipation (P

= TB + (PD × ΨJB) (5)

T

J

140

120

(°C)

J

100

) using the formula

D

MAX JUNCTION TEMPERATURE

80

60

, to estimate the junction

JB

I

= 100mA

I

L

I

= 25mA

L

= 75mA

L

= 10mA

I

L

) and power

B

= 50mA

I

L

I

= 1mA

L

) is

J

PCB LAYOUT CONSIDERATIONS

Improve heat dissipation from the package by increasing the
amount of copper attached to the pins of the ADP120. However,
as listed in Tabl e 6, a point of diminishing returns is eventually
reached, beyond which an increase in the copper size does not
yield significant heat dissipation benefits.

Place the input capacitor as close as possible to the VIN and
GND pins. Place the output capacitor as close as possible to the
VOUT and GND pins. Use of 0402- or 0603-size capacitors and
resistors achieves the smallest possible footprint solution on
boards where area is limited.

GND

ANALOG DEVICES

ADP120-xx-EVALZ

GND

40

JUNCTION TE M PERATURE,

20

0

0.5 4.54.03.53.02.52.01.51.0

140

MAX JUNCTION TEMPERATURE

120

(°C)

J

100

80

60

40

JUNCTION TEMPERATUR E ,

20

0

0.5 4.54.03.53.02.52.01.51.0

VIN – V

OUT

Figure 46. TSOT, T

I

= 100mA

L

= 25mA

I

L

VIN – V

OUT

Figure 47. WLCSP, T

(V)

= 85°C

B

I

= 75mA

L

I

L

(V)

= 85°C

B

= 10mA

I

= 50mA

L

I

= 1mA

L

C1

07589-146

VIN VOUT

GND

J1

EN

U1

C2

GND

07589-032

Figure 48. TSOT PCB Layout

ADP120CB-xx-EVALZ

VIN

07589-147

GND

J1

C1 C 2

U1

WLC

SP

VOUT

GND

EN

Rev. A | Page 17 of 20

Figure 49. WLCSP PCB Layout

7589-136

ADP120

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

A1 BALL

CORNER

2.90 BSC

54

0.50

0.30

2.80 BSC

0.95 BSC

*

1.00 MAX

SEATING
PLANE

0.20

0.08

1.60 BSC

*

0.90

0.87

0.84

0.10 MAX

123

PIN 1

1.90

BSC

*

COMPLIANT TO JEDEC STANDARDS MO-193-AB WITH

THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.

Figure 50. 5-Lead Thin Small Outline Transistor Package [TSOT]

(UJ-5)

Dimensions shown in millimeters

0.660

0.860

0.820 SQ

0.780

0.600

0.540
SEATING

PLANE

8°
4°
0°

0.60

0.45

0.30

12

TOP VIEW

(BALL SI DE DO W N)

0.280

0.260

0.240

0.230

0.200

0.170

0.40
BALL PIT CH

0.050 NOM
COPLANARITY

Figure 51. 4-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-4-2)

Dimensions shown in millimeters

BOTTOM VIEW

(BALL SI DE UP)

A

B

101507-A

Rev. A | Page 18 of 20

ADP120

www.BDTIC.com/ADI

ORDERING GUIDE

Output

Model Temperature Range

ADP120-AUJZ12R7
ADP120-AUJZ15R7
ADP120-AUJZ18R7
ADP120-AUJZ33R7
ADP120-ACBZ12R7
ADP120-ACBZ15R7
ADP120-ACBZ155R7
ADP120-ACBZ16R7
ADP120-ACBZ165R7
ADP120-ACBZ17R7
ADP120-ACBZ175R7
ADP120-ACBZ18R7
ADP120-ACBZ188R7
ADP120-ACBZ20R7
ADP120-ACBZ25R7
ADP120-ACBZ278R7
ADP120-ACBZ28R7
ADP120-ACBZ29R7
ADP120-ACBZ30R7
ADP120-ACBZ33R7
ADP120-33-EVALZ
ADP120-18-EVALZ
ADP120-15-EVALZ
ADP120-12-EVALZ
ADP120CB-2.8-EVALZ
ADP120CB-2.5-EVALZ
ADP120CB-1.8-EVALZ
ADP120CB-1.5-EVALZ
ADP120CB-1.2-EVALZ

1

For additional voltage options, contact your local Analog Devices, Inc., sales or distribution representative.

2

Z = RoHS Compliant Part.

2

–40°C to +125°C 1.2 5-Lead TSOT UJ-5 L9R

2

–40°C to +125°C 1.5 5-Lead TSOT UJ-5 L9Q

2

–40°C to +125°C 1.8 5-Lead TSOT UJ-5 L9P

2

–40°C to +125°C 3.3 5-Lead TSOT UJ-5 L9N

2

–40°C to +125°C 1.2 4-Ball WLCSP CB-4-2 LBJ

2

–40°C to +125°C 1.5 4-Ball WLCSP CB-4-2 LBK

2

–40°C to +125°C 1.55 4-Ball WLCSP CB-4-2 LBL

2

–40°C to +125°C 1.6 4-Ball WLCSP CB-4-2 LBM

2

–40°C to +125°C 1.65 4-Ball WLCSP CB-4-2 LBN

2

–40°C to +125°C 1.7 4-Ball WLCSP CB-4-2 LBP

2

–40°C to +125°C 1.75 4-Ball WLCSP CB-4-2 LBQ

2

–40°C to +125°C 1.8 4-Ball WLCSP CB-4-2 LBR

2

–40°C to +125°C 1.875 4-Ball WLCSP CB-4-2 LBS

2

–40°C to +125°C 2.0 4-Ball WLCSP CB-4-2 LBT

2

–40°C to +125°C 2.5 4-Ball WLCSP CB-4-2 LBU

2

–40°C to +125°C 2.775 4-Ball WLCSP CB-4-2 LBV

2

–40°C to +125°C 2.8 4-Ball WLCSP CB-4-2 LBW

2

–40°C to +125°C 2.9 4-Ball WLCSP CB-4-2 LBX

2

–40°C to +125°C 3.0 4-Ball WLCSP CB-4-2 LBY

2

–40°C to +125°C 3.3 4-Ball WLCSP CB-4-2 LBZ

2

3.3 ADP120 3.3 V Output Evaluation Board

2

1.8 ADP120 1.8 V Output Evaluation Board

2

1.5 ADP120 1.5 V Output Evaluation Board

2

1.2 ADP120 1.2 V Output Evaluation Board

2

2.8 ADP120 WLCSP 2.8 V Output Evaluation Board

2

2.5 ADP120 WLCSP 2.5 V Output Evaluation Board

2

1.8 ADP120 WLCSP 1.8 V Output Evaluation Board

2

1.5 ADP120 WLCSP 1.5 V Output Evaluation Board

2

1.2 ADP120 WLCSP 1.2 V Output Evaluation Board

Voltage (V)1Package Description

Package
Option Branding

Rev. A | Page 19 of 20

ADP120

www.BDTIC.com/ADI

NOTES

©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07589-0-7/08(0)

Rev. A | Page 20 of 20