Datasheet ADN2860 Datasheet (ANALOG DEVICES)

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3-Channel Digital

Potentiometer with

Nonvolatile Memory

Preliminary Technical Data ADN2860

FEATURES 3 Channels: Dual 512-Position Single 128-Position

Ω or 150KΩ Full-Scale Resistance

25K Low Temperature Coefficient: 35ppm/°C Nonvolatile Memory Retains Wiper Settings Permanent Memory Write-Protection Linear Increment/Decrement Log taper Increment/Decrement

C Compatible Serial Interface

I 3V to 5V Single Supply Operation ±2.5V Dual Supply Operation 256 Bytes General Purpose User EEPROM 11 Bytes RDAC user EEPROM GBIC and SFP Compliant EEPROM 100-year Typical Data Retention at TA=55°C

APPLICATIONS Laser Diode Drivers Optical Amplifiers TIA Gain Setting TEC Controller Temperature Set Points

GENERAL DESCRIPTION

The ADN2860 provides dual 512-position and a single 128position digitally controlled variable resistor 4x4mm LFCSP package. This device performs the same electronic adjustment function as a potentiometer, trimmer, or variable resistor. Each VR offers a completely programmable value of resistance between the A terminal and the Wiper or the B terminal and the Wiper. The fixed A-to-B terminal resistance of 25kΩ or 250kΩ has a 1% channel-to-channel matching tolerance and a nominal temperature coefficient of 35ppm/°C.

Wiper position programming, EEPROM reading, and EEPROM writing is conducted via the standard 2-wire I Previous/Default wiper position settings can be stored in memory, and refreshed upon system power-up.

Additional features of the ADN2860 include preprogrammed linear and logarithmic increment/decrement wiper changing, and actual resistor tolerances are stored in EEPROM so that the

(VR) in a single

C interface.

VDD

VSS

GND

SCL

SDA

A0_R

A1_R

A0_E

A1_E

PRB

WPB

actual end-to-end resistance is known, which is valuable for calibration in precision applications.

The ADN2860 EEPROM, channel resolution, and package size conforms to GBIC and SFP specifications. The ADN2860 is available in a 4x4mm 24-lead LFCSP package. All parts are guaranteed to operate over the extended industrial temperature range of –40C to 85°C.

1. The term nonvolatile memory, EEMEM, and EEPROM are used

2. The term programmable resistor, variable resistor, RDAC, and digital

FUNCTIONAL BLOCK DIAGRAM

256 bytes

USER EEPROM

32 bytes

RDAC EEPROM

DATA

I2C

SERIAL

INTERFACE

POWER

ON RESET

interchangeably

potentiometer are used interchangeably.

CONTROL

COMMAND DECODE LOGIC

ADDRESS DECODE LOGIC

CONTROL LOGIC

RDAC0

RDAC1

RDAC2

RDAC0

9 bit

RDAC1

9 bit

RDAC2

7 bit

REV. PrD Page 1 of 15

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Tel: 781/329-4700 www.analog.com

Preliminary Technical Data ADN2860

ADN2860 ELECTRICAL CHARACTERISTICS 25k, 250k VERSIONS

( V

= 3V to 5.5V and –40C <TA<+85C, unless otherwise noted)

Parameter Symbol Conditions Min Typ

DC CHARACTERISTICS RHEOSTAT MODE (Specifications apply to all RDACs)

Resistor Differential Nonlinearity2 R-DNL RWB -2 +2 LSB

Resistor Integral Nonlinearity2 R-INL RWB -4 +4 LSB Resistance Temperature Coefficent ∆RAB/∆T 35 ppm/°C Wiper Resistance RW V V

Channel Resistance Matching ∆RWB/RWB Ch 1 and 2 RWB, Dx = 3FFH 0.1 % Nominal Resistor tolerance ∆RWB Dx = 3FFH -30 30 %

DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications apply to all VRs

Differential Nonlinearity3 DNL –2 +2 LSB Integral Nonlinearity3 INL –4 +4 LSB

Voltage Divider Temperature Coefficent ∆VW/∆T Code = Half-scale 15 ppm/°C Full-Scale Error V Zero-Scale Error V

Code = Full-scale -1.5 0 LSB

WFSE

Code = Zero-scale 0 +1.5 LSB

WZSE

RESISTOR TERMINALS

Terminal Voltage Range4 V

Capacitance5 Ax, Bx C

VSS V

A, B, W

f = 1 MHz, measured to GND, Code = Half-scale 11 pF

A,B

Capacitance5 Wx CW f = 1 MHz, measured to GND, Code = Half-scale 80 pF Common-mode Leakage Current

5,6

DIGITAL INPUTS & OUTPUTS

Input Logic High VIH with respect to GND, VDD = 5V 2.4 V Input Logic Low VIL with respect to GND, VDD = 5V 0.8 V Input Logic High VIH with respect to GND, VDD = 3V 2.1 V Input Logic Low VIL with respect to GND, VDD = 3V 0.6 V Input Logic High VIH with respect to GND, VDD = +2.5V, VSS=-2.5V 2.0 V Input Logic Low VIL with respect to GND, VDD = +2.5V, VSS=-2.5V 0.5 V Output Logic High (SDO, RDY) VOH R Output Logic Low VOL I Input Current IIL V

Input Capacitance5 C

5 pF

POWER SUPPLIES

Single-Supply Power Range VDD V

Dual-Supply Power Range VDD/VSS ±2.25 ±2.75 V Positive Supply Current IDD V

Positive Supply Current IDD V Programming Mode Current I

VIH = VDD or VIL = GND 35 mA

DD(PG)

Negative Supply Current ISS V

Power Dissipation8 P Power Supply Sensitivity5 P

DISS

∆VDD = +5V ±10% 0.002 0.01 %/%

NOTES: See bottom of table next page.

= +5V, IW = 1V/RWB 70 100 Ω

= +3V, IW = 1V/RWB 200 Ω

= VDD/2 0.01 1 µA

= 2.2KΩ to +5V 4.9 V

PULL-UP

= 1.6mA, V

= 0V or VDD ±5 µA

= 0V 3.0 5.5 V

= VDD or VIL = GND, TA=25oC 2 4.5 µA

= VDD or VIL = GND 3.5 10 µA

= VDD or VIL = GND, V

= VDD or VIL = GND 18 50 µW

= +5V 0.4 V

LOGIC

= 2.5V, V

= -2.5V 3.5 10 µA

Max Units

Page 2 of 15

Preliminary Technical Data ADN2860

ADN2860 ELECTRICAL CHARACTERISTICS 25k, 250k VERSIONS

( V

= 3V to 5.5V and –40C <TA<+85C, unless otherwise noted)

Parameter Symbol Conditions Min Typ1 Max Units

DYNAMIC CHARACTERISTICS

Bandwidth –3dB BW VDD/VSS = +/-2.5 V, RAB = 25 kΩ / 250 kΩ 125/12 kHz Total Harmonic Distortion THDW V VW Settling Time tS V

code 000H to 200H. RAB = 25 k/250 kΩ 4 / 36 µs Resistor Noise Spectral Density e

Crosstalk (CW1/CW2) CT V making full scale change, RAB = 25 k/250 kΩ 90/21 nV-s Analog Crosstalk CTA V V Code 2 = 3FFH, RAB = 25 kΩ / 250 kΩ -81/-62 dB

INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 6,12)

SCL Clock Frequency f t

Bus free time between STOP & START t

BUF

Hold Time (repeated START) t2 After this period the first clock pulse is generated 600 ns

HD;STA

Low Period of SCL Clock t3 1.3 µs

LOW

High Period of SCL Clock t4 0.6 50 µs

HIGH

Setup Time For START Condition t5 600 ns

SU;STA

Data Hold Time t6 900 ns

HD;DAT

Data Setup Time t7 100 ns

SU;DAT

tR Rise Time of both SDA & SCL signals t8 300 ns tF Fall Time of both SDA & SCL signals t9 300 ns t

Setup time for STOP Condition t10 600 ns

SU;STO

NOTES:

1. Typical represent average readings at +25°C, VDD = +5V.

2. Resistor position non-linearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See figure 20 test circuit.

3. INL and DNL are measured at V

DNL specification limits of ±1LSB maximum are Guaranteed Monotonic operating conditions. See Figure 19 test circuit.

4. Resistor terminals A, B, W have no limitations on polarity with respect to each other.

5. Guaranteed by design and not subject to production test.

6. Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value results in the minimum overall power consumption.

7. P

8. All dynamic characteristics use V

9. See timing diagram for location of measured values.

10. Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at –40 °C, +25°C and +85°C, typical endurance at 25°C is 700,000 cycles.

11. Retention lifetime equivalent at junction temperature (T

The ADN2860 contains 21,035 transistors. Die size: 88.2 mil x 87.0 mil, 7673 sq. mil. Specifications Subject to Change without Notic

is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

temperature.

5, 9

=1Vrms, VB = 0V, f=1 kHz 0.05 %

= VDD, VB=0V, VW=0.50% error band,

RAB = 25 kΩ / 250 kΩ, TA = 25oC 20 / 64 nV√Hz

N_WB

= VDD, VB = 0V, Measured VW1 with VW2

= VA1 = +2.5 V, VSS = VB1 = -2.5 V, Measure

with V

0 400 KHz

SCL

1.3 µs

with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0V.

= +5V.

) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6eV will derate with junction

= 5V p-p @ f = 1kHz, Code1 = 200H,

Page 3 of 15

Preliminary Technical Data ADN2860

Absolute Maximum Rating1 (T

= +25°C, unless

otherwise noted)

VDD to GND..........................................................-0.3 V, +7 V

VSS to GND ..........................................................+0.3 V, -7 V

VDD to VSS........................................................................+7 V

, VB, VW to GND.............................VSS-0.3 V, VDD+0.3 V

IA, IB, IW

Intermittent

.................................................±20 mA

Continuous..................................................... ±2 mA

Digital Inputs & Output Voltage to GND... -0.3 V, VDD+0.3 V

Operating Temperature Range3.......................-40°C to +85°C

Maximum Junction Temperature (T

Storage Temperature......................................-65°C to +150°C

Lead Temperature, Soldering

MAX

)...................+150°C

Vapor Phase (60 sec) .......................................+215 °C

Infrared (15 sec)...............................................+220 °C

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADN2860 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Thermal Resistance Junction-to-Ambient θ

JA,

LFCSP-24................................................... TBD °C/W

Thermal Resistance Junction-to-Case

JC,

LFCSP-24................................................... TBD °C/W

Package Power Dissipation = (T

MAX - TA) / θ

NOTES

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

2. Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the B, and W terminals at a given resistance.

3. Includes programming of Nonvolatile memory

Page 4 of 15

Preliminary Technical Data ADN2860

ADN2860ACP PIN CONFIGURATION

PIN DESCRIPTIONS

# Name Description 1 RESET Reset the scratch pad register with current contents of the EEMEM register. Factory defaults midscale before any programming 2 WP Write Protect Pin. When active low, WP prevents any changes to the present register contents, except PR and cmd 1 and 8 will refresh the

3 SCL Serial Input Register clock pin. Shifts in one bit at a time on positive clock edges. 4 SDA Serial Data Input Pin. Shifts in one bit at a time on positive clock CLK edges. MSB loaded first. 5 DGND Ground pin, logic ground reference

Negative Supply. Connect to zero volts for single supply applications.

6 V

7 A2 A terminal of RDAC2. 8 W2 Wiper terminal of RDAC2 9 B2 B terminal of RDAC2. 10 A1 A terminal of RDAC1. 11 W1 Wiper terminal of RDAC1 12 B1 B terminal of RDAC1 13 A0 A terminal of RDAC0. 14 W0 Wiper terminal of RDAC0. 15 B0 B terminal of RDAC0 16 V 17 TEST3 Test pin 3 (Do Not Connect) 18 TEST2 Test pin 2 (Do Not Connect) 19 TEST1 Test pin 1 (Do Not Connect) 20 TEST0 Test pin 0 (Do Not Connect) 21 A1_EE I2C Device Address 1 for EEMEM 22 A0_EE I2C Device Address 0 for EEMEM 23 AD1 I2C Device Address 1 for RDAC 24 AD0 I2C Device Address 0 for RDAC

Positive Power Supply Pin.

RDAC register from EEMEM. Execute a NOP instruction before returning to WP high.

Page 5 of 15

Preliminary Technical Data ADN2860

I2C Interface Timing Diagram

SDA

SCL

PS SP

Figure 1. I2C Timing Diagram

I2C Interface General Description

From Master to Slave

From Slave to Master

S = Start Condition P = Stop Condition A = Acknowledge (SDA Low)

A = Not Acknowledge (SDA High) R/W= Read Enable at High and Write Enable at Low

S Slave Address R/W A Data A Data A/A P

0=Write

Figure 2. I

C - Master Transmitting Data to Slave

S Slave Address R/W A Data A Data

Data Transferred

(N bytes + Acknowledge)

1 Read

Figure 3. I

C - Master Reading Data From Slave

Data Transferred

(N bytes + Acknowledge)

S Slave Address

A Data

R/W

A/A

S Slave Address

R/W

A Data

A/A

Read or Write Read or Write

Figure 4. I

Repeated Start (N bytes + Acknowledge)

C – Combined Transmit/Read

(N bytes + Acknowledge)

Direction of Transfer may change at this point

Page 6 of 15

Preliminary Technical Data ADN2860

EEPROM I2C Interface Description

S 1 0 1 0 0 A

0 A Memory Address A Memory Data A Memory Data A/A P 0 E

EEPROM Slave Address

0 Write

Figure 5. EEPROM Write

S 1 0 1 0 0 A

EEPROM Slave Address

1 A Memory Data A Memory Data 0 E

1 Read

Figure 6. EEPROM Current Read

S Slave Address

A Memory Address A S Slave Address R A Memory Data

0 Write

Figure 7. EEPROM Random Read

EEPROM Interface Operation

The 256 bytes of EEPROM memory provided in the ADN2860 are organized into 16 pages of 16 bytes each. The word size of each memory location is one byte wide.

The I

C slave address of the EEPROM is 10100(A1E)(A0E), where A1E and A0E are external pin programmable address bits. The two pin programmable address bits allow a total of four ADN2860 devices to be controlled by a single I

C master

bus, each having its own EEPROM.

An internal 8-bit address counter for the EEPROM is automatically incremented following each read or write operation. For read operations, the address counter is incremented after each byte is read, and the counter will rollover from address location 255 to 0.

For write operations, the address counter will be incremented after each byte written. The counter rolls-over from the upper most address of the current page to the lower most address of the current page. For example, writing two bytes beginning at address location 31 will cause the counter to roll back to address location 16 after the first byte is written, and then the address will increment to 17 after the second byte is written.

EEPROM Write

Each write operation issued to the EEPROM can program 1 byte to 16 bytes (1 page) of memory. Figure 5 shows the EEPROM write interface, the number of bytes of data, N, the user wishes to send to the EEPROM is unrestricted. If more than 16 bytes of data are sent in a single write operation, the address counter will rollback to the beginning address, and the previously sent data will be overwritten.

Repeated Start

EEPROM Write-Acknowledge Polling

After each write operation, an internal EEPROM write cycle begins. During the EEPROM internal write cycle, the I interface of the device will be disabled. In order to determine if the internal write cycle is complete and whether the I interface is enabled, interface polling must be executed. I interface polling can be conducted by sending a start condition followed by the EEPROM slave address + desired R/W bit. If the ADN2860 I write cycle is complete and the interface is ready to proceed with further operations. Otherwise, the I polled again to determine whether the write cycle has been completed.

EEPROM Read

The ADN2860 EEPROM provides two different read operations, shown in figures 6 and 7. The number of bytes, N, read from the EEPROM in a single operation is unrestricted. If more than 256 bytes are read, the address counter will rollback to the start address, and data previously read will be read again.

Figure 6 shows the EEPROM Current Read operation. This operation does not allow an address location to be specified and reads data beginning at the current address location stored in the internal address counter.

A random read operation is shown in figure 7. This operation changes the address counter to the specified memory address by performing a “dummy write” and then performing a read operation beginning at the new address counter location.

EEPROM Write Protection

(N bytes + Acknowledge)

1 Read

C interface responds with an ACK, then the

(N bytes + Acknowledge)

C interface needs to be

A/A

Page 7 of 15

Preliminary Technical Data ADN2860

Setting the WP pin to a logic LOW protects the EEPROM memory from future write operations. In this mode, EEPROM read operations and RDAC register loading can still operate normally.

RDAC I2C Interface Description

S 0 1 0 1 1 A

RDAC Slave Address

0 0 R

0 Write

1 A RDAC EEPROM or Register Data A RDAC EEPROM or Register Data 0 R

CMD/W 0 EE/

Figure 8. RDAC Write

REG

RDAC Address

A4 A3 A2 A1 A0 A Data A Data A/ A P

(N bytes + Acknowledge)

S Slave Address

RDAC Register Addresses

0 0 1 0 1 to

Table 1. RDAC Register Address Table

RDAC R/W EEPROM Address Table

Table 2. RDAC R/W EEPROM Address Table

RDAC Slave Address

1 Read

Figure 9. RDAC Current Read

A RDAC Address A S Slave Address R A RDAC Data

0 Write

(CMD/W=0, EE/REG=0)

A4 A3 A2 A1 A0 RDAC Byte Description

0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0

1 1 1 1 1

RDAC0 RDAC0 RDAC1 RDAC1 RDAC2

(D7)(D6)(D5)(D4)(D3)(D2)(D1)(D0) – RDAC0 8 LSBs (X)(X)(X)(X)(X)(X)(X)(D8) – RDAC0 MSB (D7)(D6)(D5)(D4)(D3)(D2)(D1)(D0) – RDAC1 8 LSBs (X)(X)(X)(X)(X)(X)(X)(D8) – RDAC1 MSB (X)(D6)(D5)(D4)(D3)(D2)(D1)(D0) – RDAC2 7 bits reserved

Figure 10. RDAC Random Read

Repeated Start

(CMD/W=0, EE/REG=1) RDAC Read-Only EEPROM Address Table (CMD/W=0, EE/REG=1)

A4 A3 A2 A1 A0 Byte Description A4 A3 A2 A1 A0 Byte Description

0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0

0 0 1 0 1 to

0 1 1 1 1

RDAC0 8 LSBs RDAC0 MSB RDAC1 8 LSBs RDAC1 MSB RDAC2 7 bits

11 bytes RDAC USER EEPROM

1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0

1 0 1 0 1 to

1 1 1 1 1

(N bytes + Acknowledge)

1 Read

% Tolerance % Tolerance % Tolerance % Tolerance % Tolerance

reserved

A/A

(N bytes + Acknowledge)

Page 8 of 15

Preliminary Technical Data ADN2860

RDAC I2C Interface Description (cont’d)

S 0 1 0 1 1 A

RDAC Slave Address

RDAC Command Table (CMD/W=1)

C3 C2 C1 C0

Command Description

0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1

1 1 0 0 to

1 1 1 1

Table 3. RDAC Commands

* This command leaves the device in the EEPROM Read power state. Issue the NOP command to return the device to the idle state.

RDAC Interface Operation

Each programmable resistor wiper setting is controlled by specific RDAC registers, as shown in the RDAC Register Address Table (table 1). Each RDAC register corresponds to an EEPROM memory location, which provides non-volatile wiper storage functionality.

RDAC registers and their corresponding EEPROM memory locations can be programmed and read independently from each other. The RDAC register can be refreshed by the EEPROM locations either with a hardware reset via pin 1, or by issuing one of the various RDAC register load commands shown in the RDAC command table (table 3).

RDAC Write

Setting the wiper position requires an RDAC write operation, shown in figure 8. RDAC write operations follow a format similar to the EEPROM write interface. The only difference between an RDAC write and an EEPROM write operation is the use of an RDAC address byte in place of the memory address used in the EEPROM write operation. The RDAC address byte is described in detail in the tables 1 and 2.

As with the EEPROM write operation, the RDAC write operation disables the I cycle. Acknowledge polling, as described in the EEPROM I

C interface during the internal write

0 A CMD/ W C3 C2 C1 C0 A2 A1 A0 A P

0 R

0 Write

Figure 11. RDAC Command Write (Dummy Write)

1 Cmd

NOP Load EEPROM to RDAC* Store RDAC to EEPROM Decrement RDAC 6dB Decrement All RDACs 6dB Decrement RDAC One Step Decrement All RDACs One Step Reset: Load EEPROM to all RDACs Increment RDAC 6dB Increment All RDAC 6dB Increment RDAC One Step Increment All RDAC One Step reserved

interface section, is required to determine whether the write cycle has been completed.

RDAC Read

The ADN2860 provides two RDAC read operations. The first, shown in figure 9 reads the contents of the current RDAC address counter. Figure 10 illustrates the second read operation. This operation allows users to specify which RDAC register to read by first issuing a “dummy write” command to change the RDAC address pointer, and then proceeding with the RDAC read operation at the new address location.

The read-only RDAC EEPROM memory locations can also be read by using the address and bits specified in the RDAC ReadOnly EEPROM Address Table (table 2).

RDAC Quick Commands

Eleven shortcut “quick” commands are provided for easy manipulation of RDAC registers and their corresponding EEPROM memory locations. These commands are shown in table 3.

The interface for issuing an RDAC quick command is shown in figure 11. All quick commands require Acknowledge polling to determine whether the command has finished executing.

Page 9 of 15

Preliminary Technical Data ADN2860

A more detailed discussion about the RDAC quick commands can be found in the Operational Overview section of this document.

OPERATIONAL OVERVIEW

The ADN2860 digital potentiometer is designed to operate as a true variable resistor. The resistor wiper position is determined by the RDAC register contents. The RDAC register acts like a scratch-pad register, allowing unlimited changes of resistance settings. RDAC register contents can be changed using the ADN2860’s serial I and commands to program the RDAC registers are discussed in the RDAC I

RDAC registers also have a corresponding EEPROM memory location, which provide non-volatile storage of resistor wiper position settings. The ADN2860 provides commands to store the RDAC register contents to their respective EEPROM memory locations. During subsequent power on sequences, the RDAC registers will automatically be loaded with the stored value.

Saving data from an RDAC register to EEPROM memory takes approximately 25ms and consumes 20mA of current.

In addition to the movement of data between RDAC registers and EEPROM memory, the ADN2860 provides other shortcut commands that facilitate the users’ programming needs.

1. Restore EEPROM setting to RDAC

2. Save RDAC register contents to EEPROM

3. Decrement RDAC 6dB (Shift Data Bits Right)

4. Decrement all RDACs 6dB (Shift All Data Bits Right)

5. Decrement RDAC one step

6. Decrement all RDACs one step

7. Reset EEPROM setting to RDAC

8. Increment RDAC 6dB (Shift Data Bits Left)

9. Increment all RDACs 6dB (Shift All Data Bits Left)

10. Increment RDAC one step

11. Increment all RDACs one step

Linear Increment and Decrement Commands

The increment and decrement commands (#10, #11, #5, #6) are useful for linear step adjustment applications. These commands simplify microcontroller software coding by allowing the controller to just send an increment or decrement command to the ADN2860. The adjustment can be directed to an individual RDAC or all three RDACs.

Logarithmic Taper Mode Adjustment (±6dB/step)

The ADN2860 accommodates logarithmic taper adjustment of the RDAC wiper position(s) by shifting the register contents left/right for increment/decrement operations. Commands 8, 9, 3, and 4 can be used to logarithmically increment or decrement the wiper positions individually or change all three channel settings at the same time.

C interface. The format of the datawords

C Interface section of this document.

Table 4. ADN2860 Shortcut Commands

Incrementing the wiper position by +6dB is essentially doubling the RDAC register value, while decrementing by –6dB is halving the register content. Internally, the ADN2860 uses a shift register to shift the bits left and right to achieve a logarithmic increment or decrement.

Non-ideal ±6dB step adjustment occurs under certain conditions. Table 5 illustrates the shifting function on an individual RDAC register data bits. Each line going down the table represents a successive shift operation. Note that the left shift (#10 & #11) commands were modified such that if the data in the RDAC register is equal to zero, and the data is shifted the RDAC register is then set to code 1. Similarly, if the data in the RDAC register is greater than or equal to mid-scale, and the data is left shifted, the data in the RDAC register is automatically set to full-scale. This makes the left shift function as close to a logarithmic adjustment as possible.

The right shift commands (#3 & #4) will be ideal only if the LSB is a 0 (ideal logarithmic = no error). If the LSB is a 1 then the right shift function generates a linear half LSB error, which translates to a number of error bits.

Left Shift Right Shift 0 0000 0000 1 1111 1111 0 0000 0001 0 1111 1111 0 0000 0010 0 0111 1111 0 0000 0100 0 0011 1111

Left

Shift

(+6dB/step)

Table 5. RDAC Register Contents After ±6dB Step Adjustments

Actual conformance to a logarithmic curve between the data contents in the RDAC register and the wiper position for each right shift (#3 & #4) command execution contains an error only for odd numbers of bits. Even numbers of bits are ideal. The graph in figure 12 shows a plot of Log_Error [i.e. 20*Log10(error/code)] for the ADN2860.

Figure 12. Plot of Log_Error Conformance for Odd Numbers of

0 0000 1000 0 0001 1111 0 0001 0000 0 0000 1111 0 0010 0000 0 0000 0111 0 0100 0000 0 0000 0011 0 1000 0000 0 0000 0001 1 0000 0000 0 0000 0000 1 1111 1111 0 0000 0000 1 1111 1111

Bits Only (Even Numbers of Bits are ideal)

(-6dB/step)

Page 10 of 15

Right

Shift

Preliminary Technical Data ADN2860

Using Additional Internal Nonvolatile EEPROM

The ADN2860 contains additional internal user EEPROM for saving constants and other data. The user EEPROM I

C dataword follows the same format as the general purpose EEPROM memory shown in figures 5 and 6. User EEPROM memory addresses are shown at the bottom of table 2.

To support the use of multiple EEPROM modules on a single

C bus, the ADN2860 features two external addressing pins, pins 21 and 22 (A1_EE and A0_EE) to manually set the address of the EEPROM included with the ADN2860. This feature ensures that the correct EEPROM memory is accessed when using multiple memory modules on a single I

C bus.

Digital Input/Output Configuration

All digital inputs are ESD protected. Digital inputs are high impedence and can be driven directly from most digital sources. Active at logic low, RESET and WP should be biased to V

if they are not used. There are no internal pull-up resistors present on any of the digital input pins of the ADN2860. As a result, pull-up resistors are needed if these functions are not used.

ESD protection of the digital inputs is shown in figure 13.

INPUT

Ω

300

GND

Figure 13. Equivalent WP Input Protection

Multiple Devices On One Bus

Figure 14 shows four ADN2860 devices on the same serial bus. Each has a different slave address since the state of their AD0 and AD1 pins are different. This allows each RDAC within each device to be written to or read from independently.

R p

+ 5 V

R p

Level Shift for Bi-Directional Communication

While most old systems may be operating at one voltage, a new component may be optimized at another. When two systems transmit the same signal at two different voltages, proper level shifting is required.

In some instances, for example, a 3.3V EEPROM memory module may be used along with a 5V digital potentiometer. A level shifting scheme is required in order to enable bi-directional communication between the two devices.

= 3.3V V

DD1

M 2

SDA1

SCL1

Rp Rp

3.3V

E2PROM

ADN2860

DD2

= 5V

SDA2

SCL2

Figure 15. Level Shifting for different voltage devices on an I2C

bus

Figure 15 shows one of many possible techniques to properly level shift signals between two devices. M1 and M2 can be Nchannel FETs (2N7002). If V

falls below 2.5V, M1 and M2

should be low threshold N-channel FETs (FDV301N).

Terminal Voltage Operation Range

The ADN2860 positive V

and negative VSS power supply

inputs define the boundary conditions for proper 2-terminal programmable resistance operation. Supply signals on terminals W and B that exceed V

or VSS will be clamped by the internal

forward biased diodes of the ADN2860.

M A S T E R

S D A S C L

A D 1

A D 0

S D A S C L

V D D

S D A S C L

A D 1

A D 0

V D D

A D 1

A D 0

V D D

Figure 14. Multiple ADN2860 Devices on a Single Bus

SD A SCL

AD1

AD0

SD A

SC L

Figure 16. Maximum Terminal Voltages Set by V

& VSS

The ground pin of the ADN2860 device is primarily used as a digital ground reference, which needs to be tied to the common ground of the PCB. The digital input control signals to the ADN2860 must be referenced to the device ground pin, and satisfy the logic levels defined in the specification table of this datasheet.

An internal level shift circuit insures that the common mode voltage range of the 2-terminals extends from V

to VDD

Page 11 of 15

Preliminary Technical Data ADN2860

irrespective of the digital input level. In addition, there is no polarity constraint on the voltage across terminals W and B. The magnitude of |V

| is bounded by VDD -VSS.

Power-Up Sequence

Since there are ESD protection diodes that limit the voltage compliance at terminals A, B, and W (see figure 16), it is important to power V

/ VSS before applying any voltage to

terminals A, B, and W. Otherwise, the diode will be forward biased such that V

/ VSS will be powered unintentionally and

may affect the rest of the users’ circuit. The ideal power-up sequence is in the following order: GND, V inputs, and V

. The order of powering V A, V B, V W, and

A/B/W

, VSS, digital

digital inputs is not important as long as they are powered after V

/ VSS.

Layout and Power Supply Biasing

It is always a good practice to employ compact, minimum lead length layout design. The leads to the input should be as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance.

Similarly, it is also good practice to bypass the power supplies with quality capacitors. Low ESR (Equivalent Series Resistance) 1µF to 10µF tantalum or electrolytic capacitors should be applied at the supplies to minimize any transient disturbance and filter low frequency ripple. Figure 17 illustrates the basic supply bypassing configuration for the ADN2860.

Figure 17. Power Supply Bypassing

RDAC Structure

The patent pending RDAC contains a string of equal resistor segments, with an array of analog switches. The switches act as the wiper connection.

The ADN2860 has two RDACs with 512 connection points allowing it to provide better than 0.2% set-ability resolution. The ADN2860 also contains a third RDAC with 128 step resolution.

Figure 18 shows an equivalent structure of the connections between the two terminals that make up one channel of an RDAC. The SWB switch will always be ON, while on of the switches SW(0) to SW(2N-1) will be ON at any given time depending on the resistance position decoded from the databits in the RDAC register.

Since the switches are non-ideal, there is a 50Ω wiper resistance, R

. Wiper resistance is a function of supply voltage

and temperature, lower supply voltages and higher temperatures result in higher wiper resistances. Consideration of wiper resistance dynamics is important in applications where accurate prediction of output resistance is required.

RDAC

WIPER

DECODER

RS=R

DIGITAL CIRCUITRY OMITTED FOR CLARITY

WB_FS

SW(2N-1)

SW(1 )

SW(0 )

SWB

-2)

SW(2

Figure 18.. Equivalent RDAC structure

Calculating the Programmable Resistance

The nominal resistance of the RDAC between terminals A and B is available in 25kΩ or 250kΩ. The final two or three digits of the part number determine the nominal resistance value, e.g. 25kΩ = 25 and 250kΩ = 250.

The following discussion describes the calculation of resistance

(D) at different codes of a 25kΩ part for RDAC 0. The 9-

bit data word in the RDAC latch is decoded to select one of the 512 possible settings.

The wiper first connection starts at the B terminal for data 000H. R

independent to the full-scale resistance. The second connection is the first tap point where R for data 001H. The third connection is the next tap point

representing R

Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at R See Figure 18 for a simplified diagram of the equivalent RDAC circuit.

The general equations that determine the programmed output resistance between W and B are:

(0) is 50Ω because of the wiper resistance and it is

(1) becomes 48.8Ω + 50 = 98.8Ω

(2)=97.6+50=147.6 for data 002H and so on.

(512)=25001Ω.

Page 12 of 15

Preliminary Technical Data ADN2860

)( (RDAC 0 and 1)

R +⋅=

512

)( (RDAC 2 only)

128

(1)

(2)

Where D is the decimal equivalent of the data contained in the RDAC register and RW is the wiper resistance.

The output resistance values in table 6 will be set for the following RDAC latch codes with VDD = 5 V (applies to R

25 kΩ Digital Potentiometers):

D R

(D)

Output State

(DEC) (Ω)

511 25001 Full-Scale 256 12550 Mid-Scale 1 98.8 1 LSB 0 50 Zero-Scale (Wiper contact resistance)

Table 6. R

at Selected Codes for R

WB_FS

= 25 kΩ

Note that in the zero-scale condition a finite wiper resistance of 50Ω is present. Care should be taken to limit the current flow between W and B in this state to no more than 20mA to avoid degradation or possible destruction of the internal switches.

Channel-to-channel R

matching is better than 1%. The

change in RWB with temperature has a 35ppm/°C temperature

coefficient.

Like the mechanical potentiometer the RDAC replaces, the ADN2860 parts are totally symmetrical. The resistance between the wiper W and terminal A also produces a digitally controlled complementary resistance R

. When RWA is used, the B

terminal can be let floating or tied to the wiper. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch is increased in value. The general transfer equation for this operation is:

−

R +⋅

)( (RDAC 0 and 1) (3)

512

−

R +⋅

)( (RDAC 2 only) (4)

128

For example, the following output resistance values will be set for the following RDAC latch codes (applies to R

=25 k

Digital Potentiometers):

D RWA(D) Output State (DEC) (Ω)

511 98.8 full-scale 128 12550 Mid-scale 1 25001 1 LSB 0 25050 Zero-scale

Table 7. ADN2860. R

(D) at selected codes for RAB = 25 kΩ.

The typical distribution of R

from channel-to-channel

matches to ±0.2% within the same package. Device to device matching is process lot dependent, with a worst case of ±30% variation. Changes in R

with temperature has a 35ppm/°C

temperature coefficient.

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

The digital potentiometer can be configured to generate an output voltage at the wiper terminal, which is proportional to the input voltages applied to terminals A and B. Connecting terminal A to +5V and terminal B to ground produces an output voltage at the wiper which can be any value starting at zero volts up to +5V. Each LSB of voltage is equal to the voltage applied across terminals A and B divided by the 2

position

resolution of the potentiometer divider.

Since ADN2860 can also be supplied by dual supplies, the general equations defining the output voltage at V

with respect

to ground for any given input voltages applied to terminals A and B are:

512

V +⋅=

)( (RDAC 0 and 1) (5)

128

V +⋅=

)( (RDAC 2) (6)

Equation 5 assumes V

is buffered so that the effect of wiper

resistance is nulled. Operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. In this mode, the output voltage is dependent on the ratio of the internal resistors not the absolute value, therefore, the drift improves to 15ppm/°C. There is no voltage polarity restriction between terminals A, B, and W as long as the terminal voltage (V

) stays within VSS < V

TERM

< VDD.

APPLICATIONS

Laser Diode Driver (LDD) calibration

The ADN2860 can be used with any laser diode driver. Its high resolution, compact footprint, and superior temperature drift characteristics make it ideal for optical parameter setting.

The ADN2841 is a 2.7 Gbps laser diode driver that utilizes a unique control algorithm to manage both the laser average power and extinction ratio after initial factory calibration. It stabilizes the laser data transmission by continuously monitoring its optical power, and correcting the variations caused by temperature and the laser degradation over time. In ADN2841, the I its dual loop Power and Extinction Ratio control, calibrated by ADN2860, the internal driver controls the bias current I and consequently the average power. It also regulates the modulation current, I linearly with slope efficiency. Any changes in the laser threshold current or slope efficiency are therefore compensated. As a result, this optical supervisory system minimizes the laser characterization efforts and therefore

monitors the laser diode current. Through

MPD

by changing the modulation current

MODP

Page 13 of 15

BIAS

Preliminary Technical Data ADN2860

enables designers to apply comparable lasers from multiple sources.

Figure 19. Optical Supervisory System

Page 14 of 15

Preliminary Technical Data ADN2860

Outline Dimensions

Dimensions shown in inches and (mm).

[4x4mm 24-Lead LFCSP package diagrams To Be Provided]

Page 15 of 15

Datasheet ADN2860 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual