3 V Dual-Loop 50 Mbps to 1.25 Gbps
a
FEATURES
50 Mbps to 1.25 Gbps Operation
Single 3.3 V Operation
Bias Current Range 2 mA to 100 mA
Modulation Current Range 5 mA to 80 mA
Monitor Photo Diode Current 50 A to 1200 A
50 mA Supply Current at 3.3 V
Closed-Loop Control of Power and Extinction Ratio
Full Current Parameter Monitoring
Laser Fail and Laser Degrade Alarms
Automatic Laser Shutdown, ALS
Optional Clocked Data
Supports FEC Rates
32-Lead (5 mm × 5 mm) LFCSP Package
APPLICATIONS
SONET OC-1/3/12
SDH STM-0/1/4
Fibre Channel
Gigabit Ethernet
Laser Diode Driver
ADN2848
GENERAL DESCRIPTION
The ADN2848 uses a unique control algorithm to control both
the average power and extinction ratio of the laser diode, LD,
after initial factory setup. External component count and PCB
area are low as both power and extinction ratio control are
fully integrated. Programmable alarms are provided for laser fail
(end of life) and laser degrade (impending fail).
MPD
GND
GND
V
CC
IMPD
PSET
ERSET
FUNCTIONAL BLOCK DIAGRAM
V
CC
IBMON
IMMON
IMPDMON
ALS
CONTROL
FAIL
DEGRADE
I
MOD
I
BIAS
PAV CAPERCAP
GNDGND
IMODN
CLKSEL
ADN2848
LBWSET
CC
V
GND
IMODP
I
BIAS
ASET
GND
DATAP
DATAN
CLKP
CLKN
V
CC
LD
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
1
ADN2848–SPECIFICATIONS
(VCC = 3.0 V to 3.6 V. All specifications T
Typical values as specified at 25C.)
MIN
to T
, unless otherwise noted.
MAX
Parameter Min Typ Max Unit Conditions/Comments
LASER BIAS (BIAS)
Output Current I
BIAS
Compliance Voltage 1.2 V
During ALS 0.1 mA
I
BIAS
ALS Response Time 5 sI
CCBIAS Compliance Voltage 1.2 V
2 100 mA
CC
CC
V
V
< 10% of nominal
BIAS
MODULATION CURRENT (IMODP, IMODN)
Output Current I
MOD
Compliance Voltage 1.5 V
I
During ALS 0.1 mA
MOD
Rise Time
Fall Time
Random Jitter
Pulsewidth Distortion
2
2
2
2
580mA
CC
V
80 170 ps
80 170 ps
1 1.5 ps RMS
15 ps I
= 40 mA
MOD
MONITOR PD (MPD)
Current 50 1200 AAverage Current
Compliance Voltage 1.65 V
POWER SET INPUT (PSET)
Capacitance 80 pF
Monitor Photodiode Current into RPSET Resistor 50 1200 AAverage Current
Voltage 1.1 1.2 1.3 V
EXTINCTION RATIO SET INPUT (ERSET)
Allowable Resistance Range 1.2 25 kΩ
Voltage 1.1 1.2 1.3 V
ALARM SET (ASET)
Allowable Resistance Range 1.2 25 kΩ
Voltage 1.1 1.2 1.3 V
Hysteresis 5 %
CONTROL LOOP Low Loop Bandwidth Selection
Time Constant 0.22 s LBWSET = GND
DATA INPUTS (DATAP, DATAN, CLKP, CLKN)
3
2.25 s LBWSET = V
CC
V p-p (Single-Ended, Peak-to-Peak) 100 500 mV Data and Clock Inputs Are
Input Impedance (Single-Ended) 50 Ω AC-Coupled
4
(see Figure 1) 50 ps
t
SETUP
4
t
(see Figure 1) 100 ps
HOLD
LOGIC INPUTS (ALS, LBWSET, CLKSEL)
V
IH
V
IL
2.4 V
0.8 V
ALARM OUTPUTS (Internal 30 kΩ Pull-Up)
V
OH
V
OL
2.4 V
0.8 V
IBMON, IMMON, IMPDMON
IMMON Division Ratio 100 A/A
IMPDMON 1 A/A
Compliance Voltage 0 VCC – 1.2 V
SUPPLY
5
I
CC
6
V
CC
NOTES
1
Temperature range is as follows: –40°C to +85°C.
2
Measured into a 25 Ω load using a 0-1 pattern at 622 Mbps.
3
When the voltage on DATAP is greater than the voltage on DATAN, the modulation current flows in the IMODP pin.
4
Guaranteed by design and characterization. Not production tested.
5
I
for power calculation on page 6 is the typical ICC given.
CCMIN
6
All VCC pins should be shorted together.
Specifications subject to change without notice.
3.0 3.3 3.6 V
50 mA I
BIAS
= I
MOD
= 0
REV. 0–2–
ADN2848
ABSOLUTE MAXIMUM RATINGS
(TA = 25°C, unless otherwise noted.)
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 V
Digital Inputs
(ALS, LBWSET, CLKSEL) . . . . . . . . . –0.3 V to V
IMODN, IMODP . . . . . . . . . . . . . . . . . . . . . . . . . V
Operating Temperature Range
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
1
ORDERING GUIDE
Temperature Package
Model Range Description
+ 0.3 V
CC
+ 1.2 V
CC
ADN2848ACP-32 –40°C to +85°C 32-Lead LFCSP
ADN2848ACP-32-RL –40°C to +85°C 32-Lead LFCSP
ADN2848ACP-32-RL7 –40°C to +85°C 32-Lead LFCSP
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (T
32-Lead LFCSP Package
Power Dissipation
Thermal Impedance3 . . . . . . . . . . . . . . . . . . . . . 32°C/W
θ
JA
max) . . . . . . . . . . . . . . . . . . . 150°C
J
2
. . . . . . . . . . . . . . . . (TJ max – TA)/θJA W
SETUP
t
S
Lead Temperature (Soldering for 10 sec) . . . . . . . . . . 300°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2
Power consumption formulae are provided on Page 6.
3
θ
is defined when device is soldered in a 4-layer board.
JA
DATAP/DATAN
CLKP
Figure 1. Setup and Hold Time
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADN2848 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
HOLD
t
H
REV. 0
–3–
ADN2848
PIN CONFIGURATION
3
CC
20 ALS
19 FAIL
18 DEGRADE
21 V
IMPD 5
PSET 4
17 CLKSEL
4 8
CC
V
GND4 7
IMPDMON 6
16 CLKN
15 CLKP
14 GND1
13 DATAP
12 DATAN
1
11 V
CC
10 PAVCAP
9 ERCAP
CC
CC
CC
24 IBMON
23 IMMON
22 GND3
2 25
V
CC
IMODN 26
GND2 27
IMODP 28
GND2 29
GND2 30
31
I
BIAS
CCBIAS 32
ADN2848
TOP VIEW
ASET 2
ERSET 3
LBWSET 1
PIN FUNCTION DESCRIPTIONS
Pin Number Mnemonic Function
1 LBWSET Loop Bandwidth Select
2 ASET Alarm Threshold Set Pin
3 ERSET Extinction Ratio Set Pin
4 PSET Average Optical Power Set Pin
5 IMPD Monitor Photodiode Input
6IMPDMON Mirrored Current from Monitor Photodiode—Current Source
7 GND4 Supply Ground
8V
4 Supply Voltage
CC
9 ERCAP Extinction Ratio Loop Capacitor
10 PAVCAP Average Power Loop Capacitor
11 V
1 Supply Voltage
CC
12 DATAN Data Negative Differential Terminal
13 DATAP Data Positive Differential Terminal
14 GND1 Supply Ground
15 CLKP Data Clock Positive Differential Terminal, Used if CLKSEL = V
16 CLKN Data Clock Negative Differential Terminal, Used if CLKSEL = V
17 CLKSEL Clock Select (Active = VCC), Used if Data Is Clocked into Chip
18 DEGRADE DEGRADE Alarm Output
19 FAIL FAIL Alarm Output
20 ALS Automatic Laser Shutdown
21 V
3 Supply Voltage
CC
22 GND3 Supply Ground
23 IMMON Modulation Current Mirror Output—Current Source
24 IBMON Bias Current Mirror Output—Current Source
25 V
2 Supply Voltage
CC
26 IMODN Modulation Current Negative Output, Connect via Matching Resistor to V
27 GND2 Supply Ground
28 IMODP Modulation Current Positive Output, Connect to Laser Diode
29 GND2 Supply Ground
30 GND2 Supply Ground
31 I
BIAS
Laser Diode Bias Current Output
32 CCBIAS Extra Laser Diode Bias When AC-Coupled—Current Sink
REV. 0–4–
ADN2848
GENERAL
Laser diodes have current-in to light-out transfer functions as
shown in Figure 2. Two key characteristics of this transfer function are the threshold current, I
, and slope in the linear region
TH
beyond the threshold current, referred to as slope efficiency, LI.
P1
ER =
P0
P1 + P0
P
=
AV
2
P
P
LI =
I
I
TH
I
CURRENT
P
OPTICAL POWER
P1
AV
P0
Figure 2. Laser Transfer Function
Control
A monitor photodiode, MPD, is required to control the LD.
The MPD current is fed into the ADN2848 to control the power
and extinction ratio, continuously adjusting the bias current and
modulation current in response to the laser’s changing threshold
current and light-to-current slope efficiency.
The ADN2848 uses automatic power control, APC, to maintain
a constant average power over time and temperature.
The ADN2848 uses closed-loop extinction ratio control to
allow optimum setting of extinction ratio for every device. Thus
SONET/SDH interface standards can be met over device
variation, temperature, and laser aging. Closed-loop modulation
control eliminates the need to either overmodulate the LD or
include external components for temperature compensation.
This reduces research and development time and second
sourcing issues caused by characterizing LDs.
Average power and extinction ratio are set using the PSET and
ERSET pins, respectively. Potentiometers are connected
between these pins and ground. The potentiometer R
used to change the average power. The potentiometer R
PSET
is
ERSET
is
used to adjust the extinction ratio. Both PSET and ERSET are
kept 1.2 V above GND.
For an initial setup, R
PSET
and R
potentiometers may be
ERSET
calculated using the following formulas.
PSET
P
CW
12.
=
_
I
12
.
×
AV
V
ER
ER
()Ω
−
+
Ω
1
1
()
P
×
AV
R
ERSET
R
I
MPD CW
V
where:
is the average MPD current.
I
AV
is the dc optical power specified on the laser data sheet.
P
CW
I
is the MPD current at that specified PCW.
MPD_CW
is the average power required.
P
AV
ER is the desired extinction ratio (ER = P1/P0).
Note that I
ERSET
and I
will change from device to device;
PSET
however, the control loops will determine the actual values.
It is not required to know the exact values for LI or MPD
optical coupling.
Loop Bandwidth Selection
For continuous operation, the user should hardwire the LBWSET
pin high and use 1 µF capacitors to set the actual loop bandwidth. These capacitors are placed between the PAVCAP and
ERCAP pins and ground. It is important that these capacitors are low leakage multilayer ceramics with an insulation
resistance greater than 100 GΩ or a time constant of 1,000 sec,
whichever is less.
Operation Recommended Recommended
Mode LBWSET PAVCAP ERCAP
Continuous High 1 µF1 µF
50 Mbps to
1.25 Gbps
Optimized Low 47 nF 47 nF
for 1.25 Gbps
Setting LBSET low and using 47 nF capacitors results in a
shorter loop time constant (a 10× reduction over using 1 µF
capacitors and keeping LBWSET high).
Alarms
The ADN2848 is designed to allow interface compliance to
ITU-T-G958 (11/94) section 10.3.1.1.2 (transmitter fail) and
section 10.3.1.1.3 (transmitter degrade). The ADN2848 has two
active high alarms, DEGRADE and FAIL. A resistor between
ground and the ASET pin is used to set the current at which these
alarms are raised. The current through the ASET resistor is a ratio
of 100:1 to the FAIL alarm threshold. The DEGRADE alarm will
be raised at 90% of this level.
Example:
ImAsoI mA
==
50 45
FAIL DEGRADE
I
== =
ASET
R
ASET
*The smallest valid value for R
maximum of 100 A.
ImA
100
== =
50
FAIL
100
V
12 12
..
IA
ASET
ASET
500
is 1.2 kΩ, since this corresponds to the I
500
24
.
A
k
*
BIAS
The laser degrade alarm, DEGRADE, is provided to give a
warning of imminent laser failure if the laser diode degrades
further or environmental conditions continue to stress the LD,
such as increasing temperature.
The laser fail alarm, FAIL, is activated when the transmitter can
no longer be guaranteed to be SONET/SDH compliant. This
occurs when one of the following conditions arise:
•
The ASET threshold is reached.
•
The ALS pin is set high. This shuts off the modulation and
bias currents to the LD, resulting in the MPD current dropping to zero. This gives closed-loop feedback to the system
that ALS has been enabled.
DEGRADE will be raised only when the bias current exceeds
90% of ASET current.
REV. 0
–5–
ADN2848
Monitor Currents
IBMON, IMMON, and IMPDMON are current controlled
current sources from V
. They mirror the bias, modulation,
CC
and MPD current for increased monitoring functionality. An
external resistor to GND gives a voltage proportional to the
current monitored.
If the monitoring function IMPDMON is not required, the
IMPD pin must be grounded and the monitor photodiode
output must be connected directly to the PSET pin.
Data and Clock Inputs
Data and clock inputs are ac-coupled (10 nF capacitors recommended) and terminated via a 100 Ω internal resistor between
DATAP and DATAN and also between the CLKP and CLKN
pins. There is a high impedance circuit to set the commonmode voltage, which is designed to allow for maximum input
voltage headroom over temperature. It is necessary that ac
coupling be used to eliminate the need for matching between
common-mode voltages.
ADN2848
DATAP
DATAN
(TO FLIP-FLOPS)
50 50
V
REG
R
R = 2.5k, DATA
R = 3k, CLK
400A TYP
Figure 3. AC Coupling of Data Inputs
For input signals that exceed 500 mV p-p single-ended, it is
necessary to insert an attenuation circuit as shown in Figure 4.
R1
R2
NOTE THAT RIN = 100 = THE DIFFERENTIAL
INPUT IMPEDANCE OF THE ADN2848
DATAP /CLKP
R3
DATAN /CLKN
ADN2848
R
IN
Figure 4. Attenuation Circuit
CCBIAS
When the laser is used in ac-coupled mode, the CCBIAS and
the I
coupled mode, CCBIAS should be tied to V
pins should be tied together (see Figure 7). In dc-
BIAS
CC
.
Automatic Laser Shutdown
The ADN2848 ALS allows compliance to ITU-T-G958 (11/94),
section 9.7. When ALS is logic high, both bias and modulation
currents are turned off. Correct operation of ALS can be confirmed by the FAIL alarm being raised when ALS is asserted.
Note that this is the only time that DEGRADE will be low
while FAIL is high.
Alarm Interfaces
The FAIL and DEGRADE outputs have an internal 30 kΩ pull-
up resistor that is used to pull the digital high value to V
CC
.
However, the alarm output may be overdriven with an external
resistor allowing alarm interfacing to non-V
levels. Non-V
CC
CC
alarm output levels must be below the VCC used for the
ADN2848.
Power Consumption
The ADN2848 die temperature must be kept below 125oC. The
LFCSP package has an exposed paddle. The exposed paddle
should be connected in such a manner that it is at the same
potential as the ADN2848 ground pins. The θ
for the package
JA
is shown under the Absolute Maximum Ratings. Power consumption can be calculated using
I
= I
CC
P = V
V
MODN_PIN
T
= T
DIE
Thus, the maximum combination of I
CCMIN
CC
AMBIENT
+ 0.3 I
ICC + (I
)/2
MOD
BIAS
+ θJA P
V
BIAS_PIN
) + I
MOD (VMODP_PIN
+ I
BIAS
+
must be calcu-
MOD
lated. Where:
I
=
CCMIN
with I
T
DIE
T
AMBIENT
V
BIAS_PIN
V
MODP_PIN
V
MODN_PIN
50 mA, the typical value of ICC provided on Page 2
= I
MOD
= 0
BIAS
= die temperature
= ambient temperature
= voltage at I
BIAS
pin
= average voltage at IMODP pin
= average voltage at IMODN pin
Laser Disode Interfacing
Many laser diodes designed for 1.25 Gbps operation are packaged with an internal resistor to bring the effective impedance
up to 25 Ω in order to minimize transmission line effects. In
high current applications, the voltage drop across this resistor,
combined with the laser diode forward voltage, makes direct
connection between the laser and the driver impractical in a 3 V
system. AC coupling the driver to the laser diode removes this
headroom constraint.
REV. 0–6–
Caution must be used when choosing component values for ac
ADN2848
ADN2850
PSET
ERSET
DATAP
DATAN
IMODP
I
BIAS
DAC1
DAC2
SDI
SDO
CLK
CS
TX
RX
CLK
CS
V
CC
DATAP
DATAN
V
CC
V
CC
IMPD
IDTONE
IDTONE
coupling to ensure that the time constant (L/R and RC, see
Figure 7) are sufficiently long for the data rate and expected
number of CIDs (consecutive identical digits). Failure to do this
could lead to pattern dependent jitter and vertical eye closure.
For designs with low series resistance, or where external
components become impractical, the ADN2848 supports direct
connection to the laser diode (see Figure 6). In this case, care
must be taken to ensure that the voltage drop across the laser
diode does not violate the minimum compliance voltage on the
IMODP pin.
Optical Supervisor
The PSET and ERSET potentiometers may be replaced with a
dual-digital potentiometer, the ADN2850 (see Figure 5). The
ADN2850 provides an accurate digital control for the average
optical power and extinction ratio and ensures excellent stability
over temperature.
ALS
ADN2848
Figure 5. Application Using the ADN2850 Dual 10-Bit
Digital Potentiometer with Extremely Low Temperature
Coefficient as an Optical Supervisor
FAIL
DEGRADE
V
CC
MPD LD
1.5 k
24 17
25
V
2
CC
V
CC
*
*
*
*
10H
LD = LASER DIODE
MPD = MONITOR PHOTODIODE
IMODN
GND2
IMODP
GND2
GND2
I
BIAS
CCBIAS
V
32
CC
18
1.5k
IBMON
IMMON
LBWSET
ASET
1k
3
CC
V
GND3
ADN2848
ERSET
PSET
**
**
ALS
IMPD
FAIL
16
CLKSEL
DEGRADE
CLKN
CLKP
GND1
DATAP
DATAN
V
1
CC
PAV CAP
ERCAP
4
CC
IMPDMON
1.5k
V
GND4
10nF 10nF 10nF 10nF
1F
9
V
CC
10nF
10nF
10nF
10nF
1F
VCCs SHOULD HAVE BYPASS CAPACITORS AS CLOSE
AS POSSIBLE TO THE ACTUAL SUPPLY PINS ON THE
ADN2848 AND THE LASER DIODE USED.
CONSERVATIVE DECOUPLING WOULD INCLUDE 100pF
CAPACITORS IN PARALLEL WITH 10nF CAPACITORS.
CLKN
CLKP
DATAP
DATAN
10F
REV. 0
NOTES
* DESIGNATES COMPONENTS THAT NEED TO BE OPTIMIZED FOR THE TYPE OF LASER USED.
** FOR DIGITAL PROGRAMMING, THE ADN2850 OR THE ADN2860 OPTICAL SUPERVISOR CAN BE USED.
Figure 6. DC-Coupled 50 Mbps to 1.25 Gbps Test Circuit, Data Not Clocked
GND
–7–
ADN2848
MPD LD
FAIL
V
CC
*
*
*
V
CC
*
10H
*
*
*
*
*
1.5k
*
24 17
25
2
V
CC
IMODN
GND2
IMODP
GND2
GND2
I
BIAS
CCBIAS
32
18
1.5k
IBMON
IMMON
LBWSET
ASET
1k
3
CC
V
GND3
ADN2848
ERSET
PSET
** **
ALS
ALS
IMPD
FAIL
DEGRADE
IMPDMON
GND4
1.5k
CLKSEL
CLKN
CLKP
GND1
DATAP
DATAN
V
CC
PAV CAP
ERCAP
4
CC
V
16
10nF
10nF
10nF
1
10nF
1F
1F
9
VCCs SHOULD HAVE BYPASS CAPACITORS AS CLOSE
AS POSSIBLE TO THE ACTUAL SUPPLY PINS ON THE
ADN2848 AND THE LASER DIODE USED.
CONSERVATIVE DECOUPLING WOULD INCLUDE 100pF
CAPACITORS IN PARALLEL WITH 10nF CAPACITORS.
V
CC
DEGRADE
CLKN
CLKP
DATAP
DATAN
LD = LASER DIODE
MPD = MONITOR PHOTODIODE
NOTES
* DESIGNATES COMPONENTS THAT NEED TO BE OPTIMIZED FOR THE TYPE OF LASER USED.
** FOR DIGITAL PROGRAMMING, THE ADN2850 OR THE ADN2860 OPTICAL SUPERVISOR CAN BE USED.
Figure 7. AC-Coupled 50 Mbps to 1.25 Gbps Test Circuit, Data Not Clocked
Figure 8. A 1.244 Mbps Optical Eye. Temperature at 25C.
Average Power = 0 dBm, Extinction Ratio = 10 dB, PRBS
31 Pattern, 1 Gb Ethernet Mask. Eye Obtained Using a
DFB Laser.
10nF 10nF 10nF 10nF
GND
10F
Figure 9. A 1.244 Mbps Optical Eye. Temperature at 85C.
Average Power = 0 dBm, Extinction Ratio = 10 dBm, PRBS
31 Pattern, 1 Gb Ethernet Mask. Eye Obtained Using a
DFB Laser.
REV. 0–8–
OUTLINE DIMENSIONS
32-Lead Frame Chip Scale Package [LFCSP]
(CP-32)
Dimensions shown in millimeters
ADN2848
PIN 1
INDICATOR
1.00
0.90
0.80
12 MAX
SEATING
PLANE
5.00
BSC SQ
0.30
0.23
0.18
4.75
BSC SQ
0.25 REF
TOP
VIEW
0.70 MAX
0.65 NOM
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
0.05 MAX
0.02 NOM
COPLANARITY
0.60 MAX
0.50
BSC
0.50
0.40
0.30
0.08
0.60 MAX
25
24
17
16
BOTTOM
VIEW
3.50
REF
PIN 1
32
9
INDICATOR
1
2.25
1.70
SQ
0.75
8
REV. 0
–9–
–10–
–11–
C02746–0–1/03(0)
–12–
PRINTED IN U.S.A.
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