10.7 Gbps Active Back-Termination,
FEATURES
Up to 10.7 Gbps operation
Very low power: 670 mW (IBIAS = 40 mA, IMOD = 40 mA)
Typical 24 ps rise/fall times
Full back-termination of output transmission lines
Drives TOSAs with resistances ranging from 5 Ω to 50 Ω
PECL-/CML-compatible data inputs
Bias current range: 10 mA to 100 mA
Differential modulation current range: 10 mA to 80 mA
Automatic laser shutdown (ALS)
3.3 V operation
Compact 3 mm × 3 mm LFCSP package
Voltage input control for bias and modulation currents
XFP-compliant bias current monitor
Optical evaluation board available
APPLICATIONS
SONET OC-192 optical transceivers
SDH STM-64 optical transceivers
10 Gb Ethernet optical transceivers
XFP/X2/XENPAK/XPAK/MSA 300 optical modules
SR and VSR optical links
Differential Laser Diode Driver
ADN2525
GENERAL DESCRIPTION
The ADN2525 laser diode driver is designed for direct modulation of packaged laser diodes having a differential resistance
ranging from 5 Ω to 50 Ω. The active back-termination technique
provides excellent matching with the output transmission lines
while reducing the power dissipation in the output stage. The
back-termination in the ADN2525 absorbs signal reflections
from the TOSA end of the output transmission lines, enabling
excellent optical eye quality to be achieved even when the
TOSA end of the output transmission lines is significantly misterminated. The small package provides the optimum solution
for compact modules where laser diodes are packaged in low
pin-count optical subassemblies.
The modulation and bias currents are programmable via the
MSET and BSET control pins. By driving these pins with
control voltages, the user has the flexibility to implement
various average power and extinction ratio control schemes,
including closed-loop control and look-up tables. The automatic
laser shutdown feature allows the user to turn on/off the bias
and modulation currents by driving the ALS pin with the
proper logic levels.
The product is available in a space-saving 3 mm × 3 mm LFCSP
package specified from −40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
VCC ALS
VCC
50Ω 50Ω
GND
DATAP
DATAN
800Ω
200Ω
MSET GND BSET
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
VCC
Figure 1.
ADN2525
50ΩIMOD
VCC
800Ω
200Ω
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
200Ω 2Ω
www.analog.com
IMODP
IMODN
IBMON
IBIAS
02461-001
ADN2525
TABLE OF CONTENTS
Specifications..................................................................................... 3
Thermal Specifications ................................................................ 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ........................................................................ 9
Input Stage ..................................................................................... 9
Bias Current .................................................................................. 9
Automatic Laser Shutdown (ALS) ........................................... 10
Modulation Current ................................................................... 10
REVISION HISTORY
3/05—Revision 0: Initial Version
Load Mis-termination ............................................................... 12
Power Consumption .................................................................. 12
Applications Information .............................................................. 13
Typical Application Ci rc u it ....................................................... 13
Layout Guidelines....................................................................... 13
Design Example.......................................................................... 14
Headroom Calculations ........................................................ 14
BSET and MSET Pin Voltage Calculation .......................... 14
Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 15
Rev. 0 | Page 2 of 16
ADN2525
SPECIFICATIONS
VCC = VCC
Typical values are specified at 25°C, IMOD = 40 mA.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
BIAS CURRENT (IBIAS)
Bias Current Range 10 100 mA
Bias Current while ALS Asserted 100 µA ALS = high
Compliance Voltage1 0.6 VCC – 1.2 V IBIAS = 100 mA
0.6 VCC – 0.8 V IBIAS = 10 mA
MODULATION CURRENT (IMODP, IMODN)
Modulation Current Range 10 80 mA diff R
Modulation Current while ALS Asserted 0.5 mA diff ALS = high
Rise Time (20% to 80%)
Fall Time (20% to 80%)
Random Jitter
Deterministic Jitter3,
Differential |S22| −10 dB 5 GHz < F < 10 GHz, Z0 = 50 Ω differential
−14 dB F < 5 GHz, Z0 = 50 Ω differential
Compliance Voltage1 VCC − 1.1 VCC + 1.1 V
DATA INPUTS (DATAP, DATAN)
Input Data Rate 10.7 Gbps NRZ
Differential Input Swing 0.4 1.6 V p-p diff Differential ac-coupled
Differential |S11| −16.8 dB F < 10 GHz, Z0 = 100 Ω differential
Input Termination Resistance 85 100 115 Ω Differential
BIAS CONTROL INPUT (BSET)
BSET Voltage to IBIAS Gain 75 100 120 mA/V
BSET Input Resistance 800 1000 1200 Ω
MODULATION CONTROL INPUT (MSET)
MSET Voltage to IMOD Gain 70 88 110 mA/V See Figure 29
MSET Input Resistance 800 1000 1200 Ω
BIAS MONITOR (IBMON)
IBMON to IBIAS Ratio 10 µA/mA
Accuracy of IBIAS to IBMON Ratio −5.0 +5.0 %
−4.0 +4.0 %
−2.5 +2.5 %
−2 +2 %
AUTOMATIC LASER SHUTDOWN (ALS)
V
IH
V
IL
I
IL
I
IH
ALS Assert Time 10 µs Rising edge of ALS to fall of IBIAS and IMOD below
ALS Negate Time 10 µs Falling edge of ALS to rise of IBIAS and IMOD above
POWER SUPPLY
V
CC
I
CC5
I
SUPPLY6
1
Refers to the voltage between the pin for which the compliance voltage is specified and GND.
2
The pattern used is composed by a repetitive sequence of eight 1s followed by eight 0s at 10.7 Gbps.
3
Measured using the high speed characterization circuit shown in Figure 3.
4
The pattern used is K28.5 (00111110101100000101) at 10.7 Gbps rate.
5
Only includes current in the ADN2525 VCC pins.
6
Includes current in ADN2525 VCC pins and dc current in IMODP and IMODN pull-up inductors. See the section for total supply current calculation. Power Consumption
to VCC
MIN
2, 3
0.4 0.9 ps rms
, TA = −40°C to +85°C, 50 Ω differential load resistance, unless otherwise noted.
MAX
LOAD
2, 3
24 32.5 ps
2, 3
24 32.5 ps
4
7.2 12 ps p-p
10 mA ≤ IBIAS < 20 mA, R
20 mA ≤ IBIAS < 40 mA, R
40 mA ≤ IBIAS < 70 mA, R
70 mA ≤ IBIAS < 100 mA, R
2.4 V
0.8 V
−20 +20 µA
0 200 µA
10% of nominal; see Figure 2
90% of nominal; see Figure 2
3.07 3.3 3.53 V
39 45 mA V
157 176 mA V
BSET
BSET
= 5 Ω to 50 Ω differential
IBMON
IBMON
IBMON
IBMON
= V
= 0 V
MSET
= V
MSET
= 0 V. I
= ICC + IMODP + IMODN
SUPPLY
= 1 kΩ
= 1 kΩ
= 1 kΩ
= 1 kΩ
Rev. 0 | Page 3 of 16
ADN2525
VEEV
V
THERMAL SPECIFICATIONS
Table 2.
Parameter Min Typ Max Unit Conditions/Comments
θ
J-PAD
θ
J-TOP
IC Junction Temperature 125 °C
2.6 5.8 10.7 °C/W Thermal resistance from junction to bottom of exposed pad.
65 72.2 79.4 °C/W Thermal resistance from junction to top of package.
ALS
IBIAS
AND IMOD
90%
ALS
NEGATE TIME
t
= 50Ω
Z
0
J2
GND GND GND
J3
GND GND
10%
ALS
ASSERT TIME
Figure 2. ALS Timing Diagram
EE
TP1
VCC
DATAP
DATAN
VCC
VEE
1kΩ
TP2
ADN2525
J8 J5
VBSET
BSET IBMON IBIAS GND
GND
= 50Ω Z0 = 25Ω Z0 = 50Ω
Z
0
10nF
10nF
GND
MSET NC1 ALS GND
VMSET
GND
10Ω
IMODP
IMODN
VCC
VCC
VEE
EE
10nF
10nF
22µF
GND
GND
GND
Z
= 25Ω Z0 = 50ΩZ0 = 50ΩZ0 = 50Ω
0
GND
GND
t
02461-002
GND
BIAS TEE
35Ω
35Ω
GND
GND
BIAS TEE
GND
BIAS TEE: Picosecond Pulse Labs Model 5542-219
Adapter: Pasternack PE-9436 2.92mm female-to-female adapter
Attenuator: Pasternack PE-7046 2.92mm 20dB attenuator
70Ω
GNDGND
VEE
ADAPTER
ADAPTER
ATTENUATOR
ATTENUATOR
GND
50Ω
OSCILLOSCOPE
50Ω
GND
GND GND GND
02461-003
Figure 3. High Speed Characterization Circuit
Rev. 0 | Page 4 of 16
ADN2525
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Min Max Unit
Supply Voltage, VCC to GND −0.3 +4.2 V
IMODP, IMODN to GND VCC − 1 .5 4.75 V
DATAP, DATAN to GND VCC − 1.8 VCC − 0.4 V
All Other Pins −0.3 VCC + 0.3 V
Junction Temperature 150 °C
Storage Temperature −65 +150 °C
Soldering Temperature
(Less than 10 sec)
240 °C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 5 of 16
ADN2525
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VCC
DATAN
DATAP
VCC
161514
13
BSET
VCC
IMODP
12
11
10
9
IBMON
IBIAS
GND
02461-016
1
MSET
NC
ALS
GND
2
3
4
PIN 1
INDICATOR
ADN2525
TOP VIEW
5
678
VCC
IMODN
Figure 4. Pin Configuration
Note: The exposed pad on the bottom of the package must be connected to the VCC or GND plane.
Table 3. Pin Function Descriptions
Pin No. Mnemonic I/O Description
1 MSET Input Modulation Current Control Input
2 NC N/A No Connect—Leave Floating
3 ALS Input Automatic Laser Shutdown
4 GND Power Negative Power Supply
5 VCC Power Positive Power Supply
6 IMODN Output Modulation Current Negative Output
7 IMODP Output Modulation Current Positive Output
8 VCC Power Positive Power Supply
9 GND Power Negative Power Supply
10 IBIAS Output Bias Current Output
11 IBMON Output Bias Current Monitoring Output
12 BSET Input Bias Current Control Input
13 VCC Power Positive Power Supply
14 DATAP Input Data Signal Positive Input
15 DATAN Input Data Signal Negative Input
16 VCC Power Positive Power Supply
Exposed Pad Pad Power Connect to GND or VCC
Rev. 0 | Page 6 of 16
ADN2525
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VCC = 3.3 V, unless otherwise noted.
28.0
27.5
27.0
26.5
26.0
25.5
25.0
RISE TIME (ps)
24.5
24.0
23.5
23.0
27.5
27.0
26.5
26.0
25.5
25.0
FALL TIME (ps)
24.5
24.0
23.5
23.0
0.7
0.6
0.5
DIFFERENTIAL MODULATION CURRENT (mA)
Figure 5. Rise Time v s. IMOD
DIFFERENTIAL MODULATION CURRENT (mA)
Figure 6. Fall Time vs. IMOD
9
8
7
6
5
4
3
2
DETERMINISTIC JITTER (ps p-p)
1
1000 20406080
02461-004
0
DIFFERENTIAL MODULATION CURRENT (mA)
1000 20406080
02461-007
Figure 8. Deterministic Jitter vs. IMOD
350
300
250
200
150
100
TOTAL SUPPLY CURRENT (mA)
50
1000 20406080
02461-005
0
IBIAS = 100mA
IBIAS = 50mA
IBIAS = 10mA
DIFFERENTIAL MODULATION CURRENT (mA)
1000 20406080
02461-008
Figure 9. Total Supply Current vs. IMOD
0
–5
–10
DIFFERENTIAL |S11| (dB)
–15
–20
–25
–30
–35
–40
FREQUENCY (GHz)
Figure 10. Differential |S
1501234567891011121314
02461-009
|
11
0.4
0.3
0.2
RANDOM JITTER (ps RMS)
0.1
0
DIFFERENTIAL MODULATION CURRENT (mA)
1000 20406080
02461-006
Figure 7. Random Jitter vs. IMOD
Rev. 0 | Page 7 of 16
ADN2525
0
–5
–10
–15
–20
–25
–30
DIFFERENTIAL |S22| (dB)
–35
(ACQ LIMIT TEST) WAVEFORMS: 1000
–40
FREQUENCY (GHz)
Figure 11. Differential |S
16
14
12
10
8
6
% OCCURRENCE
4
2
0
RISE TIME (ps)
Figure 12. Worst-Case Rise Time Distribution
(VCC = 3.07 V, IBIAS = 100 mA, IMOD = 80 mA, T
16
1501234567891011121314
02461-010
|
22
Figure 14. Electrical Eye Diagram
(10.7 Gbps, PRBS31, IMOD = 80 mA)
02461-013
3023 24 25 26 27 28 29
02461-011
02461-014
Figure 15. Filtered SONET OC192 Optical Eye Diagram (for reference)
= 85°C)
A
(PRBS31 Pattern, Pav = −2 dBm, ER = 7 dB,
17% Mask Margin, NEC NX8341UJ TOSA)
14
12
10
8
6
% OCCURRENCE
4
2
0
FALL TIME (ps)
Figure 13. Worst-Case Fall Time Distribution
(VCC = 3.07 V, IBIAS = 100 mA, IMOD = 80 mA, T
= 85°C)
A
3023 24 25 26 27 28 29
02461-012
02461-015
Figure 16. Filtered 10G Ethernet Optical Eye
(PRBS31 Pattern, Pav = −2 dBm, ER = 5 dB,
41% Mask Margin, NEC NX8341UJ TOSA)
Rev. 0 | Page 8 of 16
ADN2525
THEORY OF OPERATION
As shown in Figure 1, the ADN2525 consists of an input stage
and two voltage controlled current sources for bias and modulation. The bias current is available at the IBIAS pin. It is controlled
by the voltage at the BSET pin, and can be monitored at the
IBMON pin. The differential modulation current is available at
the IMODP and IMODN pins. It is controlled by the voltage at
the MSET pin. The output stage implements the active backmatch circuitry for proper transmission line matching and
power consumption reduction. The ADN2525 can drive a load
having differential resistance ranging from 5 Ω to 50 Ω. The
excellent back-termination in the ADN2525 absorbs signal
reflections from the TOSA end of the output transmission lines,
enabling excellent optical eye quality to be achieved even when
the TOSA end of the output transmission lines is significantly
mis-terminated.
INPUT STAGE
The input stage of the ADN2525 converts the data signal applied
to the DATAP and DATAN pins to a level that ensures proper
operation of the high speed switch. The equivalent circuit of the
input stage is shown in Figure 17.
VCC
DATAP
VCC
DATAN
Figure 17. Equivalent Circuit of the Input Stage
The DATAP and DATAN pins are terminated internally with a
100 Ω differential termination resistor. This minimizes signal
reflections at the input, which could otherwise lead to degradation in the output eye diagram. It is not recommended to drive
the ADN2525 with single-ended data signal sources.
50Ω
50Ω
VCC
02461-017
The ADN2525 input stage must be ac-coupled to the signal
source to eliminate the need for matching between the commonmode voltages of the data signal source and the input stage of
the driver (see Figure 18). The ac-coupling capacitors should
have an impedance less than 50 Ω over the required frequency
range. Generally this is achieved using 10 nF to 100 nF capacitors.
50Ω 50Ω
DATA SIGNAL SOURCE
Figure 18. AC-Coupling the Data Source to the
ADN2525 Data Inputs
C
C
ADN2525
DATAP
DATAN
02461-018
BIAS CURRENT
The bias current is generated internally using a voltage-to-current
converter consisting of an internal operational amplifier and a
transistor as shown in Figure 19.
ADN2525
800Ω
200Ω
GND
Figure 19. Voltage-to-Current Converter Used to Generate IBIAS
The voltage-to-current conversion factor is set at 100 mA/V by
the internal resistors, and the bias current is monitored using a
current mirror with a gain equal to 1/100. By connecting a 1 kΩ
resistor between IBMON and GND, the bias current can be
monitored as a voltage across the resistor. A low temperature
coefficient precision resistor must be used for the IBMON
resistor (R
). Any error in the value of R
IBMON
ances, or drift in its value over temperature, contributes to the
overall error budget for the IBIAS monitor voltage. If the IBMON
voltage is being connected to an ADC for A/D conversion,
should be placed close to the ADC to minimize errors
R
IBMON
due to voltage drops on the ground plane.
VCC
RR
I
BMON
I
BIAS
200Ω
2Ω
IBMONBSET
IBIAS
due to toler-
IBMON
02461-019
Rev. 0 | Page 9 of 16
ADN2525
ALS
The equivalent circuits of the BSET, IBIAS, and IBMON pins
are shown in Figure 20, Figure 21, and Figure 22.
VCC
BSET
800Ω
200Ω
Figure 20. Equivalent Circuit of the BSET Pin
IBIAS
VCC
2Ω
Figure 21. Equivalent Circuit of the IBIAS Pin
VCC
100Ω
VCC
VCC
VCC
500Ω
2kΩ
02461-021
02461-020
two bias current levels (10 mA and 100 mA), but it can be
calculated for any bias current by using the following equation:
V
COMPLIANCE_MAX
(V) = VCC(V) − 0.75 − 4.4 × IBIAS(A)
See the Applications Information section for example headroom
calculations.
The function of the inductor L is to isolate the capacitance of
the IBIAS output from the high frequency signal path. For
recommended components, see Table 5.
AUTOMATIC LASER SHUTDOWN (ALS)
The ALS pin is a digital input that enables/disables both the bias
and modulation currents, depending on the logic state applied,
as shown in Table 4.
Table 4.
ALS Logic State IBIAS and IMOD
High Disabled
Low Enabled
Floating Enabled
The ALS pin is compatible with 3.3 V CMOS and TTL logic
levels. Its equivalent circuit is shown in Figure 24.
VCC
VCC
100Ω
VCC
IBMON
02461-022
Figure 22. Equivalent Circuit of the IBMON Pin
The recommended configuration for BSET, IBIAS, and IBMON
is shown in Figure 23.
TO LASER CATHODE
IBIAS
L
IBIAS
ADN2525
BSET
VBSET
GND
IBMON
R
1kΩ
IBMON
02461-023
Figure 23. Recommended Configuration for BSET, IBIAS, and IBMON Pins
The circuit used to drive the BSET voltage must be able to drive
the 1 kΩ input resistance of the BSET pin. For proper operation
of the bias current source, the voltage at the IBIAS pin must be
between the compliance voltage specifications for this pin over
supply, temperature, and bias current range. See the Specifications
table. The maximum compliance voltage is specified for only
100Ω
50kΩ
2kΩ
02461-024
Figure 24. Equivalent Circuit of the ALS Pin
MODULATION CURRENT
The modulation current can be controlled by applying a dc
voltage to the MSET pin. This voltage is converted into a dc
current by using a voltage-to-current converter using an
operational amplifier and a bipolar transistor as shown in
Figure 25.
VCC
IMODP
IMODN
FROM INPUT STAGE
MSET
800Ω
200Ω
GND
ADN2525
Figure 25. Generation of Modulation Current on the ADN2525
50ΩIMOD
02461-025
Rev. 0 | Page 10 of 16
ADN2525
V
V
This dc current is switched by the data signal applied to the
input stage (DATAP and DATAN pins) and gained up by the
output stage to generate the differential modulation current at
the IMODP and IMODN pins.
The output stage also generates the active back-termination,
which provides proper transmission line termination. Active
back-termination uses feedback around an active circuit to
synthesize a broadband termination resistance. This provides
excellent transmission line termination, while dissipating less
power than a traditional resistor passive back-termination. The
equivalent circuits for MSET, IMODP, and IMODN are shown
in Figure 26 and Figure 27.
CC
MSET
Figure 26. Equivalent Circuit of the MSET Pin
VCC VCC
25Ω
3.3Ω 3.3Ω
Figure 27. Equivalent Circuit of the IMODP and IMODN Pins
800Ω
200Ω
CC
02461-026
IMODPIMODN
25Ω
02461-027
The recommended configuration of the MSET, IMODP, and
IMODN pins is shown in Figure 28. See Table 5 for recommended components.
IBIAS
ADN2525
IMODP
VCC
LCL
Z0 = 25Ω Z0 = 25Ω
C
The ratio between the voltage applied to the MSET pin and the
differential modulation current available at the IMODP and
IMODN pins is a function of the load resistance value as shown
in Figure 29.
210
200
190
180
170
mA/V
160
150
140
130
120
110
100
MINIMUM
90
80
70
60
DIFFERENTIAL LOAD RESISTANCE
TYPICAL
MAXIMUM
550 5 10 15 20 25 30 35 40 45 50
02461-029
Figure 29. MSET Voltage to Modulation Current Ratio vs.
Differential Load Resistance
Using the resistance of the TOSA, the user can calculate the
voltage range that should be applied to the MSET pin to generate
the required modulation current range (see the example in the
Applications Information section).
The circuit used to drive the MSET voltage must be able to
drive the 1 kΩ resistance of the MSET pin. To be able to drive
80 mA modulation currents through the differential load, the
output stage of the ADN2525 (IMODP, IMODN pins) must be
ac-coupled to the load. The voltages at these pins have a dc
component equal to VCC, and an ac component with singleended peak-to-peak amplitude of IMOD × 25 Ω. This is the
case even if the load impedance is less than 50 Ω differential,
since the transmission line characteristic impedance sets the
peak-to-peak amplitude. For proper operation of the output stage,
the voltages at the IMODP and IMODN pins must be between
the compliance voltage specifications for this pin over supply,
temperature, and modulation current range as shown in
Figure 30. See the Applications Information section for
example headroom calculations.
VIMODP, IMODN
TOSA
= 25Ω Z0 = 25Ω
VMSET
Z
MSET
IMODN
GND
0
L
L
VCC
VCC
Figure 28. Recommended Configuration for the
02461-028
VCC + 1.1V
NORMAL OPERATION REGION
VCC
VCC – 1.1V
MSET, IMODP, and IMODN Pins
02461-030
Figure 30. Allowable Range for the Voltage at
IMODP and IMODN
Rev. 0 | Page 11 of 16
ADN2525
E
(
)
θ×+
θ×θ
×
LOAD MIS-TERMINATION
Due to its excellent S22 performance, the ADN2525 can drive
differential loads that range from 5 Ω to 50 Ω. In practice, many
TOSAs have differential resistance less than 50 Ω. In this case,
with 50 Ω differential transmission lines connecting the
ADN2525 to the load, the load end of the transmission lines are
mis-terminated. This mis-termination leads to signal reflections
back to the driver. The excellent back-termination in the
ADN2525 absorbs these reflections, preventing their reflection
back to the load. This enables excellent optical eye quality to be
achieved, even when the load end of the transmission lines is
significantly mis-terminated. The connection between the load
and the ADN2525 must be made with 50 Ω differential (25 Ω
single-ended) transmission lines so that the driver end of the
transmission lines is properly terminated.
POWER CONSUMPTION
The power dissipated by the ADN2525 is given by
V
⎛
VCCP
MSET
⎜
⎝
+×=
5.13
where:
VCC is the power supply voltage.
IBIAS is the bias current generated by the ADN2525.
is the voltage applied to the MSET pin.
V
MSET
I
is the sum of the current that flows into the VCC,
SUPPLY
IMODP, and IMODN pins of the ADN2525 when
IBIAS = IMOD = 0 expressed in amps (see Table 1).
is the average voltage on the IBIAS pin.
V
IBIAS
Considering V
to IBIAS, the dissipated power becomes
V
BSET
VCCP ×+
/IBIAS = 10 as the conversion factor from
BSET
V
⎛
MSET
⎜
⎝
+×=
To ensure long-term reliable operation, the junction temperature of the ADN2525 must not exceed 125°C, as specified in
Table 2. For improved heat dissipation, the module’s case can be
used as heat sink as shown in Figure 31. A compact optical
module is a complex thermal environment, and calculations of
device junction temperature using the package θ
ambient thermal resistance) do not yield accurate results.
I
SUPPLY
⎞
⎟
⎠
⎞
⎟
⎠
V
IBIASSUPPLY
BSET
105.13
×+
IBIASVI
V
IBIAS
(junction-to-
JA
THERMAL COMPOUND
DIE
PACKAG
PCB
COPPER PLANE
Figure 31. Typical Optical Module Structure
VIAS
MODULE CASE
T
TOP
T
J
T
PAD
THERMO-COUPLE
The following procedure can be used to estimate the IC
junction temperature:
= Temperature at top of package in °C.
T
TOP
= Temperature at package exposed paddle in °C.
T
PAD
= IC junction temperature in °C.
T
J
P = Power dissipation in W.
= Thermal resistance from IC junction to package top.
θ
J-TOP
θ
= Thermal resistance from IC junction to package exposed
J-PAD
pad.
T
TOP
J-TOP
PAD
T
TOP
02461-032
θ
P
Figure 32. Electrical Model for Thermal Calculations
T
TOP
and T
can be determined by measuring the temperature
PAD
θ
J-PAD
T
PAD
T
at points inside the module as shown in Figure 31. The thermocouples should be positioned to obtain an accurate measurement
of the package top and paddle temperatures. Using the model
shown in Figure 32, the junction temperature can be calculated
using the following formula:
PADJ
=
T
J
−
−
PADJ
−
θ×+
TOPTOPJ
θ+θ
TOPJ
−
TTP
−
PADPADJ
TOPJ
−
where θ
J-TOP
and θ
are given in Table 2 and P is the power
J-PAD
dissipated by the ADN2525.
02461-031
Rev. 0 | Page 12 of 16
ADN2525
N
APPLICATIONS INFORMATION
TYPICAL APPLICATION CIRCUIT
Figure 33 shows the typical application circuit for the ADN2525.
The dc voltages applied to the BSET and MSET pins control the
bias and modulation currents. The bias current can be monitored
as a voltage drop across the 1 kΩ resistor connected between
the IBMON pin and GND. The ALS pin allows the user to turn
on/off the bias and modulation currents, depending on the logic
level applied to the pin. The data signal source must be connected
to the DATAP and DATAN pins of the ADN2525 using 50 Ω
transmission lines. The modulation current outputs, IMODP
and IMODN, must be connected to the load (TOSA) using 50 Ω
differential (25 Ω single-ended) transmission lines. Table 5
shows recommended components for the ac-coupling interface
between the ADN2525 and TOSA. For up-to-date component
recommendations, contact your sales representative.
Table 5.
Component Value Description
R1, R2 36 Ω 0603 size resistor
R3, R4 200 Ω 0603 size resistor
C3, C4 100 nF
L2, L3, L6, L7 82 nH
L1, L4, L5, L8 10 µH
0603 size capacitor,
Phycomp 223878615649
0402 size inductor,
Murata LQW15AN82NJ0
0603 size inductor,
Murata LQM21FN100M70L
LAYOUT GUIDELINES
Due to the high frequencies at which the ADN2525 operates,
care should be taken when designing the PCB layout to obtain
optimum performance. Controlled impedance transmission
lines must be used for the high speed signal paths. The length
of the transmission lines must be kept to a minimum to reduce
losses and pattern-dependent jitter. The PCB layout must be
symmetrical, both on the DATAP, DATAN inputs, and on the
IMODP, IMODN outputs, to ensure a balance between the
differential signals. All VCC and GND pins must be connected
to solid copper planes by using low inductance connections.
When the connections are made through vias, multiple vias can
be connected in parallel to reduce the parasitic inductance.
Each GND pin must be locally decoupled with high quality
capacitors. If proper decoupling cannot be achieved using a
single capacitor, the user can use multiple capacitors in parallel
for each GND pin. A 20 µF tantalum capacitor must be used as
general decoupling capacitor for the entire module. For
guidelines on the surface-mount assembly of the ADN2525,
consult the Amkor Technology® application note “Application
Notes for Surface Mount Assembly of Amkor’s
MicroLeadFrame® (MLF) Packages.”
BSET
DATAP
DATA
MSET
+3.3V
VCC
VCC
L1
L2
GND
GND
L3
L4 R2
VCC
L8
R1
L7
C4
C3
L6
L5 R3
R4
VCC
GND
VCC VCC
Z0 = 50Ω Z0 = 25Ω Z0 = 25Ω
Z
= 50Ω
0
VCC
BSET IBMON IBIAS GND
VCC
DATAP
C1
DATAN
C2
VCC
MSET NC1 ALS GND
VCC
C7
20µF
GND
R5
1kΩ
TP1
ADN2525
ALS
C5
10nF
VCC
IMODP
IMODN
VCC
C6
10nF
GND
GND
VCC
Z0 = 25Ω Z0 = 25Ω
VCC
Figure 33. Typical ADN2525 Application Circuit
TOSA
02461-033
Rev. 0 | Page 13 of 16
ADN2525
DESIGN EXAMPLE
This design example covers
• Headroom calculations for IBIAS, IMODP, and IMODN pins.
• Calculation of the typical voltage required at the BSET and
MSET pins in order to produce the desired bias and
modulation currents.
This design example assumes that the resistance of the TOSA is
25 Ω, the forward voltage of the laser at low current is V
IBIAS = 40 mA, IMOD = 60 mA, and VCC = 3.3 V.
Headroom Calculations
To ensure proper device operation, the voltages on the IBIAS,
IMODP, and IMODN pins must meet the compliance voltage
specifications in Table 1.
Considering the typical application circuit shown in Figure 33,
the voltage at the IBIAS pin can be written as
= VCC − VF − (IBIAS × R
V
IBIAS
TOSA
) − V
LA
where:
VCC is the supply voltage.
V
is the forward voltage across the laser at low current.
F
is the resistance of the TOSA.
R
TOSA
V
is the dc voltage drop across L5, L6, L7, and L8.
LA
is the dc voltage drop across L1, L2, L3, and L4.
V
LB
= 1 V,
F
Assuming V
= 0 V and IMOD = 60 mA, the minimum voltage
LB
at the modulation output pins is equal to
VCC − (IMOD × 25)/2 = VCC − 0.75
VCC − 0.75 > VCC − 1.1 V, which satisfies the requirement.
The maximum voltage at the modulation output pins is equal to
VCC + (IMOD × 25)/2 = VCC + 0.75
VCC + 0.75 < VCC + 1.1 V, which satisfies the requirement.
Headroom calculations must be repeated for the minimum and
maximum values of the required IBIAS and IMOD ranges to
ensure proper device operation over all operating conditions.
BSET and MSET Pin Voltage Calculation
To set the desired bias and modulation currents, the BSET and
MSET pins of the ADN2525 must be driven with the appropriate
dc voltage. The voltage range required at the BSET pin to generate
the required IBIAS range can be calculated using the BSET
voltage to IBIAS gain specified in Table 1. Assuming that IBIAS
= 40 mA and the typical IBIAS/V
ratio of 100 mA/V, the
BSET
BSET voltage is given by
V
BSET
IBIAS
(mA)
mA/V100
40
100
V4.0
===
For proper operation, the minimum voltage at the IBIAS pin
should be greater than 0.6 V, as specified by the minimum
IBIAS compliance specification in Table 1.
Assuming that the voltage drop across the 25 Ω transmission
lines is negligible and that V
V
= 3.3 − 1 − (0.04 × 25) = 1.3 V
IBIAS
= 1.3 V > 0.6 V, which satisfies the requirement.
V
IBIAS
=0 V, VF = 1 V, IBIAS = 40 mA,
LA
The maximum voltage at the IBIAS pin must be less than the
maximum IBIAS compliance specification as described by the
following equation:
V
COMPLIANCE_MAX
= VCC − 0.75 − 4.4 × IBIAS(A)
For this example:
V
COMPLIANCE_MAX
V
= 1.3 V < 2.53 V, which satisfies the requirement.
IBIAS
= VCC – 0.75 − 4.4 × 0.04 = 2.53 V
To calculate the headroom at the modulation current pins
(IMODP, IMODN), the voltage has a dc component equal to
VCC due to the ac-coupled configuration and a swing equal to
IMOD × 25 Ω. For proper operation of the ADN2525, the
voltage at each modulation output pin should be within the
normal operation region shown in Figure 30.
The BSET voltage range can be calculated using the required
IBIAS range and the minimum and maximum BSET voltage to
IBIAS gain values specified in Table 1.
The voltage required at the MSET pin to produce the desired
modulation current can be calculated using
IMOD
V
MSET
=
K
where K is the MSET voltage to IMOD ratio.
The value of K depends on the actual resistance of the TOSA.
It can be read using the plot shown in Figure 29. For a TOSA
resistance of 25 Ω, the typical value of K = 120 mA/V. Assuming
that IMOD = 60 mA and using the preceding equation, the
MSET voltage is given by
MSET
IMOD
mA/V120
V
60
120
V5.0
===
(mA)
The MSET voltage range can be calculated using the required
IMOD range and the minimum and maximum K values. These
can be obtained from the minimum and maximum curves in
Figure 29.
Rev. 0 | Page 14 of 16
ADN2525
R
OUTLINE DIMENSIONS
0.50
0.40
PIN 1
INDICATO
1.00
0.85
0.80
SEATING
PLANE
12° MAX
3.00
BSC SQ
VIEW
0.30
0.23
0.18
TOP
*
2.75
BSC SQ
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION
0.45
0.50
BSC
1.50 REF
0.60 MAX
Figure 34. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body
(CP-16-3)
Dimensions shown in millimeters
13
12
(BOTTOM VIEW)
9
8
EXPOSED
PA D
0.30
16
1
4
5
PIN 1 INDICATOR
1.65
*
1.50 SQ
1.35
0.25 MIN
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
ADN2525ACPZ-WP
ADN2525ACPZ-R2
ADN2525ACPZ-REEL7
1
Z = Pb-free part.
1
−40°C to +85°C
16-Lead Lead Frame Chip Scale Package,
CP-16-3 F06
50-Piece Waffle Pack
1
−40°C to +85°C
16-Lead Lead Frame Chip Scale Package,
CP-16-3 F06
500-Piece Reel
1
−40°C to +85°C
16-Lead Lead Frame Chip Scale Package,
CP-16-3 F06
7” 1500-Piece Reel
Rev. 0 | Page 15 of 16
ADN2525
NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05077–0–3/05 (0)
Rev. 0 | Page 16 of 16
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