Datasheet ADMCF341BR, ADMCF341 Datasheet (Analog Devices)

DashDSP™ 28-Lead Flash Mixed-Signal DSP

a

FEATURES
20 MHz Fixed-Point DSP Core

Single-Cycle Instruction Execution (50 ns)
ADSP-21xx Family Code Compatibility
Independent Computational Units

ALU, Multiplier/Accumulator, Barrel Shifter
Multifunction Instructions
Single-Cycle Context Switch
Powerful Program Sequencer

Zero Overhead Looping

Conditional Instruction Execution
Two Independent Data Address Generators

Memory Configuration

512  16-Bit Data Memory RAM
512  24-Bit Program Memory RAM
4K  24-Bit Program Memory ROM
4K  24-Bit Program Flash Memory

Three Independent Flash Memory Sectors

3584  24-Bit, 256  24-Bit, 256  24-Bit

Low-Cost Pin-Compatible ROM Option
16-Bit Watchdog Timer
Programmable 16-Bit Internal Timer with Prescaler
Two Double Buffered Serial Ports with SPI Mode Support
Integrated Power-On Reset Function
Three-Phase 16-Bit PWM Generation Unit:

16-Bit Center-Based PWM Generator
Programmable PWM Pulsewidth
Edge Resolution to 50 ns
153 Hz Minimum Switching Frequency
Double/Single Duty Cycle Update Mode Control

with Enhanced Analog Front End

ADMCF341

Individual Enable and Disable for Each PWM Output
High-Frequency Chopping Mode for Transformer

Coupled Gate Drives

External PWMTRIP Pin

Integrated 6-Channel ADC Subsystem

Three Bipolar I
Sample-and-Hold Amplifier and Overcurrent Pro­tection (Usable as Three Dedicated Analog Inputs)

Muxed Auxiliary Analog Inputs

Internal Voltage Reference (2.5 V)
Acquisition Synchronized to PWM Switching
Frequency

9-Pin Digital I/O Port

Bit Configurable as Input or Output
Change of State Interrupt Support

Two 16-Bit Auxiliary PWM Timers

Synthesized Analog Output
Programmable Frequency
0% to 100% Duty Cycle
Two Programmable Operational Modes
Independent Mode/Offset Mode

Motor Types

Permanent Magnet Synchronous Motors (PMSM)
Brushless DC Motors (BDCM)
AC Induction Motors (ACIM)

APPLICATIONS
Refrigerator and Air Conditioner Compressor
Washing Machines
Industrial Variable Speed Drives
HVAC

Inputs with Programmable

SENSE

FUNCTIONAL BLOCK DIAGRAM

ADSP-21xx BASE

ARCHITECTURE

DATA

ADDRESS

GENERATORS

DAG 1 DAG 2

ARITHMETIC UNITS

DashDSP is a trademark of Analog Devices, Inc.

MACALU

PROGRAM

SEQUENCER

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

SHIFTER

POR TIMER

MEMORY BLOCK

PROGRAM

ROM

4K x 24

PROGRAM

RAM

512 x 24

REV.0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

MOTOR CONTROL PERIPHERALS

PROGRAM

FLASH
4K x 24

DATA

MEMORY

512 x 16

SERIAL PORT

SPORT 0

SPORT 1

7

MULTIPLEXED ON EXTERNAL PINS

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

ADC SUBSYSTEM

V

REF

2.5V

3

ANALOG

INPUTS 16-BIT

PIO

9

3

I

SENSE

AND TRIP

SHA

TIMERS

2 x 16-BIT

AUX

PWM

2

AMP

THREE-

PHASE

WATCH-

DOG

TIMER

6

PWM

(VDD = 5%, GND = 0 V. TA = –40C to +85C. CLKIN = 10 MHz, unless

ADMCF341–SPECIFICATIONS

otherwise noted.)

ANALOG-TO-DIGITAL CONVERTER

Parameter Min Typ Max Unit Conditions/Comments

Signal Input 0.3 3.5 V VAUX0, VAUX1, VAUX2
Resolution
Linearity Error
Zero Offset
Comparator Delay 600 ns
ADC High Level Input Current
ADC Low Level Input Current

NOTES

1

Resolution varies with PWM switching frequency (double update mode) 78.1 kHz = 8 bits, 4.9 kHz = 12 bits.

2

2.44KHz sample frequency, VAUX0, VAUX1, VAUX2.

3

Extrapolated point outside of operating range. 2.44KHz sample frequency.

Specifications subject to change without notice.

I

SENSE

Parameter Min Typ Max Unit Conditions/Comments

I

SENSE

I

SENSE

I

SENSE

I

SENSE

I

SENSE

I

SENSE

I

SENSE

I

SENSE

I

SENSE

I

SENSE

(SNR)
I

SENSE

I

SENSE

I

SENSE

TRIP Threshold Low –690 –430 mV
TRIP Threshold High +430 +690 mV
TRIP Minimum Pulsewidth

NOTES

1

Variation of gain with VDD and temperature.

2

VIN = –400 mV to +400 mV.

3

fIN = 1 kHz sine wave, VIN = –400 mV to +400 mV, fS = 4 kHz.

4

High or low trip threshold.

1

2

3

2

2

–32 0 +7 mV

–10 mAV

3 4 Bits

12 Bits

+10 mAV

= 3.5 V

IN

= 0.0 V

IN

AMPLIFIER–TRIP

Signal Operating Range –400 +400 mV
Signal Input Range –800 +800 mV
Gain –2.6 –2.51 –2.34 % VIN = –400 mV to +400 mV
Gain Channel Matching 5.5 % VIN = –400 mV to +400 mV
Gain Stability
Linearity
Internal Offset Voltage
Internal Offset Stability
Signal-to-Noise Ratio (SNRD)
Signal-to-Noise Ratio Less Distortion 54 dB

3

Total Harmonic Distortion
Input Current –130 +10 mAV
Input Resistance 11.5 kW

1

2

2

2

3

3

4

89 Bits

1.68 1.87 2.1 V

0.8 % VIN = –400 mV to +400 mV

2.1 %
51 dB

–40 dB
–53 dB

= –400 mV to +400 mV

IN

5 ms

CURRENT SOURCE

1

Parameter Min Typ Max Unit Conditions/Comments

Programming Resolution 3 Bits
Tuned Current

NOTES

1

For ADC calibration.

2

0.3 V to 3.5 V I

2

CONST

91 100 109 mA

voltage.

REV. 0–2–

ADMCF341

VOLTAGE REFERENCE

Parameter Min Typ Max Unit Conditions/Comments

Voltage Level (V

)2.442.50 2.55 V –40∞C to +85∞C

REF

Drift 110 ppm/∞C

Specifications subject to change without notice.

POWER-ON RESET

Parameter Min Typ Max Unit Conditions/Comments

Reset Threshold 3.20 3.65 4.10 V
Hysteresis 100 mV
Reset Active Timeout Period 3.2

*216 CLKOUT cycles.

Specifications subject to change without notice.

*

ms

ELECTRICAL CHARACTERISTICS

Symbol Parameter Min Typ Max Unit Conditions/Comments

V

IL

V

IH

V

OL

V

OL

V

OH

I

IL

I

IL

I

IH

I

IH

I

IH

I

OZH

I

OZL

I

DD

I

DD

NOTES

1

Output pins PIO0-PIO8, AH, AL, BH, BL, CH, CL.

2

XTAL pin.

3

Internal pull-up, RESET.

4

Internal pull-down, PWMTRIP, PIO0-PIO8.

5

Three stateable pins, DT1, RFS1, TFS1, SCLK1.

6

Outputs not switching.

Specifications subject to change without notice.

Low Level Input Voltage 0.8 V
High Level Input Voltage 2 V
Low Level Output Voltage
Low Level Output Voltage
High Level Output Voltage 4 V I
Low Level Input Current RESET Pin
Low Level Input Current –10 mAV
High Level Input Current RESET Pin
High Level Input Current
High Level Input Current 10 mAV
High Level Three-State Leakage Current
Low Level Three-State Leakage Current5–10 mAV
Supply Current (Idle)
Supply Current (Dynamic)

1

2

3

3

4

6

6

–100 mAV

5

0.4 V I

0.8 V I

30 mAV
100 mAV

100 mAV

55 mA V
135 mA V

2 mA

OL =

= 2 mA

OL

= 0.5 mA

OH

= 0 V

IN

= 0 V

IN

= V

IN

= V

IN

= V

IN

= V

IN

= 0 V

IN

= 5.25 V

DD

= 5.25 V

DD

DD

DD

DD

DD

REV. 0

–3–

ADMCF341

SPECIFICATIONS

(continued)

FLASH MEMORY

Parameter Min Typ Max Unit Conditions/Comments

Endurance 10,000 Cycles Cycle = Erase/Program/Verify
Data Retention 15 Years
Program and Erase Operating Temperature 0 85 ∞C
Read Operating Temperature –40 +85 ∞C

Specifications subject to change without notice.

TIMING PARAMETERS

Parameter Min Max Unit

Clock Signals

Signal tCK is defined as 0.5 t
a frequency equal to half the instruction rate; a 10 MHz input clock (which is
equivalent to 100 ns) yields a 50 ns processor cycle (equivalent to 20 MHz).
When t

values are within the range of 0.5 t

CK

substituted for all relevant timing parameters to obtain specification value as
in the following example:

ttns ns ns ns

=-=¥-=05 10 05 50 10 15..

CKH CK

Timing Requirements:

t

CKIN

t

CKIL

t

CKIH

CLKIN Period 100 150 ns
CLKIN Width Low 20 ns
CLKIN Width High 20 ns

Switching Characteristics:

t

CKL

t

CKH

t

CKOH

CLKOUT Width Low 0.5 tCK – 10 ns
CLKOUT Width High 0.5 tCK – 10 ns
CLKIN High to CLKOUT High 0 20 ns

Control Signals

Switching Characteristics

t

RSP

RESET Width Low 5 tCK* ns

PWM Shutdown Signals

Switching Characteristics

t

PWMTPW

*Applies after power-up sequence is complete.

Specifications subject to change without notice.

PWMTRIP Width Low t

. The ADMCF341 uses an input clock with

CKIN

period, they should be

CKIN

CK

ns

CLKIN

CLKOUT

t

CKIN

t

CKIL

t

CKL

Figure 1. Clock Signals

t

t

CKH

CKOH

t

CKIH

REV. 0–4–

ADMCF341

TIMING PARAMETERS

Parameter Min Max Unit

Serial Ports

Timing Requirements

t

SCK

t

SCS

t

SCH

t

SCP

Switching Characteristics

t

CC

t

SCDE

t

SCDV

t

RH

t

RD

t

SCDH

t

SCDD

t

TDE

t

TDV

t

RDV

Specifications subject to change without notice.

SCLK Period 100 ns
DR/TFS/RFS Setup before SCLK Low 15 ns
DR/TFS/RFS Hold after SCLK Low 20 ns
SCLKIN Width 40 ns

CLKOUT High to SCLK

OUT

0.25 t

CK

0.25 tCK + 20 ns
SCLK High to DT Enable 0 ns
SCLK High to DT Valid 30 ns
TFS/RFS
TFS/RFS

Hold after SCLK High 0 ns

OUT

Delay from SCLK High 30 ns

OUT

DT Hold after SCLK High 0 ns
SCLK High to DT Disable 30 ns
TFS (Alt) to DT Enable 0 ns
TFS (Alt) to DT Valid 25 ns
RFS (Multichannel, Frame Delay Zero) to DT Valid 30 ns

CLKOUT

SCLK

RFS
TFS

RFS

OUT

TFS

OUT

TFS

(ALTERNATE

FRAME MODE)

(MULTICHANNEL MODE,

FRAME DELAY 0 [MFD = 0])

RFS

DR

DT

t

CC

IN

IN

t

t

SCDE

t

RH

TDE

t

t

RD

SCDV

t

t

RDV

TDV

t

t

CC

SCS

t

SCK

t

t

SCDD

SCP

t

SCP

t

SCH

t

SCDH

Figure 2. Serial Port Timing

REV. 0

–5–

ADMCF341

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . –0.3 V to +7.0 V

Supply Voltage (AV

Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to V

Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to V

) . . . . . . . . . . . . . . . . . –0.3 V to +7.0 V

DD

+0.3 V

DD

+0.3 V

DD

Operating Temperature Range (Ambient) . . . –40∞C to +85∞C

Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C

Lead Temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . . . 280∞C

*Stresses greater than those listed may cause permanent damage to the device.

These are stress ratings only; functional operation of the device at these or any
other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

PIN CONFIGURATION

CLKIN

XTAL

I

SENSE

I

SENSE

I

SENSE

V

DD

1

2

3

4

5

6

7

8

9

10

11

12

3

13

2

14

1

ADMCF341

TOP VIEW

(Not to Scale)

PORTA6/DR1 PORTA7/(AUX1/PWMSYNC)

PORTA5/(FL1/DT1) PORTA8/(AUX0/CLKOUT)

PORTA4/(SCLK1/SCLK0) AL

PORTA3/TFS0

PORTA2/RFS0 BL

PORTA1/DT0 BH

PORTA0/DR0

PWMTRIP

28

27

26

25

24

23

22

21

20

19

18

17

16

15

AH

CL

CH

RESET

GND

I

CONST

VAUX2

VAUX1

VAUX0

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Pin Type

1 PORTA6/DR1 I/O
2 PORTA5/(FL1/DT1) I/O
3 PORTA4/(SCLK1/SCLK0) I/O
4 PORTA3/TFS0 I/O
5 PORTA2/RFS0 I/O
6 PORTA1/DT0 I/O
7 PORTA0/DR0 I/O
8 CLKIN I
9 XTAL O
10 V

DD

SUP
11 PWMTRIP I
12 I
13 I
14 I

3I

SENSE

2I

SENSE

1I

SENSE

15 VAUX0 I
16 VAUX1 I
17 VAUX2 I
18 I

CONST

O
19 GND GND
20 RESET I
21 CH O
22 CL O
23 BH O
24 BL O
25 AH O
26 AL O
27 PORTA8/(AUX0/CLKOUT) I/O
28 PORTA7/(AUX1/PWMSYNC) I/O

ORDERING GUIDE

Temperature Instruction Package Package

Model Range Rate Description Option

ADMCF341BR –40∞C to +85∞C 20 MHz 28-Lead Wide Body (SOIC) R-28
ADMCF341-EVALKIT N/A N/A Development Tool Kit

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADMCF341 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. 0–6–

ADMCF341

GENERAL DESCRIPTION

The ADMCF341 is a low-cost, single-chip DSP-based control­ler, suitable for permanent magnet synchronous motors, ac
induction motors, and brushless dc motors. The ADMCF341
integrates a 20 MHz, fixed-point DSP core with a complete set
of motor control and system peripherals that permits fast,
efficient development of motor controllers.

The DSP core of the ADMCF341 is completely code-compatible
with the ADSP-21xx DSP family and combines three computa­tional units, data address generators, and a program sequencer.
The computational units are an ALU, a multiplier/accumulator
(MAC), and a barrel shifter. There are special instructions for
bit manipulation, multiplication (⫻ squared), biased rounding,
and global interrupt masking. The system peripherals are the
power-on reset circuit (POR), the watchdog timer, and two
synchronous serial ports. The serial ports are configurable and
double buffered, with hardware support for UART, SCI, and
SPI port emulation. The ADMCF341 provides 512 ⫻ 24-bit
program memory RAM, 4K ⫻ 24-bit program memory ROM,
4K ⫻ 24-bit program FLASH memory, and 512 ⫻ 16-bit data
memory RAM. The user code can be stored and executed from
the flash memory. The program and data memory RAM can be
used for dynamic data storage or can be loaded through the
serial port from an external device as in other ADMCxxx family
parts. The program memory ROM contains a monitor function
as well as useful routines for erasing, programming, and verifying
the flash memory.

The motor control peripherals of the ADMCF341 provide a
12-bit analog data acquisition system with six analog input
channels with three dedicated I

inputs (combining internal

SENSE

amplification, sampling, and overcurrent PWM shutdown
features) and an internal voltage reference. In addition, a three­phase, 16-bit, center-based PWM generation unit can be used

to produce high accuracy PWM signals with minimal processor
overhead. The ADMCF341 also contains two 16-bit auxiliary
PWM timer outputs and nine lines of digital I/O.

Because the ADMCF341 has a limited number of pins, functions
such as the auxiliary PWM timers and the serial communication
ports are multiplexed with the nine programmable digital input/
output (PIO) pins. The pin functions can be independently
selected to allow maximum flexibility for different applications.

DSP CORE ARCHITECTURE OVERVIEW

Figure 3 is an overall block diagram of the DSP core of the
ADMCF341. The flexible architecture and comprehensive
instruction set allow the processor to perform multiple opera­tions in parallel. In one processor cycle (50 ns with a 10 MHz
CLKIN) the DSP core can:

∑

Generate the next program address

∑

Fetch the next instruction

∑

Perform one or two data moves

∑

Update one or two data address pointers

∑

Perform a computational operation

This all takes place while the processor continues to:

∑

Receive and transmit through the serial ports

∑

Decrement the interval timer

∑

Generate three-phase PWM waveforms for a power inverter

∑

Generate two signals using the 16-bit auxiliary PWM timers

∑

Acquire four analog signals

∑

Decrement the watchdog timer

DATA

ADDRESS

GENERATOR

#1

INPUT REGS

ALU

OUTPUT REGS

DATA

ADDRESS

GENERATOR

#2

INPUT REGS

OUTPUT REGS

MAC

INSTRUCTION

REGISTER

PM ROM
4K  24

PROGRAM

SEQUENCER

16

R BUS

14

14

24

BUS

EXCHANGE

16

INPUT REGS

SHIFTER

OUTPUT REGS

PM RAM

512  24

CONTROL

LOGIC

Figure 3. DSP Core Block Diagram

PMA BUS

DMA BUS

PMD BUS

DMD BUS

COMPANDING

CIRCUITRY

FLASH

PROGRAM

MEMORY

4K  24

TRANSMIT REG

RECEIVE REG

SERIAL

PORT

6

DM RAM
512  16

TIMER

REV. 0

–7–

ADMCF341

The processor contains three independent computational units:
the arithmetic and logic unit (ALU), the multiplier/accumulator
(MAC), and the shifter. The computational units process 16-bit
data directly and have provisions to support multiprecision
computations. The ALU performs a standard set of arithmetic
and logic operations as well as provides support for division
primitives. The MAC performs single-cycle multiply, multiply/add,
and multiply/subtract operations with 40 bits of accumulation.
The shifter performs logical and arithmetic shifts, normalization,
denormalization, and derive-exponent operations. The shifter
can be used to efficiently implement numeric format control,
including floating-point representations. The internal result (R)
bus directly connects the computational units so that the output
of any unit may be the input of any unit on the next cycle.

A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these compu­tational units. The sequencer supports conditional jumps and
subroutine calls and returns in a single cycle. With internal loop
counters and loop stacks, the ADMCF341 executes looped code
with zero overhead; no explicit jump instructions are required to
maintain the loop.

Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches from data memory and pro­gram memory. Each DAG maintains and updates four address
pointers (I registers). Whenever the pointer is used to access
data (indirect addressing), it is post-modified by the value in
one of four modifications (M registers). A length value may be
associated with each pointer (L registers) to implement auto­matic modulo addressing for circular buffers. The circular
buffering feature is also used by the serial ports for automatic
data transfers to and from on-chip memory. DAG1 generates
only data memory addresses and provides an optional bit-reversal
capability. DAG2 may generate either program or data memory
addresses but has no bit-reversal capability. Efficient data trans­fer is achieved with the use of five internal buses:

∑

Program memory address (PMA) bus

∑

Program memory data (PMD) bus

∑

Data memory address (DMA) bus

∑

Data memory data (DMD) bus

∑

Result (R) bus

Program memory can store both instructions and data, permit­ting the ADMCF341 to fetch two operands in a single cycle—
one from program memory and one from data memory. The
ADMCF341 can fetch an operand from on-chip program
memory and the next instruction in the same cycle. The
ADMCF341 writes data from its 16-bit registers to the 24-bit
program memory using the PX register to provide the lower 8
bits. When it reads data (not instructions) from 24-bit program
memory to a 16-bit data register, the lower 8 bits are placed in
the PX register.

The ADMCF341 can respond to a number of distinct DSP
core and peripheral interrupts. The DSP interrupts comprise a
serial port receive interrupt, a serial port transmit interrupt, a
timer interrupt, and two software interrupts. Additionally, the
motor control peripherals include two PWM interrupts and a
PIO interrupt.

Serial port 0 (SPORT0) provides a complete synchronous serial
interface with optional companding in hardware and a wide
variety of framed and unframed data transmit and receive

modes of operation. Serial port 1 (SPORT1) is available with a
limited number of I/Os. It is mainly intended for codebooting to
serial ROMs (SROM) and support of the debugging tools.
SPORT0 and SPORT1 can generate an internal programmable
serial clock or accept an external serial clock.

A programmable interval counter is also included in the DSP
core and can be used to generate periodic interrupts. A 16-bit
count register (TCOUNT) is decremented every n processor
cycles, where n – 1 is a scaling value stored in the 8-bit TSCALE
register. When the value of the counter reaches zero, an inter­rupt is generated, and the count register is reloaded from a
16-bit period register (TPERIOD).

The ADMCF341 instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Each instruction is executed in a single 50 ns
processor cycle (for a 10 MHz CLKIN). The ADMCF341
assembly language uses an algebraic syntax for ease of coding
and readability. A comprehensive set of development tools
supports program development. For further information on the
DSP core, refer to the ADSP-2100 Family User’s Manual, Third
Edition, with particular reference to the ADSP-2171.

SERIAL PORTS

The ADMCF341 incorporates two complete synchronous serial
ports (SPORT1 and SPORT0) for serial communication and
multiprocessor communication.

Following is a brief list of capabilities of the ADMCF341
SPORTs. Refer to the ADSP-2100 Family User’s Manual, Third
Edition, for further details.

∑

SPORTs are bidirectional and have a separate, double-buff­ered transmit and receive section.

∑

SPORTs use an external serial clock or generate their own
serial clock internally.

∑

SPORTs have independent framing for the receive and
transmit sections. Sections run in a frameless mode or with
frame synchronization signals internally or externally gener­ated. Frame synchronization signals are active high or
inverted, with either of two pulsewidths and timings.

∑

SPORTs support serial data word lengths from 3 bits to
16 bits and provides optional A-law and m-law companding
according to ITU (formerly CCITT) recommendation
G.711.

∑

SPORT receive and transmit sections can generate unique
interrupts on completing a data word transfer.

∑

SPORTs can receive and transmit an entire circular buffer
of data with only one overhead cycle per data word. An
interrupt is generated after a data buffer transfer.

∑

SPORT0 has a multichannel interface to selectively receive
and transmit a 24-word, or 32-word, timedivision multi­plexed, serial bitstream.

∑

SPORT0 can be configured as an SPI port (master mode
only). The clock phase and polarity are programmable
through the MODECTRL register.

∑

SPORT1 is the default port for program/data memory boot
loading and for development tools interface. The DT1/FL1
pin can be configured as SROM/E

2

PROM reset signal.

REV. 0–8–

ADMCF341

PIN FUNCTION DESCRIPTION

The ADMCF341 is available in a 28-lead SOIC package.
Table I describes the pins.

Table I. Pin List

Pin Group No. of Input/
Name Pins Output Function

RESET 1I Processor Reset Input
SPORT1

SPORT0

CLKOUT 1

1

1

2 I/O Serial Port 1 Pins (DT1/FL1,

DR1, SCLK1/SCLK0

5 I/O Serial Port 0 Pins (DT0, DR0

1

I/O Processor Clock Output

TFSO, SCLK1/SCLK0

2

)

2

)

CLKIN, XTAL 2 I, O External Clock or Quartz

Crystal Connection Point
PORTA0– 9 I/O Digital I/O Port Pins
PORTA8

1

AUX0–AUX112O Auxiliary PWM Outputs
AH–CL 6 O PWM Outputs
PWMTRIP 1I PWM Trip Signal

1– 3 I I

I

SENSE

3

I

SENSE

SENSE

Inputs

VAUX0–VAUX2 3 I Auxiliary Analog Inputs
I

CONST

1O ADC Constant Current

Source
V

DD

1I Power Supply

GND 1 I Ground

NOTES

1

Multiplexed pins, individually selectable through PORTA_SELECT
and PORTA_DATA registers.

2

SCLK1/SCLK0 multiplexed signals. Selectable through MODECTRL
Register Bit 4.

INTERRUPT OVERVIEW

The ADMCF341 can respond to 18 different interrupt sources
with minimal overhead, seven of which are internal DSP core
interrupts and 11 from the motor control peripherals. The
seven DSP core interrupts are SPORT1 receive (or IRQ0) and
transmit (or IRQ1), SPORT0 receive and transmit, the internal
timer, and two software interrupts. The motor control periph­eral interrupts are the nine programmable I/Os and two from
the PWM (PWMSYNC pulse and PWMTRIP). All motor
control interrupts are multiplexed into the DSP core through
the peripheral IRQ2 interrupt. The interrupts are internally
prioritized and individually maskable. A detailed description of the
entire interrupt system of the ADMCF341 is presented later,
following a more detailed description of each peripheral block.

MEMORY MAP

The ADMCF341 has two distinct memory types: program and
data. In general, program memory contains user code and coef­ficients, while the data memory is used to store variables and
data during program execution. Three kinds of program
memory are provided on the ADMCF341: RAM, ROM, and
FLASH. The motor control peripherals are memory mapped
into a region of the data memory space starting at 0x2000. The
complete program and data memory maps are given in Tables II
and III, respectively.

Table II. Program Memory Map

Memory

Address Range Type Function

0x0000–0x002F RAM Internal Vector Table
0x0030–0x01FF RAM User Program Memory
0x0200–0x07FF Reserved
0x0800–0x17FF ROM Reserved Program Memory
0x1800–0x1FFF Reserved
0x2000–0x20FF FLASH User Program Memory

Sector 0

0x2100–0x21FF FLASH User Program Memory

Sector 1

0x2200–0x2FFF FLASH User Program Memory

Sector 2

0x3000–0x3FFF Reserved

Table III. Data Memory Map

Memory

Address Range Type Function

0x0000–0x1FFF Reserved
0x2000–0x20FF Memory Mapped Registers
0x2100–0x37FF Reserved
0x3800–0x39FF RAM User Data Memory
0x3A00–0x3BFF RAM Reserved
0x3C00–0x3FFF Memory Mapped Registers

FLASH MEMORY SUBSYSTEM

The ADMCF341 has 4K ⫻ 24-bits of user-programmable,
nonvolatile flash memory. A flash programming utility is pro­vided with the development tools, which perform the basic
device programming operations: erase, program, and verify.

The flash memory array is portioned into three asymmetrically
sized sectors of 256 words, 256 words, and 3584 words, labeled
sector 0, sector 1, and sector 2, respectively. These sectors are
mapped into external program memory address space.

Four flash memory interface registers are connected to the DSP.
These 16-bit registers are mapped into the register area of data
memory space. They are named flash memory control register
(FMCR), flash memory address register (FMAR), flash memory
data register low (FMDRL), and flash memory data register
high (FMDRH). These registers are diagrammed later in this
data sheet. They are used by the flash memory programming
utility. The user program may read these registers, but should
not modify them directly. The flash programming utility pro­vides a complete interface to the flash memory.

It should be noted that the core accesses flash memory through
an external memory interface that multiplexes the program
memory and data memory buses into a single external bus.
Therefore, if more than one external transfer must be made in
the same instruction, there will be at least an overhead cycle
required.

REV. 0

–9–

ADMCF341

Special Flash Registers

The flash module has four nonvolatile 8-bit registers called
special flash registers (SFRs) that are accessible independent of
the main flash array, via the flash programming utility. These
registers are for general-purpose, nonvolatile storage. When
erased, the special flash registers contain all 0s. To read special
flash registers from the user program, call the read_reg routine
contained in ROM. Refer to the ADMCF34x DSP Motor Con-
troller Developers Reference Manual for an example.

Boot-from-Flash Code

A security feature is available in the form of a code that, when
set, causes the processor to execute the program in flash
memory at power-up or reset. In this mode, the flash program­ming utility and debugger are unable to communicate with the
ADMCF341. Consequently, the contents of the flash memory
can be neither programmed nor read.

The boot-from-flash code may be set via the flash programming
utility, when the user’s program is thoroughly tested and loaded
into flash program memory at address 0x2200. The user’s program
must contain a mechanism for clearing the boot-from-flash code
if reprogramming the flash memory is desired. The only way to
clear boot-from-flash is from within the user program, by calling
the flash_init or auto_erase_reg routines that are included in the
ROM. The user program must be signaled in some way to call
the necessary routine to clear the boot-from-flash code. An
example would be to detect a high level on a PIO pin during
startup initialization and then call the flash_init or auto_erase_reg
routine. The flash_init routine will erase the entire user program
in flash memory before clearing the boot-from-flash code, thus
ensuring the security of the user program. If security is not a
concern, the auto_erase_reg routine can be used to clear the
boot-from-flash code while leaving the user program intact.

Refer to the ADMCF34x DSP Motor Controller Developer’s Refer-
ence Manual for further instructions and an example of using the
boot-from-flash code.

FLASH PROGRAM BOOT SEQUENCE

On power-up or reset, the processor begins instruction execu­tion at address 0x0800 of internal program ROM. The ROM
monitor program that is located there checks the boot-from­flash code. If that code is set, the processor jumps to location
0x2200 in external flash program memory, where it expects to
find the user’s application program.

If the boot-from-flash code is not set, the monitor attempts to
boot from an external device as described in the ADMCF34x
DSP Motor Controller Developers Reference Manual.

SYSTEM INTERFACE

Figure 4 shows a basic system configuration for the ADMCF341
with an external crystal.

CLKOUT

ADMCF341

RESET

XTAL

CLKIN

22pF

10MHz

22pF

Figure 4. Basic System Configuration

Clock Signals

The ADMCF341 can be clocked either by a crystal or a TTL­compatible clock signal. For normal operation, the CLKIN
input cannot be halted, changed during operation, or operated
below the specified minimum frequency. If an external clock is
used, it should be a TTL-compatible signal running at half the
instruction rate. The signal is connected to the CLKIN pin of
the ADMCF341. In this mode, with an external clock signal,
the XTAL pin must be left unconnected. The ADMCF341 uses
an input clock with a frequency equal to half the instruction
rate; a 10 MHz input clock yields a 50 ns processor cycle (which
is equivalent to 20 MHz). Normally, instructions are executed
in a single processor cycle. All device timing is relative to the
internal instruction rate, which is indicated by the CLKOUT
signal when enabled.

Because the ADMCF341 includes an on-chip oscillator feed­back circuit, an external crystal may be used instead of a clock
source, as shown in Figure 4. The crystal should be connected
across the CLKIN and XTAL pins, with two capacitors as
shown in Figure 4. A parallel-resonant, fundamental frequency,
microprocessor grade crystal should be used. A clock output
signal (CLKOUT) is generated by the processor at the
processor’s cycle rate of twice the input frequency.

Reset

The ADMCF341 DSP core and peripherals must be correctly
reset when the device is powered up to assure proper unitiza­tion. The ADMCF341 contains an integrated power-on-reset
(POR) circuit that provides a complete system reset on power­up and power-down. The POR circuit monitors the voltage on
the ADMCF341 VDD pin and holds the DSP core and periph­erals in reset while VDD is less than the threshold voltage level,
VRST. When this voltage is exceeded, the ADMCF341 is held
in reset for an additional 216 DSP clock cycles (T
ure 5). During this time (T

), the supply voltage must reach

RST

RST

in Fig-

the recommended operating condition. On power-down, when
the voltage on the VDD pin falls below V

RST

–V

HYST

, the

ADMCF341 will be reset. Also, if the external RESET pin is
actively pulled low at any time after power-up, a complete hard­ware reset of the ADMCF341 is initiated.

V

RST

V

DD

V

V

RST

HYST

–

RESET

T

RST

Figure 5. Power-On Reset Operation

REV. 0–10–

ADMCF341

The ADMCF341 sets all internal stack pointers to the empty
stack condition, masks all interrupts, clears the MSTAT register,
and performs a full reset of all of the motor control peripherals.
Following a power-up, it is possible to initiate a DSP core and
motor control peripheral reset by pulling the RESET pin low.
The RESET signal must be the minimum pulsewidth specifica­tion, t

. Following the reset sequence, the DSP core starts

RSP

executing code from the internal PM ROM located at 0x0800.

DSP Control Registers

The DSP core has a system control register, SYSCNTL,
memory-mapped at DM (0x3FFF). SPORT1 must be configured
as a serial port by setting Bit 10. SPORT0 and SPORT1 are
enabled by setting Bit 11 and Bit 12.

The DSP core has a wait state control register, MEMWAIT,
memory-mapped at DM (0x3FFE). The default value of this
register is 0xFFFF. For proper operation of the ADMCF341,
this register must always contain the value 0x8000. This value
sets the minimum access time to the program memory.

The configurations of both the SYSCNTL and MEMWAIT regis­ters of the ADMCF341 are shown at the end of the data sheet.

THREE-PHASE PWM CONTROLLER
Overview

The PWM generator block of the ADMCF341 is a flexible,
programmable three-phase PWM waveform generator that can
be programmed to generate the required switching patterns to
drive a three-phase voltage source inverter for ac induction
motors (ACIM) or permanent magnet synchronous motors
(PMSM). In addition, the PWM block contains special func­tions that considerably simplify the generation of the required

PWM switching patterns for control of brushless dc motors
(BDCM), including electronically commutated motors (ECM).

The six PWM output signals consist of three high side drive
signals (AH, BH, and CH) and three low side drive signals
(AL, BL, and CL). The switching frequency, dead time, and
minimum pulsewidths of the generated PWM patterns are pro­grammable using, respectively, the PWMTM, PWMDT, and
PWMPD registers. In addition, three registers (PWMCHA,
PWMCHB, and PWMCHC) control the duty cycles of the
three pairs of PWM signals.

Each of the six PWM output signals can be enabled or disabled
by separate output enable bits of the PWMSEG register. In
addition, three control bits of the PWMSEG register permit
crossover of the two signals of a PWM pair for easy control of
ECM or BDCM. In crossover mode, the high side PWM signals
are diverted to the complementary low side output and the low
side signals are diverted to the corresponding high side outputs.

In many applications, there is a need to provide an isolation
barrier in the gate-drive circuits that turn on the power devices
of the inverter. In general, there are two common isolation
techniques: optical isolation using optocouplers, and trans­former isolation using pulse transformers. The PWM controller
of the ADMCF341 permits mixing of the output PWM signals
with a high-frequency chopping signal to permit an easy inter­face to such pulse transformers. The features of this gate-drive
chopping mode can be controlled by the PWMGATE register.
There is an 8-bit value within the PWMGATE register that
directly controls the chopping frequency. In addition, high­frequency chopping can be independently enabled for the high
side and the low side outputs using separate control bits in the
PWMGATE register.

PWM CONFIGURATION

REGISTERS

PWMTM (15...0)
PWMDT (9...0)
PWMPD (9...0)
PWMSYNCWT (7...0)
MODECTRL (6)

THREE-PHASE

PWM TIMING

CLK RESETSYNC

PWMSYNC

TO INTERRUPT
CONTROLLER

PWMTRIP

PWM DUTY CYCLE

REGISTERS

PWMCHA (15...0)
PWMCHB (15...0)
PWMCHC (15...0)

UNIT

PWMSEG (8...0)

OUTPUT

CONTROL

UNIT

SYNC

OR

PWMSWT (0)

PWM SHUTDOWN CONTROLLER

PWMGATE (9...0)

OVER-

CURRENT

Figure 6. Overview of the PWM Controller of the ADMCF341

GATE

DRIVE

UNIT

CLK

TRIP

CLKOUT

ANALOG BLOCK

AH
AL
BH

BL
CH
CL

PWMTRIP

I

SENSE

I

SENSE

I

SENSE

1

2

3

REV. 0

–11–

ADMCF341

The PWM generator is capable of operating in two distinct modes:
single update mode and double update mode. In single update
mode, the duty cycle values are programmable only once per
PWM period, so that the resultant PWM patterns are symmetrical
about the midpoint of the PWM period. In double update mode,
a second updating of the PWM duty cycle values is implemented
at the midpoint of the PWM period. In this mode, it is possible
to produce asymmetrical PWM patterns that produce lower
harmonic distortion in three-phase PWM inverters. This tech­nique also permits the closed-loop controller to change the
average voltage applied to the machine winding at a faster rate,
allowing wider closed-loop bandwidths to be achieved. The
operating mode of the PWM block (single or double update
mode) is selected by a control bit in MODECTRL register.

The PWM generator of the ADMCF341 also provides an inter­nal signal that synchronizes the PWM switching frequency to
the A/D operation. In single update mode, a PWMSYNC pulse
is produced at the start of each PWM period. In double update
mode, an additional PWMSYNC pulse is produced at the mid­point of each PWM period. The width of the PWMSYNC pulse
is programmable through the PWMSYNCWT register.

The PWM signals produced by the ADMCF341 can be shut off
in a number of different ways. First, there is a dedicated asyn­chronous PWM shutdown pin, PWMTRIP, which, when
brought LOW, instantaneously places all six PWM outputs in
the OFF state. In addition, PWM shutdown is initiated when
the voltage on any of the input pins (I

) exceeds the trip

SENSE

thresholds (high or low) or the input is unconnected (floating).
Because these two hardware shutdown mechanisms are asyn­chronous, and the associated PWM disable circuitry does not
use clocked logic, the PWM will shut down even if the DSP
clock is not running. The PWM system may also be shut down
from software by writing to the PWMSWT register.

Status information about the PWM system of the ADMCF341
is available to the user in the SYSSTAT register. In particular,
the state of PWMTRIP is available, as well as a status bit that
indicates whether the operation is in the first half or the second
half of the PWM period.

A functional block diagram of the PWM controller is shown in
Figure 6. The generation of the six output PWM signals on pins
AH to CL is controlled by four important blocks:

∑

The three-phase PWM timing unit, which is the core of the
PWM controller, generates three pairs of complemented
and dead-time-adjusted center-based PWM signals.

∑

The output control unit allows the redirection of the out­puts of the three-phase timing unit for each channel to
either the high side or the low side output. In addition, the
output control unit allows individual enabling/disabling of
each of the six PWM output signals.

∑

The GATE drive unit provides the high chopping frequency
and its subsequent mixing with the PWM signals.

∑

The PWM shutdown controller manages the three PWM
shutdown modes (via the PWMTRIP pin, the analog block,
or the PWMSWT register) and generates the correct
RESET signal for the timing unit.

The PWM controller is driven by a clock at the same frequency
as the DSP instruction rate, CLKOUT, and is capable of gener­ating two interrupts to the DSP core. One interrupt is generated
on the occurrence of a PWMSYNC pulse, and the other is
generated on the occurrence of any PWM shutdown action.

Three-Phase Timing Unit

The 16-bit three-phase timing unit is the core of the PWM
controller and produces three pairs of pulsewidth modulated
signals with high resolution and minimal processor overhead.
There are four main configuration registers (PWMTM,
PWMDT, PWMPD, and PWMSYNCWT) that determine the
fundamental characteristics of the PWM outputs. In addition,
the operating mode of the PWM (single or double update
mode) is selected by bit 6 of the MODECTRL register. These
registers, in conjunction with the three 16-bit duty cycle regis­ters (PWMCHA, PWMCHB and PWMCHC), control the
output of the three-phase timing unit.

PWM Switching Frequency: PWMTM Register

The PWM switching frequency is controlled by the PWM
period register, PWMTM. The fundamental timing unit of
the PWM controller is t

CK

= 1/f

CLKOUT

, where f

CLKOUT

is the
CLKOUT frequency (DSP instruction rate). Therefore, for a
20 MHz CLKOUT, the fundamental time increment is 50 ns.
The value written to the PWMTM register is effectively the
number of t

clock increments in half a PWM period. The

CK

required PWMTM value is a function of the desired PWM
switching frequency (f

PWMTM

) and is given by:

PWM

f

CLKOUT

=

¥=2

f

CLKIN

f

f

PWM

PWM

Therefore, the PWM switching period, TS, can be written as:

T PWMTM t

=¥ ¥2

SCK

For example, for a 20 MHz CLKOUT and a desired PWM
switching frequency of 10 kHz (T

= 100 ms), the correct value

S

to load into the PWMTM register is:

6

¥

PWMTM x E=

20 10

¥¥

21010

3

==

1000 0 3 8

The largest value that can be written to the 16-bit PWMTM
register is 0xFFFF = 65,535, which corresponds to a minimum
PWM switching frequency of:

6

¥

fHz

PWM,min

20 10

=

¥

265535

=

153

,

for a CLKOUT frequency of 20 MHz.

PWM Switching Dead Time: PWMDT Register

The second important PWM block parameter that must be
initialized is the switching dead time. This is a short delay time
introduced between turning off one PWM signal (e.g., AH) and
turning on its complementary signal (e.g., AL). This short time
delay is introduced to permit the power switch being turned off
to completely recover its blocking capability before the comple­mentary switch is turned on. This time delay prevents a
potentially destructive short-circuit condition from developing
across the dc link capacitor of a typical voltage source inverter.

REV. 0–12–

ADMCF341

Dead time is controlled by the PWMDT register. The dead time
is inserted into the three pairs of PWM output signals. The dead
time, TD, is related to the value in the PWMDT register by:

T PWMDT t

=¥¥=¥22

DCK

PWMDT

f

CLKOUT

Therefore, a PWMDT value of 0x00A (= 10), introduces a
1 ms delay between the turn-off of any PWM signal (for example,
AH) and the turn-on of its complementary signal (for example,
AL). The amount of the dead time can therefore be programmed
in increments of 2 t

(or 100 ns for a 20 MHz CLKOUT).

CK

The PWMDT register is a 10-bit register. For a CLKOUT
rate of 20 MHz its maximum value of 0x3FF
(= 1023) corresponds to a maximum programmed dead time of:

Tt

=¥¥

1023 2

DCKmax

=¥¥¥

1023 2 50 10

=m

102

s

-

9

sec

The dead time can be programmed to zero by writing 0 to the
PWMDT register.

PWM Operating Mode: MODECTRL and
SYSSTAT Registers

The PWM controller of the ADMCF341 can operate in two
distinct modes: single update mode and double update mode.
The operating mode of the PWM controller is determined by
the state of Bit 6 of the MODECTRL register. If this bit is
cleared, the PWM operates in the single update mode. Setting
Bit 6 places the PWM in the double update mode. By default,
following either a peripheral reset or power-on, Bit 6 of the
MODECTRL register is cleared. This means that the default
operating mode is single update mode.

In single update mode, a single PWMSYNC pulse is produced
in each PWM period. The rising edge of this signal marks the
start of a new PWM cycle and is used to latch new values from
the PWM configuration registers (PWMTM, PWMDT, PWMPD,
and PWMSYNCWT) and the PWM duty cycle registers
(PWMCHA, PWMCHB, and PWMCHC) into the three-phase
timing unit. The PWMSEG register is also latched into the
output control unit on the rising edge of the PWMSYNC pulse.
In effect, this means that the parameters of the PWM signals
can be updated only once per PWM period at the start of each
cycle. Thus, the generated PWM patterns are symmetrical
about the midpoint of the switching period.

In double update mode, there is an additional PWMSYNC
pulse produced at the midpoint of each PWM period. The
rising edge of this new PWMSYNC pulse is again used to latch
new values of the PWM configuration registers, duty cycle
registers, and the PWMSEG register. As a result, it is possible
to alter both the characteristics (switching frequency, dead time,
minimum pulsewidth, and PWMSYNC pulsewidth) and the
output duty cycles at the midpoint of each PWM cycle. Conse­quently, it is possible to produce PWM switching patterns that
are no longer symmetrical about the midpoint of the period
(asymmetrical PWM patterns).

In double update mode, operation in the first half or the second
half of the PWM cycle is indicated by bit 3 of the SYSSTAT
register. In double update mode, this bit is cleared during

operation in the first half of each PWM period (between the
rising edge of the original PWMSYNC pulse and the rising edge
of the new PWMSYNC pulse, which is introduced in double
update mode). Bit 3 of the SYSSTAT register is set during the
second half of each PWM period. If required, a user may deter­mine the status of this bit during a PWMSYNC interrupt
service routine.

The advantages of double update mode are that lower harmonic
voltages can be produced by the PWM process and wider
control bandwidths are possible. However, for a given PWM
switching frequency, the PWMSYNC pulses occur at twice the
rate in the double update mode. Because new duty cycle values
must be computed in each PWMSYNC interrupt service rou­tine, there is a larger computational burden on the DSP in
double update mode.

Width of the PWMSYNC Pulse: PWMSYNCWT Register

The PWM controller of the ADMCF341 produces an internal
PWM synchronization pulse at a rate equal to the PWM switching
frequency in single update mode and at twice the PWM fre­quency in double update mode. This PWMSYNC synchronizes
the operation of the PWM unit with the A/D converter system.
The width of this PWMSYNC pulse is programmable by the
PWMSYNCWT register. The width of the PWMSYNC pulse,
T

PWMSYNC

, is given by:

TtPWMSYNCWT

PWMSYNC CK

=¥ +()1

which means that the width of the pulse is programmable from

to 256 tCK (corresponding to 50 ns to 12.8 ms for a CLKOUT

t

CK

rate of 20 MHz). Following a reset, the PWMSYNCWT
register contains 0x27 (= 39) so that the default PWMSYNC
width is 2.0 ms.

PWM Duty Cycles: PWMCHA, PWMCHB, PWMCHC
Registers

The duty cycles of the six PWM output signals are controlled
by the three duty cycle registers, PWMCHA, PWMCHB, and
PWMCHC. The integer value in the register PWMCHA con­trols the duty cycle of the signals on AH and AL. PWMCHB
controls the duty cycle of the signals on BH and BL, and
PWMCHC controls the duty cycle of the signals on CH and
CL. The duty cycle registers are programmed in integer counts
of the fundamental time unit, t

, and define the desired on-time

CK

of the high side PWM signal produced by the three-phase timing
unit over half the PWM period. The switching signals produced
by the three-phase timing unit are also adjusted to incorporate
the programmed dead time value in the PWMDT register.

The PWM is center-based. This means that in single update
mode the resulting output waveforms are symmetrical and cen­tered in the PWMSYNC period. Figure 7 presents a typical
PWM timing diagram illustrating the PWM-related registers
(PWMCHA, PWMTM, PWMDT, and PWMSYNCWT) con­trol over the waveform timing in both half cycles of the PWM
period. The magnitude of each parameter in the timing diagram
is determined by multiplying the integer value in each register

(typically 50 ns). It may be seen in the timing diagram

by t

CK

how dead time is incorporated into the waveforms by moving
the switching edges away from the original values set in the
PWMCHA register.

REV. 0

–13–

ADMCF341

T

PWMCHA PWMCHA

PWMDT PWMDT T

AH

CK

=

+-

-¥

(

)

12

12

AH

2  PWMDT

AL

PWMSYNC

SYSSTAT (3)

Figure 7. Typical PWM Outputs of Three-Phase
Timing Unit in Single Update Mode

Each switching edge is moved by an equal amount (PWMDT ⫻

) to preserve the symmetrical output patterns. The

t

CK

PWMSYNC pulse, whose width is set by the PWMSYNCWT
register, is also shown. Bit 3 of the SYSSTAT register indicates
which half cycle is active. This can be useful in double update
mode, as will be discussed later.

The resultant on-times of the PWM signals shown in Figure 7
may be written as:

T PWMCHA PWMDT t

=¥ - ¥2( )

AH CK

T PWMTM PWMCHA PWMDT t

=¥ - - ¥2( )

AL CK

The corresponding duty cycles are:

d

AH

T

d

AL

==

AL

T

S

Obviously, negative values of TAH and TAL are not permitted
because the minimum permissible value is zero, corresponding
to a 0% duty cycle. In a similar fashion, the maximum value is

, corresponding to a 100% duty cycle.

T

S

The output signals from the timing unit for operation in double
update mode are shown in Figure 8. This illustrates a com­pletely general case where the switching frequency, dead time,
and duty cycle are all changed in the second half of the PWM
period. Of course, the same value for any or all of these quanti­ties could be used in both halves of the PWM cycle. However, it
can be seen that there is no guarantee that symmetrical PWM
signals will be produced by the timing unit in this double update
mode. Additionally, it is seen that the dead time is inserted into
the PWM signals in the same way as in single update mode.

PWMCHA PWMCHA

PWMSYNCWT + 1

PWMTM

T

==

PWMCHA PWMDT

AH

T

S

PWMTM PWMCHA PWMDT

PWMTM

--

PWMTM

-

PWMTM

2  PWMDT

1

PWMCHA

2

2  PWMDT

PWMSYNCWT2 + 1

PWMTM

2

2

AH

PWMSYNC

SYSSTAT (3)

AL

2  PWMDT

PWMSYNCWT1 + 1

PWMTM

PWMCHA

1

1

Figure 8. Typical PWM Outputs of Three-Phase
Timing Unit in Double Update Mode

In general, the on-times of the PWM signals in double update
mode are defined by:

T

=

AL

PWMTM PWMTM PWMCHA

(

PWMCHA PWMDT PWMDT t

T

d

AH

==

AH

T

S

PWMCHA PWMCHA

PWMTM PWMTM

T

d

AL

==

AL

T

S

PWMCHA PWMDT PWMCHA

PWMTM PWMTM

+- -

12 1

-- ¥

212

+

12

+

12

PWMTM PWMTM PWMCHA

PWMTM PWMTM

++

21 1

+

12

PWMDT PWMDT

-

PWMTM PWMTM

++

12 1

+

12

)

CK

+

12

+

12

-

because for the completely general case in double update mode,
the switching period is given by:

TPWMTM PWMTM t

=+¥()

SCK

12

Again, the values of TAH and TAL are constrained to lie between
zero and T

.

S

PWM signals similar to those illustrated in Figure 7 and Figure 8
can be produced on the BH, BL, CH, and CL outputs by
programming the PWMCHB and PWMCHC registers in a
manner identical to that described for PWMCHA.

The PWM controller does not produce any PWM outputs until
all of the PWMTM, PWMCHA, PWMCHB, and PWMCHC
registers have been written to at least once. After these registers
have been written, the counters in the three-phase timing unit
are enabled. Writing to these registers also starts the main PWM
timer. If, during initialization, the PWMTM register is written
before the PWMCHA, PWMCHB, and PWMCHC registers,
the first PWMSYNC pulse (and interrupt if enabled) will be
generated (1.5 ¥ t

¥ PWMTM) seconds after the initial write

CK

to the PWMTM register in single update mode. In double up­date mode, the first PWMSYNC pulse will be generated (t

CK

¥
PWMTM) seconds after the initial write to the PWMTM regis­ter in single update mode.

REV. 0–14–

ADMCF341

Effective PWM Resolution

In single update mode, the same values of PWMCHA,
PWMCHB, and PWMCHC are used to define the on-times in
both half cycles of the PWM period. As a result, the effective
resolution of the PWM generation process is 2 t

(or 100 ns

CK

for a 20 MHz CLKOUT), since incrementing one of the duty
cycle registers by one changes the resultant on-time of the asso­ciated PWM signals by t

in each half period (or 2 tCK for the

CK

full period).

In double update mode, improved resolution is possible since
different values of the duty cycle registers are used to define the
on-times in both the first and second halves of the PWM period.
As a result, it is possible to adjust the on-time over the whole
period in increments of tCK. This corresponds to an effective
PWM resolution of t

in double update mode (or 50 ns for a

CK

20 MHz CLKOUT).

Table IV. Achievable PWM Resolution in Single and Double
Update Modes

Resolution Single Update Mode Double Update Mode
(Bit) (kHz) PWM Frequency (kHz) PWM Frequency

8 39.1 78.4
9 19.5 39.1
10 9.8 19.5
11 4.9 9.8
12 2.4 4.9

Minimum Pulsewidth: PWMPD Register

In many power converter switching applications, it is desirable
to eliminate PWM switching pulses shorter than a certain width.
It takes a finite time to both turn on and turn off modern power
semiconductor devices. Therefore, if the width of any of the
PWM pulses is shorter than some minimum value, it may be
desirable to completely eliminate the PWM switching for that
particular cycle.

The allowable minimum on-time for any of the six PWM out­puts for half a PWM period that can be produced by the PWM
controller may be programmed using the PWMPD register. The
minimum on-time is programmed in increments of tCK so that
the minimum on-time produced for any half PWM period,

, is related to the value in the PWMPD register by:

T

MIN

TPWMPD t

=¥

MIN CK

A PWMPD value of 0x002 defines a permissible minimum
on-time of 100 ns for a 20 MHz CLKOUT.

In each half cycle of the PWM, the timing unit checks the on­time of each of the six PWM signals. If any of the times is found
to be less than the value specified by the PWMPD register, the
corresponding PWM signal is turned OFF for the entire half
period, and its complementary signal is turned completely ON.

Consider the example where PWMTM = 200, PWMCHA = 5,
PWMDT = 3, and PWMPD = 10 with a CLKOUT of 20 MHz,
while operating in single update mode. For this case, the
PWM switching frequency is 50 kHz and the dead time is
300 ns. The minimum permissible on-time of any PWM signal
over one-half of any period is 500 ns. Clearly, for this example,
the dead-time adjusted on-time of the AH signal for one-half a
PWM period is (5–3) ¥ 50 ns = 100 ns. Because this is less than
the minimum permissible value, output AH of the timing unit

will remain OFF (0% duty cycle). Additionally, the AL signal
will be turned ON for the entire half period (100% duty cycle).

Output Control Unit: PWMSEG Register

The operation of the output control unit is managed by the 9-bit
read/write PWMSEG register. This register sets two distinct
features of the output control unit that are directly useful in the
control of ECM or BDCM.

The PWMSEG register contains three crossover bits, one for
each pair of PWM outputs. Setting bit 8 of the PWMSEG regis­ter enables the crossover mode for the AH/AL pair of PWM
signals; setting bit 7 enables crossover on the BH/BL pair of
PWM signals; and setting bit 6 enables crossover on the CH/CL
pair of PWM signals. If crossover mode is enabled for any pair
of PWM signals, the high side PWM signal from the timing unit
(for example, AH) is diverted to the associated low side output
of the output control unit so that the signal will ultimately
appear at the AL pin. Of course, the corresponding low side
output of the timing unit is also diverted to the complementary
high side output of the output control unit so that the signal
appears at pin AH. Following a reset, the three crossover bits
are cleared so that the crossover mode is disabled on all three
pairs of PWM signals.

The PWMSEG register also contains six bits (bits 0 to 5) that
can be used to individually enable or disable each of the six
PWM outputs. If the associated bit of the PWMSEG register is
set, the corresponding PWM output is disabled regardless of the
value of the corresponding duty cycle register. This PWM out­put signal will remain in the OFF state as long as the
corresponding enable/disable bit of the PWMSEG register is
set. The PWM output enable function gates the crossover func­tion. After a reset, all six enable bits of the PWMSEG register
are cleared, thereby enabling all PWM outputs by default.

In a manner identical to the duty cycle registers, the PWMSEG
is latched on the rising edge of the PWMSYNC signal so that
changes to this register only become effective at the start of each
PWM cycle in single update mode. In double update mode, the
PWMSEG register can also be updated at the midpoint of the
PWM cycle.

In the control of an ECM, only two inverter legs are switched at
any time, and often the high side device in one leg must be
switched ON at the same time as the low side driver in a second
leg. Therefore, by programming identical duty cycles for two
PWM channels (for example, let PWMCHA = PWMCHB) and
setting bit 7 of the PWMSEG register to cross over the BH/BL
pair of PWM signals, it is possible to turn ON the high side
switch of phase A and the low side switch of phase B at the
same time. In the control of an ECM, one inverter leg (phase C
in this example) is disabled for a number of PWM cycles. This
disable may be implemented by disabling both the CH and CL
PWM outputs by setting bits 0 and 1 of the PWMSEG register.
This is illustrated in Figure 7, where it can be seen that both the
AH and BL signals are identical, because PWMCHA = PWM
CHB, and the crossover bit for phase B is set. In addition, the
other four signals (AL, BH, CH, and CL) have been disabled by
setting the appropriate enable/disable bits of the PWMSEG
register. For the situation illustrated in Figure 9, the appropriate
value for the PWMSEG register is 0x00A7. In ECM operation,
because each inverter leg is disabled for a certain period of time,
the PWMSEG register is changed based upon the position of
the rotor shaft (motor commutation).

REV. 0

–15–

ADMCF341

PWMCHA = PWMCHB

AH

2  PWMDT

AL

BH

BL

CH

CL

PWMTM

2  PWMDT

PWMTM

Figure 9. An Example of PWM Signals Suitable for
ECM Control. PWMCHA = PWMCHB, BH/BL are a
Crossover Pair. AL, BH, CH, and CL Outputs are
Disabled. Operation Is in Single Update Mode.

Gate Drive Unit: PWMGATE Register

The gate drive unit of the PWM controller adds features that
simplify the design of isolated gate drive circuits for PWM
inverters. If a transformer-coupled power device gate drive
amplifier is used, the active PWM signal must be chopped at a
high frequency. The PWMGATE register allows the programming
of this high-frequency chopping mode. The chopped active
PWM signals may be required for the high side drivers only, for
the low side drivers only, or for both the high side and low side
switches. Therefore, independent control of this mode for both
high side and low side switches is included with two separate
control bits in the PWMGATE register.

Typical PWM output signals with high-frequency chopping
enabled on both high side and low side signals are shown in
Figure 10. Chopping of the high side PWM outputs (AH, BH
and CH) is enabled by setting Bit 8 of the PWMGATE register.
Chopping of the low side PWM outputs (AL, BL, and CL) is
enabled by setting Bit 9 of the PWMGATE register. The high
chopping frequency is controlled by the 8-bit word (GDCLK)
written to Bits 0 to 7 of the PWMGATE register. The period
and the frequency of this high-frequency carrier are:

T GDCLK t

=¥

()

[]

CHOP CK

f

=

CHOP

GDCLK

41

¥+

()

[]

f

CLKOUT

+

¥41

The GDCLK value may range from 0 to 255, corresponding to
a programmable chopping frequency rate from 19.5 kHz to 5 MHz
for a 20 MHz CLKOUT rate. The gate drive features must
be programmed before operation of the PWM controller and
typically are not changed during normal operation of the PWM
controller. Following a reset, by default, all bits of the
PWMGATE register are cleared so that high-frequency chop­ping is disabled.

PWMCHA PWMCHA

AH



PWMDT

2

PWMTM

AL



2

PWMDT

PWMTM

[4



(GDCLK+1)]

Figure 10. Typical PWM Signals with High­Frequency Gate Chopping Enabled on Both
High Side and Low Side Switches. (GDCLK Is
the Integer Equivalent of the Value in Bits 0
to 7 of the PWMGATE Register.)

PWM Shutdown

In the event of external fault conditions, it is essential that the
PWM system be instantaneously shut down. Two methods of
sensing a fault condition are provided by the ADMCF341. For
the first method, a low level on the PWMTRIP pin initiates an
instantaneous, asynchronous (independent of DSP clock) shut­down of the PWM controller. This places all six PWM outputs
in the OFF state, disables the PWMSYNC pulse and associated
interrupt signal, and generates a PWMTRIP interrupt signal.
The PWMTRIP pin has an internal pull-down resistor so that
even if the pin becomes disconnected, the PWM outputs will be
disabled. The state of the PWMTRIP pin can be read from Bit 0
of the SYSSTAT register.

The second method for detecting a fault condition is through
the I
the voltage at any of the I
(high or low), or the I

pins of the analog block of the ADMCF341. When

SENSE

SENSE

pins exceeds the trip threshold

SENSE

pin is in high impedance (floating),

PWMTRIP will be internally pulled low. The negative edge of
the internal PWMTRIP will generate a shutdown in the same
manner as a negative edge on pin PWMTRIP.

It is possible through software to initiate a PWM shutdown by
writing to the 1-bit read/write PWMSWT register (0x2061).
Writing to this bit generates a PWM shutdown in a manner
identical to the PWMTRIP or I

pins. Following a PWM

SENSE

shutdown, it is possible to determine if the shutdown was gener­ated from hardware or software by reading the same PWMSWT
register. Reading this register also clears it.

Restarting the PWM after a fault condition is detected requires
clearing the fault and reinitializing the PWM. Clearing the fault
requires PWMTRIP to return to a HIGH state and I
return to a voltage in the I

trip level range. After the fault

SENSE

SENSE

to

has been cleared, the PWM can be restarted by writing to registers
PWMTM, PWMCHA, PWMCHB, and PWMCHC. After the
fault is cleared and the PWM registers are initialized, internal
timing of the three-phase timing unit will resume, and the new
duty cycle values will be latched on the next rising edge of
PWMSYNC.

PWM Registers

The configuration of the PWM registers is described at the end
of the data sheet. The parameters of the PWM block are tabu­lated in Table V.

REV. 0–16–

ADMCF341

Table V. Fundamental Characteristics of PWM Generation Unit of ADMCF341

Parameter Min Typ Max Unit

16-BIT PWM TIMER

Counter Resolution 16 Bits
Edge Resolution (Single Update Mode) 100 ns
Edge Resolution (Double Update Mode) 50 ns
Programmable Dead Time Range 0 102 ms
Programmable Dead Time Increments 100 ns
Programmable Pulse Deletion Range 0 51 ms
Programmable Pulse Deletion Increments 50 ns
PWM Frequency Range 153
PWMSYNC Pulsewidth (T

) 2.0 12.8 ms

CRST

Gate Drive Chop Frequency Range 0.02 5 MHz

NOTES

1

153 Hz is calculated based on 16-bit resolution.

2

78,431 Hz is calculated based on 8-bit resolution.

1

78,431

2

Hz

ADC Overview

The ADC of the ADMCF341 is based upon the single slope con­version technique. This approach offers an inherently monotonic
conversion process within the noise and stability of its compo­nents, and there will be no missing codes.

The single slope technique has been adopted on the
ADMCF341 for four channels that are simultaneously con­verted. Refer to Figure 11 for the functional schematic of the
ADC. The main inputs (I

SENSE

1 to I

3) are connected to

SENSE

the ADC converter through three front end blocks. Figure 15
shows the block diagram of a single front end block. Each front
end block has a bipolar current amplifier (gain = –2.5) designed
to acquire the voltage on a current-sensing resistor, whose volt­age can be either positive or negative with respect to the power
supply ground rail.

The fourth channel has been configured with a serially con­nected 4-to-1 multiplexer. Table VI shows the multiplexer input
selection codes. One of these auxiliary multiplexed channels is
used to acquire the internal voltage reference (V

) for calibra-

REF

tion purposes.

Table VI. ADC Auxiliary Channel Selection

MODECTRL (1) MODECTRL (0)

Select ADCMUX1 ADCMUX0

VAUX0 0 0
VAUX1 0 1
VAUX2 1 0
Calibration (V

)1 1

REF

I

_TRIM

CONST

REG <2:0>

FILTER

MODECTRL

REG <07>

CLK

V1L

V2L

V3L

12-BIT ADC TIMER BLOCK

VAUXL

ADC1
ADC2
ADC3

ADCAUX

I

SENSE

I

SENSE

I

SENSE

VAUX0
VAUX1

VAUX2

I

CONST

1

2

3

MODECTRL REG

<09..10..11>

VOLTAGE

CURRENT

VOLTAGE

CURRENT

VOLTAGE

CURRENT

VAUX0 (V)
VAUX1 (V)
VAUX2 (V)
VAUX3 (V)

V

REF

CHANNEL1

CHANNEL2

CHANNEL3

MULTIPLEXER

MODECTRL REG <0..1>

4-1

CAPACITOR RESET

PWMSYNC (CONVST)

I

CONST

COMP

COMP

COMP

COMP

Figure 11. ADC Overview

Single Slope ADC Operations

The ADC conversion process is done by comparing each ADC
input to a reference ramp voltage and timing the comparison of
the two signals. The actual conversion point is the time-point
intersection of the input voltage and the ramp voltage (VC), as
shown in Figure 12. This time is converted to counts by the 12­bit ADC timer block and is stored in the ADC registers. The
ramp voltage used to perform the conversion is generated by
driving a fixed current into an off-chip capacitor, where the
capacitor voltage is:

VICt

=¥()

C

REV. 0

–17–

ADMCF341

Following reset, VC = 0 at t = 0. This reset and the start of the
conversion process are initiated by the PWMSYNC pulse, as
shown in Figure 12. The width of the PWMSYNC pulse is
controlled by the PWMSYNCWT register and should be pro­grammed according to Figure 13 to ensure complete resetting.

In order to compensate for IC process manufacturing tolerances
(and to adjust for capacitor tolerances), the current source of
the ADMCF341 is software-programmable. Using software to
set the magnitude of the ICONST current generator is accom­plished by selecting one of eight steps over approximately 20%
current range.

V

PWMSYNC

COMPARATOR

OUTPUT

T

PWM

C

T

VIL

– T

CRST

V

CMAX

T

CRST

V1

Figure 12. Analog Input Block Operation

The ADC system consists of four comparators and a single
timer, which may be clocked at either the DSP rate or half the
DSP rate, depending on the setting of the ADCCNT bit (bit 7)
of the MODECTRL register. When this bit is cleared, the timer
counts at a slower rate of CLKIN. When this bit is set, it counts
at CLKOUT or twice the rate of CLKIN. ADC1, ADC2,
ADC3, and ADCAUX are the registers that capture the conver­sion times, which are the timer values when the associated
comparator trips.

200

150

100

DECIMAL COUNTS

50

0

0 2 4 6 8 10

CHARGING CAPACITOR – nF

Figure 13. PWMSYNCWT Program Value

ADC Resolution

The ADC is intrinsically linked to the PWM block through the
PWMSYNC pulse’s control of the ADC conversion process.
Because of this link, the effective resolution of the ADC is a
function of both the PWM switching frequency and the rate at
which the ADC counter timer is clocked. For a CLKOUT
period of t

and a PWM period of T

CK

, the maximum count

PWM

of the ADC is given by:

where T

Max Count T T t

Max Count T T t

PWM

=-

min

(,( )/)

4095 2

for MODECTRL Bit

=-

min

(,( )/)

for MODECTRL Bit

PWM CRST CK

4095

PWM CRST CK

=

70

=

71

is equal to the PWM period if operating in single
update mode or equal to half that period if operating in
double update mode. For an assumed CLKOUT frequency
of 20 MHz and PWMSYNC pulsewidth of 2.0 ms, the effec-
tive resolution of the ADC block is tabulated for various
PWM switching frequencies in Table VII.

Table VII. ADC Resolution Examples

PWM MODECTRL[7] = 0 MODECTRL[7] = 1
Frequency Max Effective Max Effective
(kHz) Count Resolution Count Resolution

2.4 4095 12 4095 12
4 2480 >11 4095 12
8 1230 >10 2460 >11
18 535 >9 1070 >10
25 380 >8 760 >9

Programmable Current Source

The ADMCF341 has an internal current source that is used to
charge an external capacitor, generating the voltage ramp used
for conversion. The magnitude of the output of the current
source circuit is subject to manufacturing variations and can
vary from one device to the next. Therefore, the ADMCF341
includes a programmable current source whose output can
always be tuned to within 5% of the target 100 mA. A 3-bit
register, I

_TRIM, allows the user to make this adjust-

CONST

ment. The output current is proportional to the value written to
the register: 0x0 produces the minimum output and 0x7 pro­duces the maximum output. The default value of I

CONST

_TRIM

after reset is 0x0.

Charging Capacitor Selection

The charging capacitor value is selected based on the sample
(PWM) frequency desired. A too-small capacitor value will re­duce the available resolution of the ADC by having the ramp
voltage rise rapidly and convert too quickly, not utilizing all pos­sible counts available in the PWM cycle. A too-large capacitor
may not convert in the available PWM cycle returning 0x000.

To select a charging capacitor use Figure 14. Select the sam­pling frequency desired, determine if the current source is to be
tuned to a nominal 100 mA or left in the default (0x0 code) trim
state, then determine the proper charge capacitor off the appro­priate curve.

REV. 0–18–

ADMCF341

100

– nF

10

NOM

C

DEFAULT I

1

1 10 100

CONST

TUNED I

CONST

Figure 14. Timing Capacitor Selection

Analog Front End

The main analog inputs of the ADMCF341 (I

SENSE

1 to I

SENSE

3)
are connected to the ADC converter through three front end
blocks. Figure 15 shows the block diagram of a single analog
front end.

1 2 3 4 5 6 7 8 9 10 11 12

CYCLE

N–1 N N+1 N+2 N+3

VOLTAGE (THIS IS NOT AVAILABLE EXTERNALLY ON THE ADMCF341)

TRIP
(TO PWMTRIP FILTER)

SHA

ADC CONVERSION

STATUS BIT

(ADC REGISTER)

/V)

SENSE

MUX

CURRENT

PWMSYNC

CLOCKOUT

TRIP REF HIGH

TRIP REF LOW

SHA TIMER

COUNTER

SHA TIMER

REGISTER

OVERCURRENT

COMPARATOR

–2.5

SHA

STATE

MACHINE

MODECTRL REGISTER
CHANNEL SELECTION (I

Figure 15. Analog Front End Block Diagram

N+4

N+5

VxL
(TO ADC)

PWMSYNC

VC

SHA TIMER

COUNTER

SHA STATUS

I

INPUT

SENSE

ADC REGISTER

T

T

SAMPLE

T

SAMPLE

X T H T H H T H

SS

DATA READY
SAMPLED ON

CYCLE N–2

INVALID

LSB = 1

DATA READY
SAMPLED ON

CYCLE N

T

SAMPLE

TRACK

INVALID

LSB = 1

SAMPLE

S

DATA READY
SAMPLED ON

CYCLE N+2

S

DATA READY

SAMPLED ON

CYCLE N+4

Figure 16. ADC Conversion Sequence of a Current Input

REV. 0

–19–

ADMCF341

Table VIII. Fundamental Characteristics of Auxiliary PWM Timers

Parameter Test Conditions Min Typ Max Unit

Resolution 16 Bits
PWM Frequency 10 MHz CLKIN 0.152 MHz

Each analog front end has two analog inputs: voltage and cur­rent. A 2-to-1 multiplexer selects which input will be converted;
the multiplexer selection is determined by the MODECTRL
register. Note that in the ADMCF341 only the current inputs

) are externally available.

(I

SENSE

The current input (I

) is amplified through a bipolar ampli-

SENSE

fier (gain –2.5). There is an output offset that matches the
amplifier output signal range to the input signal range of the
A/D converter. The amplifier has built-in overcurrent and open­circuit protection. The overcurrent protection shuts the PWM
Block when the voltage at any of the I

pins exceeds the trip

SENSE

threshold (high or low). The open-circuit detection shuts the
PWM block when any of the I

inputs is in high impedance

SENSE

(for example, the current sense resistor or transducer is discon­nected). The shutdown signals generated by the amplifiers are
then OR-ed and filtered in order to avoid a spurious trip caused
by the switching of the power devices. The amplifier is followed
by a sample-and-hold amplifier (SHA). The SHA time is user­programmable through the SHA timer register. The sampling
time is set as a delay from the rising edge of the PWMSYNC
signal and is calculated as:

T SHA CNT t

=+¥(_ )2

SAMPLE CK

The SHA timer counter has a minimum reload value of 0x0003,
which ensures a minimum settling time of the SHA output in
case the user is programming the SHA timer register to a value
smaller than 0x0003. This means that the sampling time is
programmable from 5 t

to 65,535 tCK (corresponding to 250 ns

CK

to 3.28 ms for a CLKOUT rate of 20 MHz). The sampling time
is limited, however, to the rising edge of the following PWMSYNC
cycle. Each channel has an independent amplifier, SHA, and
SHA timing unit/state machine. Figure 16 shows a conversion
sequence of a single channel.

At the beginning of the cycle N (rising edge of PWMSYNC
signal (1), the timer counter is loaded with the value contained
in the SHA_CNT register. After the timer counter has been
reloaded, it starts counting down at the CLKOUT rate. In this
phase the SHA state-machine forces the SHA in TRACK
(sample) status.

When the counter reaches the value of 0x0000 (after the time
T

from the rising edge of PWMSYNC), the SHA state-

SAMPLE

machine forces the SHA in HOLD status.

The conversion of the sampled value is then taking place in the
cycle N + 1 [from (4) to (5)] in Figure 16 and the result of the
conversion is available on the ADC register at the cycle N + 2
[rising edge of PWMSYNC (5)].

On cycle N + 2, the reload value of the timer counter exceeds
the period of the PWMSYNC signal. In this case the SHA state­machine forces the SHA in HOLD status at the rising edge of
PWMSYNC of the next cycle (7). The conversion then takes place
on cycle N + 3, and the conversion result is available on the ADC
register at the cycle N + 4 [rising edge of PWMSYNC (9)].

During the acquire phase (the PWMSYNC cycle during the
sampling of the input value) the conversion takes place. How­ever, the value on the ADC registers is not considered valid.
This condition is signaled by the ADC by setting the LSB of the
ADC register to high.

On cycle N + 4, at the rising edge of the PWMSYNC signal (9),
the timer counter is reloaded with a value smaller than the
PWMSYNC pulsewidth. In this case the SHA samples within
the PWMSYNC pulsewidth and the conversion takes place in
the same PWMSYNC cycle [from (10) to (11)].

AUXILIARY PWM TIMERS
Overview

The ADMCF341 provides two variable frequency, variable duty
cycle, 16-bit, auxiliary PWM outputs that, when enabled, are
available at the AUX1 and AUX0 pins. These auxiliary PWM
outputs can be used to provide switching signals to other
circuits in typical motor control systems, such as power factor
corrected front end converters or other switching power con­verters. Alternatively, by adding a suitable filter network, the
auxiliary PWM output signals can be used as simple single-bit
digital-to-analog converters as shown in Figure 17. The auxiliary
PWM system of the ADMCF341 can operate in two different
modes: independent mode and offset mode. The operating
mode of the auxiliary PWM system is controlled by Bit 8 of the
MODECTRL register. Setting Bit 8 of the MODECTRL regis­ter places the auxiliary PWM system in the independent mode.
In this mode, the two auxiliary PWM generators are completely
independent and separate switching frequencies and duty cycles
may be programmed for each auxiliary PWM output. In this
mode, the 16-bit AUXTM0 register sets the switching frequency
of the signal at the AUX0 output pin. Similarly, the 16-bit
AUXTM1 register sets the switching frequency of the signal at
the AUX1 pin. The fundamental time increment for the auxiliary
PWM outputs is twice the DSP instruction rate (or 2 t

CK

) and

the corresponding switching periods are given by:

T AUXTM t

T AUXTM t

201

=¥ +¥

AUX CK

AUX CK

()

0

211

=¥ + ¥

()

1

Since the values in both AUXTM0 and AUXTM1 can range
from 0 to 0xFFFF, the achievable switching frequency of the
auxiliary PWM signals may range from 152.59 Hz to 10 MHz
for a CLKOUT frequency of 20 MHz. The on-time of the two
auxiliary PWM signals is programmed by the two 16-bit
AUXCH0 and AUXCH1 registers, according to:

T AUX AUXCH t

,()

02 0

ON CK

T AUX AUXCH t

,()

ON CK

=¥ ¥

12 1

=¥ ¥

so that output duty cycles from 0% to 100% are possible. Duty
cycles of 100% are produced if the on-time value exceeds the
period value. Typical auxiliary PWM waveforms in independent
mode are shown in Figure 18a. When bit 8 of the MODECTRL
register is cleared, the auxiliary PWM channels are placed

REV. 0–20–

in offset mode. In offset mode, the switching frequency of the
two signals on the AUX0 and AUX1 pins are identical and
controlled by AUXTM0 in a manner similar to that previously
described for independent mode. In addition, the on-times of
both the AUX0 and AUX1 signals are controlled by the AUXCH0
and AUXCH1 registers as before.

In this mode, however, the AUXTM1 register defines the offset
time from the rising edge of the signal on the AUX0 pin to that
on the AUX1 pin according to:

T AUXTM t

=¥ +¥21()1

OFFSET CK

For correct operation in this mode, the value written to the
AUXTM1 register must be less than the value written to the
AUXTM0 register. Typical auxiliary PWM waveforms in offset
mode are shown in Figure 18b. Again, duty cycles from 0% to
100% are possible in this mode.

In both operating modes, the resolution of the auxiliary PWM
system is 16 bits only at the minimum switching frequency
(AUXTM0 = AUXTM1 = 65,535 in independent mode,
AUXTM0 = 65,535 in offset mode). Obviously, as the switch­ing frequency is increased, the resolution is reduced.

Values can be written to the auxiliary PWM registers at any
time. However, new duty cycle values written to the AUXCH0
and AUXCH1 registers only become effective at the start of the
next cycle. Writing to the AUXTM0 or AUXTM1 registers
causes the internal timers to be reset to 0 and new PWM cycles
to begin. By default following a reset, bit 8 of the MODECTRL
register is cleared, thus enabling offset mode. In addition, the
registers AUXTM0 and AUXTM1 default to 0xFFFF, corre­sponding to the minimum switching frequency and zero offset.
The on-time registers AUXCH0 and AUXCH1 default to
0x0000.

AUXPWM

R1 R2

C1 C2

ADMCF341

2  AUXCH0

AUX0

AUX1

2  (AUXTM1 + 1)

Figure 18b. Typical Auxiliary PWM Signals
(All Times in Increments of t

WATCHDOG TIMER

The ADMCF341 incorporates a watchdog timer that can
perform a full reset of the DSP and motor control peripherals
in the event of software error. The watchdog timer is enabled by
writing a timeout value to the 16-bit WDTIMER register. The
timeout value represents the number of CLKIN cycles required
for the watchdog timer to count down to zero. When the watchdog
timer reaches zero, a full DSP core and motor control peripheral
reset is performed. In addition, bit 1 of the SYSSTAT register is
set so that after a watchdog reset, the ADMCF341 can determine
that the reset was due to the timeout of the watchdog timer and
was not an external reset. Following a watchdog reset, bit 1 of
the SYSSTAT register may be cleared by writing zero to the
WDTIMER register. This clears the status bit but does not
enable the watchdog timer.

On reset, the watchdog timer is disabled and is only enabled
when the first timeout value is written to the WDTIMER
register. To prevent the watchdog timer from timing out, the
user must write to the WDTIMER register at regular intervals
(shorter than the programmed WDTIMER period value). On
all but the first write to WDTIMER, the particular value written
to the register is unimportant, since writing to WDTIMER
simply reloads the first value written to this register.

2  (AUXTM0 + 1)

2  (AUXTM0 + 1)

2  AUXCH1

), Offset Mode

CK

R1 = R2 = 13k
C1 = C2 = 10nF

Figure 17. Auxiliary PWM Output Filter

Auxiliary PWM Interface, Registers, and Pins

The registers of the auxiliary PWM system are summarized at
the end of the data sheet.

2  AUXCH0

AUX0

2  AUXCH1

AUX1

2  (AUXTM0 + 1)

2  (AUXTM1 + 1)

2  AUXCH1

Figure 18a. Typical Auxiliary PWM Signals
(All Times in Increments of t

), Independent

CK

Mode

REV. 0

–21–

PROGRAMMABLE DIGITAL INPUT/OUTPUT

The ADMCF341 has a nine-pin programmable digital input/
output (PIO) port (PORTA). The nine pins (PORTA0–
PORTA8) are multiplexed with other on-chip peripheral
functions, in accordance with Table IX. When configured as a
PIO, each of these nine pins can act as an input or output, or an
interrupt source.

The operating mode (PIO or alternate function) of pins PORTA0
to PORTA8 is controlled by the PORTA_SELECT register.
This 9-bit register has a bit for each input so that the mode of
each pin may be selected individually.

Bit 0 of PORTA_SELECT controls the operation of the
PORTA0 pin, bit 1 controls the PORTA1 pin, etc. Setting the
appropriate bit in the PORTA_SELECT register causes the
corresponding pin to be configured for PIO functionality.
Clearing the bit selects the alternate mode of the corresponding
pin. Following power-on reset, all bits of PORTA_SELECT
are set such that PIO functionality is selected. The second
alternate function of PORTA7 is selected by bit 14 of the
PORTA_SELECT register. The second alternate function of

ADMCF341

Table IX. Port A Multiplexing

PORTA Pin First Alternate Function (Peripheral) Second Alternate Function (Peripheral)

PORTA8 AUX0 (Auxiliary PWM Output) CLKOUT (System CLOCK)
PORTA7 AUX1 (Auxiliary PWM Output) PWMSYNC (PWM)
PORTA6 DR1 (Data Receive SPORT1) None
PORTA5 FL1 (Flag Out SPORT1) DT1 (Data Transmit SPORT1)
PORTA4 SCLK1 (Serial Clock SPORT1) SCLK0 (Serial Clock SPORT0)
PORTA3 TFS0 (Transmit Frame Sync SPORT0) None
PORTA2 RFS0 (Receive Frame Sync SPORT0) None
PORTA1 DT0 (Data Transmit SPORT0) None
PORTA0 DR0 (Data Receive SPORT0) None

PORTA8 is selected by bit 15 of the PORTA_SELECT
register.

The second alternate function of the PORTA4 and PORTA5
pins is selected by bit 4 of MODECTRL Register (SPORT1
mode: boot mode/UART mode).

Once PIO functionality has been selected for any or all of these
nine pins, the direction may be set by the 9-bit PORTA_DIR
register. Clearing any bit configures the corresponding PIO line
as an input, while setting the bit configures it as an output. By
default, following a reset all bits of PORTA_DIR are cleared,
configuring the PIO lines as inputs. The data of the PORTA0
to PORTA8 lines is controlled by the PORTA_DATA register.
These registers can be used to read data from those PIO lines
configured as inputs and write data to those configured as outputs.
Any of the nine pins that have been configured for PIO func­tionality can be made to act as an interrupt source by setting
the appropriate bit of the PORTA_INTEN register. In order to
act as an interrupt source the pin must also be configured as an
input. An interrupt is generated upon a change of state (low-to­high transition or high-to-low transition) on any input that has
been configured as an interrupt source. Following a change of
state event on any such input, the corresponding bit is set in the
PORTA_FLAG register and a common PIO interrupt is generated.

Reading the PORTA_FLAG register permits determining the
interrupt source. Reading the PORTA_FLAG register automati­cally clears all bits of the registers. Following power-on or reset,
all bits of PORTA_INTEN are cleared so that no interrupts are
enabled.

Each PIO line has an internal pull-down resistor so that follow­ing power-on or reset all nine lines are configured as input PIOs
and will be read as logic lows if left unconnected.

PIO Registers

The configuration of all registers of the PIO system is shown at
the end of the data sheet.

INTERRUPT CONTROL

The ADMCF341 can respond to 18 different interrupt sources
with minimal overhead. Seven of these interrupts are internal
DSP core interrupts and 11 are from the on-chip peripherals.
The seven DSP core interrupts are SPORT0 receive and
transmit, SPORT1 receive (or IRQ0) and transmit (or IRQ1),

the internal timer, and two software interrupts. The motor
control interrupts are the nine PORTA PIOs and two from the
PWM block (PWMSYNC pulse and PWMTRIP). All the on-chip
peripheral interrupts are multiplexed into the DSP core via the
peripheral IRQ2 interrupt. They are also internally prioritized
and individually maskable. The start address in the interrupt
vector table for the ADMCF341 interrupt sources is shown in
Table X. The interrupts are listed from highest to lowest prior­ity. The PWMSYNC interrupt is triggered by a low-to-high
transition on the PWMSYNC pulse. The PWMTRIP interrupt
is triggered on a high-to-low transition on the PWMTRIP pin.
A PIO interrupt is detected on any change of state (high-to-low
or low-to-high) on the PIO lines.

The entire interrupt control system of the ADMCF341 is con­figured and controlled by the IFC, IMASK, and ICNTL
registers of the DSP core, the IRQFLAG register for the
PWMSYNC and PWMTRIP interrupts, and PORTA_FLAG
register for the PIO interrupts.

Table X. Interrupt Vector Addresses

Interrupt Source Interrupt Vector Address

PWMTRIP 0x002C (Highest Priority)
Peripheral Interrupt (IRQ2) 0x0004
PWMSYNC 0x000C
PIO 0x0008
Software Interrupt 1 0x0018
Software Interrupt 0 0 x001C
SPORT0 Transmit Interrupt 0x0010
SPORT0 Receive Interrupt 0x0014
SPORT1 Transmit Interrupt (or IRQ1) 0x0020
SPORT1 Receive Interrupt (or IRQ0) 0x0024
Timer 0x0028 (Lowest Priority)

Interrupt Masking

Interrupt masking (or disabling) is controlled by the IMASK
register of the DSP core. This register contains individual bits
that must be set to enable the various interrupt sources. If any
peripheral interrupt is to be enabled, the IRQ2 interrupt enable
bit (bit 9) of the IMASK register must be set. The configuration
of the IMASK register of the ADMCF341 is shown at the end
of the data sheet.

REV. 0–22–

ADMCF341

Interrupt Configuration

The IFC and ICNTL registers of the DSP core control and
configure the interrupt controller of the DSP core. The IFC
register is a 16-bit register that may be used to force and/or clear
any of the eight DSP interrupts. Bits 0 to 7 of the IFC register
may be used to clear the DSP interrupts while Bits 8 to 15 can
be used to force a corresponding interrupt. Writing to Bits 11
and 12 in IFC is the only way to create the two software inter­rupts. The ICNTL register is used to configure the sensitivity
(edge- or level-) of the IRQ0, IRQ1, and IRQ2 interrupts and to
enable/disable interrupt nesting. Setting Bit 0 of ICNTL config­ures the IRQ0 as edge-sensitive, while clearing the bit configures
it as level-sensitive. Bit 1 is used to configure the IRQ1 interrupt
and Bit 2 is used to configure the IRQ2 interrupt. It is recom­mended that the IRQ2 interrupt always be configured as
level-sensitive as this ensures that no peripheral interrupts are
lost. Setting Bit 4 of the ICNTL register enables interrupt nesting.
The configuration of both IFC and ICNTL registers is shown at
the end of the data sheet.

INTERRUPT OPERATION

Following a reset, the ROM code on the ADMCF341 must
copy a default interrupt vector table into program memory
RAM from address 0x0000 to 0x002F. Since each interrupt
source has a dedicated four-word space in this vector table, it is
possible to code short interrupt service routines (ISR) in place.
Alternatively, it may be necessary to insert a JUMP instruction
to the appropriate start address of the ISR if the ISR requires
more memory. When an interrupt occurs, the program sequencer
ensures that there is no latency (beyond synchronization delay)
when processing unmasked interrupts. In the case of the timer,
SPORT0, SPORT1, and software interrupts, the interrupt
controller automatically jumps to the appropriate location in the
interrupt vector table. At this point, a JUMP instruction to the
appropriate ISR is required. Motor control peripheral interrupts
are slightly different. When a peripheral interrupt is detected,
a bit is set in the IRQFLAG register for PWMSYNC and
PWMTRIP or in the PORTA_FLAG register for a PIO inter­rupt, and the IRQ2 line is pulled low until all pending interrupts
are acknowledged. The DSP software must determine the
source of the interrupts by reading the IRQFLAG register. If more
than one interrupt occurs simultaneously, the higher priority
interrupt service routine is executed. Reading the IRQFLAG
register clears the PWMTRIP and PWMSYNC bits and acknowl­edges the interrupt, thus allowing further interrupts when the
ISR exits. A user’s PIO interrupt service routine must read the
PORTA_FLAG register to determine which PIO port is the
source of the interrupt. Reading register PORTA_FLAG clears
all bits in the registers and acknowledges the interrupt, thus
allowing further interrupts after the ISR exits. The configuration
of all these registers is shown at the end of the data sheet.

SYSTEM CONTROLLER

The system controller block of the ADMCF341 performs the
following functions:

1. Manages the interface and data transfer between the DSP
core and the motor control peripherals.

2. Handles interrupts generated by the motor control periph­erals and generates a DSP core interrupt signal IRQ2.

3. Controls the ADC multiplexer select lines.

4. Enables PWMTRIP and PWMSYNC interrupts.

5. Controls the multiplexing of the SPORT1 and SPORT0
pins.

6. Controls the PWM single/double update mode.

7. Controls the ADC conversion time modes and the SHA
timers.

8. Controls the auxiliary PWM operation mode.

9. Contains a status register (SYSSTAT) that indicates the
state of the PWMTRIP pin, the watchdog timer, and the
PWM timer.

10. Performs a reset of the motor control peripherals and
control registers following a hardware, software, or watch­dog initiated reset.

SPORT1 and SPORT0 Control

The ADMCF341 has two serial ports: SPORT0 and SPORT1.
SPORT1 is available with a limited number of pins and is mainly
intended as a secondary port for development tools interfacing
and/or code booting from, as well as external serial memory.
Figure 19 shows the internal multiplexing of the SPORT0 and
SPORT1 signals. SPORT0 is intended as a general-purpose
communication port. SPORT0 can support the following
operating modes: SPORT, UART, and SPI.

SPORT1 Configuration

There are two operating modes for SPORT1: boot mode and
UART mode. These modes are selectable through Bit 4 of the
MODECTRL register. With SPORT1 in boot mode, the
SPORT1 serial clock (SCLK1) is externally available through
the SCLK1/SCLK0 pin. The signal SCLK1 is used to drive the
external serial memory input clock.

The SPORT1 flag signal (FL1) is externally available through
the FL1/DT1 pin. This signal is used to drive the external serial
memory input reset.

With SPORT1 configured in UART mode, the SPORT0 serial
clock (SCLK0) is externally available through the SCLK1/
SCLK0 pin. The SPORT1 data transmit (DT1) is externally
available through the FL1/DT1 pin.

SPORT0 Configuration

SPORT0 can be configured in the following modes: SPORT
mode, UART mode, and SPI mode.

SPORT0 can be configured for UART mode. In this mode the
DR0 and RFS0 signals of the internal serial port are connected
together.

SPORT0 can be configured to operate as the master SPI inter­face. The SPI mode is set through Bit 14 of the MODECTRL
register. When SPORT0 is configured as the SPI interface, the
SPORT I/O pins assume the configuration shown in Table XI.

REV. 0

–23–

ADMCF341

Table XI. SPORT0 Pin Assignment in SPI Mode

SPORT I/O Signal SPI Mode SPI Mode I/O

DT0 (Data Transmit) MOSI Output

(Master Output/
Slave Input)

DR0 MISO Input

(Master Input/
Slave Output)

TFS0 SS Output

(Slave Select)

RFS0 Unused N/A

SCLK0 SCK Output

(Serial Clock)

MODECTRL REGISTER (04)

SPORT1 BOOT MODE/UART MODE

DT1

FL1

DSP
CORE
SPORT1

TFS1

RFS1

DR1

SCLK1

The slave select pin automatically generates the select signal
at each word transfer. This pin can also be used as a general­purpose I/O during the SPI transfer without affecting the
SPORT operations.

The SPI clock polarity and phase are configurable through
Bits 13 and 12 of the MODECTRL Register. The SPI transfer
using clock phase is shown in Figures 20 and 21.

DT1/FL1

DR1

SCLK1/SCLK0

DT1

FL1

DSP
CORE
SPORT0

MODECTRL REGISTER (15)

SPORT0 SPORT MODE/UART MODE

TFS1

RFS1

SCLK1

SPI

CONTROL

BLOCK

MODECTRL REGISTER (14..13..12)

SPORT0 SPI INTERFACE CONTROL

DT0

DR0

TFS0

RFS0

Figure 19. SPORT0 and SPORT1 Internal Multiplexing (Simplified Diagram)

REV. 0–24–

ADMCF341

SCK CYCLE #

SCK (POLARITY = 0)

SCK (POLARITY = 1)

MOSI

MOSO

SCK CYCLE #

SCK (POLARITY = 0)

SCK (POLARITY = 1)

MOSI

MOSO

12345 N

SS

SEE NOTE 1

SEE NOTE 2

NOTE

1. LSB OF PREVIOUSLY TRANSMITTED WORD

2. UNDEFINED

MSB

MSB

Figure 20. SPI Transfer Using Clock Phase CPHA = 0

12345 N

SS

SEE NOTE 1

SEE NOTE 2

MSB

MSB

LSB

LSB

LSB

LSB

NOTES

1. LSB OF PREVIOUSLY TRANSMITTED WORD

2. UNDEFINED

Figure 21. SPI Transfer Using Clock Phase CPHA = 1

REV. 0

–25–

ADMCF341

Table XII. Peripheral Register Map

Address (hex) Name Bits Used Function

0x2000 ADC1 [15 ...4] ADC Results for I
0x2001 ADC2 [15 ...4] ADC Results for I
0x2002 ADC3 [15 ...4] ADC Results for I
0x2003 ADCAUX [15 ...4] ADC Results for VAUX
0x2004 PORTA_DIR [8 . . . 0] PA8 . . . PA0 Direction Setting
0x2005 PORTA_DATA [8 . . . 0] PA8 . . . PA0 Input/Output Data
0x2006 PORTA_INTEN [8 . . . 0] PA8 . . . PA0 Interrupt Enable
0x2007 PORTA_FLAG [8 . . . 0] PA8 . . . PA0 Interrupt Status
0x2008 PWMTM [15 ...0] PWM Period
0x2009 PWMDT [9 . . . 0] PWM Dead Time
0x200A PWMPD [9 . . . 0] PWM Pulse Deletion Time
0x200B PWMGATE [9 . . . 0] PWM Gate Drive Configuration
0x200C PWMCHA [15 ...0] PWM Channel A Pulsewidth
0x200D PWMCHB [15 ...0] PWM Channel B Pulsewidth
0x200E PWMCHC [15 ...0] PWM Channel C Pulsewidth
0x200F PWMSEG [8 . . . 0] PWM Segment Select
0x2010 AUXCH0 [7 . . . 0] AUX PWM Output 0
0x2011 AUXCH1 [7 . . . 0] AUX PWM Output 1
0x2012 AUXTM0 [7 . . . 0] Auxiliary PWM Frequency Value
0x2013 AUXTM1 [7 . . . 0] Auxiliary PWM Frequency Value/Offset
0x2014 Reserved
0x2015 MODECTRL [8 . . . 0] Mode Control Register
0x2016 SYSSTAT [3 . . . 0] System Status
0x2017 IRQFLAG [1 . . . 0] Interrupt Status
0x2018 WDTIMER [15 ...0] Watchdog Timer
0x2019 . . . 48 Reserved
0x2049 PORTA-SELECT [8 . . . 0] PA8 . . . PA0 Mode Select
0x204A . . . 5F Reserved
0x2060 PWMSYNCWT [7 . . . 0] PWMSYNC Pulsewidth
0x2061 PWMSWT [0] PWM S/W Trip Bit
0x2062 . . . 67 Reserved
0x2068 I

_TRIM [2 . . . 0] I

CONST

CONST

_TRIM
0x2069 SHA1_TM [15 ...0] Sample Hold Timer 1
0x206A SHA2_TM [15 ...0] Sample Hold Timer 2
0x206B SHA3_TM [15 ...0] Sample Hold Timer 3
0x2070 Reserved
0x2080 FMCR [15 ...0] Flash Memory Control Register
0x2081 FMAR [11 ...0] Flash Memory Address Register
0x2082 FMDRH [13 ...0] Flash Memory Data Register High
0x2083 FMDRL [15 ...0] Flash Memory Data Register Low
0x2084 . . . FF Reserved

SENSE

SENSE

SENSE

1
2
3

REV. 0–26–

ADMCF341

Table XIII. DSP Core Registers

Address (hex) Name Bits Function

0x3FFF SYSCNTL [15 . . . 0] System Control Register
0x3FFE MEMWAIT [15 . . . 0] Memory Wait State Control Register
0x3FFD TPERIOD [15 . . . 0] Interval Timer Period Register
0x3FFC TCOUNT [15 . . . 0] Interval Timer Count Register
0x3FFB TSCALE [7 . . . 0] Interval Timer Scale Register
0x3FFA SPORT0_RX_WORDS1 [15 . . . 0] SPORT0 Multichannel Word 1 Receive
0x3FF9 SPORT0_RX_WORDS0 [15 . . . 0] SPORT0 Multichannel Word 0 Receive
0x3FF8 SPORT0_TX_WORDS1 [15 . . . 0] SPORT0 Multichannel Word 1 Transmit
0x3FF7 SPORT0_TX_WORDS0 [15 . . . 0] SPORT0 Multichannel Word 0 Transmit
0x3FF6 SPORT0_CTRL_REG [15 . . . 0] SPORT0 Control Register
0x3FF5 SPORT0_SCLKDIV [15 . . . 0] SPORT0 Clock Divide Register
0x3FF4 SPORT0_RFSDIV [15 . . . 0] SPORT0 Receive Frame Sync Divide
0x3FF3 SPORT0_AUTOBUF_CTRL [15 . . . 0] SPORT0 Autobuffer Control Register
0x3FF2 SPORT1_CTRL_REG [15 . . . 0] SPORT1 Control Register
0x3FF1 SPORT1_SCLKDIV [15 . . . 0] SPORT1 Clock Divide Register
0x3FF0 SPORT1_RFSDIV [15 . . . 0] SPORT1 Receive Frame Sync Divide
0x3FEF SPORT1_AUTOBUF_CTRL [15 ...0] SPORT1 Autobuffer Control Register

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BOOT ⬇ MEMORY ⬇ FLASH ⬇ CODE

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED

ALWAYS READ 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED

ALWAYS READ 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FLASH MEMORY CONTROL REGISTER

FLASH MEMORY ADDRESS REGISTER

0000000000000000

ADDRESS 11 ⬇ 0

FLASH MEMORY DATA REGISTER LOW (FMDRL)

0000000000000000

STATUS 5 ⬇ 0 DATA 7 ⬇ 0

FLASH MEMORY DATA REGISTER HIGH (FMDRH)

0000000000000000

0

000000000000001

0x2080

0x2081

0x2083

0x2082

DATA 23 ⬇ 8

MOST SIGNIFICANT BIT IS ON THE LEFT. FOR EXAMPLE, DATA23 IS BIT 15 OF FMDRH.

Figure 22. Configuration of Flash Memory Registers

Default bit values are shown; if no value is shown, the bit field is undefined at reset.
Reserved bits are shown on a gray field—these bits should always be written as shown.

REV. 0

–27–

ADMCF341

PWMTM (R/W)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PWMDT (R/W)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

00000000

PWMSEG (R/W)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

00 00 000

00000000

000000000

DM (0x 2008)

PWMTM

f

=

PWM

2  PWMTM

CLKOUT

2  PWMTM

f

CLKOUT

f

DM (0x2009)

PWMDT

TD =

DM (0x200F)

0 = NO CROSSOVER
1 = CROSSOVER

A CHANNEL CROSSOVER

B CHANNEL CROSSOVER

C CHANNEL CROSSOVER

PWMSYNCWT (R/W)

15 14 13 12 11 10 9 8 7 6 5 4 3 2

0100011100000000

PWMSWT (R/W)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

00 0 0

000000000000

1

0

0

Figure 23. Configuration of PWM Registers

Default bit values are shown; if no value is shown, the bit field is undefined at reset.
Reserved bits are shown on a gray field—these bits should always be written as shown.

CH OUTPUT DISABLE

CL OUTPUT DISABLE

BH OUTPUT DISABLE

BL OUTPUT DISABLE

AH OUTPUT DISABLE

AL OUTPUT DISABLE

DM (0x2060)

PWMSYNCWT

T

PWMSYNC, ON

DM (0x2061)

=

0 = ENABLE
1 = DISABLE

PWMSYNCWT + 1

f

CLKOUT

REV. 0–28–

0 = DISABLE
1 = ENABLE

PWMPD (R/W)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

00000000

PWMGATE (R/W)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

000000

LOW SIDE GATE CHOPPING

HIGH SIDE GATE CHOPPING

PWMCHA (R/W)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DM (0x200A)

00000000

PWMPD

PWMPD

=

T

MIN

f

CLKOUT

DM (0x200B)

0000000000

GDCLK
GATE DRIVE CHOPPING FREQUENCY

f

CLKOUT

=

f

CHOP

4  (GDCLK + 1)

DM (0x200C)

ADMCF341

PWMCHB (R/W)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PWMCHC (R/W)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Figure 24. Configuration of Additional PWM Registers

Default bit values are shown; if no value is shown, the bit field is undefined at reset.
Reserved bits are shown on a gray field—these bits should always be written as shown.

PWM CHANNEL A
DUTY CYCLE

DM (0x200D)

PWM CHANNEL B
DUTY CYCLE

DM (0x200E)

PWM CHANNEL C
DUTY CYCLE

REV. 0

–29–

ADMCF341

PORTA_DIR (R/W)

14

15

0

13 12 11 10 9 8 7 6 5 4 3 2 1 0

0

0

0

000000000000

DM (0x2004)

0 = CLOCKOUT

1 = AUX0

0 = PWMSYNC

1 = AUX1

PA0-PA8

PORTA_DATA (R/W)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

00000000

PORTA_SELECT (R/W)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0000

0 = AUX0/CLOCKOUT

0 = AUX1/PWMSYNC

1 = PA8

1 = PA7

0 = DR1
1 = PA6

0 = DT1/FL1

1 = PA5

1000

00000000

PA0-PA8

11111111

0 = LOW LEVEL
1 = HIGH LEVEL

0 = INPUT
1 = OUTPUT

DM (0x2005)

DM (0x2049)

0 = DR0
1 = PA0

0 = DT0
1 = PA1

0 = RFS0
1 = PA2

0 = TFS0
1 = PA3

0 = SCLK1/SCLK0

1 = PA4

Figure 25. Configuration of PIO Registers

Default bit values are shown; if no value is shown, the bit field is undefined at reset.
Reserved bits are shown on a gray field—these bits should always be written as shown.

REV. 0–30–

ADMCF341

PORTA_INTEN (R/W)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

00000000

PORTA_FLAG (R/W)

000000000000

Figure 26. Configuration of Additional PIO Registers

Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these
bits should always be written as shown.

DM (0x2006)

0000

0 = INTERRUPT DISABLE
1 = INTERRUPT ENABLE

DM (0x2007)

0000

0 = INTERRUPT DISABLE
1 = INTERRUPT ENABLE

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

AUXCH0 (R/W)

AUXCH1 (R/W)

AUXTM0 (R/W)

AUXTM1 (R/W)

000000000000

T

= 2  (AUXCH0) 

ON, AUX0

000000000000

T

= 2  (AUXCH1) 

ON, AUX1

111111111111

AUX0 PERIOD = 2  (AUXTM0 + 1) 

AUX1 PERIOD = 2  (AUXTM1) 
OFFSET = 2  (AUXTM1) 

Figure 27. Configuration of Auxiliary PWM Register

0000

0000

1111

1111111111111111

DM (0x2010)

t

CK

DM (0x2011)

t

CK

DM (0x2012)

DM (0x2013)

t

CK

t

CK

t

CK

Default bit values are shown; if no value is shown, the bit field is undefined at reset.

REV. 0

–31–

ADMCF341

I

CONST

ADC1 (R)

ADC2 (R)

ADC3 (R)

ADCAUX (R)

_TRIM (R/W)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0000000000000000

0000 DM (0x2000)

CONVERSION
STATUS

DM (0x2001)

0000

CONVERSION
STATUS

DM (0x2002)

0000

CONVERSION
STATUS

DM (0x2003)

0000

DM (0x2068)

0 = DATA READY

1 = NOT READY

0 = DATA READY

1 = NOT READY

0 = DATA READY

1 = NOT READY

I

MIN = BITS 0 – 2 CLEARED.

CONST

I

MAX = BITS 0 – 2 SET.

CONST

SHA1_TM (R/W)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DM (0x2069)

0000000000000000

SHA2 _TM (R/W)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DM (0x206A)

0000000000000000

SHA3 _TM (R/W)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DM (0x206B)

0000000000000000

Figure 28. Configuration of ADC Registers

Default bit values are shown; if no value is shown, the bit field is undefined at reset.
Reserved bits are shown on a gray field—these bits should always be written as shown.

REV. 0–32–

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MODECTRL (R/W)

0000000000000000

ADMCF341

DM (0x2015)

0 = SPORT MODE

1 = UART MODE

0 = SPORT

1 = SPI MODE

0 = STANDARD

1 = REVERSE

0 = PHA0
1 = PHA1

0 = I

SENSE

1 = VOLTAGE

0 = I

SENSE

1 = VOLTAGE

0 = I

SENSE

1 = VOLTAGE

0 = OFFSET MODE

1 = INDEPENDENT MODE

SPORT 0

MODE SELECT

SPORT 0

SPI MODE

SPI CLOCK

POLARITY

SPI CLOCK

CHANNEL 3
SELECTION

CHANNEL 2
SELECTION

CHANNEL 1
SELECTION

AUX PWM

MODE SELECT

PHASE

ADC MUX CONTROL
00 VAUX0
01 VAUX1
10 VAUX2
11 VREF

PWMTRIP

INTERRUPT

PWMSYNC
INTERRUPT

SPORT1 MODE
SELECT

ADC MUX
CONTROL

PWM UPDATE
MODE SELECT

0 = DISABLE
1 = ENABLE

0 = DISABLE
1 = ENABLE

0 = BOOT MODE
1 = UART MODE

NOT USED IN ADMCF341
SET BIT TO ZERO

0 = SINGLE UPDATE MODE
1 = DOUBLE UPDATE MODE

0 = CLKIN RATE

1 = CLKOUT RATE

ADC

COUNTER

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 = 1ST HALF OF PWM
CYCLE
1 = 2ND HALF OF PWM
CYCLE

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PWM TIMER

STATUS

SYSSTAT (R)

IRQFLAG (R)

WDTIMER (W)

01

00000000000

000000000000

0000000000000000

DM (0x2016)

PWMTRIP

PIN STATUS

WATCHDOG

STATUS

0000

DM (0x2017)

PWMTRIP INTERRUPT

PWMSYNC INTERRUPT

DM (0x2018)

0 = LOW
1 = HIGH

0 = NORMAL
1 = WATCHDOG RESET
OCCURRED

0 = NO INTERRUPT
1 = INTERRUPT
OCCURRED

Figure 29. Configuration of Status/Control Registers

Default bit values are shown; if no value is shown, the bit field is undefined at reset.
Reserved bits are shown on a gray field—these bits should always be written as shown.

REV. 0

–33–

ADMCF341

ICNTL

43210

11000

DSP REGISTER

0 = DISABLE
1 = ENABLE

INTERRUPT FORCE INTERRUPT CLEAR

IRQ2

SPORT0 TRANSMIT

SPORT0 RECEIVE

SOFTWARE 1

SOFTWARE 0

SPORT1 TRANSMIT OR IRQ1

SPORT1 RECEIVE OR IRQ0

INTERRUPT NESTING

IFC

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IRQ0 SENSITIVITY

IRQ1 SENSITIVITY

IRQ2 SENSITIVITY

0 = LEVEL
1 = EDGE

DSP REGISTER

0000000000000000

TIMER

SPORT1 RECEIVE OR IRQ0

SPORT1 TRANSMIT OR IRQ1

SOFTWARE 0

SOFTWARE 1

SPORT0 RECEIVE

SPORT0 TRANSMIT

TIMER

IMASK (R/W)

0000000000000110

DSP REGISTER

TIMER

SPORT1 RECEIVE

(OR IRQ0)

SPORT1 TRANSMIT

(OR IRQ1)

SOFTWARE 0

0 = DISABLE

(MASK)

1 = ENABLE

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PERIPHERAL (OR IRQ2)

SPORT0 TRANSMIT

SPORT0 RECEIVE

SOFTWARE 1

Figure 30. Configuration of Interrupt Control Registers

Default bit values are shown; if no value is shown, the bit field is undefined at reset.
Reserved bits are shown on a gray field—these bits should always be written as shown.

IRQ2

0 = DISABLE
(MASK)
1 = ENABLE

REV. 0–34–

ADMCF341

00

SPORT1 CONFIGURE

MEMWAIT (R/W)

SYSCNTL (R/W)

11000000011111

0 = FI, FO, IRQ0, IRQ1, SCLK
1 = SERIAL PORT

0 = DISABLED
1 = DISABLED

0 = DISABLED
1 = ENABLED

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SPORT0 ENABLE

SPORT1 ENABLE

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1

1111111 1 1111111

Figure 31. Configuration of Registers

Default bit values are shown; if no value is shown, the bit field is undefined at reset.
Reserved bits are shown on a gray field—these bits should always be written as shown.

DM (0x3FFF)

DM (0x3FFE)

REV. 0

–35–

ADMCF341

OUTLINE DIMENSIONS

Dimensions shown in mm and (inches).

28-Lead Wide-Body SOIC

(R-28)

18.10 (0.7125)

17.70 (0.6969)

28 15

1

PIN 1

1.27

0.30 (0.0118)

0.10 (0.0040)

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE
ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE
FOR USE IN DESIGN

(0.0500)

BSC

0.51 (0.020)

0.33 (0.013)

14

2.65 (0.1043)

2.35 (0.0926)

SEATING
PLANE

7.60 (0.2992)

7.40 (0.2914)

10.65 (0.419)

10.00 (0.394)

0.32 (0.0125)

0.23 (0.0091)

0.75 (0.029)

0.25 (0.010)

8
0

 45

1.27 (0.0500)

0.40 (0.016)

C02470–0–4/02(0)

–36–

PRINTED IN U.S.A.

REV. 0