Datasheet ADM8830 Datasheet (Analog Devices)

Charge Pump Regulator

TIMING

GENERATOR

LDO

VOLTA

GE

REGULATOR

VOLTA

GE

DOUBLER

CONTROL

LOGIC

DISCHARGE

SHUTDOWN

CONTROL

C1+

C1–

VOUT

LDO IN

+5

VOUT

+5

VIN

C2+

C2–

C3+

C3–

+15VOUT

C4+

C4–

–10VOUT

C1

2.2F

C6

2.2F

C2
1F

C7

2.2F

+5.1V

C3
1F

+15.3V

C8
1F

C4
1F

–10.2V
C9
1F

VOLTA

GE

TRIPLER

DOUBLE

TRIPLE

VOLTAGE

INVERTE

R

OSCILLATOR

CLKIN

SCAN/BLANK

LDO_ON/OFF

SHDN

GND

V

CC

ADM8830

C5

2.2F

for Color TFT Panel

ADM8830

FEATURES
3 Output Voltages (+5.1 V, +15.3 V, –10.2 V) from

One 3 V Input Supply

Power Efciency Optimized for Use with TFT in

Mobile Phones
Low Quiescent Current
Low Shutdown Current (<1 A)
Fast Transient Response
Shutdown Function
Power Saving during Blanking Period
Option to Use External LDO

APPLICATIONS
Handheld Instruments
TFT LCD Panels
Cellular Phones

GENERAL DESCRIPTION

The ADM8830 is a charge pump regulator used for color thin
lm transistor (TFT) liquid crystal displays (LCDs). Using
charge pump technology, the device can be used to generate three
output voltages (+5.1 V ± 2%, +15.3 V, –10.2 V) from a single
3 V input supply. These outputs are then used to provide
supplies for the LCD controller (5.1 V) and the gate drives for
the transistors in the panel (+15.3 V and –10.2 V). Only a few
external capacitors are needed for the charge pumps. An efcient
low dropout voltage regulator also ensures that the power
efciency is high and provides a low ripple 5.1 V output. This
LDO can be shut down and an external LDO used to regulate
the 5 V doubler output and drive the input to the charge pump
section, which generates the +15.3 V and –10.2 V outputs if so
required by the user.

The ADM8830 has an internal 100 kHz oscillator for use in
scanning mode, but the part must be clocked by an external clock
source in blanking (low current) mode. The internal oscillator is
used to clock the charge pumps during scanning mode where the
current is highest. During blanking periods, the ADM8830
switches to use an external, lower frequency clock. This allows the
user to vary the frequency and maximize power efciency during
blanking periods. The tolerances on the output voltages are

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
that may result from its use. No license is granted by implication or oth­erwise under any patent or patent rights of Analog Devices. Trademarks
and registered trademarks are the property of their respective owners.

FUNCTIONAL BLOCK DIAGRAM

seamlessly maintained when switching from scanning mode to
blanking mode or vice versa.

The ADM8830 has a number of power saving features, including
low power shutdown and reduced quiescent current consumption
during the blanking periods mentioned above. The 5.1 V output
consumes the most power, so power efciency is also maximized
on this output with an oscillator enabling scheme (Green Idle™).
This effectively senses the load current that is owing and turns
on the charge pump only when charge needs to be delivered to
the 5 V pump doubler output.

The ADM8830 is fabricated using CMOS technology for minimal
power consumption. The part is packaged in 20-lead LFCSP
and TSSOP packages.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

(VCC = 2.6 V to 3.6 V, TA = –40C to +85C, unless otherwise noted, C1, C5, C6,

ADM8830–SPECIFICATIONS

Parameter Min Typ Max Unit Test Conditions

INPUT VOLTAGE, VCC 2.6 3.6 V

SUPPLY CURRENT, ICC 150 400 µA Unloaded, Scanning Period
70 140 µA Unloaded, Blanking Period
1 µA Shutdown Mode, TA = 25°C

+5.1 V OUTPUT
Output Voltage 5.0 5.1 5.2 V IL = 10 µA to 8 mA
Output Current 4 5 mA Scanning Period
5 8 mA Scanning Period, VCC > 2.7 V
50 200 µA Blanking Period
Power Efciency 80 % VCC = 3 V, IL = 5 mA (Scanning)
70 % VCC = 3 V, IL = 200 µA (Blanking)
Output Ripple 10 mV p-p 8 mA Load
Transient Response 5 µs IL Stepped from 10 µA to 8 mA

+15.3 V OUTPUT
Output Voltage 14.4 15.3 15.6 V IL = 1 µA to 100 µA
Output Current 50 100 µA Scanning Period
1 10 µA Blanking Period
Output Ripple 50 mV p-p IL = 100 µA

–10.2 V OUTPUT
Output Voltage –10.4 –10.2 –9.6 V IL = –1 µA to –100 µA
Output Current –100 –50 µA Scanning Period
–10 –1 µA Blanking Period
Output Ripple 50 mV p-p IL = –100 µA

POWER EFFICIENCY 90 % Relative to 5.1 V Output, IL = 100 µA (Scanning)
(+15.3 V and –10.2 V Outputs) 80 % Relative to 5.1 V Output, IL =10 µA (Blanking)

CHARGE PUMP FREQUENCY 60 100 140 kHz Scanning Period

CONTROL PINS
SHDN
Input Voltage, V

0.7 VCC V SHDN High = Normal Mode
Digital Input Current ±1 µA
Digital Input Capacitance* 10 pF
SCAN/BLANK
Input Voltage 0.3 VCC V Low = BLANK Period

0.7 VCC V High = SCAN Period
Digital Input Current ±1 µA
Digital Input Capacitance* 10 pF
LDO_ON/OFF
Input Voltage 0.3 VCC V Low = External LDO

0.7 VCC V High = Internal LDO
Digital Input Current ±1 µA
Digital Input Capacitance* 10 pF
CLKIN
Minimum Frequency 0.9 1 kHz Duty Cycle = 50%, Rise/Fall Times = 20 ns
Input Voltage
VIL 0.3 VCC V
VIH 0.7 VCC V
Digital Input Current ±1 µA
Digital Input Capacitance* 10 pF

*Guaranteed by design. Not 100% production tested.

Specications are subject to change without notice.

0.3 VCC V SHDN Low = Shutdown Mode

SHDN

C7 = 2.2 F, C2, C3, C4, C8, C9 = 1 F, CLKIN = 1 kHz in blanking mode.)

–2–

REV. B

(VCC = 2.6 V to 3.6 V, TA = –40C to +85C, unless otherwise noted, C1, C5, C6,

TIMING SPECIFICATIONS

C7 = 2.2 F, C2, C3, C4, C8, C9 = 1 F, CLKIN = 1 kHz in blanking mode.)

Parameter Min Typ Max Unit Test Conditions

POWER-UP SEQUENCE
+5 V Rise Time, t
+15 V Rise Time, t
–10 V Fall Time, t

300 µs 10% to 90%, Figure 2

R5V

8 ms 10% to 90%, Figure 2

R15V

12 ms 90% to 10%, Figure 2

F10V

Delay between –10 V Fall
and +15 V, t

3 ms Figure 2

DELAY

POWER-DOWN SEQUENCE
+5 V Fall Time, t
+15 V Fall Time, t
–10 V Rise Time, t

Specications are subject to change without notice.

75 ms 90% to 10%, Figure 2

F5V

40 ms 90% to 10%, Figure 2

F15V

40 ms 10% to 90%, Figure 2

R10V

ADM8830

ABSOLUTE MAXIMUM RATINGS*

(TA = 25°C, unless otherwise noted.)

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.0 V

Input Voltage to Digital Inputs . . . . . . . . . . . . . –0.3 V to +4.0 V

Output Short Circuit Duration to GND . . . . . . . . . . . . . 10 sec

Output Voltage

+5.1 V Output . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

–10.2 V Output . . . . . . . . . . . . . . . . . . . . . . . .–12 V to +0.3 V

+15.3 V Output . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V

Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.55 W

(Derate 33 mW/°C above 25°C)

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class I

*This is a stress rating only; functional operation of the device at these or any other

conditions above those indicated in the operational sections of this specication is
not implied. Exposure to absolute maximum rating conditions for extended periods
of time may affect reliability.

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADM8830ACP –40ºC to +85ºC Lead Frame Chip Scale Package CP-20-1
ADM8830ACP-REEL7 –40ºC to +85ºC Lead Frame Chip Scale Package CP-20-1
ADM8830ARU –40ºC to +85ºC Thin Shrink Small Outline Package RU-20
ADM8830ARU-REEL –40ºC to +85ºC Thin Shrink Small Outline Package RU-20
ADM8830ARU-REEL7 –40ºC to +85ºC Thin Shrink Small Outline Package RU-20
EVAL-ADM8830EB Evaluation Board

THERMAL CHARACTERISTICS

20-Lead TSSOP Package:


= 72°C/W

A

J

20-Lead LFCSP Package:


= 31°C/W

A

J

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although the ADM8830
features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high
energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

REV. B

–3–

ADM8830

15 C4–
14 C2+
13 C2–
12 C3+

VCC 1

VOUT 2

LDO_IN 3

20 C1+

11 C3–

LDO_ON/OFF 6

SHDN 7

SCAN/BLANK 8

CLKIN 9

+15VOUT 10

+5VOUT 4

+5

VIN 5

19 C1–

18 GND

17 –10V

OUT

16 C4

+

PIN 1
INDICATOR

TOP VIEW

ADM8830

TOP VIEW

(Not to Scale)

ADM8830

C1–

GND

C1+

–10VOUT

V

CC

C4+

VOUT

C4–

LDO_IN

C2+

+5

VOUT

C2–

+5

VIN

C3+

LDO_ON/OFF

C3–

SHDN

+15VOUT

SCAN/BLANK

CLKIN

1

2

3

4

5

6

7

8

9

10 11

12

13

14

15

16

17

18

19

20

PIN CONFIGURATIONS

TSSOP

LFCSP

PIN FUNCTION DESCRIPTIONS

Pin Number

TSSOP LFCSP Mnemonic Function

1, 2 19, 20 C1–, C1+ External capacitor C1 is connected between these pins. A 2.2 µF capacitor is recommended.

3 1 VCC Positive Supply Voltage Input. Connect this pin to 3 V supply with a 2.2 µF decoupling capacitor.

4 2 VOUT Voltage Doubler Output. This is derived by doubling the 3 V supply. A 2.2 µF capacitor to

ground is required on this pin.

5 3 LDO_IN Voltage Regulator Input. The user has the option to bypass this circuit using the

LDO_ON/OFF pin.

6 4 +5VOUT +5.1 V Output Pin. This is derived by doubling and regulating the 3 V supply. A 2.2 µF ca-

pacitor to ground is required on this pin to stabilize the regulator.

7 5 +5VIN +5.1 V Input Pin. This is the input to the voltage tripler and doubler inverter charge pump

circuits.

8 6 LDO_ON/OFF Control Logic Input. 3 V CMOS logic. A logic high selects the internal LDO for regulation of

the 5 V voltage doubler output. A logic low isolates the internal LDO from the rest of the charge
pump circuits. This allows the use of an external LDO to regulate the 5 V voltage doubler
output. The output of this LDO is then fed back into the voltage tripler and doubler/inverter
circuits of the ADM8830.

9 7 SHDN Digital Input. 3 V CMOS logic. Active low shutdown control. This shuts down the timing

generator and enables the discharge circuit to dissipate the charge on the voltage outputs,
thus driving them to 0 V.

10 8 SCAN/BLANK Drive Mode Input. 3 V CMOS logic. A logic high places the part in scan (high current) mode

and the charge pump is driven by the internal oscillator. A logic low places the part in blanking
(low current) mode and the charge pump is driven by the (slower) external oscillator. This is
a power saving feature on the ADM8830.

11 9 CLKIN External CLOCK Input. During a blanking period, the oscillator circuit selects this pin to drive

the charge pump circuit. This is at a lower frequency than the internal oscillator, resulting in
lower quiescent current consumption, thus saving power.

12 10 +15VOUT +15.3 V Output Pin. This is derived by tripling the +5.1 V regulated output. A 1 µF capacitor

13, 14 11, 12 C3–, C3+ External capacitor C3 is connected between these pins. A 1 µF capacitor is recommended.

15, 16 13, 14 C2–, C2+ External capacitor C2 is connected between these pins. A 1 µF capacitor is recommended.

17, 18 15, 16 C4–, C4+ External capacitor C4 is connected between these pins. A 1 µF capacitor is recommended.

19 17 –10VOUT –10.2 V Output Pin. This is derived by doubling and inverting the +5.1 V regulated output.

20 18 GND Device Ground Pin.

is required on this pin.

A 1 µF capacitor is required on this pin.

–4–

REV. B REV. B

Typical Performance Characteristics–ADM8830

OUTPUT CURRENT – A

80

50

10

10

LDO POWER EFFICIENCY – %

20

30

40

60

70

30 50 70 90 110 130 150 170 190

OUTPUT CURRENT – mA

85

2

LDO POWER EFFICIENCY – %

4 6 8

84

83

82

81

80

79

78

0 3 5 7

1

VCC – V

5.30

5.25

5.20

5.15

5.10

5.00

4.95

4.90

5.05

5.0V O/P – V

2.6

DEVICE 1 @ –40C

DEVICE 1 @ +25C

DEVICE 1 @ +85C

2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6

BLANKING FREQUENCY – Hz

5.0752

100

LDO OUTPUT VOLTAGE – V

1000 10000

5.0750

5.0748

5.0746

5.0744

5.0742

5.0740

5.0738

5.0736

5.0734

OUTPUT CURRENT – A

100

4

+15V/–10V EFFICIENCY – %

6 8 10

90

80

70

60

2

VCC – V

2.6 3.62.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4

300

SUPPLY CURRENT – A

250

200

150

100

50

0

ICC (BLANK)

ICC (SCAN)

3.5

I

LOAD

– mA

5.104

2

LDO O/P – V

4 6 8

5.102

5.100

5.098

5.096

5.094

5.092

5.090
0 3 5 7

1

OUTPUT CURRENT – A

100

40

+15V/–10V EFFICIENCY – %

60 80 100

90

80

70

60

200

50

40

V

OUT

5V OUTPUT RIPPLE

VCC RIPPLE

TPC 1. LDO Efciency in Blanking
Mode with VCC = 3 V

TPC 4. LDO Efciency in Scanning
Mode with VCC = 3 V

TPC 2. LDO Output Voltage (Unloaded)
vs. Blanking Mode Frequency

TPC 5. +15 V/–10 V Efciency vs. Output
Current in Blanking Mode, VCC = 3 V

TPC 3. LDO O/P Voltage vs. Load
Current in Scanning Mode, VCC = 3.3 V

TPC 6. +15 V/–10 V Efciency vs. Output
Current in Scanning Mode, VCC = 3 V

TPC 7. LDO Variation over Supply
and Temperature

TPC 8. Supply Current vs. Voltage

–5–

TPC 9. Output Ripple on LDO
(5 V Output)

ADM8830 ADM8830

LOAD ENABLE

5V OUTPUT

+15V OUTPUT

–10V OUTPUT

5VOUT

LOAD DISABLE

5V OUTPUT

TEMPERATURE – C

DISSIPATED POWER – mW

19.4
–40 –20

0 20

40

60

80

19.5

19.6

19.7

19.8

19.9

20.0

20.1

+15V OUTPUT

–10V OUTPUT

5VOUT

TPC 10. 5 V Output Transient
Response for Maximum Load
Current

TPC 13. +15 V and –10 V Outputs at
Power-Down (Unloaded)

TPC 11. 5 V Output Transient Response,
Load Disconnected

TPC 14. Power Dissipation over Tem­perature, VCC = 3.6 V, Scanning Mode
with All O/Ps at Maximum Load

TPC 12. +15 V and –10 V Outputs at
Power-Up

–6–

REV. B REV. B

SCANNING AND BLANKING

90%

10%

t

R

t

F

t

H

t

T

t

R

: RISE TIME

t

F

: FALL TIME

t

H

t

T

@ 100% = DUTY CYCLE

V

CC

LOAD

SCAN/BLANK

EXTERNAL CLOCK

SHDN

+5V

+15V

–10V

t

F5V

t

F15V

t

R10V

t

R15V

t

R5V

t

DELAY

t

F10V

–3V

90%

10%

10%

90%

SOLDER MASK

BOARD METALLIZATION

DIMENSIONS IN

MILLIMETERS

0.2

0.25

0.5

0.75

0.28

0.4

0.25

0.9

3.10

1.95

2.10

A TFT LCD panel is essentially made up of a bank of capacitors,
each representing a pixel in the display. These capacitors store
different levels of charge, depending on the amount of lumines­cence required for a given pixel. When a picture is being displayed
on the panel, a scan of all the pixel capacitors is performed, placing
different levels of charge on each in order to create the image. The
process of updating the display like this is called “scanning.” Once
scanned, an image will be held by pixel capacitance and the con­troller and source line drivers can be put into a low power mode.
This low power mode is referred to as the blanking mode on the
ADM8830. Over a nite period of time, this pixel charge will leak
and the capacitors will have to be refreshed in order to maintain
the image.

The ADM8830 caters to the two modes of operation described
above as follows. When the TFT LCD panel is in scanning mode,
a logic high on the SCAN/BLANK input places the device in high
current power mode, providing extra power (extra current) to the
LCD controller and the source line drivers. If the panel continues
to be updated (as when a moving picture is being displayed), then
the ADM8830 can be continually operated in scanning mode. If
the same image is kept on the panel, a logic low is applied to the
SCAN/BLANK input and the ADM8830 enters blanking (low
current) mode. Depending on how often the image is being updated,
the ADM8830 can be operated with a variable SCAN/BLANK
duty cycle. This helps to maximize power efciency and therefore
extends the battery life.

Figure 2. Power Sequence

TRANSIENT RESPONSE

The ADM8830 features extremely fast transient response, making
it very suitable for fast image updates on TFT LCD panels. This
means that even under changing load conditions there is still very
effective regulation of the 5 V output. TPCs 10 and 11 show how
the 5.1 V output responds when a maximum load is dynamically
connected and disconnected. Note that the output settles within
5 µs to less than 1% of the output level.

POWER SEQUENCING

The gate drive supplies must be sequenced such that the –10 V
supply is up before the +15 V supply for the TFT panel to power
up correctly. The ADM8830 controls this sequence. When the
device is turned on (a logic high on SHDN), the ADM8830 allows
the –10 V output to ramp immediately but holds off the +15 V
output. It continues to do this until the negative output has reached
–3 V. At this point, the positive output is enabled and allowed to
ramp up to +15 V. This sequence is highlighted in Figure 2.

Figure 1. Duty Cycle of External Clock

EXTERNAL CLOCK

The ADM8830 has an internal 100 kHz oscillator, but an external
clock source can also be used to clock the part. This clock source
must be applied to the CLKIN pin. Power is saved during blank­ing periods by disabling the internal oscillator and switching to
the lower frequency external clock source. To achieve optimum
performance of the charge pump circuitry, it is important that the
duty cycle of the external clock source be 50% and that the rise
and fall times be less than 20 ns.

Figure 3. Suggested LFCSP 4 mm  4 mm 20-Lead
Land Pattern

–7–

ADM8830

20

1

11

10

6.40 BSC

4.50

4.40

4.30

PIN 1

6.60

6.50

6.40

SEATING

PLANE

0.15

0.05

0.30

0.19

0.65
BSC

1.20

MAX

0.20

0.09

0.75

0.60

0.45

8
0

COMPLIANT TO JEDEC STANDARDS MO-153AC

COPLANARITY

0.10

1

20

5

6

11

16

15

BOTTOM

VIEW

10

2.25

2.10 SQ

1.95

0.75

0.55

0.35

0.30

0.23

0.18

0.50

BSC

12 MAX

0.20
REF

0.80 MAX

0.65 TYP

0.05 MAX

0.02 NOM

1.00

0.85

0.80

SEATING

PLANE

PIN 1

INDICATOR

TOP

VIEW

3.75

BSC SQ

4.0

BSC SQ

COPLANARITY

0.08

0.60

MAX

0.60

MAX

0.25 MIN

COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1

OUTLINE DIMENSIONS

20-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-20)

Dimensions shown in millimeters

C02565–0–10/03(B)

20-Lead Lead Frame Chip Scale Package [LFCSP]

4 mm  4 mm Body

(CP-20-1)

Dimensions shown in millimeters

Revision History

Location Page

10/03—Data Sheet changed from REV. A to REV. B.

Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3/03—Data Sheet changed from REV. SpA to REV. A.

Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Edits to TPC 12 and TPC 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

11/02—Data Sheet changed from REV. 0 to REV. SpA.

Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Changes to THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Edits to captions of TPCs 2, 3, and 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Edits to caption of TPC 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Added TPC 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

–8–

REV. B