Datasheet ADM8696AN, ADM8697ARW, ADM8697ARU, ADM8696ARW, ADM8696ARU Datasheet (Analog Devices)

Microprocessor

a

FEATURES
Upgrade for ADM696/ADM697, MAX696/MAX697
Specified Over Temperature
Adjustable Low Line Voltage Monitor
Power OK/Reset Time Delay
Reset Assertion Down to 1 V V
Watchdog Timer—100 ms, 1.6 s, or Adjustable
Low Switch On Resistance

0.7 V Normal, 7 V in Backup
400 nA Standby Current
Automatic Battery Backup Switching (ADM8696)
Fast On-Board Gating of Chip Enable Signals (ADM8697)
Voltage Monitor for Power Fail or Low Battery Warning
Also Available in TSSOP Package

APPLICATIONS
Microprocessor Systems
Computers
Controllers
Intelligent Instruments
Automotive Systems
Critical mP Power Monitoring

CC

V

BATT

V

CC

LL

OSC IN

OSC SEL

WATCHDOG

INPUT (WDI)

POWER FAIL

INPUT (PFI)

Supervisory Circuits

ADM8696/ADM8697

FUNCTIONAL BLOCK DIAGRAMS

BATT ON

IN

RESET GENERATOR

TIMEBASE FOR RESET

AND WATCHDOG

WATCHDOG

TRANSITION DETECTOR

1.3V

WATCHDOG

TIMER

ADM8696

V

OUT

LOW LINE

RESET

RESET

WATCHDOG
OUTPUT (WDO)

POWER FAIL
OUTPUT (PFO)

GENERAL DESCRIPTION

The ADM8696/ADM8697 supervisory circuits offer complete
single chip solutions for power supply monitoring and battery
control functions in microprocessor systems. These functions
include µP reset, backup battery switchover, watchdog timer,
CMOS RAM write protection and power failure warning.

The ADM8696/ADM8697 are available in 16-pin DIP and small
outline packages (including TSSOP) and provide the following
functions:

1. Power-On Reset output during power-up, power-down and
brownout conditions. The RESET voltage threshold is
adjustable using an external voltage divider. The
put remains operational with V

as low as 1 V.

CC

RESET out-

2. A Reset pulse if the optional watchdog timer has not been
toggled within specified time.

3. Separate watchdog timeout and low line status outputs.

4. Adjustable reset and watchdog timeout periods.

5. A 1.3 V threshold detector for power fail warning, low battery
detection or to monitor a power supply other than VCC.

6. Battery backup switching for CMOS RAM, CMOS micro­processor or other low power logic (ADM8696).

7. Write protection of CMOS RAM or EEPROM (ADM8697).

CE

LL

OSC IN

OSC SEL

WATCHDOG

INPUT (WDI)

POWER FAIL

INPUT (PFI)

IN

IN

RESET GENERATOR

TIMEBASE FOR RESET

AND WATCHDOG

WATCHDOG

TIMER

WATCHDOG

TRANSITION DETECTOR

ADM8697

1.3V

CE

OUT

LOW LINE

RESET

RESET

WATCHDOG
OUTPUT (WDO)

POWER FAIL
OUTPUT (PFO)

The ADM8696/ADM8697 is fabricated using an advanced
epitaxial CMOS process combining low power consumption
(0.7 mW), extremely fast Chip Enable gating (2 ns) and high re­liability.

RESET assertion is guaranteed with VCC as low as 1 V.
In addition, the power switching circuitry is designed for mini­mal voltage drop thereby permitting increased output current drive
of up to 100 mA without the need for an external pass transistor.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1997

ADM8696/ADM8697–SPECIFICATIONS

P

arameter Min Typ Max Units Test Conditions/Comments

unless otherwise noted.)

(VCC = Full Operating Range, V

= +2.8 V, TA = T

BATT

VCC Operating Voltage Range 3.0 5.5 V
V

Operating Voltage Range 2.0 VCC – 0 3 V

BATT

BATTERY BACKUP SWITCHING (ADM8696)

V

Output Voltage VCC – 0.005 VCC – 0.0025 V I

OUT

VCC – 0.2 VCC – 0.125 V I

V

in Battery Backup Mode V

OUT

Supply Current (Excludes I

) 115 200 µAI

OUT

– 0.005 V

BATT

– 0.002 V I

BATT

Supply Current in Battery Backup Mode 0.4 1 µAVCC = 0 V, V
Battery Standby Current 5.5 V > VCC > V

= 1 mA

OUT

≤ 100 mA

OUT

= 250 µA, VCC < V

OUT

= 100 mA

OUT

BATT

= 2.8 V

+ 0.2 V

BATT

BATT

(+ = Discharge, – = Charge) –0.1 +0.02 µA
Battery Switchover Threshold 70 mV Power-Up
VCC – V

BATT

50 mV Power-Down
Battery Switchover Hysteresis 20 mV
BATT ON Output Voltage 0.3 V I
BATT ON Output Short Circuit Current 30 mA BATT ON = V

0.5 2.5 25 µA BATT ON = V

= 3.2 mA

SINK

= 2.4 V Sink Current

OUT

, VCC = 0 V, Source Current

OUT

RESET AND WATCHDOG TIMER

Low Line Threshold (LLIN) 1.25 1.3 1.35 V
Reset Timeout Delay 35 50 70 ms OSC SEL = HIGH
Watchdog Timeout Period, Internal Oscillator 1.0 1.6 2.25 s Long Period

70 100 140 ms Short Period

Watchdog Timeout Period, External Clock 4032 4063 4097 Cycles Long Period

960 1011 1025 Cycles Short Period

Minimum WDI Input Pulse Width 50 ns VIL = 0.8, VIH = 3.75 V, VCC = 5 V

100 ns VIL = 0.8, VIH = 3.5 V, VCC = 5 V

100 ns VIL = 0.8, VIH = 2.6 V, VCC = 3 V
RESET Output Voltage @ VCC = +1 V 4 20 mV I
RESET, RESET Output Voltage 0.1 0.4 V I

0.1 0.4 V I

3.5 V I

2.7 V I

LOW LINE, WDO Output Voltage 0.4 V I

3.5 V I

2.7 V I
Output Short Circuit Source Current 1 10 25 µAVCC = 5 V
WDI Input Threshold

1

= 10 µA, VCC = 1 V

SINK

= 400 µA, VCC = 2 V, V

SINK

= 3.2 mA, 3 V < VCC < 5.5 V

SINK

= 1 µA, VCC = 5 V

SOURCE

= 1 µA, VCC = 3 V

SOURCE

= 3.2 mA,

SINK

= 1 µA, VCC = 5 V

SOURCE

= 1 µA, VCC = 3 V

SOURCE

Logic Low 0.8 V
Logic High 3.5 V VCC = 5 V

1.2 V VCC = 3 V
WDI Input Current 1 10 µA WD1 = V

OUT

, (VCC)

–10 –1 µA WD1 = 0 V

POWER FAIL DETECTOR

PFI Input Threshold 1.2 1.3 1.4 V
PFI–LLIN Threshold Difference –50 ±15 +50 mV
PFI Input Current –25 ±0.01 +25 nA
LLIN Input Current –50 ±0.01 +50 nA
PFO Output Voltage 0.4 V I

3.5 V I

2.7 V I

= 3.2 mA

SINK

= 1 µA

SOURCE

= 1 µA, VCC = 3 V

SOURCE

PFO Short Circuit Source Current 1 10 25 µA PFI = Low, PFO = 0 V

CHIP ENABLE GATING (ADM8697)

CE

Threshold 0.8 V V

IN

3.0 V V

IL
IH

1.2 V VCC = 3 V

CE

Pull-Up Current 3 µA

IN

CE

Output Voltage 0.4 V I

OUT

VCC – 0.5 V I

= 3.2 mA

SINK
SOURCE

= 800 µA

CE Propagation Delay 2 7 ns VCC = 5.0 V

4nsV

= 3.0 V

CC

OSCILLATOR

OSC IN Input Current ±2 µA
OSC SEL Input Pull-Up Current 5 µA
OSC IN Frequency Range 0 500 kHz OSC SEL = 0 V

OSC IN Frequency with Ext. Capacitor 4 kHz OSC SEL = 0 V, C

NOTE

1

WDI is a three-level input internally biased to 38% of VCC and has an input impedance of approximately 5 MΩ.

= 47 pF

OSC

Specifications subject to change without notice.

–2–

MIN

– 0.2 V

= 0 V

BATT

to T

MAX

REV. 0

ADM8696/ADM8697

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

(TA = +25°C unless otherwise noted)

VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

V

All Other Inputs . . . . . . . . . . . . . . . . . . –0.3 V to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

BATT

OUT

+ 0.5 V

Input Current

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA

CC

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

BATT

GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Power Dissipation, N-16 DIP . . . . . . . . . . . . . . . . . . .600 mW

θ

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 135°C/W

JA

Power Dissipation, R-16 SOIC . . . . . . . . . . . . . . . . . .600 mW

θ

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 110°C/W

JA

Operating Temperature Range

Industrial (A Version) . . . . . . . . . . . . . . . . .–40°C to +85°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum ratings for
extended periods of time may affect device reliability.

Power Dissipation, RU-16 TSSOP . . . . . . . . . . . . . . .500 mW

θ

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 158°C/W

JA

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADM8696/ADM8697 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.

ORDERING GUIDE

PIN CONFIGURATIONS

Package

Model Temperature Range Option*

1

V

ADM8696AN –40°C to +85°C N-16
ADM8696ARW –40°C to +85°C R-16
ADM8696ARU –40°C to +85°C RU-16

ADM8697AN –40°C to +85°C N-16
ADM8697ARW –40°C to +85°C R-16
ADM8697ARU –40°C to +85°C RU-16

*N = Plastic DIP; R = Small Outline (Wide Body); RU = Thin Shrink Small

Outline (TSSOP).

BATT

V

OUT

V

GND

BATT ON

LOW LINE

OSC IN

OSC SEL

CC

2

3

ADM8696

4

(Not to Scale)

5
6

7

8

TOP VIEW

16

15
14

13

12

11

10

9

RESET

RESET

WDO
LL

IN

NC

WDI

PFO

PFI

REV. 0

–3–

TEST

V
LL

GND

LOW LINE

OSC IN

OSC SEL

NC

CC

IN

1

2

3

ADM8697

4

TOP VIEW

(Not to Scale)

5

6

7

8

16

RESET

15

RESET

14

WDO

13

CE

IN

12

CE

OUT

11

WDI

10

PFO

9

PFI

ADM8696/ADM8697

Pin No.

Mnemonic ADM8696 ADM8697 Function

PIN FUNCTION DESCRIPTION

V
V
V

CC
BATT
OUT

3 3 Power Supply Input +3 V to +5 V.
1 — Backup Battery Input.
2 — Output Voltage, VCC or V

the highest potential. When V
threshold, V
reset threshold, V
RAM. Connect V

is switched to V

CC

is switched to V

BATT

to VCC if V

OUT

is internally switched to V

BATT

is higher than V

CC

. When VCC is lower than V

OUT

OUT

OUT

and V

depending on which is at

OUT

and LLIN is higher than the reset

BATT

. V

can supply up to 100 mA to power CMOS

OUT

are not used.

BATT

and LLIN is below the

BATT

GND 4 5 0 V. Ground reference for all signals.
RESET 15 15 Logic Output. RESET goes low whenever LLIN falls below 1.3 V and remains low for 50 ms

after LL
abled but not serviced within its timeout period. The

goes above 1.3 V. RESET also goes low for 50 ms if the watchdog timer is en-

IN

RESET pulse width can be adjusted as

shown in Table I.

WDI 11 11 Watchdog Input, WDI is a three level input. If WDI remains either high or low for longer

than the watchdog timeout period,

RESET pulses low and WDO goes low. The timer resets
with each transition at the WDI input. The watchdog timer is disabled when WDI is left
floating or is driven to midsupply.

PFI 9 9 Power Fail Input. PFI is the noninverting input to the Power Fail Comparator when PFI is

less than 1.3 V,

PFO goes low. Connect PFI to GND or V

OUT

when not used. See Figure 1.

PFO 10 10 Power Fail Output. PFO is the output of the Power Fail Comparator. It goes low when PFI

is less than 1.3 V. The comparator is turned off and
V

.

BATT

CE

CE

IN
OUT

— 13 Logic Input. The input to the CE gating circuit. Connect to GND or V
— 12 Logic Output. CE

is above 1.3 V. If LLIN is below 1.3 V, CE

is a gated version of the CEIN signal. CE

OUT

OUT

BATT ON 5 — Logic Output. BATT ON goes high when V

It goes low when V

is internally switched to VCC. The output typically sinks 7 mA and

OUT

OUT

PFO goes low when VCC is below

OUT

tracks CEIN when LL

OUT

is forced high.

is internally switched to the V

if not used.

input.

BATT

IN

can directly drive the base of an external PNP transistor to increase the output current above
the 100 mA rating of V

OUT

.

LOW LINE 6 6 Logic Output. LOW LINE goes low when LLIN falls below 1.3 V. It returns high as soon as

LL

rises above 1.3 V.

IN

RESET 16 16 Logic Output. RESET is an active high output. It is the inverse of

RESET.

OSC SEL 8 8 Logic Oscillator Select Input. When OSC SEL is unconnected or driven high, the internal

oscillator sets the reset time delay and watchdog timeout period. When OSC SEL is low, the
external oscillator input, OSC IN, is enabled. OSC SEL has a 3 µA internal pull-up. See
Table I and Figure 4.

OSC IN 7 7 Logic Oscillator Input. When OSC SEL is low, OSC IN can be driven by an external clock

to adjust both the reset delay and the watchdog timeout period. The timing can also be
adjusted by connecting an external capacitor to this pin. See Table I and Figure 4. When
OSC SEL is high or floating, OSC IN selects between fast and slow watchdog timeout periods.

WDO 14 14 Logic Output. The Watchdog Output, WDO, goes low if WDI remains either high or low

for longer than the watchdog timeout period.
WDI. If WDI is unconnected or at midsupply,
when

LOW LINE goes low.

WDO is set high by the next transition at

WDO remains high. WDO also goes high

NC 12 2 No Connect. It should be left open.
LL

IN

13 4 Voltage Sensing Input. The voltage on the low line input, LLIN, is compared with a 1.3 V

reference voltage. This input is normally used to monitor the power supply voltage. The
output of the comparator generates a
RESET/

RESET output. The comparator output also controls the battery switchover circuitry.

LOW LINE output signal. It also generates a

TEST — 1 This is a special test pin using during device manufacture. It should be connected to GND.

–4–

REV. 0

ADM8696/ADM8697

t

1

t

1

= RESET TIME
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2–V1

V2

V2

V1

V1

t

1

LL

IN

LOW LINE

RESET

CIRCUIT INFORMATION
Battery Switchover Section (ADM8696)

The battery switchover circuit is designed to switch over to
battery backup in the event of a power failure. When LL
is below the reset threshold and VCC is below V
V

is switched to V

BATT

During normal operation, with V
internally switched to V

.

OUT

higher than V

CC

via an internal PMOS transistor

OUT

BATT

BATT

switch. This switch has a typical on resistance of 0.7 Ω and can
supply up to 100 mA at the V

terminal. V

OUT

is normally

OUT

used to drive a RAM memory bank which may require instanta­neous currents of greater than 100 mA. If this is the case, then
a bypass capacitor should be connected to V

. The capacitor

OUT

will provide the peak current transients to the RAM. A capaci­tance value of 0.1 µF or greater may be used.

If the continuous output current requirement at V
100 mA or if a lower V

CC–VOUT

voltage differential is desired,

OUT

an external PNP pass transistor may be connected in parallel
with the internal transistor. The BATT ON output can directly
drive the base of the external transistor.

A 7 Ω MOSFET switch connects the V

input to V

BATT

ing battery backup. This MOSFET has very low input-to-out­put differential (dropout voltage) at the low current levels
required for battery backup of CMOS RAM or other low power
CMOS circuitry. The supply current in battery backup is typi­cally 0.4 µA.

The ADM8696 operates with battery voltages from 2.0 V to
V

–0.3 V). High value capacitors, either standard electrolytic

CC

or the farad-size double layer capacitors, can also be used for
short-term memory backup. A small charging current of typi­cally 10 nA (0.1 µA max) flows out of the V

terminal. This

BATT

current is useful for maintaining rechargeable batteries in a fully
charged condition. This extends the life of the backup battery
by compensating for its self-discharge current. Also note that
this current poses no problem when lithium batteries are used
for backup since the maximum charging current (0.1 µA) is safe
for even the smallest lithium cells.

If the battery switchover section is not used, V
connected to GND and V

V

CC

V

BATT

700

mV

GATE DRIVE

100
mV

should be connected to VCC.

OUT

INTERNAL
SHUTDOWN SIGNAL
WHEN
V

BATT

> (VCC + 0.7V)

should be

BATT

V

OUT

BATT ON
(ADM8691, ADM8693,
ADM8695, ADM8696)

Figure 1. Battery Switchover Schematic

IN

, then

, VCC is

exceeds

dur-

OUT

Low Line RESET OUTPUT

RESET is an active low output that provides a RESET signal to
the microprocessor whenever the Low Line Input (LL
low 1.3 V. The LL
power supply voltage. An internal timer holds
50 ms after the voltage on LL
tended as a power-on

input is normally used to monitor the

IN

RESET low for

rises above 1.3 V. This is in-

IN

RESET signal for the processor. It allows

) is be-

IN

time for the power supply and microprocessor to stabilize. On
power-down, the

RESET output remains low, with VCC as low
as 1 V. This ensures that the microprocessor is held in a stable
shutdown condition.

The LL

comparator has approximately 12 mV of hysteresis

IN

for enhanced noise immunity.
In addition to

available. This is the complement of

RESET, an active high RESET output is also

RESET and is useful for

processors requiring an active high RESET.

Figure 2. Power-Fail Reset Timing

Watchdog Timer RESET

The watchdog timer circuit monitors the activity of the micro­processor in order to check that it is not stalled in an indefinite
loop. An output line on the processor is used to toggle the
Watchdog Input (WDI) line. If this line is not toggled within
the selected timeout period, a

RESET pulse is generated. The
ADM8696/ADM8697 may be configured for either a fixed
“short” 100 ms or a “long” 1.6 second timeout period or for an
adjustable timeout period. If the “short” period is selected,
some systems may be unable to service the watchdog timer im­mediately after a reset, so a “long” timeout is automatically ini­tiated directly after a reset is issued. The watchdog timer is
restarted at the end of Reset, whether the Reset was caused by
lack of activity on WDI or by LL

falling below the reset

IN

threshold.
The normal (short) timeout period becomes effective following

the first transition of WDI after

RESET has gone inactive. The
watchdog timeout period restarts with each transition on the
WDI pin. To ensure that the watchdog timer does not time out,
either a high-to-low or low-to-high transition on the WDI pin
must occur at or less than the minimum timeout period. If WDI
remains permanently either high or low, reset pulses will be is­sued after each timeout period (1.6 s). The watchdog monitor
can be deactivated by floating the Watchdog Input (WDI) or by
connecting it to midsupply.

REV. 0

–5–

ADM8696/ADM8697

Table I. ADM8696, ADM8697 Reset Pulse Width and Watchdog Timeout Selections

Watchdog Timeout Period Reset Active Period

OSC SEL OSC IN Normal Immediately After Reset

Low External Clock Input 1024 CLKS 4096 CLKS 512 CLKS Low External Capacitor 400 ms × C/47 pF 1.6 s × C/47 pF 200 ms × C/47 pF Floating or High Low 100 ms 1.6 s 50 ms Floating or High Floating or High 1.6 s 1.6 s 50 ms

NOTE
With the OSC SEL pin low, OSC IN can be driven by an external clock signal, or an external capacitor can be connected between OSC IN and GND. The nominal
internal oscillator frequency is 10.24 kHz. The nominal oscillator frequency with external capacitor is: F

(Hz) = 184,000/C (pF).

OSC

WDI

WDO

t

2

RESET

t

t

= RESET TIME

1

t

= NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD

2

t

= WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESET

3

1

t

1

t

3

t

1

Figure 3. Watchdog Timeout Period and Reset Active Time

The watchdog timeout period defaults to 1.6 s and the reset
pulse width defaults to 50 ms, but these times to be adjusted as
shown in Table I. Figure 4 shows the various oscillator configu­rations that can be used to adjust the reset pulse width and
watchdog timeout period.

The internal oscillator is enabled when OSC SEL is high or
floating. In this mode, OSC IN selects between the 1.6 second
and 100 ms watchdog timeout periods. In either case, immedi­ately after a reset the timeout period is 1.6 s. This gives the mi­croprocessor time to reinitialize the system. If OSC IN is low,
the 100 ms watchdog period becomes effective after the first
transition of WDI. The software should be written such that the
I/O port driving WDI is left in its power-up reset state until the
initialization routines are completed and the microprocessor is
able to toggle WDI at the minimum watchdog timeout period of
70 ms.

8

OSC SEL

ADM869x

7

C

OSC

OSC IN

Figure 4b. External Capacitor

NC

NC

8

7

OSC IN

OSC SEL

ADM869x

Figure 4c. Internal Oscillator (1.6 s Watchdog)

NC

8

7

OSC SEL

ADM869x

OSC IN

Figure 4d. Internal Oscillator (100 ms Watchdog)

Watchdog Output (WDO)

The Watchdog Output WDO provides a status output that goes
low if the watchdog timer “times out” and remains low until set
high by the next transition on the watchdog input.
set high when LL

goes below the reset threshold.

IN

WDO is also

8

OSC SEL

CLOCK

0 TO 500kHz

7

OSC IN

Figure 4a. External Clock Source

ADM869x

–6–

REV. 0

ADM8696/ADM8697

CE Gating and RAM Write Protection (ADM8697)

The ADM8697 contains memory protection circuitry that
ensures the integrity of data in memory by preventing write
operations when LL
LL

is greater than 1.3 V, CE

IN

with a 2 ns propagation delay. When LL
threshold, an internal gate forces

CE

.

IN

CE

typically drives the CE, CS or Write input of battery

OUT

is below the threshold voltage. When

IN

is a buffered replica of CEIN,

OUT

CE

falls below the 1.3 V

IN

high, independent of

OUT

backed up CMOS RAM. This ensures the integrity of the data
in memory by preventing write operations when V

is at an in-

CC

valid level.

ADM8697

CE

IN

LL

LOW = 0

IN

LLIN OK = 1

CE

OUT

Figure 5. Chip Enable Gating

LL

RESET

LOW LINE

CE

CE

OUT

IN

IN

V2 V2

t

1

t

= RESET TIME

1

V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2–V1

V1

V1

t

1

Figure 6. Chip Enable Timing

Power Fail Warning Comparator

An additional comparator is provided for early warning of fail­ure in the microprocessor’s power supply. The Power Fail Input
(PFI) is compared to an internal +1.3 V reference. The Power

Fail Output (

PFO) goes low when the voltage at PFI is less than

1.3 V. Typically PFI is driven by an external voltage divider
which senses either the unregulated dc input to the system’s 5 V
regulator or the regulated 5 V output. The voltage divider ratio

can be chosen such that the voltage at PFI falls below 1.3 V
several milliseconds before the +5 V power supply falls below
the reset threshold.

PFO is normally used to interrupt the
microprocessor so that data can be stored in RAM and the shut­down procedure executed before power is lost.

INPUT

POWER

R1

POWER

R2

FAIL

INPUT

ADM869x

1.3V

PFO

POWER
FAIL
OUTPUT

Figure 7. Power Fail Comparator

Table II. Input and Output Status In Battery Backup Mode

Signal Status

V

OUT

(ADM8696) V

is connected to V

OUT

BATT

via an

internal PMOS switch.
RESET Logic low.
RESET Logic high. The open circuit output voltage is

equal to V

OUT

.
LOW LINE Logic low.
BATT ON (ADM8696) Logic high. The open circuit volt-

age is equal to V

OUT

.

WDI WDI is ignored. It is internally disconnected

from the internal pull-up resistor and does not
source or sink current as long as its input voltage
is between GND and V

. The input voltage

OUT

does not affect supply current.

WDO Logic high. The open circuit voltage is equal to

V

.

OUT

PFI The Power Fail Comparator is turned off and

has no effect on the Power Fail Output.

PFO Logic low.

CE

IN

CE

is ignored. It is internally disconnected

IN

from its internal pull-up and does not source or
sink current as long as its input voltage is be­tween GND and V

. The input voltage does

OUT

not affect supply current.

CE

OUT

Logic high. The open circuit voltage is equal to
V

.

OUT

OSC IN OSC IN is ignored.
OSC SEL OSC SEL is ignored.

REV. 0

–7–

ADM8696/ADM8697–T ypical Performance Curves

5

4.99

4.98

– Volts

4.97

OUT

V

4.96

4.95

4.94
10 10020 30 40 50 60 70 80 90

Figure 8. V

2.8

2.798

2.796

2.794

– Volts

2.792

OUT

V

2.79

OUT

vs. I

I

– mA

OUT

Normal Operation

OUT

53

VCC = +5V

52

51

RESET ACTIVE TIME – ms

50

49

20 120

40

TEMPERATURE –

1008060

°

C

Figure 11. RESET Active Time vs. Temperature

A4 3.36 V

100

90

2.788

2.786
150 1050250 350 450 550 650 750 850 950

Figure 9. V

1.32

1.31

1.30

PFI INPUT THRESHOLD – V

1.29
20 120

OUT

40

I

– µA

OUT

vs. I

TEMPERATURE – °C

Battery Backup

OUT

1008060

Figure 10. PFI Input Threshold vs. Temperature

10

0%

1V

Figure 12.

5.5

5.0

4.5

4.0

– Volts

3.5

CC

V

3.0

2.5

2.0
10 100 100001000

Figure 13.

1V

RESET

Output Voltage vs. Supply Voltage

RESET

500ms

TA = +25°C

TIME DELAY – ms

Timeout Delay vs. V

CC

REV. 0–8–

ADM8696/ADM8697

ADM869x

R2

1.3V

R1

PFO

7805

R4

R3

+7V TO +15V

INPUT

POWER

+5V

PFI

V

CC

TO
µP NMI

V

H

= 1.3V (1+ ––– + ––– )

V

L

= 1.3V (1+ ––– – ––––––––––––– )

ASSUMING R

4

< < R

3

THEN

HYSTERESIS VH – V

L

= 5V (––– )

R

1

R

2

R

1

R

3

R

1

R

2

R

1

R

2

R1 (5V – 1.3V)

1.3V (R

3 + R4

)

WDI

ADM869x

WATCHDOG

STROBE

CONTROL

INPUT

APPLICATIONS INFORMATION
Increasing the Drive Current (ADM8696)

If the continuous output current requirements at V
100 mA or if a lower V

CC–VOUT

voltage differential is desired,

OUT

exceeds

an external PNP pass transistor may be connected in parallel
with the internal transistor. The BATT ON output (ADM8696)
can directly drive the base of the external transistor.

+5V

INPUT

POWER

BATTERY

0.1µF

V

BATT

TRANSISTOR

V

CC

ADM8696

PNP

BATT

ON

0.1µF

V

OUT

Figure 14. Increasing the Drive Current

Using a Rechargeable Battery for Backup (ADM8696)

If a capacitor or a rechargeable battery is used for backup, the
charging resistor should be connected to V

since this elimi-

OUT

nates the discharge path that would exist during power-down if
the resistor is connected to V

+5V

INPUT

POWER

0.1µF

RECHARGABLE

BATTERY

V

CC

V

BATT

.

V

OUT

I =

CC

ADM8696

– V

R

BATT

R

0.1µF

V

OUT

This circuit is not entirely foolproof and it is possible a software
fault could erroneously three-state the buffer. This would pre­vent the ADM869x from detecting that the microprocessor is no
longer operating correctly. In most cases, a better method is to

Figure 16. Adding Hysteresis to the Power Fail Comparator

extend the watchdog period rather than disabling the watchdog.
This may be done under program control using the circuit
shown in Figure 17b. When the control input is high, the OSC
SEL pin is low and the watchdog timeout is set by the external
capacitor. A 0.01 µF capacitor sets a watchdog timeout delay of
100 s. When the control input is low, the OSC SEL pin is
driven high, selecting the internal oscillator. The 100 ms or the

1.6 s period is chosen, depending on which diode in Fig­ure 17b is used. With D1 inserted, the internal timeout is set at
100 ms while with D2 inserted the timeout is set at 1.6 s.

Figure 15. Rechargeable Battery

Adding Hysteresis to the Power Fail Comparator

For increased noise immunity, hysteresis may be added to the
power fail comparator. Since the comparator circuit is nonin­verting, hysteresis can be added by connecting a resistor be­tween the PFO output and the PFI input as shown in Fig­ure 16. When PFO is low, resistor R3 sinks current from the
summing junction at the PFI pin. When PFO is high, the series
combination of R3 and R4 source current into the PFI summing
junction. This results in differing trip levels for the comparator.

Alternate Watchdog Input Drive Circuits

The watchdog feature can be enabled and disabled under pro­gram control by driving WDI with a three-state buffer (Figure
17a). When three-stated, the WDI input will float, thereby dis­abling the watchdog timer.

REV. 0

–9–

Figure 17a. Programming the Watchdog Input

CONTROL

INPUT*

D1 D2

OSC SEL

ADM869x

OSC IN

*LOW = INTERNAL TIMEOUT
HIGH = EXTERNAL TIMEOUT

Figure 17b. Programming the Watchdog Input

ADM8696/ADM8697

TYPICAL APPLICATIONS
ADM8696

Figure 18 shows the ADM8696 in a typical power monitoring,
battery backup application. V
Under normal operating conditions with V
internally connected to V
decay and V

will be switched to V

OUT

CC

powers the CMOS RAM.

OUT

present, V

CC

OUT

is

. If a power failure occurs, VCC will

, thereby maintaining

BATT

power for the CMOS RAM.

Power Fail RESET

The VCC power supply is also monitored by the Low Line In­put, LL

1.3 V.

. A RESET pulse is generated when LLIN falls below

IN

RESET will remain low for 50 ms after LLIN returns
above 1.3 V. This allows for a power-on reset and prevents re­peated toggling of
Resistors R3 and R4 should be chosen to give the desired V

RESET if the VCC power supply is unstable.

CC

reset threshold.

Watchdog Timer

The Watchdog Timer Input (WDI) monitors an I/O line from
the µP system. This line must be toggled once every 1.6 s to
verify correct software execution. Failure to toggle the line indi­cates that the µP system is not correctly executing its program
and may be tied up in an endless loop. If this happens, a reset
pulse is generated to initialize the processor.

If the watchdog timer is not needed the WDI input should be
left floating.

Power Fail Detector

The Power Fail Input, PFI, monitors the input power supply via
a resistive divider network R1 and R2. This input is intended as
an early warning power fail input. The voltage on the PFI input
is compared with a precision 1.3 V internal reference. If the in­put voltage drops below 1.3 V, a power fail output (PFO) signal
is generated. This warns of an impending power failure and may
be used to interrupt the processor so that the system may be
shut down in an orderly fashion. The resistors in the sensing
network are ratioed to give the desired power fail threshold volt­age V

. The threshold should be set at a higher voltage than the

T

RESET threshold so there is sufficient time available to com­plete the shutdown procedure before the processor is RESET
and power is lost.

+5V

R1

RESET

R3

R4

BATTERY

V

CC

IN

ADM8696

RESET

BATT

GND

V

OUT

PFO

WDI

PFI

LL

R2

V

+

µP POWER

CMOS RAM
POWER

µP SYSTEM

µP RESET
µP NMI

I/O LINE

Figure 18b shows a similar application for the ADM8696 but in
this case the PFI input monitors the unregulated input to the
7805 voltage regulator. This gives an earlier warning of an im­pending power failure. It is useful with processors operating at
low speeds or where there are a significant number of house­keeping tasks to be completed before the power is lost.

INPUT

POWER

7805

0.1µF

BATT

V

CC

V

ON

BATT

3V

R1

BATTERY

0.1µF

V

OUT

V

CC

CMOS RAM

ADM8696

PFI

NC

RESET

GND

OSC IN
OSC SEL

LL

IN

LOW LINE

SYSTEM STATUS

INDICATORS

WDI

PFO

RESET

WDO

R2

R3

R4

A0–A15
I/O LINE
NMI
RESET

µP

POWER

µP

Figure 18b. ADM8696 Typical Application Circuit B

This application also shows an optional external transistor that
may be used to provide in excess of 100 mA current on V
When V

is higher than V

CC

, the BATT ON output goes

BATT

OUT

.

low, providing 25 mA of base drive for the external PNP transis­tor. The maximum current available is dependent on the power
rating of the external transistor.

RAM Write Protection

The ADM8697 CE
CMOS RAM.

CE

reset threshold. If LL

line drives the Chip Select inputs of the

OUT

follows CEIN as long as LLIN is above the

OUT

falls below the reset threshold, CE

IN

OUT

goes high, independent of the logic level at CEIN. This prevents
the microprocessor from writing erroneous data into RAM dur­ing power-up, power-down, brownouts and momentary power
interruptions.

Figure 18a. ADM8696 Typical Application Circuit A

–10–

REV. 0

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

16-Pin Plastic DIP (N-16)

0.840 (21.33)

0.745 (18.93)

0.210 (5.33)
MAX

0.200 (5.05)

0.125 (3.18)

16

18

PIN 1

0.022 (0.558)

0.014 (0.356)

0.100
(2.54)

BSC

9

0.280 (7.11)

0.240 (6.10)

0.060 (1.52)

0.015 (0.38)

0.150
(3.81)
MIN

0.070 (1.77)

0.045 (1.15)

SEATING
PLANE

0.325 (8.25)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

0.195 (4.95)

0.115 (2.93)

16-Lead Thin Shrink Small Outline Package (RU-16)

0.201 (5.10)

0.193 (4.90)

16 9

ADM8696/ADM8697

0.006 (0.15)

0.002 (0.05)

SEATING

PLANE

0.299
(7.60)

0.012
(0.3)

0.177 (4.50)

0.169 (4.30)

1

PIN 1

0.0256
(0.65)

BSC

0.0118 (0.30)

0.0075 (0.19)

8

0.256 (6.50)

0.246 (6.25)

0.0433
(1.10)
MAX

0.0079 (0.20)

0.0035 (0.090)

16-Lead Wide Body SOIC (R-16)

0.413 (10.50)

16 9

0.419

(10.65)

81

0.030

PIN 1

0.05 (1.27)
BSC

0.019
(0.49)

0.014
(2.65)

SEATING
PLANE

(0.75)

0.013
(0.32)

8°
0°

0.028 (0.70)

0.020 (0.50)

0.042
(1.07)

REV. 0

–11–

C2977–10–2/97

–12–

PRINTED IN U.S.A.