Datasheet ADM8691ARN, ADM8691AN, ADM8690ARN, ADM8690AN, ADM8695ARW Datasheet (Analog Devices)

REV. 0

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otherwise under any patent or patent rights of Analog Devices.

a

Microprocessor

Supervisory Circuits

ADM8690–ADM8695

FEATURES
Upgrade for ADM690/ADM695, MAX690–MAX695
Specified Over Temperature
Low Power Consumption (0.7 mW)
Precision Voltage Monitor
Reset Assertion Down to 1 V V

CC

Low Switch On-Resistance 0.7 V Normal,

7 V in Backup
High Current Drive (100 mA)
Watchdog Timer—100 ms, 1.6 s, or Adjustable
400 nA Standby Current
Automatic Battery Backup Power Switching
Extremely Fast Gating of Chip Enable Signals (3 ns)
Voltage Monitor for Power Fail
Available in TSSOP Package

APPLICATIONS
Microprocessor Systems
Computers
Controllers
Intelligent Instruments
Automotive Systems

FUNCTIONAL BLOCK DIAGRAMS

ADM8691
ADM8693
ADM8695

4.65V

1

RESET AND

WATCHDOG

TIMEBASE

RESET

GENERATOR

WATCHDOG

TRANSITION DETECTOR

WATCHDOG

TIMER

1.3V

V

OUT

CE

OUT

LOW LINE

RESET

RESET

WATCHDOG
OUTPUT (WDO)

POWER FAIL
OUTPUT (PFO)

V

BATT

V

CC

CE

IN

OSC IN

OSC SEL

WATCHDOG
INPUT (WDI)

POWER FAIL

INPUT (PFI)

BATT ON

1

VOLTAGE DETECTOR = 4.65V (ADM8691, ADM8695)

4.40V (ADM8693)

ADM8690
ADM8692
ADM8694

4.65V

1

V

OUT

RESET

POWER FAIL
OUTPUT (PFO)

V

BATT

V

CC

WATCHDOG
INPUT (WDI)

POWER FAIL

INPUT (PFI)

1

VOLTAGE DETECTOR = 4.65V (ADM8690, ADM8694)

4.40V (ADM8692)

2

RESET PULSE WIDTH = 50ms (AD8690, ADM8692)

200ms (ADM8694)

WATCHDOG

TRANSITION DETECTOR

(1.6s)

RESET

GENERATOR

2

1.3V

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1997

GENERAL DESCRIPTION

The ADM8690–ADM8695 family of supervisory circuits offers
complete single chip solutions for power supply monitoring and
battery control functions in microprocessor systems. These
functions include µP reset, backup battery switchover, watchdog
timer, CMOS RAM write protection and power failure warning.
The complete family provides a variety of configurations to sat­isfy most microprocessor system requirements.

The ADM8690, ADM8692 and ADM8694 are available in
8-pin DIP packages and provide:

1. Power-on reset output during power-up, power-down and
brownout conditions. The

RESET output remains opera-

tional with V

CC

as low as 1 V.

2. Battery backup switching for CMOS RAM, CMOS
microprocessor or other low power logic.

3. A reset pulse if the optional watchdog timer has not been
toggled within a specified time.

4. A 1.3 V threshold detector for power fail warning, low battery
detection or to monitor a power supply other than +5 V.

The ADM8691, ADM8693 and ADM8695 are available in
16-pin DIP and small outline packages (including TSSOP) and
provide three additional functions:

1. Write protection of CMOS RAM or EEPROM.

2. Adjustable reset and watchdog timeout periods.

3. Separate watchdog timeout, backup battery switchover, and
low V

CC

status outputs.

The ADM8690–ADM8695 family is fabricated using an ad­vanced epitaxial CMOS process combining low power con­sumption (0.7 mW), extremely fast Chip Enable gating (3 ns)
and high reliability.

RESET assertion is guaranteed with VCC as
low as 1 V. In addition, the power switching circuitry is de­signed for minimal voltage drop thereby permitting increased
output current drive of up to 100 mA without the need of an
external pass transistor.

ADM8690–ADM8695–SPECIFICA TIONS

Parameter Min Typ Max Units Test Conditions/Comments

BATTERY BACKUP SWITCHING

V

CC

Operating Voltage Range
ADM8690, ADM8691, ADM8694, ADM8695 4.75 5.5 V
ADM8692, ADM8693 4.5 5.5 V

V

BATT

Operating Voltage Range
ADM8690, ADM8691, ADM8694, ADM8695 2.0 4.25 V
ADM8692, ADM8693 2.0 4.0 V

V

OUT

Output Voltage VCC – 0.005 VCC – 0.0025 V I

OUT

= 1 mA

V

CC

– 0.2 VCC – 0.125 V I

OUT

≤ 100 mA

V

OUT

in Battery Backup Mode V

BATT

– 0.005 V

BATT

– 0.002 V I

OUT

= 250 µA, VCC < V

BATT

– 0.2 V

Supply Current (Excludes I

OUT

) 140 200 µAI

OUT

= 100 µA

Supply Current in Battery Backup Mode 0.4 1 µAV

CC

= 0 V, V

BATT

= 2.8 V

Battery Standby Current 5.5 V > V

CC

> V

BATT

+ 0.2 V

(+ = Discharge, – = Charge) –0.1 +0.02 µAT

A

= +25°C
Battery Switchover Threshold 70 mV Power-Up
V

CC

– V

BATT

50 mV Power-Down
Battery Switchover Hysteresis 20 mV
BATT ON Output Voltage 0.3 V I

SINK

= 3.2 mA

BATT ON Output Short Circuit Current 55 mA BATT ON = V

OUT

= 4.5 V Sink Current

0.5 2.5 25 µA BATT ON = 0 V Source Current

RESET AND WATCHDOG TIMER

Reset Voltage Threshold

ADM8690, ADM8691, ADM8694, ADM8695 4.5 4.65 4.73 V

ADM8692, ADM8693 4.25 4.4 4.48 V
Reset Threshold Hysteresis 40 mV
Reset Timeout Delay

ADM8690, ADM8691, ADM8692, ADM8693 35 50 70 ms OSC SEL = HIGH

ADM8694, ADM8695 140 200 280 ms OSC SEL = HIGH
Watchdog Timeout Period, Internal Oscillator 1.0 1.6 2.25 s Long Period

70 100 140 ms Short Period

Watchdog Timeout Period, External Clock 3840 4064 4097 Cycles Long Period

768 1011 1025 Cycles Short Period

Minimum WDI Input Pulse Width 50 ns V

IL

= 0.4, VIH = 3.5 V

RESET Output Voltage @ VCC = +1 V 4 20 mV I

SINK

= 10 µA, VCC = 1 V

RESET, LOW LINE Output Voltage 0.05 0.4 V I

SINK

= 1.6 mA, VCC = 4.25 V

3.5 V I

SOURCE

= 1 µA

RESET, WDO Output Voltage 0.4 V I

SINK

= 1.6 mA

3.5 V I

SOURCE

= 1 µA
Output Short Circuit Source Current 1 10 25 µA
Output Short Circuit Sink Current 25 mA
WDI Input Threshold Note 1

Logic Low 0.8 V
Logic High 3.5 V

WDI Input Current 1 10 µA WDI = V

OUT

–10 –1 µA WDI = 0 V

POWER FAIL DETECTOR

PFI Input Threshold 1.25 1.3 1.35 V V

CC

= +5 V
PFI Input Current –25 ±0.01 +25 nA
PFO Output Voltage 0.4 V I

SINK

= 3.2 mA

3.5 V I

SOURCE

= 1 µA

PFO Short Circuit Source Current 1 3 25 µA PFI = Low, PFO = 0 V
PFO Short Circuit Sink Current 25 mA PFI = High, PFO = V

OUT

CHIP ENABLE GATING

CE

IN

Threshold 0.8 V V

IL

3.0 V V

IH

CE

IN

Pull-Up Current 3 µA

CE

OUT

Output Voltage 0.4 V I

SINK

= 3.2 mA

V

OUT

– 1.5 V I

SOURCE

= 3.0 mA

V

OUT

– 0.05 V I

SOURCE

= 1 µA, VCC = 0 V

CE Propagation Delay 3 7 ns

REV. 0

–2–

(VCC = Full Operating Range, V

BATT

= +2.8 V, TA = T

MIN

to

T

MAX

unless otherwise noted)

Parameter Min Typ Max Units Test Conditions/Comments

OSCILLATOR

OSC IN Input Current ±2 µA
OSC SEL Input Pull-Up Current 5 µA
OSC IN Frequency Range 0 500 kHz OSC SEL = 0 V
OSC IN Frequency with External Capacitor 4 kHz OSC SEL = 0 V, C

OSC

= 47 pF

NOTE

1

WDI is a three level input which is internally biased to 38% of VCC and has an input impedance of approximately 5 MΩ.

Specifications subject to change without notice.

ADM8690–ADM8695

REV. 0

–3–

ABSOLUTE MAXIMUM RATINGS*

(TA = +25°C unless otherwise noted)

VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

V

BATT

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

All Other Inputs . . . . . . . . . . . . . . . . . . –0.3 V to V

OUT

+ 0.5 V

Input Current

V

CC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA

V

BATT

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Power Dissipation, N-8 DIP . . . . . . . . . . . . . . . . . . . .400 mW

θ

JA

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 120°C/W

Power Dissipation, N-16 DIP . . . . . . . . . . . . . . . . . . .600 mW

θ

JA

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 135°C/W

Power Dissipation, RU-16 DIP . . . . . . . . . . . . . . . . . . 600 mW

θ

JA

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 158°C/W

Power Dissipation, R-16 SOIC . . . . . . . . . . . . . . . . . .600 mW

θ

JA

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 110°C/W

Operating Temperature Range

Industrial (A Version) . . . . . . . . . . . . . . . . .–40°C to +85°C

Extended (S Version) . . . . . . . . . . . . . . . . .–55°C to +125°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum ratings for
extended periods of time may affect device reliability.

ORDERING GUIDE

Model Temperature Range Package Options*

ADM8690AN –40°C to +85°C N-8
ADM8690ARN –40°C to +85°C SO-8

ADM8691AN –40°C to +85°C N-16
ADM8691ARN –40°C to +85°C R-16A
ADM8691ARW –40°C to +85°C R-16
ADM8691ARU –40°C to +85°C RU-16

ADM8692AN –40°C to +85°C N-8
ADM8692ARN –40°C to +85°C SO-8

ADM8693AN –40°C to +85°C N-16
ADM8693ARN –40°C to +85°C R-16A
ADM8693ARW –40°C to +85°C R-16
ADM8693ARU –40°C to +85°C RU-16

ADM8694AN –40°C to +85°C N-8
ADM8694ARN –40°C to +85°C SO-8

ADM8695AN –40°C to +85°C N-16
ADM8695ARW –40°C to +85°C R-16

WARNING!

ESD SENSITIVE DEVICE

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADM8690–ADM8695 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.

*N = Plastic DIP; R = Small Outline (Wide); R = Small Outline (Narrow);

RU = Thin Shrink Small Outline; SO = Small Outline.

ADM8690–ADM8695

REV. 0

–4–

PIN FUNCTION DESCRIPTION

Mnemonic Function

V

CC

Power Supply Input: +5 V Nominal.

V

BATT

Backup Battery Input.

V

OUT

Output Voltage, VCC or V

BATT

is internally switched to V

OUT

depending on which is at the highest potential. V

OUT

can supply up to 100 mA to power CMOS RAM. Connect V

OUT

to VCC if V

OUT

and V

BATT

are not used.
GND 0 V. Ground reference for all signals.
RESET Logic Output. RESET goes low if

1. V

CC

falls below the Reset Threshold

2. The watchdog timer is not serviced within its timeout period.
The reset threshold is typically 4.65 V for the ADM8690/ADM8691/ADM8694/ADM8695 and 4.4 V for the ADM8692

and ADM8693.

RESET remains low for 50 ms (ADM8690/ADM8691/ADM8692/ADM8693) or 200 ms (ADM8694/

ADM8695) after V

CC

returns above the threshold. RESET also goes low for 50 (200) ms if the watchdog timer is

enabled but not serviced within its timeout period. The

RESET pulse width can be adjusted on the ADM8691/ADM8693/

ADM8695 as shown in Table I. The

RESET output has an internal 3 µA pull up, and can either connect

to an open collector Reset bus or directly drive a CMOS gate without an external pull-up resistor.

WDI Watchdog Input. WDI is a three level input. If WDI remains either high or low for longer than the watchdog timeout

period,

RESET pulses low and WDO goes low. The timer resets with each transition on the WDI line. The watchdog

timer may be disabled if WDI is left floating or is driven to midsupply.

PFI Power Fail Input. PFI is the noninverting input to the Power Fail Comparator when PFI is less than 1.3 V,

PFO

goes low. Connect PFI to GND or V

OUT

when not used.

PFO Power Fail Output. PFO is the output of the Power Fail Comparator. It goes low when PFI is less than 1.3 V. The

comparator is turned off and

PFO goes low when VCC is below V

BATT

.

CE

IN

Logic Input. The input to the CE gating circuit. Connect to GND or V

OUT

if not used.

CE

OUT

Logic Output. CE

OUT

is a gated version of the CEIN signal. CE

OUT

tracks CEIN when VCC is above the reset

threshold. If V

CC

is below the reset threshold, CE

OUT

is forced high. See Figures 5 and 6.

BATT ON Logic Output. BATT ON goes high when V

OUT

is internally switched to the V

BATT

input. It goes low when V

OUT

is internally switched to VCC. The output typically sinks 35 mA and can directly drive the base of an external
PNP transistor to increase the output current above the 100 mA rating of V

OUT

.

LOW LINE Logic Output. LOW LINE goes low when VCC falls below the reset threshold. It returns high as soon as VCC rises

above the reset threshold.

RESET Logic Output. RESET is an active high output. It is the inverse of

RESET.

OSC SEL Logic Oscillator Select Input. When OSC SEL is unconnected (floating) or driven high, the internal oscillator sets

the reset active time and watchdog timeout period. When OSC SEL is low, the external oscillator input, OSC IN,
is enabled. OSC SEL has a 3 µA internal pull-up (see Table I).

OSC IN Oscillator Logic Input. With OSC SEL low, OSC IN can be driven by an external clock signal or an external

capacitor can be connected between OSC IN and GND. This sets both the reset active pulse timing and the watch­dog timeout period (see Table I and Figure 4). With OSC SEL high or floating, the internal oscillator is enabled
and the reset active time is fixed at 50 ms typ. (ADM8691/ADM8693) or 200 ms typ (ADM8695). In this mode the
OSC IN pin selects between fast (100 ms) and slow (1.6 s) watchdog timeout periods. In both modes, the timeout
period immediately after a reset is 1.6 s typical.

WDO Logic Output. The Watchdog Output, WDO, goes low if WDI remains either high or low for longer than the

watchdog timeout period.

WDO is set high by the next transition at WDI. If WDI is unconnected or at midsupply,

the watchdog timer is disabled and WDO remains high. WDO also goes high when LOW LINE goes low.

ADM8690–ADM8695

REV. 0

–5–

PIN CONFIGURATIONS

1
2
3
4

8
7
6
5

TOP VIEW

(Not to Scale)

ADM8690
ADM8692
ADM8694

V

OUT

PFO

WDI

RESET

V

BATT

V

CC

GND

PFI

14
13
12
11

16
15

10

9

8

1
2
3
4

7

6

5

TOP VIEW

(Not to Scale)

ADM8691
ADM8693
ADM8695

V

BATT

CE

IN

WDO

RESET

RESET

V

OUT

V

CC

GND

PFO

WDI

CE

OUT

BATT ON

LOW LINE

OSC IN

OSC SEL

PFI

CIRCUIT INFORMATION
Battery Switchover Section

The battery switchover circuit compares VCC to the V

BATT

input, and connects V

OUT

to whichever is higher. Switchover

occurs when V

CC

is 50 mV higher than V

BATT

as VCC falls, and

when V

CC

is 70 mV greater than V

BATT

as VCC rises. This

20 mV of hysteresis prevents repeated rapid switching if V

CC

falls very slowly or remains nearly equal to the battery voltage.

V

CC

V

BATT

V

OUT

BATT ON
(ADM8690,
ADM8695)

100
mV

700
mV

INTERNAL
SHUTDOWN SIGNAL
WHEN
V

BATT

> (VCC + 0.7V)

GATE DRIVE

Figure 1. Battery Switchover Schematic

During normal operation, with VCC higher than V

BATT

, VCC is

internally switched to V

OUT

via an internal PMOS transistor
switch. This switch has a typical on-resistance of 0.7 Ω and can
supply up to 100 mA at the V

OUT

terminal. V

OUT

is normally
used to drive a RAM memory bank which may require instanta­neous currents of greater than 100 mA. If this is the case then a
bypass capacitor should be connected to V

OUT

. The capacitor
will provide the peak current transients to the RAM. A capaci­tance value of 0.1 µF or greater may be used.

If the continuous output current requirement at V

OUT

exceeds

100 mA, or if a lower V

CC–VOUT

voltage differential is desired,
an external PNP pass transistor may be connected in parallel with
the internal transistor. The BATT ON output (ADM8691/
ADM8693/ADM8695) can directly drive the base of the exter­nal transistor.

A 7 Ω MOSFET switch connects the V

BATT

input to V

OUT

dur­ing battery backup. This MOSFET has very low input-to-out­put differential (dropout voltage) at the low current levels
required for battery back up of CMOS RAM or other low power
CMOS circuitry. The supply current in battery back up is typi­cally 0.4 µA.

The ADM8690/ADM8691/ADM8694/ADM8695 operates with
battery voltages from 2.0 V to 4.25 V, and the ADM8692/
ADM8693 operates with battery voltages from 2.0 V to 4.0 V.
High value capacitors, either standard electrolytic or the farad
size double layer capacitors, can also be used for short-term
memory backup. A small charging current of typically 10 nA
(0.1 µA max) flows out of the V

BATT

terminal. This current is
useful for maintaining rechargeable batteries in a fully charged
condition. This extends the life of the backup battery by com­pensating for its self discharge current. Also note that this cur­rent poses no problem when lithium batteries are used for
backup since the maximum charging current (0.1 µA) is safe for
even the smallest lithium cells.

If the battery switchover section is not used, V

BATT

should be

connected to GND and V

OUT

should be connected to VCC.

PRODUCT SELECTION GUIDE

Part Nominal Reset Nominal V

CC

Nominal Watchdog Battery Backup Base Drive Chip Enable

Number Time Reset Threshold Timeout Period Switching Ext PNP Signals

ADM8690 50 ms 4.65 V 1.6 s Yes No No
ADM8691 50 ms or ADJ 4.65 V 100 ms, 1.6 s, ADJ Yes Yes Yes
ADM8692 50 ms 4.4 V 1.6 s Yes No No
ADM8693 50 ms or ADJ 4.4 V 100 ms, 1.6 s, ADJ Yes Yes Yes
ADM8694 200 ms 4.65 V 1.6 s Yes No No
ADM8695 200 ms or ADJ 4.65 V 100 ms, 1.6 s, ADJ Yes Yes Yes

ADM8690–ADM8695

REV. 0

–6–

Watchdog Timer RESET

The watchdog timer circuit monitors the activity of the micro­processor in order to check that it is not stalled in an indefinite
loop. An output line on the processor is used to toggle the
Watchdog Input (WDI) line. If this line is not toggled within the
selected timeout period, a

RESET pulse is generated. The
nominal watchdog timeout period is preset at 1.6 seconds on the
ADM8690/ADM8692/ADM8694. The ADM8691/ADM8693/
ADM8695 may be configured for either a fixed “short” 100 ms
or a “long” 1.6 second timeout period or for an adjustable
timeout period. If the “short” period is selected, some systems
may be unable to service the watchdog timer immediately after a
reset, so the ADM8691/ADM8693/ADM8695 automatically se­lects the “long” timeout period directly after a reset is issued.
The watchdog timer is restarted at the end of reset, whether the
reset was caused by lack of activity on WDI or by V

CC

falling be-

low the reset threshold.
The normal (short) timeout period becomes effective following

the first transition of WDI after

RESET has gone inactive. The
watchdog timeout period restarts with each transition on the
WDI pin. To ensure that the watchdog timer does not time out,
either a high-to-low or low-to-high transition on the WDI pin
must occur at or less than the minimum timeout period. If WDI
remains permanently either high or low, reset pulses will be
issued after each “long” (1.6 s) timeout period. The watchdog
monitor can be deactivated by floating the Watchdog Input
(WDI) or by connecting it to midsupply.

WDI

WDO

RESET

t

3

t

2

t

1

t

1

t

1

t

1

= RESET TIME

t

2

= NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD

t

3

= WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESET

Figure 3. Watchdog Timeout Period and Reset Active
Time

Power Fail RESET Output

RESET is an active low output that provides a RESET signal
to the Microprocessor whenever V

CC

is at an invalid level.

When V

CC

falls below the reset threshold, the RESET output
is forced low. The nominal reset voltage threshold is 4.65 V
(ADM8690/ADM8691/ADM8694/ADM8695) or 4.4 V
(ADM8692/ADM8693).

V

CC

RESET

LOW LINE

t

1

t

1

t

1

= RESET TIME
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2–V1

V1

V2V2

V1

Figure 2. Power Fail Reset Timing

On power-up, RESET will remain low for 50 ms (200 ms for
ADM8694 and ADM8695) after V

CC

rises above the appropri­ate reset threshold. This allows time for the power supply and
microprocessor to stabilize. On power-down, the

RESET out-

put remains low with V

CC

as low as 1 V. This ensures that the

microprocessor is held in a stable shutdown condition.
This

RESET active time is adjustable on the ADM8691/
ADM8693/ADM8695 by using an external oscillator or by
connecting an external capacitor to the OSC IN pin. Refer to
Table I and Figure 4.

The guaranteed minimum and maximum thresholds of the
ADM8690/ADM8691/ADM8694/ADM8695 are 4.5 V and

4.73 V, while the guaranteed thresholds of the ADM8692/
ADM8693 are 4.25 V and 4.48 V. The ADM8690/ADM8691/
ADM8694/ADM8695 is, therefore, compatible with 5 V sup­plies with a +10%, –5% tolerance while the ADM8692/
ADM8693 is compatible with 5 V ± 10% supplies. The reset
threshold comparator has approximately 50 mV of hysteresis.
The response time of the reset voltage comparator is less than 1
µs. If glitches are present on the V

CC

line which could cause

spurious reset pulses, then V

CC

should be decoupled close to

the device.
In addition to

RESET the ADM8691/ADM8693/ADM8695

contain an active high

RESET output. This is the complement

of

RESET and is intended for processors requiring an active

high RESET signal.

ADM8690–ADM8695

REV. 0

–7–

Table I. ADM8691, ADM8693, ADM8695 Reset Pulse Width and Watchdog Timeout Selections

Watchdog Timeout Period Reset Active Period

Immediately

OSC SEL OSC IN Normal After Reset ADM8691/ADM8693 ADM8695

Low External Clock Input 1024 CLKS 4096 CLKS 512 CLKS 2048 CLKS
Low External Capacitor 400 ms × C/47 pF 1.6 s × C/47 pF 200 ms × C/47 pF 520 ms × C/47 pF
Floating or High Low 100 ms 1.6 s 50 ms 200 ms
Floating or High Floating or High 1.6 s 1.6 s 50 ms 200 ms

NOTE
With the OSC SEL pin low, OSC IN can be driven by an external clock signal, or an external capacitor can be connected between OSC IN and GND. The nominal
internal oscillator frequency is 10.24 kHz. The nominal oscillator frequency with external capacitor is: F

OSC

(Hz) = 184,000/C (pF)

On the ADM8690/ADM8692 the watchdog timeout period is
fixed at 1.6 seconds and the reset pulse width is fixed at 50 ms.
On the ADM8694 the watchdog timeout period is also 1.6 sec­onds but the reset pulse width is fixed at 200 ms. The ADM8691/
ADM8693/ADM8695 allow these times to be adjusted as
shown in Table I. Figure 4 shows the various oscillator configu­rations that can be used to adjust the reset pulse width and
watchdog timeout period.

The internal oscillator is enabled when OSC SEL is high or
floating. In this mode, OSC IN selects between the 1.6 second
and 100 ms watchdog timeout periods. With OSC IN connected
high or floating, the 1.6 second timeout period is selected; while
with it connected low, the 100 ms timeout period is selected. In
either case, immediately after a reset the timeout period is 1.6
seconds. This gives the microprocessor time to reinitialize the
system. If OSC IN is low, then the 100 ms watchdog period be­comes effective after the first transition of WDI. The software
should be written such that the I/O port driving WDI is left in
its power-up reset state until the initialization routines are com­pleted and the microprocessor is able to toggle WDI at the mini­mum watchdog timeout period of 70 ms.

Watchdog Output (WDO)

The Watchdog Output WDO (ADM8691/ADM8693/
ADM8695) provides a status output which goes low if the
watchdog timer “times out” and remains low until set high by
the next transition on the Watchdog Input.

WDO is also set

high when V

CC

goes below the reset threshold.

8

7

CLOCK

0 TO 500kHz

OSC SEL

OSC IN

ADM8691
ADM8693
ADM8695

Figure 4a. External Clock Source

8

7

OSC SEL

OSC IN

ADM8691
ADM8693
ADM8695

C

OSC

Figure 4b. External Capacitor

8

7

NC

NC

OSC SEL

OSC IN

ADM8691

ADM8693

ADM8695

Figure 4c. Internal Oscillator (1.6 Second Watchdog)

8

7

OSC SEL

OSC IN

ADM8691
ADM8693
ADM8695

NC

Figure 4d. Internal Oscillator (100 ms Watchdog)

ADM8690–ADM8695

REV. 0

–8–

(PFI) is compared to an internal +1.3 V reference. The Power
Fail Output (

PFO) goes low when the voltage at PFI is less than

1.3 V. Typically PFI is driven by an external voltage divider that
senses either the unregulated dc input to the system’s 5 V regu­lator or the regulated 5 V output. The voltage divider ratio can
be chosen such that the voltage at PFI falls below 1.3 V several
milliseconds before the +5 V power supply falls below the reset
threshold.

PFO is normally used to interrupt the microprocessor
so that data can be stored in RAM and the shut down procedure
executed before power is lost

ADM869x

1.3V

POWER
FAIL
OUTPUT

POWER

FAIL

INPUT

PFO

R1

R2

INPUT

POWER

Figure 7. Power Fail Comparator

Table II. Input and Output Status In Battery Backup Mode

Signal Status

V

OUT

V

OUT

is connected to V

BATT

via an internal

PMOS switch.
RESET Logic low.
RESET Logic high. The open circuit output voltage is

equal to V

OUT

.
LOW LINE Logic low.
BATT ON Logic high. The open circuit voltage is equal to

V

OUT.

WDI WDI is ignored. It is internally disconnected

from the internal pull-up resistor and does not
source or sink current as long as its input voltage
is between GND and V

OUT

. The input voltage

does not affect supply current.

WDO Logic high. The open circuit voltage is equal

to V

OUT

.

PFI The Power Fail Comparator is turned off and

has no effect on the Power Fail Output.

PFO Logic low.

CE

IN

CE

IN

is ignored. It is internally disconnected
from its internal pull-up and does not source or
sink current as long as its input voltage is
between GND and V

OUT

. The input voltage

does not affect supply current.

CE

OUT

Logic high. The open circuit voltage is equal to
V

OUT

.

OSC IN OSC IN is ignored.
OSC SEL OSC SEL is ignored.

CE Gating and RAM Write Protection (ADM8691/ADM8693/
ADM8695)

The ADM8691/ADM8693/ADM8695 products include
memory protection circuitry which ensures the integrity of data
in memory by preventing write operations when V

CC

is at an in-

valid level. There are two additional pins,

CE

IN

and CE

OUT

,
which may be used to control the Chip Enable or Write inputs
of CMOS RAM. When V

CC

is present, CE

OUT

is a buffered rep-

lica of

CE

IN

, with a 3 ns propagation delay. When VCC falls be-

low the reset voltage threshold or V

BATT

, an internal gate forces

CE

OUT

high, independent of CEIN.

CE

OUT

typically drives the CE, CS or write input of battery
backed up CMOS RAM. This ensures the integrity of the data
in memory by preventing write operations when V

CC

is at an in­valid level. Similar protection of EEPROMs can be achieved by
using the

CE

OUT

to drive the store or write inputs.

ADM869x

CE

IN

CE

OUT

VCC LOW = 0
V

CC

OK = 1

Figure 5. Chip Enable Gating

V

CC

RESET

LOW LINE

t

1

t

1

t

1

= RESET TIME
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2–V1

V1

V2V2

V1

CE

IN

CE

OUT

Figure 6. Chip Enable Timing

Power Fail Warning Comparator

An additional comparator is provided for early warning of fail­ure in the microprocessor’s power supply. The Power Fail Input

T ypical Performance Curves–ADM8690–ADM8695

REV. 0

–9–

I

OUT

– mA

5.00

20 10040 60 80

V

OUT

– Volts

4.94
10 30 50 70 90

4.99

4.98

4.97

4.96

4.95

Figure 8. V

OUT

vs. I

OUT

Normal

Operation

TEMPERATURE – °C

1.315

1.295

1.28
–60 –30 120030 90

1.29

1.285

PFI INPUT THRESHOLD – Volts

60

1.31

1.305

1.3

Figure 11. PFI Input Threshold vs.
Temperature

TIME – µs

6

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

5

0

1.35

1.25

2
1

4
3

VCC = 5V
T

A

= +25°C

PFO

V

PFI

1.3V

30pF

Figure 14. Power Fail Comparator
Response Time

I

OUT

– µA

2.8

1050

2.786
150 250 350 450 550 650 750 850 950

2.798

2.794

2.792

2.79

2.788

2.796

V

OUT

– Volts

Figure 9. V

OUT

vs. I

OUT

Battery

Backup

TEMPERATURE – °C

53

52

49

20 40 120

60 80 100

51

50

RESET ACTIVE TIME – ms

VCC = +5V

ADM8690
ADM8691
ADM8692
ADM8693

Figure 12. Reset Active Time vs.
Temperature

TIME – µs

6

0

10 20 30 40 50 60 70 80

5

0

1.35

1.25

2
1

4
3

VCC = 5V
T

A

= +25°C

PFO

V

PFI

1.3V

30pF

90

Figure 15. Power Fail Comparator
Response Time

10

90

100

0%

3.36 V

500ms

A4

1V1V

Figure 10. Reset Output Voltage vs

Supply Voltage

TEMPERATURE – °C

4.69

4.67

4.55
–60 –30 120

30 60 90

4.65

4.63

RESET VOLTAGE THRESHOLD – V

VCC = +5V

4.61

4.59

4.57

0

Figure 13. Reset Voltage Threshold
vs. Temperature

TIME – µs

6

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

5

0

1.35

1.25

2
1

4
3

VCC = 5V
T

A

= +25°C

PFO

V

PFI

1.3V

30pF

10kΩ

+5V

1.8

Figure 16. Power Fail Comparator
Response Time with Pull-Up Resistor

ADM8690–ADM8695

REV. 0

–10–

+APPLICATION INFORMATION
Increasing the Drive Current

If the continuous output current requirements at V

OUT

exceed

100 mA, or if a lower V

CC–VOUT

voltage differential is desired,
an external PNP pass transistor may be connected in parallel
with the internal transistor. The BATT ON output (ADM8691/
ADM8693/ADM8695) can directly drive the base of the exter­nal transistor.

PNP TRANSISTOR

0.1µF

0.1µF

BATTERY

+5V INPUT

POWER

V

CC

BATTONV

OUT

V

BATT

ADM8691
ADM8693
ADM8695

Figure 17. Increasing the Drive Current

Using a Rechargeable Battery for Backup

If a capacitor or a rechargeable battery is used for backup then
the charging resistor should be connected to V

OUT

since this
eliminates the discharge path that would exist during power­down if the resistor is connected to V

CC

.

0.1µF

0.1µF

RECHARGEABLE

BATTERY

+5V INPUT

POWER

V

CC

V

OUT

V

BATT

ADM869x

R

I =

V

OUT

– V

BATT

R

Figure 18. Rechargeable Battery

Adding Hysteresis to the Power Fail Comparator

For increased noise immunity, hysteresis may be added to the
power fail comparator. Since the comparator circuit is nonin­verting, hysteresis can be added simply by connecting a resistor be­tween the

PFO output and the PFI input as shown in Figure 19.

When

PFO is low, resistor R3 sinks current from the summing

junction at the PFI pin. When

PFO is high, the series combina­tion of R3 and R4 source current into the PFI summing junc­tion. This results in differing trip levels for the comparator.

ADM869x

1.3V

PFI

PFO

R

1

R

2

+7V TO +15V

INPUT

POWER

R

4

R

3

V

CC

TO µP NMI

+5V

7805

5V

0V

PFO

0V V

L

V

H

V

IN

VH = 1.3V (1+ +

)

VL = 1.3V (1+ –

)

ASSUMING R4 < < R3 THEN

R

1

R

2

R

1

R

3

R

1

R

2

R1 (5V – 1.3V)

1.3V (R

3

+ R4)

R

1

R

2

HYSTERESIS VH – VL = 5V (

)

Figure 19. Adding Hysteresis to the Power Fail Comparator

Monitoring the Status of the Battery

The power fail comparator can be used to monitor the status of
the backup battery instead of the power supply if desired. This
is shown in Figure 20. The PFI input samples the battery volt­age and generates an active low

PFO signal when the battery
voltage drops below a chosen threshold. It may be necessary to
apply a test load in order to determine the loaded battery volt­age. This can be done under processor control using

CE

OUT.

Since CE

OUT

is forced high during the battery backup mode, the
test load will not be applied to the battery while it is in use, even
if the microprocessor is not powered.

ADM869x

PFO

+5V INPUT

POWER

CE

IN

CE

OUT

PFI

V

BATT

V

CC

BATTERY

20kΩ

OPTIONAL

TEST LOAD

10MΩ

10MΩ

LOW BATTERY
SIGNAL TO
µP I/O PIN

FROM µP I/O PIN
APPLIES TEST LOAD
TO BATTERY

Figure 20. Monitoring the Battery Status

Alternate Watchdog Input Drive Circuits

The watchdog feature can be enabled and disabled under pro­gram control by driving WDI with a three-state buffer (Figure
21a). When three-stated, the WDI input will float, thereby dis­abling the watchdog timer.

WDI

ADM869x

WATCHDOG

STROBE

CONTROL

INPUT

Figure 21a. Programming the Watchdog Input

This circuit is not entirely foolproof, and it is possible that a
software fault could erroneously three-state the buffer. This
would then prevent the ADM869x from detecting that the mi­croprocessor is no longer operating correctly. In most cases a
better method is to extend the watchdog period rather than dis­abling the watchdog. This may be done under program control
using the circuit shown in Figure 21b. When the control input is
high, the OSC SEL pin is low and the watchdog timeout is set
by the external capacitor. A 0.01 µF capacitor sets a watchdog
timeout delay of 100 seconds. When the control input is low,
the OSC SEL pin is driven high, selecting the internal oscillator.
The 100 ms or the 1.6 s period is chosen, depending on which di­ode in Figure 21b is used. With D1 inserted, the internal timeout is
set at 100 ms; with D2 inserted the timeout is set at 1.6 s.

D2D1

CONTROL

INPUT*

ADM869x

OSC SEL

OSC IN

*LOW = INTERNAL TIMEOUT

HIGH = EXTERNAL TIMEOUT

Figure 21b. Programming the Watchdog Input

ADM8690–ADM8695

REV. 0

–11–

TYPICAL APPLICATIONS
ADM8690, ADM8692 and ADM8694

Figure 22a shows the ADM8690/ADM8692/ADM8694 in a
typical power monitoring, battery backup application. V

OUT

powers the CMOS RAM. Under normal operating conditions
with V

CC

present, V

OUT

is internally connected to VCC. If a

power failure occurs, V

CC

will decay and V

OUT

will be switched

to V

BATT

thereby maintaining power for the CMOS RAM. A
RESET pulse is also generated when VCC falls below 4.65 V for
the ADM8690/ADM8694 or 4.4 V for the ADM8692.

RESET

will remain low for 50 ms (200 ms for ADM8694) after V

CC

re-

turns to 5 V.
The watchdog timer input (WDI) monitors an I/O line from the

µP system. This line must be toggled once every 1.6 seconds to
verify correct software execution. Failure to toggle the line indi­cates that the µP system is not correctly executing its program
and may be tied up in an endless loop. If this happens, a reset
pulse is generated to initialize the processor.

If the watchdog timer is not needed, the WDI input should be
left floating.

The Power Fail Input, PFI, monitors the input power supply via
a resistive divider network. The voltage on the PFI input is com­pared with a precision 1.3 V internal reference. If the input volt­age drops below 1.3 V, a power fail output (

PFO) signal is
generated. This warns of an impending power failure and may
be used to interrupt the processor so that the system may be
shut down in an orderly fashion. The resistors in the sensing
network are ratioed to give the desired power fail threshold
voltage V

T

.

V

T

= (1.3 R1/R2) + 1.3 V

R1/R2 = (V

T

/1.3) – 1

+

BATTERY

R

1

R

2

+5V

0.1µF

ADM8690
ADM8692
ADM8694

V

CC

PFI

V

BATT

V

OUT

WDI

PFO

RESET

GND

µP POWER

CMOS RAM
POWER

µP SYSTEM

µP RESET
µP NMI

I/O LINE

Figure 22a. ADM8690/ADM8692/ADM8694 Typical Applica­tion Circuit A

Figure 22b shows a similar application but in this case the PFI
input monitors the unregulated input to the 7805 voltage regu­lator. This gives an earlier warning of an impending power fail­ure. It is useful with processors operating at low speeds or where
there are a significant number of housekeeping tasks to be com­pleted before the power is lost.

+

BATTERY

R

1

R

2

INPUT

POWER

V > 8V

0.1µF

0.1µF

7805

+5V

µP POWER

CMOS RAM
POWER

µP SYSTEM

µP RESET
µP NMI

I/O LINE

ADM8690
ADM8692
ADM8694

V

CC

PFI

V

BATT

V

OUT

WDI

PFO

RESET

GND

Figure 22b. ADM8690/ADM8692/ADM8694 Typical Applica­tion Circuit B

ADM8691, ADM8693 and ADM8695

A typical connection for the ADM8691/ADM8693/ADM8695
is shown in Figure 23. CMOS RAM is powered from V

OUT

.

When 5 V power is present this is routed to V

OUT

. If VCC fails

then V

BATT

is routed to V

OUT

. V

OUT

can supply up to 100 mA

from V

CC

, but if more current is required, an external PNP tran-

sistor can be added. When V

CC

is higher than V

BATT

, the BATT
ON output goes low, providing up to 25 mA of base drive for
the external transistor. A 0.1 µF capacitor is connected to V

OUT

to supply the transient currents for CMOS RAM. When VCC is
lower than V

BATT

, an internal 20 Ω MOSFET connects the

backup battery to V

OUT

.

3V

BATTERY

R

1

R

2

0.1µF

0.1µF

0.1µF

RESET

SYSTEM STATUS

INDICATORS

NC

INPUT POWER
+5V

A0–A15
I/O LINE
NMI

RESET

µP

ADM8691
ADM8693
ADM8695

BATT

ON

V

CC

V

OUT

V

BATT

CE

OUT

CE

IN

PFI
GND

OSC IN
OSC SEL

WDI

PFO

RESET

LOW LINE

WDO

ADDRESS

DECODE

CMOS

RAM

Figure 23. ADM8691/ADM8693/ADM8695 Typical
Application

ADM8690–ADM8695

REV. 0

–12–

RESET Output

The internal voltage detector monitors VCC and generates a
RESET output to hold the microprocessor’s Reset line low
when V

CC

is below 4.65 V (4.4 V for ADM8693). An internal

timer holds

RESET low for 50 ms (200 ms for the ADM8695)

after V

CC

rises above 4.65 V (4.4 V for ADM8693). This pre-

vents repeated toggling of

RESET even if the 5 V power drops

out and recovers with each power line cycle.
The crystal oscillator normally used to generate the clock for

microprocessors can take several milliseconds to stabilize. Since
most microprocessors need several clock cycles to reset,

RESET

must be held low until the microprocessor clock oscillator has
started. The power-up

RESET pulse lasts 50 ms (200 ms for the
ADM8695) to allow for this oscillator start-up time. If a differ­ent reset pulse width is required, then a capacitor should be
connected to OSC IN or an external clock may be used. Please
refer to Table I and Figure 4. The manual reset switch and the

0.1 µF capacitor connected to the reset line can be omitted if a
manual reset is not needed. An inverted, active high, RESET
output is also available.

Power Fail Detector

The +5 V V

CC

power line is monitored via a resistive potential
divider connected to the Power Fail Input (PFI). When the
voltage at PFI falls below 1.3 V, the Power Fail Output (

PFO)
drives the processor’s NMI input low. If for example a Power
Fail threshold of 4.8 V is set with resistors R

1

and R2, the micro-

processor will have the time when V

CC

falls from 4.8 V to 4.65 V
to save data into RAM. An earlier power fail warning can be gen­erated if the unregulated dc input to the 5 V regulator is avail­able for monitoring. This will allow more time for micro­processor housekeeping tasks to be completed before power is
lost.

RAM Write Protection

The ADM8691/ADM8693/ADM8695 CE

OUT

line drives the

Chip Select inputs of the CMOS RAM.

CE

OUT

follows CEIN as

long as V

CC

is above the 4.65 V (4.4 V for ADM8693) reset

threshold.
If V

CC

falls below the reset threshold, CE

OUT

goes high, inde-

pendent of the logic level at

CE

IN

. This prevents the micropro­cessor from writing erroneous data into RAM during power-up,
power-down, brownouts and momentary power interruptions.

Watchdog Timer

The microprocessor drives the Watchdog Input (WDI) with an
I/O line. When OSC IN and OSC SEL are unconnected, the
microprocessor must toggle the WDI pin once every 1.6 seconds
to verify proper software execution. If a hardware or software
failure occurs such that WDI is not toggled, the ADM8691/
ADM8693 will issue a 50 ms (200 ms for ADM8695)

RESET

pulse after 1.6 seconds. This typically restarts the micro­processor’s power-up routine. A new

RESET pulse is issued
every 1.6 seconds until WDI is again strobed. If a different
watchdog timeout period is required, then a capacitor should be
connected to OSC IN or an external clock may be used. Please
refer to Table I and Figure 4.

The Watchdog Output (

WDO) goes low if the watchdog timer

is not serviced within its timeout period. Once

WDO goes low,
it remains low until a transition occurs at WDI. The watchdog
timer feature can be disabled by leaving WDI unconnected.

The

RESET output has an internal 3 µA pull-up, and can either
connect to an open collector reset bus or directly drive a CMOS
gate without an external pull-up resistor.

ADM8690–ADM8695

REV. 0

–13–

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

8-Pin Plastic DIP

(N-8)

8

14

5

0.430 (10.92)

0.348 (8.84)

0.280 (7.11)

0.240 (6.10)

PIN 1

SEATING
PLANE

0.022 (0.558)

0.014 (0.356)

0.060 (1.52)

0.015 (0.38)

0.210 (5.33)
MAX

0.150
(3.81)
MIN

0.070 (1.77)

0.045 (1.15)

0.100
(2.54)

BSC

0.160 (4.06)

0.115 (2.93)

0.325 (8.25)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

0.195 (4.95)

0.115 (2.93)

16-Lead Plastic DIP

(N-16)

16

18

9

0.840 (21.33)

0.745 (18.93)

0.280 (7.11)

0.240 (6.10)

PIN 1

SEATING
PLANE

0.022 (0.558)

0.014 (0.356)

0.060 (1.52)

0.015 (0.38)

0.210
(5.33)

0.150
(3.81)

0.070 (1.77)

0.045 (1.15)

0.100
(2.54)

BSC

0.200 (5.05)

0.125 (3.18)

0.325 (8.25)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

0.195 (4.95)

0.115 (2.93)

ADM8690–ADM8695

REV. 0

–14–

8-Lead Small Outline

(SO-8)

0.1968 (5.00)

0.1890 (4.80)

8

5

41

0.2440 (6.20)

0.2284 (5.80)

PIN 1

0.1574 (4.00)

0.1497 (3.80)

0.0688 (1.75)

0.0532 (1.35)

SEATING

PLANE

0.0098 (0.25)

0.0040 (0.10)

0.0192 (0.49)

0.0138 (0.35)

0.0500
(1.27)

BSC

0.0098 (0.25)

0.0075 (0.19)

0.0500 (1.27)

0.0160 (0.41)

8°
0°

0.0196 (0.50)

0.0099 (0.25)

x 45°

16-Lead Small Outline (Wide Body)

(R-16)

16 9

81

PIN 1

0.413 (10.50)

0.419

(10.65)

0.299
(7.60)

SEATING

PLANE

0.05 (1.27)
BSC

0.104
(2.65)

0.019 (0.49)

0.012
(0.3)

0.013 (0.32)

0.042 (1.07)

0.030 (0.75)

16-Lead Small Outline (Narrow Body)

(R-16A)

16 9

81

0.3937 (10.00)

0.3859 (9.80)

0.2550 (6.20)

0.2284 (5.80)

0.1574 (4.00)

0.1497 (5.80)

PIN 1

SEATING

PLANE

0.0098 (0.25)

0.0040 (0.10)

0.0192 (0.49)

0.0138 (0.35)

0.0688 (1.75)

0.0532 (1.35)

0.0500
(1.27)

BSC

0.0099 (0.25)

0.0075 (0.19)

0.0500 (1.27)

0.0160 (0.41)

8°
0°

0.0196 (0.50)

0.0099 (0.25)

x 45°

ADM8690–ADM8695

REV. 0

–15–

16-Lead Thin Shrink Small Outline

(RU-16)

16 9

8

1

0.201 (5.10)

0.193 (4.90)

0.256 (6.50)

0.246 (6.25)

0.177 (4.50)

0.169 (4.30)

PIN 1

SEATING

PLANE

0.006 (0.15)

0.002 (0.05)

0.0118 (0.30)

0.0075 (0.19)

0.0256
(0.65)

BSC

0.0433
(1.10)
MAX

0.0079 (0.20)

0.0035 (0.090)

0.028 (0.70)

0.020 (0.50)

8°
0°

C2932–10–2/97

PRINTED IN U.S.A.

–16–