Page 1
1.3V
V
OUT
V
BATT
V
CC
WATCHDOG
INPUT (WDI)
POWER FAIL
INPUT (PFI) POWER FAIL
OUTPUT (PFO)
RESET
WATCHDOG
TIMER
BATT ON
OSC IN
OSC SEL
WATCHDOG
OUTPUT (WDO)
RESET
LOW LINE
LL
IN
RESET GENERATOR
TIMEBASE FOR RESET
AND WATCHDOG
WATCHDOG
TRANSITION DETECTOR
ADM696
1.3V
CE
OUT
WATCHDOG
INPUT (WDI)
POWER FAIL
INPUT (PFI) POWER FAIL
OUTPUT (PFO)
RESET
WATCHDOG
TIMER
OSC IN
OSC SEL
WATCHDOG
OUTPUT (WDO)
RESET
LOW LINE
LL
IN
RESET GENERATOR
TIMEBASE FOR RESET
AND WATCHDOG
WATCHDOG
TRANSITION DETECTOR
ADM697
CE
IN
Microprocessor
a
FEATURES
Superior Upgrade for MAX696/MAX697
Specified Over Temperature
Adjustable Low Line Voltage Monitor
Power OK/Reset Time Delay
Reset Assertion Down to 1 V V
Watchdog Timer—100 ms, 1.6 s, or Adjustable
Low Switch On Resistance
1.5 V Normal, 20 V in Backup
600 nA Standby Current
Automatic Battery Backup Switching (ADM696)
Fast On-Board Gating of Chip Enable Signals (ADM697)
Voltage Monitor for Power Fail or Low Battery Warning
APPLICATIONS
Microprocessor Systems
Computers
Controllers
Intelligent Instruments
Automotive Systems
Critical mP Power Monitoring
CC
Supervisory Circuits
ADM696/ADM697
FUNCTIONAL BLOCK DIAGRAMS
GENERAL DESCRIPTION
The ADM696/ADM697 supervisory circuits offer complete
single chip solutions for power supply monitoring and battery
control functions in microprocessor systems. These functions
include µP reset, backup-battery switchover, watchdog timer,
CMOS RAM write protection, and power failure warning.
The ADM696/ADM697 are available in 16-pin DIP and small
outline packages and provide the following functions:
1. Power-On Reset output during power-up, power-down and
brownout conditions. The RESET voltage threshold is
adjustable using an external voltage divider. The
output remains operational with V
as low as 1 V.
CC
2. A Reset pulse if the optional watchdog timer has not been
toggled within specified time.
3. Separate watchdog time-out and low line status outputs.
4. Adjustable reset and watchdog timeout periods.
5. A 1.3 V threshold detector for power fail warning, low battery detection, or to monitor a power supply other than VCC.
6. Battery backup switching for CMOS RAM, CMOS microprocessor or other low power logic (ADM696).
7. Write protection of CMOS RAM or EEPROM (ADM697).
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
RESET
The ADM696/ADM697 is fabricated using an advanced epitaxial
CMOS process combining low power consumption (5 mW),
extremely fast Chip Enable gating (5 ns) and high reliability.
RESET assertion is guaranteed with VCC as low as 1 V. In
addition, the power switching circuitry is designed for minimal
voltage drop thereby permitting increased output current drive
of up to 100 mA without the need for an external pass transistor.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
Page 2
(VCC = Full Operating Range, V
ADM696/ADM697–SPECIFICATIONS
P
arameter Min Typ Max Units Test Conditions/Comments
unless otherwise noted.)
= +2.8 V, TA = T
BATT
MIN
to T
VCC Operating Voltage Range 3.0 5.5 V
V
Operating Voltage Range 2.0 VCC – 0 3 V
BATT
BATTERY BACKUP SWITCHING (ADM696)
V
Output Voltage VCC – 0.05 VCC – 0.025 V I
OUT
V
in Battery Backup Mode V
OUT
Supply Current (Excludes I
) 1 1.95 mA I
OUT
VCC – 0.5 VCC – 0.25 V I
– 0.05 V
BATT
– 0.02 V I
BATT
Supply Current in Battery Backup Mode 0.6 1 µAVCC = 0 V, V
Battery Standby Current 5.5 V > VCC > V
(+ = Discharge, – = Charge) –0.1 +0.02 µAT
= 1 mA
OUT
≤ 100 mA
OUT
= 250 µA, VCC < V
OUT
= 100 mA
OUT
= +25°C
A
BATT
= 2.8 V
+ 0.2 V
BATT
BATT
– 0.2 V
–1 +0.02 µA
Battery Switchover Threshold 70 mV Power-Up
VCC – V
BATT
50 mV Power-Down
Battery Switchover Hysteresis 20 mV
BATT ON Output Voltage 0.4 V I
BATT ON Output Short Circuit Current 7 mA BATT ON = V
0.5 1 25 µA BATT ON = V
= 1.6 mA
SINK
= 2.4 V Sink Current
OUT
, VCC = 0 V, Source Current
OUT
RESET AND WATCHDOG TIMER
Low Line Threshold (LLIN) 1.25 1.3 1.35 V VCC = +5 V, +3 V
Reset Timeout Delay 35 50 70 ms OSC SEL = HIGH, VCC= 5 V, TA = +25°C
Watchdog Timeout Period, Internal Oscillator 1.0 1.6 2.25 s Long Period, VCC = 5 V, TA = +25°C
70 100 140 ms Short Period, VCC = 5 V, TA = +25°C
Watchdog Timeout Period, External Clock 4032 4097 Cycles Long Period
960 1025 Cycles Short Period
Minimum WDI Input Pulse Width 50 ns VIL = 0.4, VIH = 3.5 V, VCC = 5 V
RESET Output Voltage @ VCC = +1 V 4 200 mV I
RESET, RESET Output Voltage 0.4 V I
0.4 V I
3.5 V I
LOW LINE, WDO Output Voltage 0.4 V I
3.5 V I
Output Short Circuit Source Current 1 3 25 µA
WDI Input Threshold VCC = 5 V
= 10 µA, VCC = 1 V
SINK
= 400 µA, VCC = 2 V, V
SINK
= 1.6 mA, 3 V < VCC < 5.5 V
SINK
= 1 µA, VCC = 5 V
SOURCE
= 1.6 mA,
SINK
= 1 µA, VCC = 5 V
SOURCE
1
BATT
= 0 V
Logic Low 0.8 V
Logic High 3.5 V
WDI Input Current 20 50 µA WD1 = V
, (VCC) TA = +25°C
OUT
–50 –15 µA WD1 = 0 V, TA = +25°C
MAX
POWER FAIL DETECTOR
PFI Input Threshold 1.2 1.3 1.4 V VCC = +3 V, +5 V
PFI–LLIN Threshold Difference –50 ± 15 +50 mV VCC = +3 V, +5 V
PFI Input Current –25 ±0.01 +25 nA
LLIN Input Current –50 ±0.01 +50 nA
PFO Output Voltage 0.4 V I
3.5 V I
= 1.6 mA
SINK
= 1 µA, VCC = 5 V
SOURCE
PFO Short Circuit Source Current 1 3 25 µA PFI = Low, PFO = 0 V
CHIP ENABLE GATING (ADM697)
CEIN Threshold 0.8 V V
IL
3.0 V VIH, VCC = 5 V
CE
Pullup Current 3 µA
IN
CE
Output Voltage 0.4 V I
OUT
VCC – 0.5 V I
CE Propagation Delay 5 25 ns
= 1.6 mA
SINK
SOURCE
= 800 µA
OSCILLATOR
OSC IN Input Current ±2 µA
OSC SEL Input Pullup Current 5 µA
OSC IN Frequency Range 0 250 kHz OSC SEL = 0 V
OSC IN Frequency with Ext. Capacitor 4 kHz OSC SEL = 0 V, C
NOTE
1
WDI is a three-level input which is internally biased to 38% of VCC and has an input impedance of approximately 125 kΩ .
Specifications subject to change without notice.
= 47 pF
OSC
REV. 0–2–
Page 3
ADM696/ADM697
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
V
All Other Inputs . . . . . . . . . . . . . . . . . . –0.3 V to V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
BATT
OUT
+ 0.5 V
Input Current
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
CC
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
BATT
GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Power Dissipation, N-16 DIP . . . . . . . . . . . . . . . . . . . 600 mW
θ
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 135°C/W
JA
Power Dissipation, Q-16 DIP . . . . . . . . . . . . . . . . . . . 600 mW
θ
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 100°C/W
JA
Power Dissipation, R-16 SOIC . . . . . . . . . . . . . . . . . .600 mW
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 110°C/W
θ
JA
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . .–40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . . .–55°C to +125°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum ratings for extended periods of time may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADM696/ADM697 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
PIN CONFIGURATIONS
Model Temperature Range Package Option
WARNING!
ESD SENSITIVE DEVICE
ADM696AN –40°C to +85°C N-16
ADM696AR –40°C to +85°C R-16
ADM696AQ –40°C to +85°C Q-16
ADM696SQ –55°C to +125°C Q-16
ADM697AN –40°C to +85°C N-16
ADM697AR –40°C to +85°C R-16
ADM697AQ –40°C to +85°C Q-16
ADM697SQ –55°C to +125°C Q-16
V
BATT
V
OUT
V
GND
BATT ON
LOW LINE
OSC IN
OSC SEL
TEST
V
LL
GND
LOW LINE
OSC IN
OSC SEL
NC
CC
CC
IN
1
2
3
4
5
(Not to Scale)
6
7
8
1
2
3
4
5
(Not to Scale)
6
7
8
ADM696
TOP VIEW
ADM697
TOP VIEW
15
14
13
11
16
12
10
9
15
16
14
13
12
11
10
9
RESET
RESET
WDO
LL
IN
NC
WDI
PFO
PFI
RESET
RESET
WDO
CE
CE
WDI
PFO
PFI
IN
OUT
REV. 0
–3–
Page 4
ADM696/ADM697
Pin No.
Mnemonic ADM696 ADM697 Function
PIN FUNCTION DESCRIPTION
V
V
V
CC
BATT
OUT
3 3 Power Supply Input +3 V to +5 V.
1 — Backup Battery Input. Connect to Ground if a backup battery is not used.
2 — Output Voltage, VCC or V
highest potential. V
V
if V
CC
OUT
and V
OUT
BATT
is internally switched to V
BATT
depending on which is at the
OUT
can supply up to 100 mA to power CMOS RAM. Connect V
are not used.
OUT
to
GND 4 5 0 V. Ground reference for all signals.
RESET 15 15 Logic Output. RESET goes low whenever LLIN falls below 1.3 V or when VCC falls below
the V
input voltage. RESET remains low for 50 ms after LLIN goes above 1.3 V,
BATT
RESET also goes low for 50 ms if the watchdog timer is enabled but not serviced within its
timeout period. The
RESET pulse width can be adjusted as shown in Table I.
WDI 11 11 Watchdog Input, WDI is a three level input. If WDI remains either high or low for longer
than the watchdog timeout period,
RESET pulses low and WDO goes low. The timer resets
with each transition at the WDI input. The watchdog timer is disabled when WDI is left
floating or is driven to midsupply.
PFI 9 9 Power Fail Input. PFI is the noninverting input to the Power Fail Comparator when PFI is
less than 1.3 V,
PFO goes low. Connect PFI to GND or V
OUT
when not used. See Figure 1.
PFO 10 10 Power Fail Output. PFO is the output of the Power Fail Comparator. It goes low when PFI
is less than 1.3 V. The comparator is turned off and
V
.
BATT
CE
CE
IN
OUT
— 13 Logic Input. The input to the CE gating circuit. Connect to GND or V
— 12 Logic Output. CE
is above 1.3 V. If LLIN is below 1.3 V, CE
is a gated version of the CEIN signal. CE
OUT
OUT
BATT ON 5 — Logic Output. BATT ON goes high when V
It goes low when V
is internally switched to VCC. The output typically sinks 7 mA and
OUT
OUT
PFO goes low when VCC is below
OUT
tracks CEIN when LL
OUT
is forced high.
is internally switched to the V
if not used.
input.
BATT
IN
can directly drive the base of an external PNP transistor to increase the output current above
the 100 mA rating of V
OUT
.
LOW LINE 6 6 Logic Output. LOW LINE goes low when LLIN falls below 1.3 V. It returns high as soon as
LL
rises above 1.3 V.
IN
RESET 16 16 Logic Output. RESET is an active high output. It is the inverse of
RESET.
OSC SEL 8 8 Logic Oscillator Select Input. When OSC SEL is unconnected or driven high, the internal
oscillator sets the reset time delay and watchdog time-out period. When OSC SEL is low,
the external oscillator input, OSC IN, is enabled. OSC SEL has a 3 µA internal pullup. See
Table I and Figure 4.
OSC IN 7 7 Logic Oscillator Input. When OSC SEL is low, OSC IN can be driven by an external clock
to adjust both the reset delay and the watchdog time-out period. The timing can also be
adjusted by connecting an external capacitor to this pin. See Table I and Figure 4. When
OSC SEL is high or floating, OSC IN selects between fast and slow watchdog time-out periods.
WDO 14 14 Logic Output. The Watchdog Output, WDO, goes low if WDI remains either high or low
for longer than the watchdog time-out period.
WDI. If WDI is unconnected or at midsupply,
when
LOW LINE goes low.
WDO is set high by the next transition at
WDO remains high. WDO also goes high
NC 12 2 No Connect. It should be left open.
LL
IN
13 4 Voltage Sensing Input. The voltage on the low line input, LLIN, is compared with a 1.3 V
reference voltage. This input is normally used to monitor the power supply voltage. The
output of the comparator generates a
RESET/
RESET output.
LOW LINE output signal. It also generates a
TEST — 1 This is a special test pin using during device manufacture. It should be connected to GND.
REV. 0–4–
Page 5
ADM696/ADM697
t
1
t
1
= RESET TIME
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2–V1
V2 V2
V1 V1
t
1
LL
IN
LOW LINE
RESET
CIRCUIT INFORMATION
Battery-Switchover Section (ADM696)
The battery switchover circuit compares VCC to the V
input, and connects V
occurs when V
when V
CC
is 50 mV higher than V
CC
is 70 mV greater than V
to whichever is higher. Switchover
OUT
BATT
as VCC falls, and
BATT
as VCC rises. This
20 mV of hysteresis prevents repeated rapid switching if V
BATT
CC
falls very slowly or remains nearly equal to the battery voltage.
During normal operation with V
internally switched to V
OUT
CC
via an internal PMOS transistor
higher than V
BATT
, VCC is
switch. This switch has a typical on resistance of 1.5 Ω and can
supply up to 100 mA at the V
OUT
terminal. V
is normally
OUT
used to drive a RAM memory bank which may require instantaneous currents of greater than 100 mA. If this is the case, then
a bypass capacitor should be connected to V
. The capacitor
OUT
will provide the peak current transients to the RAM. A capacitance value of 0.1 µF or greater may be used.
If the continuous output current requirement at V
100 mA or if a lower V
CC–VOUT
voltage differential is desired,
OUT
exceeds
Low Line RESET OUTPUT
RESET is an active low output which provides a RESET signal
to the microprocessor whenever the Low Line Input (LL
below 1.3 V. The LL
power supply voltage. An internal timer holds
50 ms after the voltage on LL
tended as a power-on
input is normally used to monitor the
IN
RESET low for
rises above 1.3 V. This is in-
IN
RESET signal for the processor. It allows
) is
IN
time for the power supply and microprocessor to stabilize. On
power-down, the
RESET output remains low with VCC as low
as 1 V. This ensures that the microprocessor is held in a stable
shutdown condition.
The LL
comparator has approximately 12 mV of hysteresis
IN
for enhanced noise immunity.
In addition to
available. This is the complement of
RESET, an active high RESET output is also
RESET and is useful for
processors requiring an active high RESET.
an external PNP pass transistor may be connected in parallel
with the internal transistor. The BATT ON output can directly
drive the base of the external transistor.
A 20 Ω MOSFET switch connects the V
input to V
BATT
OUT
during battery backup. This MOSFET has very low input-tooutput differential (dropout voltage) at the low current levels
required for battery backup of CMOS RAM or other low power
CMOS circuitry. The supply current in battery backup is typically 0.6 µA.
The ADM696 operates with battery voltages from 2.0 V to V
CC
–0.3 V). High value capacitors, either standard electrolytic or
the farad-size double layer capacitors, can also be used for shortterm memory backup. A small charging current of typically
10 nA (0.1 µA max) flows out of the V
rent is useful for maintaining rechargeable batteries in a fully
charged condition. This extends the life of the backup battery
by compensating for its self discharge current. Also note that
this current poses no problem when lithium batteries are used
for backup since the maximum charging current (0.1 µA) is safe
for even the smallest lithium cells.
If the battery-switchover section is not used, V
connected to GND and V
V
CC
V
BATT
should be connected to VCC.
OUT
terminal. This cur-
BATT
should be
BATT
V
OUT
Watchdog Timer RESET
The watchdog timer circuit monitors the activity of the microprocessor in order to check that it is not stalled in an indefinite
loop. An output line on the processor is used to toggle the
Watchdog Input (WDI) line. If this line is not toggled within
the selected timeout period, a
ADM696/ADM697 may be configured for either a fixed
“short” 100 ms or a “long” 1.6 second timeout period or for an
adjustable timeout period. If the “short” period is selected some
systems may be unable to service the watchdog timer immediately after a reset, so a “long” timeout is automatically initiated
directly after a reset is issued. The watchdog timer is restarted
at the end of Reset, whether the Reset was caused by lack of activity on WDI or by LL
GATE DRIVE
The normal (short) timeout period becomes effective following
the first transition of WDI after
100
mV
INTERNAL
700
mV
SHUT DOWN SIGNAL
WHEN
> (VCC + 0.7V)
V
BATT
BATT ON
(ADM691, ADM693,
ADM695, ADM696)
watchdog timeout period restarts with each transition on the
WDI pin. To ensure that the watchdog timer does not time out,
either a high-to-low or low-to high transition on the WDI pin
must occur at or less than the minimum timeout period. If WDI
remains permanently either high or low, reset pulses will be is-
Figure 2. Power-Fail Reset Timing
RESET pulse is generated. The
falling below the reset threshold.
IN
RESET has gone inactive. The
sued after each timeout period (1.6 s). The watchdog monitor
can be deactivated by floating the Watchdog Input (WDI) or by
connecting it to midsupply.
Figure 1. Battery Switchover Schematic
REV. 0
–5–
Page 6
ADM696/ADM697
OSC IN
OSC SEL
ADM69x
8
7
NC
NC
OSC IN
OSC SEL
ADM69x
8
7
NC
Table I. ADM696, ADM697 Reset Pulse Width and Watchdog Timeout Selections
Watchdog Timeout Period Reset Active Period
OSC SEL OSC IN Normal Immediately After Reset
Low External Clock Input 1024 CLKS 4096 CLKS 512 CLKS Low External Capacitor 400 ms × C/47 pF 1.6 s × C/47 pF 200 ms × C/47 pF Floating or High Low 100 ms 1.6 s 50 ms Floating or High Floating or High 1.6 s 1.6 s 50 ms
NOTE
With the OSC SEL pin low, OSC IN can be driven by an external clock signal, or an external capacitor can be connected between OSC IN and GND. The nominal
internal oscillator frequency is 10.24 kHz. The nominal oscillator frequency with external capacitor is: F
WDI
WDO
(Hz) = 184,000/C (pF).
OSC
8
7
C
OSC
OSC SEL
ADM69x
OSC IN
t
2
RESET
t
1
t
= RESET TIME
1
t
= NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD
2
t
= WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESET
3
t
1
t
3
t
1
Figure 3. Watchdog Timeout Period and Reset Active Time
The watchdog timeout period defaults to 1.6 s and the reset
pulse width defaults to 50 ms but these times to be adjusted as
shown in Table I. Figure 4 shows the various oscillator configurations which can be used to adjust the reset pulse width and
watchdog timeout period.
The internal oscillator is enabled when OSC SEL is high or
floating. In this mode, OSC IN selects between the 1.6 second
and 100 ms watchdog timeout periods. In either case, immediately after a reset the timeout period is 1.6 s. This gives the microprocessor time to reinitialize the system. If OSC IN is low,
then the 100 ms watchdog period becomes effective after the
first transition of WDI. The software should be written such
that the I/O port driving WDI is left in its power-up reset state
until the initialization routines are completed and the microprocessor is able to toggle WDI at the minimum watchdog timeout
period of 70 ms.
Figure 4b. External Capacitor
Figure 4c. Internal Oscillator (1.6 s Watchdog)
Figure 4d. Internal Oscillator (100 ms Watchdog)
Watchdog Output (WDO)
The Watchdog Output WDO provides a status output which
goes low if the watchdog timer “times out” and remains low
until set high by the next transition on the watchdog input.
WDO is also set high when LLIN goes below the reset threshold.
8
OSC SEL
CLOCK
0 TO 250kHz
7
OSC IN
ADM69x
Figure 4a. External Clock Source
REV. 0–6–
Page 7
ADM696/ADM697
ADM69x
POWER
FAIL
INPUT
R2
INPUT
POWER
1.3V
PFO
POWER
FAIL
OUTPUT
R1
CE Gating and RAM Write Protection (ADM697)
The ADM697 contains memory protection circuitry which
ensures the integrity of data in memory by preventing write
operations when LL
LL
is greater than 1.3 V, CE
IN
with a 5 ns propagation delay. When LL
threshold, an internal gate forces
is below the threshold voltage. When
IN
is a buffered replica of CEIN,
OUT
CE
falls below the 1.3 V
IN
high, independent of
OUT
CEIN.
CE
typically drives the CE, CS, or Write input of battery
OUT
Fail Output (PFO) goes low when the voltage at PFI is less than
1.3 V. Typically PFI is driven by an external voltage divider
which senses either the unregulated dc input to the system’s 5 V
regulator or the regulated 5 V output. The voltage divider ratio
can be chosen such that the voltage at PFI falls below 1.3 V
several milliseconds before the +5 V power supply falls below
the reset threshold.
PFO is normally used to interrupt the
microprocessor so that data can be stored in RAM and the shutdown procedure executed before power is lost.
backed up CMOS RAM. This ensures the integrity of the data
in memory by preventing write operations when V
is at an in-
CC
valid level.
CE
If the 5 ns typical propagation delay of
nect
CEIN to GND and use the resulting CE
is excessive, con-
OUT
to control a
OUT
high speed external logic gate.
ADM697
CE
IN
LOW = 0
LL
IN
LLIN OK = 1
CE
OUT
Figure 7. Power Fail Comparator
Table II. Input and Output Status In Battery Backup Mode
Signal Status
Figure 5. Chip Enable Gating
V
OUT
(ADM696) V
is connected to V
OUT
BATT
via an
internal PMOS switch.
LL
V2 V2
IN
V1 V1
RESET Logic low.
RESET Logic high. The open circuit output voltage is
RESET
t
1
t
1
equal to V
OUT
.
LOW LINE Logic low.
BATT ON (ADM696) Logic high. The open circuit voltage
LOW LINE
is equal to V
WDI WDI is ignored. It is internally disconnected
OUT
.
from the internal pullup resistor and does not
source or sink current as long as its input voltage
CE
is between GND and V
does not affect supply current.
IN
WDO Logic high. The open circuit voltage is equal to
V
.
OUT
. The input voltage
OUT
PFI The Power Fail Comparator is turned off and
CE
OUT
has no effect on the Power Fail Output.
PFO Logic low.
t
= RESET TIME
1
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2–V1
Figure 6. Chip Enable Timing
Power Fail Warning Comparator
An additional comparator is provided for early warning of failure in the microprocessor’s power supply. The Power Fail Input
(PFI) is compared to an internal +1.3 V reference. The Power
REV. 0
CE
IN
CEIN is ignored. It is internally disconnected
from its internal pullup and does not source or
sink current as long as its input voltage is between GND and V
not affect supply current.
CE
OUT
Logic high. The open circuit voltage is equal to
V
.
OUT
OSC IN OSC IN is ignored.
OSC SEL OSC SEL is ignored.
–7–
. The input voltage does
OUT
Page 8
ADM696/ADM697–Typical Performance Curves
53
49
20 120
52
50
40
51
1008060
VCC = +5V
TEMPERATURE –
°
C
RESET ACTIVE TIME – ms
5.5
3.0
2.0
10 100 100001000
4.5
2.5
3.5
4.0
5.0
TIME DELAY – ms
V
CC
– Volts
TA = +25°C
5.00
VCC = +5V
= +25°C
T
A
4.95
– V
4.90
OUT
V
4.85
4.80
0 100
Figure 8. V
2.80
2.79
– V
2.78
OUT
V
2.77
20
SLOPE = 1.5Ω
vs. I
OUT
SLOPE = 20Ω
I
– mA
OUT
Normal Operation
OUT
VCC = 0V
V
BATT
T
A
806040
= +2.8V
= +25°C
Figure 11. RESET Active Time vs. Temperature
A4
3.36 V
100
90
10
0%
2.76
1.303
1.302
1.301
1.300
PFI INPUT THRESHOLD – V
1.299
Figure 10. PFI Input Threshold vs. Temperature
0 1000
200
I
– µA
OUT
Figure 9. V
20 120
40
vs. Battery Backup
OUT
TEMPERATURE – °C
800600400
1008060
1V
1V
500ms
Figure 12. RESET Output Voltage vs. Supply Voltage
Figure 13. RESET Timeout Delay vs. V
CC
–8–
REV. 0
Page 9
ADM696/ADM697
APPLICATIONS INFORMATION
Increasing the Drive Current (ADM696)
If the continuous output current requirements at V
100 mA or if a lower V
CC–VOUT
voltage differential is desired,
OUT
exceeds
an external PNP pass transistor may be connected in parallel
with the internal transistor. The BATT ON output (ADM696)
can directly drive the base of the external transistor.
+5V
INPUT
POWER
0.1µF
BATTERY
PNP TRANSISTOR
V
CC
V
BATT
ADM696
BATT
ON
0.1µF
V
OUT
Figure 14. Increasing the Drive Current
Using a Rechargeable Battery for Backup (ADM696)
If a capacitor or a rechargeable battery is used for backup, then
the charging resistor should be connected to V
since this
OUT
eliminates the discharge path that would exist during powerdown if the resistor is connected to V
+5V
INPUT
POWER
0.1µF
RECHARGABLE
BATTERY
V
V
BATT
CC
CC
V
OUT
I =
R
ADM696
.
– V
BATT
R
0.1µF
V
OUT
Figure 15. Rechargeable Battery
Adding Hysteresis to the Power Fail Comparator
For increased noise immunity, hysteresis may be added to the
power fail comparator. Since the comparator circuit is noninverting, hysteresis can be added simply by connecting a resistor
between the PFO output and the PFI input as shown in Figure 16. When PFO is low, resistor R3 sinks current from the
summing junction at the PFI pin. When PFO is high, the series
combination of R3 and R4 source current into the PFI summing
junction. This results in differing trip levels for the comparator.
Alternate Watchdog Input Drive Circuits
The watchdog feature can be enabled and disabled under program control by driving WDI with a 3-state buffer (Figure 17a).
When three-stated, the WDI input will float thereby disabling
the watchdog timer.
This circuit is not entirely foolproof, and it is possible that a
software fault could erroneously 3-state the buffer. This would
then prevent the ADM69x from detecting that the microprocessor is no longer operating correctly. In most cases a better
+5V
+7V TO +15V
INPUT
POWER
7805
V
R1
R2
= 1.3V (1+ ––– + –––
V
H
VL = 1.3V (1+ ––– – –––––––––––––
ASSUMING R
HYSTERESIS V
PFI
ADM69x
R
R
1
1
R
R
3
2
R
R1 (5V – 1.3V)
1
R
1.3V (R
2
R3 THEN
< <
4
– VL = 5V (–––
H
1.3V
)
3 + R4
R
R
CC
PFO
R3
)
)
1
)
2
R4
TO
µP NMI
Figure 16. Adding Hysteresis to the Power Fail Comparator
method is to extend the watchdog period rather than disabling
the watchdog. This may be done under program control using
the circuit shown in Figure 17b. When the control input is high,
the OSC SEL pin is low and the watchdog timeout is set by the
external capacitor. A 0.01 µF capacitor sets a watchdog timeout
delay of 100 s. When the control input is low, the OSC SEL pin
is driven high, selecting the internal oscillator. The 100 ms or
the 1.6 s period is chosen, depending on which diode in Figure 17b is used. With D1 inserted, the internal timeout is set at
100 ms while with D2 inserted the timeout is set at 1.6 s.
WATCHDOG
STROBE
CONTROL
INPUT
WDI
ADM69x
Figure 17a. Programming the Watchdog Input
CONTROL
INPUT*
D1
D2
OSC SEL
ADM69x
OSC IN
*LOW = INTERNAL TIMEOUT
HIGH = EXTERNAL TIMEOUT
Figure 17b. Programming the Watchdog Input
REV. 0
–9–
Page 10
ADM696/ADM697
Replacing the Back-Up Battery
When changing the back-up battery with system power on, spurious resets can occur when the battery is removed. This occurs
because the leakage current flowing out of the V
charge up the stray capacitance. If the voltage on V
within 50 mV of V
, a reset pulse is generated.
CC
BATT
pin will
reaches
BATT
If spurious resets during battery replacement are acceptable,
then no action is required. If not, then one of the following solutions should be considered:
1. A capacitor from V
to GND. This gives time while the
BATT
capacitor is charging up to change the battery. The leakage
current will charge up the external capacitor towards the
V
level. The time taken is related to the charging current,
CC
the size of external capacitor and the voltage differential between the capacitor and the charging voltage supply.
t = C
EXT
× V
DIFF
/I
The maximum leakage (charging) current is 1 µA over tem-
perature and V
DIFF
= VCC V
. Therefore, the capacitor
BATT
size should be chosen such that sufficient time is available to
make the battery replacement.
= T
C
EXT
If a replacement time of 5 s is allowed and assuming a V
of 4.5 V and a V
BATT
2. A resistor from V
on V
from rising to within 50 mV of VCC during battery
BATT
REQD
(1 µA/(V
CC
– V
BATT
))
of 3 V,
C
= 3.33 µF
EXT
to GND. This will prevent the voltage
BATT
CC
replacement.
R = (V
– 50 mV)/1 µA
CC
Note that the resistor will discharge the battery slightly.
With a V
supply of 4.5 V, a suitable resistor is 4.3 MΩ.
CC
With a 3 V battery, this will draw around 700 nA. This will
be negligible in most cases.
TYPICAL APPLICATIONS
ADM696
Figure 18 shows the ADM696 in a typical power monitoring,
battery backup application. V
Under normal operating conditions with V
internally connected to V
decay and V
will be switched to V
OUT
CC
powers the CMOS RAM.
OUT
present, V
CC
OUT
is
. If a power failure occurs, VCC will
, thereby maintaining
BATT
power for the CMOS RAM.
Power Fail RESET
The VCC power supply is also monitored by the Low Line Input, LL
1.3 V.
. A RESET pulse is generated when LLIN falls below
IN
RESET will remain low for 50 ms after LLIN returns
above 1.3 V. This allows for a power-on reset and prevents repeated toggling of
Resistors R3 and R4 should be chosen to give the desired V
RESET if the VCC power supply is unstable.
CC
reset threshold.
Watchdog Timer
The Watchdog Timer Input (WDI) monitors an I/O line from
the µP system. This line must be toggled once every 1.6 s to
verify correct software execution. Failure to toggle the line indicates that the µP system is not correctly executing its program
and may be tied up in an endless loop. If this happens, a reset
pulse is generated to initialize the processor.
If the watchdog timer is not needed the WDI input should be
left floating.
Power Fail Detector
The Power Fail Input, PFI, monitors the input power supply via
a resistive divider network R1 and R2. This input is intended as
an early warning power fail input. The voltage on the PFI input
is compared with a precision 1.3 V internal reference. If the input voltage drops below 1.3 V, a power fail output (PFO) signal
is generated. This warns of an impending power failure and may
be used to interrupt the processor so that the system may be
shut down in an orderly fashion. The resistors in the sensing
network are ratioed to give the desired power fail threshold voltage V
. The threshold should be set at a higher voltage than the
T
RESET threshold so that there is sufficient time available to
complete the shutdown procedure before the processor is
RESET and power is lost.
+5V
R1
RESET
R3
R4
BATTERY
R2
+
PFI
LL
V
IN
BATT
V
CC
ADM696
RESET
GND
V
PFO
WDI
OUT
µP POWER
CMOS RAM
POWER
µP SYSTEM
µP RESET
µP NMI
I/O LINE
Figure 18a. ADM696 Typical Application Circuit A
Figure 18b shows a similar application for the ADM696 but in
this case the PFI input monitors the unregulated input to the
7805 voltage regulator. This gives an earlier warning of an impending power failure. It is useful with processors operating at
low speeds or where there are a significant number of housekeeping tasks to be completed before the power is lost.
INPUT
POWER
7805
R1
R2
R3
R4
3V
BATTERY
NC
RESET
0.1µF
V
CC
V
BATT
ADM696
PFI
GND
OSC IN
OSC SEL
LL
IN
LOW LINE WDO
SYSTEM STATUS
INDICATORS
BATT
ON
V
OUT
WDI
PFO
RESET
0.1µF
CMOS
RAM
V
CC
A0–A15
I/O LINE
NMI
RESET
µP
POWER
µP
Figure 18b. ADM696 Typical Application Circuit B
REV. 0–10–
Page 11
ADM696/ADM697
This application also shows an optional, external transistor
which may be used to provide in excess of 100 mA current on
. When VCC is higher than V
V
OUT
, the BATT ON output
BATT
goes low, providing 25 mA of base drive for the external PNP
transistor. The maximum current available is dependent on the
power rating of the external transistor.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Pin Plastic DIP (N-16)
1
6
PIN 1
1
0.840 (21.33)
0.745 (18.93)
0.210
(5.33)
0.200 (5.05)
0.125 (3.18)
0.022 (0.558)
0.014 (0.356)
0.100 (2.54)
BSC
0.070 (1.77)
0.045 (1.15)
RAM Write Protection
The ADM697 CE
CMOS RAM.
reset threshold. If LL
line drives the Chip Select inputs of the
OUT
CE
follows CEIN as long as LLIN is above the
OUT
falls below the reset threshold, CE
IN
OUT
goes high, independent of the logic level at CEIN. This prevents
the microprocessor from writing erroneous data into RAM during power-up, power-down, brownouts and momentary power
interruptions.
9
0.280 (7.11)
0.240 (6.10)
8
0.325 (8.25)
0.060 (1.52)
0.015 (0.38)
0.150
(3.81)
SEATING
PLANE
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
PIN 1
SEATING
PLANE
0.299
(7.60)
0.012
(0.3)
0.200
(5.08)
MAX
0.022 (0.558)
0.014 (0.356)
16
1
16
1
0.413 (10.50)
0.05 (1.27)
REF
16-Pin Cerdip (Q-16)
9
0.310 (7.87)
0.220 (5.59)
8
0.840 (21.34) MAX
0.100 (2.54)
BSC
0.070 (1.78)
0.30 (0.76)
0.060 (1.52)
0.015 (0.38)
16-Lead SOIC (R-16)
9
0.419
(10.65)
8
0.030
(0.75)
0.104
(2.65)
0.019 (0.49)
0.013
(0.32)
0.150
(3.81)
MIN
0.320 (8.13)
0.290 (7.37)
0.015 (0.381)
0.008 (0.204)
0.042
(1.07)
REV. 0
–11–
Page 12
C1783–18–4/93
–12–
PRINTED IN U.S.A.
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