Page 1
Low Voltage Supervisory Circuits with
Watchdog and Manual Reset in 5-Lead SOT-23
Preliminary Technical Data
FEATURES
Precision low voltage monitoring down to 1.8 V
9 reset threshold options:
1.58 V to 4.63 V
140 ms (min) reset timeout
Watchdog timer with 1.6s timeout
Manual reset input
Reset output stages
Push-pull active-low
Open-drain active-low
Push-pull active-high
Low power consumption (3 µA)
Guaranteed reset output valid to V
Power supply glitch immunity
Specified from –40°C to +125°C
5-lead SOT-23 package
APPLICATIONS
Microprocessor systems
Computers
Controllers
Intelligent instruments
Portable equipment
GENERAL DESCRIPTION
The ADM6821–ADM6825 are supervisory circuits that monitor
power supply voltage levels and code execution integrity in
microprocessor-based systems. As well as providing power on
reset signals, an on-chip watchdog timer can reset the
microprocessor if it fails to strobe within a preset timeout
period. A reset signal can also be asserted by means of an
external push-button, through a manual reset input. The parts
feature different combinations of watchdog input, manual reset
Table 1. Selection Table
Part No. Watchdog Timer Manual Reset
ADM6821 Yes Yes - Push-Pull
ADM6822 Yes Yes Open-Drain -
ADM6823 Yes Yes Push-Pull ADM6824 Yes - Push-Pull Push-Pull
ADM6825 - Yes Push-Pull Push-Pull
= 1 V
CC
ADM6821–ADM6825
FUNCTIONAL BLOCK DIAGRAM
V
ADM6823
V
MR
CC
V
REF
DEBOUNCE
GND
RESET
GENERATOR
WATCHDOG
DETECTOR
WDI
Figure 1.
input and output stage configuration, as shown in table 1.
Each part is available in a choice of nine reset threshold options
ranging from 1.58 V to 4.63 V. The reset and watchdog timeout
periods are fixed at 140 ms (min) and 1.6s (typ), respectively.
The ADM6821–ADM6825 are available in 5-lead SOT-23
packages and typically consume only 3 µA, making them
suitable for use in low power portable applications.
Output Stage
RESET
RESET
CC
RESET
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703 © 2005 Analog Devices, Inc. All rights reserved.
Page 2
ADM6821–ADM6825 Preliminary Technical Data
TABLE OF CONTENTS
Specifications..................................................................................... 3
Watchdog Input.............................................................................9
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configurations And Functional Descriptions ....................... 6
Typical Performance Characteristics ............................................. 7
Circuit Description........................................................................... 9
Reset Output ................................................................................. 9
Manual Reset Input ...................................................................... 9
REVISION HISTORY
Revision 0: Initial Version
Application Information................................................................ 10
Watchdog Input Current........................................................... 10
Negative-Going V
Ensuring Reset Valid to V
Watchdog Software Considerations......................................... 10
Outline Dimensions....................................................................... 11
ORDERING GUIDE.................................................................. 11
Transients ................................................ 10
CC
= 0 V............................................ 10
CC
Rev. PrB | Page 2 of 11
Page 3
Preliminary Technical Data ADM6821–ADM6825
SPECIFICATIONS
Table 1. VCC = 4. 5 V to 5.5 V for ADM682_L/M, VCC = 2.7 V to 3.6 V for ADM682_T/S/R, VCC = 2.1 V to 2.75 V for
ADM682_Z/Y, V
Parameter Min Typ Max Unit Test Conditions/Comments
SUPPLY
VCC Operating Voltage Range 1 5.5 V TA = 0°C to +85°C
1.2 V TA = -40°C to 125°C
Supply Current 10 20 µA
7 16 µA
RESET THRESHOLD VOLTAGE
ADM682_L
V
ADM682_M
V
ADM682_T
V
ADM682_S
V
ADM682_R
V
ADM682_Z
V
ADM682_Y
V
ADM682_W
ADM682_V
RESET THRESHOLD TEMPERATURE COEFFICIENT 60 ppm/°C
RESET THRESHOLD HYSTERESIS 10 mV
RESET TIMEOUT PERIOD 140 200 280 ms
VCC TO RESET DELAY 40 µs VTH − VCC = 100mV
RESET
Output Voltage
VOL 0.3 V V
0.3 V V
0.3 V VCC >=2.55V, I
0.4 V VCC>=4.25V, I
VOH 0.8 × VCC V V
0.8 × VCC V V
0.8 × VCC V V
RESET
Output leakage Current
RESET Output Voltage
VOL 0.3 V V
0.3 V V
0.4 V VCC >=4.75V, I
VOH 0.8 × VCC V V
0.8 × VCC V V
0.8 × VCC V V
0.8 × VCC V V
WATCHDOG INPUT (ADM6821/2/3/4)
Watchdog Timeout Period 1.12 1.6 2.40 s
= 1.53 V to 2.0 V for ADM682_W/V, TA = –40°C to +125°C, unless otherwise noted
CC
4.50 4.63 4.75 V
4.25 4.38 4.50 V
3.00 3.08 3.15 V
2.85 2.93 3.00 V
2.55 2.63 2.70 V
2.25 2.32 2.38 V
2.13 2.19 2.25 V
1.62 1.67 1.71 V
1.52 1.58 1.62 V
1 µA
WDI and MR unconnected,
V
=5.5V
CC
WDI and MR unconnected,
V
=3.6V
CC
>=1V, I
CC
>=1.2V, I
CC
>=1.8V, I
CC
>=3.15V, I
CC
>=4.75V, I
CC
RESET
>=1.8V, I
CC
>=3.15V, I
CC
> = 1V, I
CC
>=1.5V, I
CC
>=2.55V, I
CC
>=4.25V, I
CC
= 50µA
SINK
= 100µA
SINK
= 1.2mA
SINK
= 3.2mA
SINK
= 200µA
SOURCE
SOURCE
SOURCE
not asserted
= 500µA
SINK
= 1.2mA
SINK
= 3.2mA
SINK
= 1µA
SOURCE
= 100µA
SOURCE
SOURCE
SOURCE
= 500µA
= 800µA
= 500µA
= 800µA
Rev. PrB | Page 3 of 11
Page 4
ADM6821–ADM6825 Preliminary Technical Data
Parameter Min Typ Max Unit Test Conditions/Comments
WDI Pulse Width 50 ns
WDI Input Threshold
VIL 0.3 × VCC V
VIH 0.7 × VCC V
WDI Input Current 120 160 µA V
−20 −15 µA V
MANUAL RESET INPUT (ADM6821/2/3/5)
MR
Input Threshold
0.3 × V
V
CC
0.7 × VCC V
MR
Input Pulse Width
MR
Glitch Rejection
MR
Pull-up Resistance
MR
to Reset Delay
1 µs
100 ns
25 52 75
k⍀
200 ns
V
= 0.4 V, V
IL
= VCC, time average
WDI
= 0, time average
WDI
= 0.8×V
IH
CC
Rev. PrB | Page 4 of 11
Page 5
Preliminary Technical Data ADM6821–ADM6825
ABSOLUTE MAXIMUM RATINGS
Table 2. TA = 25°C, unless otherwise noted
Parameter Rating
VCC −0.3 V to +6 V
Output Current (RESET,
Operating Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +150°C
θJA Thermal Impedance
Lead Temperature
Soldering (10 sec) 300°C
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
RESET
)
20 mA
270°C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. PrB | Page 5 of 11
Page 6
ADM6821–ADM6825 Preliminary Technical Data
PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS
1
RESET
ADM6821
2
GND
MR
TOP VIEW
(Not to Scale)
3
Figure 2. ADM6821. Pin Configuration
RESET
1
ADM6824
2
GND
RESET
TOP VIEW
(Not to Scale)
3
V
5
CC
4
WDI
04535-0-002
Figure 3. ADM6822/ ADM6823 Pin Configuration
V
5
CC
4
WDI
04535-0-004
Figure 4. ADM6824 Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Name Description
1
RESET
(ADM6822/ADM6823/ADM6824/
ADM6825)
Active-Low Reset Output. Asserted whenever V
Open-Drain Output Stage for ADM6822.
Push-Pull Output Stage for ADM6823/ADM6824/ADM6825.
RESET (ADM6821) Active-High, Push Pull Reset Output
2 GND Ground
3
MR
(ADM6821/ADM6822/ADM6823)
Manual Reset Input. This is an active-low input which, when forced low for at least 1 µs,
generates a reset.
Features a 52 k⍀ internal pull-up.
RESET (ADM6824/ADM6825) Active-High Push-Pull Reset Output.
4
WDI
(ADM6821/ADM6822/ADM6823/
ADM6824)
MR
(ADM6825)
Watchdog Input. Generates a reset if the voltage on the pin remains low or high for the
duration of the watchdog timeout. The timer is cleared if a logic transition occurs on this
pin or if a reset is generated.
Manual Reset Input.
5 VCC Power Supply Voltage Being Monitored.
RESET
GND
MR
1
ADM6822/
2
ADM6823
TOP VIEW
(Not to Scale)
3
V
5
CC
4
WDI
04535-0-003
RESET
GND
RESET
1
ADM6825
2
TOP VIEW
(Not to Scale)
3
V
5
CC
4
MR
04535-0-004
Figure 5. ADM6825 Pin Configuration
is below the reset threshold, VTH.
CC
Rev. PrB | Page 6 of 11
Page 7
Preliminary Technical Data ADM6821–ADM6825
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 6. Supply Current vs. Temperature
Figure 7. Normalized RESET Timeout Period vs. Temperature
Figure 9. Normalized Watchdog Timeout Period vs. Temperature
Figure 10. Normalised RESET Threshold vs. Temperature
Figure 8. V
to RESET Output Delay vs. Temperature
CC
Figure 11.Maximum V
Rev. PrB | Page 7 of 11
Transient Duration vs. RESET Threshold Overdrive
CC
Page 8
ADM6821–ADM6825 Preliminary Technical Data
Figure 12. Voltage Output Low vs. I
SINK
Figure 13. Voltage Output High vs. I
SOURCE
Rev. PrB | Page 8 of 11
Page 9
Preliminary Technical Data ADM6821–ADM6825
CIRCUIT DESCRIPTION
The ADM6821/2/3/4/5 provide microprocessor supply voltage
supervision by controlling the microprocessor’s reset input.
Code-execution errors are avoided during power-up, powerdown, and brownout conditions by asserting a reset signal when
the supply voltage is below a preset threshold and by allowing
supply voltage stabilization with a fixed-timeout reset pulse
after the supply voltage rises above the threshold. In addition,
problems with microprocessor code execution can be
monitored and corrected with a watchdog timer
(ADM6821/2/3/4). By including watchdog strobe instructions
in microprocessor code, a watchdog timer can detect if the
microprocessor code breaks down or becomes stuck in an
infinite loop. If this happens, the watchdog timer asserts a reset
pulse that restarts the microprocessor in a known state. If the
user detects a problem with the system’s operation, a manual
reset input is available (ADM6821/2/3/5) to reset the
microprocessor by means of an external push-button, for
example.
RESET OUTPUT
The ADM6821/3 feature an active-low, push-pull reset output
while the ADM6822 features an active-low open drain reset
output. The ADM6824/5 feature dual active-low and activehigh push-pull reset outputs. For active-low and active-high
outputs, the reset signal is guaranteed to be logic low and logic
high respectively for V
down to 1 V.
CC
MANUAL RESET INPUT
The ADM6821/2/3/5 feature a manual reset input (MR) which,
when driven low, asserts the reset output. When
transitions
MR
from low to high, reset remains asserted for the duration of the
reset active timeout period before deasserting. The
MR
input
has a 52 k⍀ internal pull-up so that the input is always high
when unconnected. An external push-button switch can be
connected between
and ground so that the user can
MR
generate a reset. Debounce circuitry is integrated on-chip for
this purpose. Noise immunity is provided on the
input and
MR
fast, negative-going transients of up to 100 ns (typ) are ignored.
A 0.1 µF capacitor between
and ground provides additional
MR
noise immunity.
WATCHDOG INPUT
The ADM6821/2/3/4 feature a watchdog timer which monitors
microprocessor activity. A timer circuit is cleared with every
low-to-high or high-to-low logic transition on the watchdog
input pin (WDI), which detects pulses as short as 50 ns. If the
timer counts through the preset watchdog timeout period (t
reset is asserted. The microprocessor is required to toggle the
WDI pin to avoid being reset. Failure of the microprocessor to
toggle WDI within the timeout period therefore indicates a
code execution error, and the reset pulse generated restarts the
microprocessor in a known state.
WD
),
The reset output is asserted when V
threshold (V
), when MR is driven low or when WDI is not
TH
serviced within the watchdog timeout period (t
is below the reset
CC
). Reset
WD
remains asserted for the duration of the reset active timeout
period (t
) after VCC rises above the reset threshold, after MR
RP
transitions from low-to-high, or after the watchdog timer times
out. Figure 14 illustrates the behavior of the reset outputs.
V
V
RESET
RESET
CC
CC
1V
0V
V
CC
0V
V
CC
1V
0V
V
TH
t
RP
t
RP
Figure 14. Reset Timing Diagram
V
TH
t
RD
t
RD
04534-0-018
In addition to logic transitions on WDI, the watchdog timer is
also cleared by a reset assertion due to an undervoltage condition on V
or MR being pulled low. When reset is asserted, the
CC
watchdog timer is cleared and does not begin counting again
until reset deassserts. The watchdog timer can be disabled by
leaving WDI floating or by three-stating the WDI driver.
V
CC
V
CC
1V
0V
V
WDI
CC
0V
V
CC
0V
RESET
V
TH
t
RP
Figure 15. Watchdog Timing Diagram
t
WD
t
RD
04534-0-021
Rev. PrB | Page 9 of 11
Page 10
ADM6821–ADM6825 Preliminary Technical Data
APPLICATION INFORMATION
WATCHDOG INPUT CURRENT
In order to minimize watchdog input current (and minimize
overall power consumption), leave WDI low for the majority of
the watchdog timeout period. When driven high, WDI can draw
as much as 160 µA. Pulsing WDI low-high-low at a low duty
cycle reduces the effect of the large input current. When WDI is
unconnected, a window comparator disconnects the watchdog
timer from the reset output circuitry so that reset is not asserted
when the watchdog timer times out.
NEGATIVE-GOING VCC TRANSIENTS
To avoid unnecessary resets caused by fast power supply
transients, the ADM6821/2/3/4/5 are equipped with glitch
rejection circuitry. The typical performance characteristic in
Error! Reference source not found. plots V
transient
CC
duration versus the transient magnitude. The curves show
combinations of transient magnitude and duration for which a
reset is not generated for 4.63 V and 2.93 V reset threshold
parts. For example, with the 2.93 V threshold, a transient that
goes 100 mV below the threshold and lasts 8 µs typically does
not cause a reset, but if the transient is any bigger in magnitude
or duration, a reset is generated. An optional 0.1 µF bypass
capacitor mounted close to V
provides additional glitch
CC
rejection.
ENSURING RESET VALID TO VCC = 0 V
Both active-low and active-high reset outputs are guaranteed to
be valid for V
resistor with push-pull configured reset outputs, valid outputs
as low as 0 V are possible. For an active-low reset output,
for V
CC
a resistor connected between
output low when it is unable to sink current. For the active-high
case, a resistor connected between RESET and V
output high when it is unable to source current. A large
resistance such as 100 kΩ should be used so that it does not
overload the reset output when V
as low as 1V. However, by using an external
CC
and ground pulls the
RESET
is above 1 V.
CC
V
CC
V
CC
pulls the
CC
WATCHDOG SOFTWARE CONSIDERATIONS
In implementing the microprocessor’s watchdog strobe code,
quickly switching WDI low-high and then high-low
(minimizing WDI high time) is desirable for current
consumption reasons. However, a more effective way of using
the watchdog function can be considered.
A low-high-low WDI pulse within a given subroutine prevents
the watchdog timing out. However, if the subroutine becomes
stuck in an infinite loop, the watchdog could not detect this
because the subroutine continues to toggle WDI. A more
effective coding scheme for detecting this error involves using a
slightly longer watchdog timeout. In the program that calls the
subroutine, WDI is set high. The subroutine sets WDI low when
it is called. If the program executes without error, WDI is
toggled high and low with every loop of the program. If the
subroutine enters an infinite loop, WDI is kept low, the
watchdog times out, and the microprocessor is reset.
START
SET WDI
HIGH
PROGRAM
CODE
SUBROUTINE
SET WDI
LOW
RETURN
Figure 17. Watchdog Flow Diagram
V
CC
RESET
INFINITE LOOP:
WATCHDOG
TIMES OUT
04534-0-020
ADM6822/3/4/5
TBD
RESET
100k⍀
GND
Figure 16. Ensuring Reset Valid to V
ADM6821/4/5
GND
= 0 V
CC
100k⍀
RESET
Rev. PrB | Page 10 of 11
RESET
ADM6823
MR
WDI I/O
Figure 18. Typical Application Circuit
RESET
m P
Page 11
Preliminary Technical Data ADM6821–ADM6825
blank
OUTLINE DIMENSIONS
2.90 BSC
4 5
0.50
0.30
3
2.80 BSC
0.95 BSC
1.45 MAX
SEATING
PLANE
(RJ-5)
0.22
0.08
10°
5°
0°
0.60
0.45
0.30
1.60 BSC
1
2
PIN 1
1.30
1.15
0.90
0.15MAX
1.90
BSC
COMPLIANT TO JEDEC STANDARDS MO-178AA
Figure 19. 5-Lead Small Outline Transistor Package [SOT-23]
Dimensions shown in millimeters
ORDERING GUIDE
Table 4. ADM6821/2/3/4/5 Ordering Guide
ADM682_ _YRJZ-RL7
GENERIC NUMBER
(1 TO 5)
RESET
THRESHOLD
NUMBER
L: 4.63V
TEMPERATURE RANGE
Y: -40oC TO +125oC
M: 4.38V
T: 3.08V
S: 2.93V
R: 2.63V
Z: 2.32V
Y: 2.19V
W: 1.67V
V: 1.58V
Figure 2. Ordering Code Structure
1,2
Model
Reset
Threshold (V)
Reset Timeout
(ms)
Temperature
Range
ADM6823TYRJZ-RL7 3.08 140 –40°C to +125°C 3k RJ-5 N0C
ADM6823SYRJZ-RL7 2.93 140 –40°C to +125°C 3k RJ-5 N0C
1
ORDERING QUANTITY
RL7: 3,000 PIECE REEL
Z: LEAD FREE
PACKAGE CODE
RJ: 5-LEAD SOT-23
Quantity Package
Type
Branding
1
Complete the ordering code by inserting the part number and reset threshold suffixes from Table 4.
1
Contact Sales for the availability of nonstandard models.
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective companies.
Printed in the U.S.A.
PR04535-0-3/05(PrB)
Rev. PrB | Page 11 of 11
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