Page 1
5 V, Slew-Rate Limited, Half-Duplex and
V
V
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
FEATURES
EIA RS-485-/RS-422-compliant
Data rate options
ADM4850/ADM4854: 115 kbps
ADM4851/ADM4855: 500 kbps
ADM4852/ADM4856: 2.5 Mbps
ADM4853/ADM4857: 10 Mbps
Half- and full-duplex options
Full-Duplex RS-485/RS-422 Transceivers
FUNCTIONAL BLOCK DIAGRAMS
CC
ADM4850/ADM4851/
ADM4852/ADM4853
RO
RE
DE
R
A
B
Reduced slew rates for low EMI
True fail-safe receiver inputs
DI
D
5 μA (maximum) supply current in shutdown mode
Up to 256 transceivers on one bus
Outputs high-Z when disabled or powered off
−7 V to +12 V bus common-mode range
Thermal shutdown and short-circuit protection
Pin-compatible with the MAX308x
Specified over the −40°C to +85°C temperature range
Available in 8-lead SOIC, LFCSP, and MSOP packages
Qualified for automotive applications
RO
GND
Figure 1.
CC
ADM4854/ADM4855/
ADM4856/ADM4857
R
04931-001
A
B
APPLICATIONS
Low power RS-485 applications
EMI-sensitive systems
DTE-DCE interfaces
Industrial control
Packet switching
Local area networks
Level translators
DI
D
GND
Figure 2.
Z
Y
04931-028
GENERAL DESCRIPTION
The ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/
ADM4855/ADM4856/ADM4857 are differential line transceivers
suitable for high speed half- and full-duplex data communication on
multipoint bus transmission lines. They are designed for balanced
data transmission and comply with EIA Standards RS-485 and
RS-422. The ADM4850/ADM4851/ADM4852/ADM4853 are halfduplex transceivers that share differential lines and have separate
enable inputs for the driver and receiver. The full-duplex
ADM4854/ADM4855/ADM4856/ADM4857 transceivers have
dedicated differential line driver outputs and receiver inputs.
The parts have a 1/8-unit-load receiver input impedance, which
allows up to 256 transceivers on one bus. Because only one driver
should be enabled at any time, the output of a disabled or powered-down driver is three-stated to avoid overloading the bus.
The receiver inputs have a true fail-safe feature, which ensures
a logic high output level when the inputs are open or shorted.
This guarantees that the receiver outputs are in a known state
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
before communication begins and when communication ends.
The driver outputs are slew-rate limited to reduce EMI and data
errors caused by reflections from improperly terminated buses.
Excessive power dissipation caused by bus contention or by output
shorting is prevented with a thermal shutdown circuit.
The parts are fully specified over the commercial and industrial
temperature ranges and are available in 8-lead SOIC, LFCSP
(ADM4850/ADM4851/ADM4852/ADM4853), and MSOP
(ADM4850 only) packages.
Table 1. Selection Table
Part No. Half-/Full-Duplex Data Rate
ADM4850 Half 115 kbps
ADM4851 Half 500 kbps
ADM4852 Half 2.5 Mbps
ADM4853 Half 10 Mbps
ADM4854 Full 115 kbps
ADM4855 Full 500 kbps
ADM4856 Full 2.5 Mbps
ADM4857 Full 10 Mbps
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2004–2012 Analog Devices, Inc. All rights reserved.
Page 2
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
TABLE OF CONTENTS
Features.............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagrams............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
ADM4850/ADM4854 Timing Specifications........................... 4
ADM4851/ADM4855 Timing Specifications........................... 4
ADM4852/ADM4856 Timing Specifications........................... 5
ADM4853/ADM4857 Timing Specifications........................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 9
Test Circuits..................................................................................... 11
Switching Characteristics .............................................................. 12
Circuit Description......................................................................... 13
Slew-Rate Control ...................................................................... 13
Receiver Input Filtering............................................................. 13
Half-/Full-Duplex Operation ................................................... 13
High Receiver Input Impedance .............................................. 14
Three-State Bus Connection..................................................... 14
Shutdown Mode ......................................................................... 14
Fail-Safe Operation .................................................................... 14
Current Limit and Thermal Shutdown ................................... 14
Outline Dimensions....................................................................... 15
Ordering Guide .......................................................................... 16
Automotive Product................................................................... 16
REVISION HISTORY
1/12—Rev. C to Rev. D
Change to Features Section............................................................. 1
Changes to Ordering Guide.......................................................... 15
Added Automotive Products Section .......................................... 15
1/11—Rev. B to Rev. C
Change to Table 8, Pin 3 Description ............................................ 7
Changes to Figure 29...................................................................... 12
Changes to Ordering Guide.......................................................... 15
7/09—Rev. A to Rev. B
Added MSOP Package.................................................. Throughout
Changes to Table 2............................................................................ 3
Changes to Table 7............................................................................ 6
Added Figure 4; Renumbered Figures Sequentially..................... 7
Moved Typical Performance Characteristics Section .................. 8
Changes to Figure 24, Figure 27 ................................................... 11
Changes to Figure 29...................................................................... 12
Change to Shutdown Mode Section............................................. 13
Updated Outline Dimensions....................................................... 14
Changes to Ordering Guide.......................................................... 15
4/09—Rev. 0 to Rev. A
Changes to Ordering Guide.......................................................... 15
10/04—Revision 0: Initial Version
Rev. D | Page 2 of 16
Page 3
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
SPECIFICATIONS
VCC = 5 V ± 5%, TA = T
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Differential Output Voltage, VOD V
2.0 5 V R = 50 Ω (RS-422), see Figure 18
1.5 5 V R = 27 Ω (RS-485), see Figure 18
|V
| 1.5 5 V V
OD3
∆|VOD| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, see Figure 18
Common-Mode Output Voltage, VOC 3 V R = 27 Ω or 50 Ω, see Figure 18
∆|VOC| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, see Figure 18
Output Short-Circuit Current, V
Output Short-Circuit Current, V
DRIVER INPUT LOGIC
CMOS Input Logic Threshold Low 0.8 V
CMOS Input Logic Threshold High 2.0 V
CMOS Logic Input Current (DI) ±1 μA
DE Input Resistance to GND 220 kΩ
RECEIVER
Differential Input Threshold Voltage, VTH −200 −125 −30 mV −7 V < VOC < +12 V
Input Hysteresis 20 mV −7 V < VOC < +12 V
Input Resistance (A, B) 96 150 kΩ −7 V < VOC < +12 V
Input Current (A, B) 0.125 mA VIN = +12 V
−0.1 mA V
CMOS Logic Input Current (RE)
CMOS Output Voltage Low 0.4 V I
CMOS Output Voltage High 4.0 V I
Output Short-Circuit Current 7 85 mA V
Three-State Output Leakage Current ±2 μA 0.4 V ≤ V
POWER SUPPLY CURRENT
115 kbps Options (ADM4850/ADM4854) 5 μA
36 60 μA
100 160 μA DE = VCC
500 kbps Options (ADM4851/ADM4855) 5 μA
80 120 μA
120 200 μA DE = VCC
2.5 Mbps Options (ADM4852/ADM4856) 5 μA
250 400 μA
320 500 μA DE = VCC
10 Mbps Options (ADM4853/ADM4857) 5 μA
250 400 μA
320 500 μA DE = VCC
1
Guaranteed by design.
MIN
to T
, unless otherwise noted.
MAX
V R = ∞, see Figure 181
CC
= High −200 +200 mA −7 V < V
OUT
= Low −200 +200 mA −7 V < V
OUT
±1 μA
= −7 V to 12 V, see Figure 19
TST
< +12 V
OUT
< +12 V
OUT
= −7 V
IN
= +4 mA
OUT
= −4 mA
OUT
= GND or VCC
OUT
≤ 2.4 V
OUT
DE = 0 V, RE
DE = 0 V, RE
DE = 0 V, RE
DE = 0 V, RE
DE = 0 V, RE
DE = 0 V, RE
DE = 0 V, RE
DE = 0 V, RE
= VCC (shutdown)
= 0 V
= VCC (shutdown)
= 0 V
= VCC (shutdown)
= 0 V
= VCC (shutdown)
= 0 V
Rev. D | Page 3 of 16
Page 4
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
ADM4850/ADM4854 TIMING SPECIFICATIONS
VCC = 5 V ± 5%, TA = T
Table 3.
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Maximum Data Rate 115 kbps
Propagation Delay, t
Skew, t
70 ns R
SKEW
Rise/Fall Times, tR, tF 600 2400 ns R
Enable Time, tZH 2000 ns RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4850
Disable Time, tZL 2000 ns RL = 500 Ω, CL = 15 pF, see Figure 21, ADM4850
Enable Time from Shutdown 4000 ns RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4850
RECEIVER
Propagation Delay, t
Differential Skew, t
Enable Time 5 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4850
Disable Time 20 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4850
Enable Time from Shutdown 4000 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4850
Time to Shutdown 50 330 3000 ns ADM48501
1
The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
to T
MIN
, t
PLH
, t
PLH
255 ns CL = 15 pF, see Figure 22
SKEW
, unless otherwise noted.
MAX
600 2500 ns R
PHL
400 1000 ns CL = 15 pF, see Figure 22
PHL
= 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
LDIFF
= 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
LDIFF
= 54 Ω, C
LDIFF
L1
= CL2 = 100 pF, see Figure 20
ADM4851/ADM4855 TIMING SPECIFICATIONS
VCC = 5 V ± 5%, TA = T
Table 4.
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Maximum Data Rate 500 kbps
Propagation Delay, t
Skew, t
40 ns R
SKEW
Rise/Fall Times, tR, tF 200 600 ns R
Enable Time, tZH 1000 ns RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4851
Disable Time, tZL 1000 ns RL = 500 Ω, CL = 15 pF, see Figure 21, ADM4851
Enable Time from Shutdown 4000 ns RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4851
RECEIVER
Propagation Delay, t
Differential Skew, t
Enable Time 5 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4851
Disable Time 20 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4851
Enable Time from Shutdown 4000 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4851
Time to Shutdown 50 330 3000 ns ADM48511
1
The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
to T
MIN
, t
PLH
, t
PLH
250 ns CL = 15 pF, see Figure 22
SKEW
, unless otherwise noted.
MAX
250 600 ns R
PHL
400 1000 ns CL = 15 pF, see Figure 22
PHL
= 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
LDIFF
= 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
LDIFF
= 54 Ω, CL1 = C
LDIFF
= 100 pF, see Figure 20
L2
Rev. D | Page 4 of 16
Page 5
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
ADM4852/ADM4856 TIMING SPECIFICATIONS
VCC = 5 V ± 5%, TA = T
Table 5.
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Maximum Data Rate 2.5 Mbps
Propagation Delay, t
Skew, t
50 ns R
SKEW
Rise/Fall Times, tR, tF 140 ns R
Enable Time, tZH 180 ns RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4852
Disable Time, tZL 180 ns RL = 500 Ω, CL = 15 pF, see Figure 21, ADM4852
Enable Time from Shutdown 4000 ns RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4852
RECEIVER
Propagation Delay, t
Differential Skew, t
Enable Time 5 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4852
Disable Time 20 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4852
Enable Time from Shutdown 4000 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4852
Time to Shutdown 50 330 3000 ns ADM48521
1
The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
to T
MIN
, t
PLH
, t
PLH
50 ns CL = 15 pF, see Figure 22
SKEW
, unless otherwise noted.
MAX
50 180 ns R
PHL
55 190 ns CL = 15 pF, see Figure 22
PHL
= 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
LDIFF
= 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
LDIFF
= 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
LDIFF
ADM4853/ADM4857 TIMING SPECIFICATIONS
VCC = 5 V ± 5%, TA = T
Table 6.
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Maximum Data Rate 10 Mbps
Propagation Delay, t
Skew, t
10 ns R
SKEW
Rise/Fall Times, tR, tF 30 ns R
Enable Time, tZH 35 ns RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4853
Disable Time, tZL 35 ns RL = 500 Ω, CL = 15 pF, see Figure 21, ADM4853
Enable Time from Shutdown 4000 ns RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4853
RECEIVER
Propagation Delay, t
Differential Skew, t
Enable Time 5 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4853
Disable Time 20 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4853
Enable Time from Shutdown 4000 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4853
Time to Shutdown 50 330 3000 ns ADM48531
1
The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
to T
MIN
, t
PLH
, t
PLH
30 ns CL = 15 pF, see Figure 22
SKEW
, unless otherwise noted.
MAX
0 30 ns R
PHL
55 190 ns CL = 15 pF, see Figure 22
PHL
= 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
LDIFF
= 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
LDIFF
= 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
LDIFF
Rev. D | Page 5 of 16
Page 6
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter Rating
VCC to GND 6 V
Digital I/O Voltage (DE, RE, DI, RO)
Driver Output/Receiver Input Voltage −9 V to +14 V
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +125°C
θJA Thermal Impedance
SOIC 110°C/W
LFCSP 62°C/W
MSOP 133.1°C/W
Lead Temperature
Soldering (10 sec) 300°C
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
−0.3 V to V
+ 0.3 V
CC
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. D | Page 6 of 16
Page 7
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
A
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
DM4850/ADM4851/
ADM4852/ADM4853
PIN 1
1RO
INDICATOR
RO
RE
DE
DI
1
ADM4850/
ADM4851/
2
ADM4852/
ADM4853
TOP VIEW
4
(Not to Scale)
8
V
CC
7
B
A
63
GND
5
04931-002
Figure 3. ADM4850/ADM4851/ADM4852/ADM4853 Pin Configuration,
NOTES
1. THE EXPOSED PADDLE ON THE UNDERSIDE
OF THE PACKAGE SHOULD BE SOLDERED
RELIABILITY OF THE SOLDER JOINTSAND
THE PACKAGE.
Figure 4. ADM4850/ADM4851/ADM4852/ADM4853 Pin Configuration, LFCSP
2RE
TOP VIEW
3DE
(Not to Scale)
4DI
TO THE GROUND PL ANE TO INCREASE THE
TO MAXIMIZE THE THERMAL CAPABILITY OF
SOIC and MSOP
Table 8. ADM4850/ADM4851/ADM4852/ADM4853 Pin Descriptions
Pin No. Mnemonic Description
1 RO Receiver Output. When RO is enabled, if (A − B) ≥ −30 mV, RO = high; if (A − B) ≤ −200 mV, RO = low.
2
Receiver Output Enable. A low level on this pin enables the receiver output, RO. A high level places RO
RE
into a high impedance state.
3 DE
Driver Output Enable. A high level on this pin enables the driver differential outputs, A and B. A low level
places them into a high impedance state.
4 DI
Driver Input. When the driver is enabled, a logic low on DI forces A low and B high, whereas a logic high
on DI forces A high and B low.
5 GND Ground.
6 A Noninverting Receiver Input A/Noninverting Driver Output A.
7 B Inverting Receiver Input B/Inverting Driver Output B.
8 V
CC
5 V Power Supply.
8V
CC
7B
6A
5GND
04931-029
Rev. D | Page 7 of 16
Page 8
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
1
V
ADM4854/
CC
ADM4855/
2
RO
ADM4856/
ADM4857
DI
TOP VIEW
4
GND
(Not to Scale)
Figure 5. ADM4854/ADM4855/ADM4856/ADM4857 Pin Configuration, SOIC
Table 9. ADM4854/ADM4855/ADM4856/ADM4857 Pin Descriptions
Pin No. Mnemonic Description
1 V
CC
5 V Power Supply.
2 RO Receiver Output. When RO is enabled, if (A − B) ≥ −30 mV, RO = high; if (A − B) ≤ −200 mV, RO = low.
3 DI
Driver Input. When the driver is enabled, a logic low on DI forces Y low and Z high, whereas a logic high
on DI forces Y high and Z low.
4 GND Ground.
5 Y Noninverting Driver Output.
6 Z Inverting Driver Output.
7 B Inverting Receiver Input.
8 A Noninverting Receiver Input.
8
A
7
B
Z
63
Y
5
04931-003
Rev. D | Page 8 of 16
Page 9
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
TYPICAL PERFORMANCE CHARACTERISTICS
400
350
300
250
200
150
ADM4853: DE = V
ADM4853: DE = GND
ADM4850: DE = V
CC
CC
0.40
0.35
0.30
0.25
100
UNLOADED SUPPLY CURRENT (μA)
50
0
–50 –25 0 25 50 75 100 125
TEMPERATURE (° C)
ADM4850: DE = GND
Figure 6. Unloaded Supply Current vs. Temperature
50
45
40
35
30
25
20
15
10
RECEIVER OUTPUT CURRENT (mA)
5
0
0 0.2 0.4 0.6 0.8 1. 0 1. 2 1.4 1.6 1.8 2.0
RECEIVER OUTPUT LOW VOLTAGE (V)
Figure 7. Receiver Output Current vs. Receiver Output Low Voltage
04931-014
04931-015
OUTPUT LOW VOLTAGE (V)
0.20
0.15
–50–250 255075100125
TEMPERATURE (
°
C)
Figure 9. Receiver Output Low Voltage vs. Temperature
4.6
4.5
4.4
4.3
4.2
OUTPUT HIGH VOLTAGE (V)
4.1
4.0
–50 –25 0 25 50 75 100 125
TEMPERATURE (° C)
Figure 10. Receiver Output High Voltage vs. Temperature
04931-017
04931-018
5
0
–5
–10
–15
RECEIVER OUTPUT CURRENT (mA)
–20
3.5 4.0 4.5 5.0 5.5
RECEIVER OUTPUT HIGH VOLTAGE (V)
Figure 8. Receiver Output Current vs. Receiver Output High Voltage
04931-016
Rev. D | Page 9 of 16
90
80
70
60
50
40
30
20
DRIVER OUTPUT CURRENT (mA)
10
0
0 0.5 1.0 1.5 2.0 2.5 3. 0 3.5 4.0 4. 5 5.0
DIFFERENTIAL OUTPUT VOLTAGE (V)
Figure 11. Driver Output Current vs. Differential Output Voltage
04931-019
Page 10
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
120
100
80
800
700
600
500
ADM4855
60
40
OUTPUT CURRENT (mA)
20
0
0 0.5 1.0 1.5 2.0 2.5 3. 0 3.5 4.0 4. 5 5.0
OUTPUT VOLTAGE (V)
Figure 12. Output Current vs. Driver Output Low Voltage
–10
–30
–50
–70
OUTPUT CURRENT (mA)
–90
–110
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
OUTPUT VOLTAGE (V)
Figure 13. Output Current vs. Driver Output High Voltage
04931-020
04931-021
400
300
200
PROPAGATION DELAY (ns)
ADM4853
100
0
–50 –25 0 25 50 75 100 125
TEMPERATURE (° C)
Figure 15. Receiver Propagation Delay vs. Temperature
3
2
4
CH1 1.00V
CH3 2.00V
Ω
Ω
B
W
B
W
CH2 1.00V
CH4 5.00VΩ
B
W
Ω
M 400ns CH3 2.00V
04931-024
Figure 16. Driver/Receiver Propagation Delay (ADM4855, 500 kbps)
04931-023
450
400
350
ADM4855
1
300
250
200
150
PROPAGATION DELAY (ns)
100
50
0
–50 –25 0 25 50 75 100 125
ADM4853
TEMPERATURE (° C)
Figure 14. Driver Propagation Delay vs. Temperature
04931-022
2
4
B
CH1 2.00VΩ
CH3 1.00VΩ
W
CH2 1.00VΩ M 50. 0ns CH1 480mV
B
W
CH4 5.00VΩ
Figure 17. Driver/Receiver Propagation Delay (ADM4857, 4 Mbps)
04931-025
Rev. D | Page 10 of 16
Page 11
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
TEST CIRCUITS
V
R
V
OD
R
Figure 18. Driver Voltage Measurement
A
0V OR 3V
V
OC
04931-004
DE IN
DE
S1
C
B
V
L
Figure 21. Driver Enable/Disable
R
OUT
CC
L
S2
04931-007
375Ω
V
V
OD3
60Ω
375Ω
TST
04931-005
Figure 19. Driver Voltage Measurement over Common-Mode Voltage Range
A
R
LDIFF
B
C
L1
C
L2
04931-006
Figure 20. Driver Propagation Delay
A
V
RE
B
OUT
C
L
04931-008
Figure 22. Receiver Propagation Delay
+1.5V
–1.5V
RE IN
S1
RE
C
L
V
CC
R
L
S2
V
OUT
04931-009
Figure 23. Receiver Enable/Disable
Rev. D | Page 11 of 16
Page 12
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
V
A
A
A
SWITCHING CHARACTERISTICS
3
1.5V
0V
B
V
OD
A
5V
0V
1/2V
OD
90% POINT
10% POINT
t
PLH
t
=
|t
SKEW
PLH –tPHL
t
R
Figure 24. Driver Propagation Delay, Rise/Fall Timing
, B
0V
1.5V
DE
t
PHL
, B
|
90% POINT
10% POINT
t
F
04931-010
, B
1.5V
t
ZL
t
ZH
2.3V
2.3V
1.5V
t
LZ
t
HZ
Figure 26. Driver Enable/Disable Timing
RE
0V
t
1.5V
ZL
1.5V
t
LZ
V
V
OL
OH
+ 0.5V
– 0.5V
3V
0V
V
OL
V
OH
0V
04931-012
3V
0V
1.5V
OUTPUT LOW
t
ZH
OUTPUT HIGH
1.5V
V
+ 0.5V
OL
t
HZ
V
– 0.5V
OH
Figure 27. Receiver Enable/Disable Timing
V
OL
V
OH
04931-013
RO
t
PLH
1.5V 1.5V
t
=
|t
SKEW
PLH –tPHL
t
PHL
|
Figure 25. Receiver Propagation Delay
RO
V
OH
V
OL
04931-011
RO
0V
Rev. D | Page 12 of 16
Page 13
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
VCCV
CIRCUIT DESCRIPTION
The ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/
ADM4855/ADM4856/ADM4857 are high speed RS-485/
RS-422 transceivers offering enhanced performance over
industry-standard devices. All devices in the family contain
one driver and one receiver, but offer a choice of performance
options. The devices feature true fail-safe operation, which
means that a logic high receiver output is guaranteed when
the receiver inputs are open-circuit or short-circuit, or when
they are connected to a terminated transmission line with all
drivers disabled (see the Fail-Safe Operation section).
SLEW-RATE CONTROL
The ADM4850 and ADM4854 feature a controlled slew-rate
driver that minimizes electromagnetic interference (EMI) and
reduces reflections caused by incorrectly terminated cables,
allowing error-free data transmission rates up to 115 kbps. The
ADM4851 and ADM4855 offer a higher limit on driver output
slew rate, allowing data transmission rates up to 500 kbps. The
driver slew rates of the ADM4852 and ADM4856 and the
ADM4853 and ADM4857 are not limited, offering data
transmission rates up to 2.5 Mbps and 10 Mbps, respectively.
RECEIVER INPUT FILTERING
The receivers of all the devices incorporate input hysteresis. In
addition, the receivers of the 115 kbps ADM4850 and ADM4854
and the 500 kbps ADM4851 and ADM4855 incorporate input
filtering. This enhances noise immunity with differential signals
that have very slow rise and fall times. However, it causes the
propagation delay to increase by 20%.
HALF-/FULL-DUPLEX OPERATION
Half-duplex operation implies that the transceiver can transmit
and receive, but it can do only one of these at any given time. However, with full-duplex operation, the transceiver can transmit and
receive simultaneously. The ADM4850/ADM4851/ADM4852/
ADM4853 are half-duplex devices in which the driver and the
receiver share differential bus terminals. The ADM4854/
ADM4855/ADM4856/ADM4857 are full-duplex devices that
have dedicated driver output and receiver input pins. Figure 28
and Figure 29 show typical half- and full-duplex topologies.
ADM4850/ADM4851/
ADM4852/ADM4853
RO
RE
DE
DI
D
R
A
B
AB
R
ADM4852/ADM4853
ADM4850/ADM4851/
RO RE DE DI
MAXIMUM NUMBER OF TRANSCEIVERS ON BUS: 256
D
AB
R
ADM4852/ADM4853
ADM4850/ADM4851/
RO RE DE DI
D
ADM4850/ADM4851/
ADM4852/ADM4853
A
B
R
D
RO
RE
DE
DI
04931-026
Figure 28. Typical Half-Duplex RS-485 Network Topology
CC
ADM4854/ADM4855/
ADM4856/ADM4857
RO
DI
R
D
GND
A
B
Z
Y
Figure 29. Typical Full-Duplex Point-to-Point RS-485 Network Topology
Rev. D | Page 13 of 16
ADM4854/ADM4855/
ADM4856/ADM4857
Y
D
Z
B
R
A
GND
DI
RO
04931-027
Page 14
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
HIGH RECEIVER INPUT IMPEDANCE
The input impedance of the ADM4850/ADM4851/ADM4852/
ADM4853/ADM4854/ADM4855/ADM4856/ADM4857 receivers
is 96 kΩ, which is eight times higher than the standard RS-485
unit load of 12 kΩ. This 96 kΩ impedance enables a standard
driver to drive 32 unit loads or to be connected to 256 ADM4850/
ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/
ADM4856/ADM4857 receivers. An RS-485 bus, driven by a
single standard driver, can be connected to a combination of
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/
ADM4855/ADM4856/ADM4857 devices and standard unit
load receivers, up to an equivalent of 32 standard unit loads.
THREE-STATE BUS CONNECTION
The half-duplex parts (ADM4850/ADM4851/ADM4852/
ADM4853) have a driver enable (DE) pin that enables the
driver outputs when taken high, or puts the driver outputs
into a high impedance state when taken low. Similarly, the
half-duplex devices have an active low receiver enable (
Taking this pin low enables the receiver, whereas taking it high
puts the receiver outputs into a high impedance state. This
allows several driver outputs to be connected to an RS-485 bus.
Note that only one driver should be enabled at a time, but that
many receivers can be enabled.
RE
) pin.
SHUTDOWN MODE
The ADM4850/ADM4851/ADM4852/ADM4853 have a low
RE
power shutdown mode, which is enabled by taking
DE low. If shutdown mode is not used, the fact that DE is active
high and
device between transmit and receive by tying DE and
If DE is driven low and
the devices are guaranteed not to enter shutdown mode. If DE
is driven low and
devices are guaranteed to enter shutdown mode.
RE
is active low offers a convenient way of switching the
RE
is driven high for less than 50 ns,
RE
is driven high for at least 3000 ns, the
high and
RE
together.
FAIL-SAFE OPERATION
The ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/
ADM4855/ADM4856/ADM4857 offer true fail-safe operation
while remaining fully compliant with the ±200 mV EIA/TIA-485
standard. A logic high receiver output is generated when the
receiver inputs are shorted together or open circuit, or when
they are connected to a terminated transmission line with all
drivers disabled. This is done by setting the receiver threshold
between −30 mV and −200 mV. If the differential receiver input
voltage (A − B) is greater than or equal to −30 mV, RO is logic
high. If (A − B) is less than or equal to −200 mV, RO is logic low.
In the case of a terminated bus with all transmitters disabled,
the differential input voltage of the receiver is pulled to 0 V by
the internal circuitry of the ADM4850/ADM4851/ADM4852/
ADM4853/ADM4854/ADM4855/ADM4856/ADM4857, which
results in a logic high with 30 mV minimum noise margin.
CURRENT LIMIT AND THERMAL SHUTDOWN
The ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/
ADM4855/ADM4856/ADM4857 incorporate two protection
mechanisms to guard the drivers against short circuits, bus contention, or other fault conditions. The first is a current limiting
output stage, which protects the driver against short circuits over
the entire common-mode voltage range by limiting the output
current to approximately 70 mA. Under extreme fault conditions
where the current limit is not effective, a thermal shutdown circuit
puts the driver outputs into a high impedance state if the die
temperature exceeds 150°C, and does not turn them back on
until the temperature falls to 130°C.
Rev. D | Page 14 of 16
Page 15
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DE SIGN.
85
1
1.27 (0.0500)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
BSC
6.20 (0.2441)
5.80 (0.2284)
4
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
8°
0°
0.25 (0.0098)
0.17 (0.0067)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
0.40 (0.0157)
Figure 30. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
3.20
3.00
45°
012407-A
2.80
PIN 1
IDENTIFIER
0.95
0.85
0.75
0.15
0.05
COPLANARITY
Figure 31. 8-Lead Mini Small Outline Package [MSOP]
3.20
3.00
2.80
815
0.65 BSC
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
5.15
4.90
4.65
4
1.10 MAX
0.40
0.25
6°
0°
(RM-8)
Dimensions shown in millimeter
15° MAX
0.23
0.09
0.80
0.55
0.40
10-07-2009-B
s
3.25
3.00 SQ
2.75
2.95
0.70 MAX
0.65 TYP
0.30
0.23
0.18
2.75 SQ
2.55
0.05 MAX
0.01 NOM
0.20 REF
INDICATOR
0.90 MAX
0.85 NOM
SEATING
PLANE
PIN 1
12° MAX
TOP
VIEW
Figure 32. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]
3 mm × 3 mm Body, Very Thin, Dual Lead
Dimensions shown in millimeters
0.60 MAX
0.50
0.40
0.30
(CP-8-2)
0.60 MAX
5
(BOTTOM VIEW)
4
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CO NFIGURATION AND
FUNCTIO N DESCRIPT IONS
SECTION OF THIS DATA SHEET.
EXPOSED
PAD
0.50
BSC
8
1
1.89
1.74
1.59
1.60
1.45
1.30
PIN 1
INDICATOR
90308-B
Rev. D | Page 15 of 16
Page 16
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
ORDERING GUIDE
Model1, 2 Temperature Range Package Description Package Option Branding
ADM4850ACPZ-REEL7 −40°C to +85°C 8-Lead LFCSP_VD CP-8-2 M8Q
ADM4850ARZ −40°C to +85°C 8-Lead SOIC_N R-8
ADM4850ARZ-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8
ADM4850ARMZ −40°C to +85°C 8-Lead MSOP RM-8 M8Q
ADM4850ARMZ-REEL7 −40°C to +85°C 8-Lead MSOP RM-8 M8Q
ADM4851ARZ −40°C to +85°C 8-Lead SOIC_N R-8
ADM4851ARZ-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8
ADM4852ACPZ-REEL7 −40°C to +85°C 8-Lead LFCSP_VD CP-8-2 M9M
ADM4852ARZ −40°C to +85°C 8-Lead SOIC_N R-8
ADM4852ARZ-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8
ADM4853ACPZ-REEL7 −40°C to +85°C 8-Lead LFCSP_VD CP-8-2 F0B
ADM4853ARZ −40°C to +85°C 8-Lead SOIC_N R-8
ADM4853ARZ-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8
ADM4853WARZ-RL7 −40°C to +85°C 8-Lead SOIC_N R-8
ADM4854ARZ −40°C to +85°C 8-Lead SOIC_N R-8
ADM4855AR-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8
ADM4855ARZ −40°C to +85°C 8-Lead SOIC_N R-8
ADM4856ARZ −40°C to +85°C 8-Lead SOIC_N R-8
ADM4856ARZ-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8
ADM4857ARZ −40°C to +85°C 8-Lead SOIC_N R-8
ADM4857ARZ-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8
1
Z = RoHS Compliant Part.
2
W = qualified for automotive products.
AUTOMOTIVE PRODUCT
The ADM4853WARZ-RL7 model is available with controlled manufacturing to support the quality and reliability requirements of
automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore,
designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for
use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and
to obtain the specific Automotive Reliability reports for this model.
©2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04931-0-1/12(D)
Rev. D | Page 16 of 16
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