Page 1
615 kV ESD Protected, EMC Compliant
D
R
A
B
DI
DE
RE
RO
ADM483E
a
FEATURES
Robust RS-485 Transceiver
15 kV ESD Protection Using HBM
2 kV EFT Protection Meets IEC1000-4-4
High EM Immunity Meets IEC1000-4-3
Reduced Slew Rate for Low EM Interference
250 kbps Data Rate
Single +5 V 6 10% Supply
–7 V to +12 V Bus Common-Mode Range
12 kV Input Impedance
Short Circuit Protection
Excellent Noise Immunity
36 mA Supply Current
0.1 mA Shutdown Current
APPLICATIONS
Low Power RS-485 Systems
Electrically Harsh Environments
EMI Sensitive Applications
DTE-DCE Interface
Packet Switching
Local Area Networks
Slew Rate Limited, EIA RS-485 Transceiver
ADM483E
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The ADM483E is a robust, low power differential line transceiver suitable for communication on multipoint bus transmission lines. Internal protection against electrostatic discharge
(ESD), electrical fast transient (EFT) and electromagnetic
immunity (EMI) allows operation in electrically harsh environments. ESD protection on the I-O lines meets ±15 kV when
tested using the Human Body Model. EFT protection meets
± 2 kV in accordance with IEC1000-4-4, while EMI immunity is
in excess of 10 V/m meeting IEC1000-4-3.
The level of unwanted emissions is also carefully controlled
using slew limiting on the driver outputs. This reduces reflections with improperly terminated cables and also minimizes
electromagnetic interference. The controlled slew rate limits the
data rate to 250 kbps.
The ADM483E is intended for balanced data transmission and
complies with both EIA Standards RS-485 and RS-422. It
contains a differential line driver and a differential line receiver
and is suitable for half duplex data transmission, as the driver
and receiver share the same differential pins.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
The input impedance on the ADM483E is 12 kΩ, allowing up
to 32 transceivers on the bus.
The ADM483E operates from a single +5 V ± 10% power supply. Excessive power dissipation caused by bus contention or by
output shorting is prevented by a thermal shutdown circuit. This
feature forces the driver output into a high impedance state if,
during fault conditions, a significant temperature increase is
detected in the internal driver circuitry.
The receiver contains a fail-safe feature that results in a logic
high output state if the inputs are unconnected (floating).
The ADM483E is fabricated on BiCMOS, an advanced mixed
technology process combining low power CMOS with robust
bipolar technology.
It is fully specified over the industrial temperature range and is
available in 8-lead DIP and SOIC packages.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703 © Analog Devices, Inc., 1997
Page 2
ADM483E–SPECIFICATIONS
(VCC = +5 V 6 10%. All specifications T
MIN
to T
unless otherwise noted)
MAX
Parameter Min Typ Max Units Test Conditions/Comments
DRIVER
Differential Output Voltage, V
OD
5.0 V V
= 5.25 V. R = ∞, Figure 1
CC
2.0 5.0 V R = 50 Ω (RS-422), Figure 1
1.5 5.0 V R = 27 Ω (RS-485), Figure 1
1.5 5.0 V V
∆|V
| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, Figure 1
OD
Common-Mode Output Voltage V
∆|V
| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω
OC
Output Short Circuit Current (V
Output Short Circuit Current (V
CMOS Input Logic Threshold Low, V
CMOS Input Logic Threshold High, V
OC
= High) 250 mA –7 V ≤ VO ≤ +12 V
OUT
= Low) 250 mA –7 V ≤ VO ≤ +12 V
OUT
INL
INH
2.0 1.4 V
3 V R = 27 Ω or 50 Ω, Figure 1
1.4 0.8 V
= –7 V to +12 V, Figure 2, V
TST
≥ 4.75 V
CC
Logic Input Current (DE, DI) ±1.0 µA
RECEIVER
Differential Input Threshold Voltage, V
Input Voltage Hysteresis, ∆V
TH
TH
Input Resistance 12 kΩ –7 V ≤ V
Input Current (A, B) +1 mA V
Logic Enable Input Current (
CMOS Output Voltage Low, V
CMOS Output Voltage High, V
RE) ±1 µA
OL
OH
Short Circuit Output Current 7 85 mA V
Three-State Output Leakage Current ±1.0 µA 0.4 V ≤ V
–0.2 +0.2 V –7 V ≤ VCM ≤ +12 V
70 mV VCM = 0 V
≤ +12 V
CM
= 12 V
–0.8 mA V
0.4 V I
4.0 V I
IN
= –7 V
IN
= +4.0 mA
OUT
= –4.0 mA
OUT
= GND or V
OUT
≤ +2.4 V
OUT
CC
POWER SUPPLY CURRENT Outputs Unloaded, Receivers Enabled
I
(ADM483E) 36 60 µA DE = 0 V (Disabled) RE = 0 V
CC
Supply Current in Shutdown 0.1 10 µA DE = 0 V, RE = V
270 360 µA DE = 5 V (Enabled) =
CC
RE = 0 V
ESD/EFT IMMUNITY
ESD Protection ±15 kV HBM Air Discharge. A, B Pins
±3.5 kV HBM 3015.7 Contact Discharge. All Pins
EFT Protection ±2 kV IEC1000-4-4, A, B Pins
EMI Immunity 10 V/m IEC1000-4-3
Specifications subject to change without notice.
TIMING SPECIFICATIONS
(VCC = +5 V 6 10%. All specifications T
MIN
to T
unless otherwise noted.)
MAX
Parameter Min Typ Max Units Test Conditions/Comments
DRIVER
Propagation Delay Input to Output T
Driver O/P to
Driver Rise/Fall Time T
O/P T
SKEW
R
, T
F
Driver Enable to Output Valid 250 2000 ns R
Driver Disable Timing 300 3000 ns R
PLH
, T
250 2000 ns R
PHL
100 800 ns R
250 2000 ns R
Diff = 54 Ω C
L
Diff = 54 Ω C
L
Diff = 54 Ω C
L
= 500 Ω, C
L
= 500 Ω, C
L
= CL2 = 100 pF, Figure 5
L1
= CL2 = 100 pF, Figure 5
L1
= CL2 = 100 pF, Figure 5
L1
= 100 pF, Figure 3
L
= 15 pF, Figure 3
L
RECEIVER
Propagation Delay Input to Output T
Skew |T
PLH–TPHL
Receiver Enable T
Receiver Disable T
| 200 ns
EN1
EN2
PLH
, T
250 2000 ns CL = 15 pF, Figure 5
PHL
10 50 ns R
10 50 ns R
= 1 kΩ, C
L
= 1 kΩ, C
L
= 15 pF, Figure 4
L
= 15 pF, Figure 4
L
SHUTDOWN
Time to Shutdown 50 200 600 ns
Driver Enable from Shutdown 2000 ns R
Receiver Enable from Shutdown 2500 ns R
Specifications subject to change without notice.
= 500 Ω, C
L
= 1 kΩ, C
L
= 100 pF, Figure 3
L
= 15 pF, Figure 4
L
–2– REV. 0
Page 3
ADM483E
RE
DE
DI
V
CC
B
A
GND
1
2
3
4
8
7
6
5
TOP VIEW
(Not to Scale)
ADM483E
RO
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7 V
Inputs
Driver Input (DI) . . . . . . . . . . . . . . . . –0.5 V to V
Control Inputs (DE, RE) . . . . . . . . . . –0.5 V to V
+ 0.5 V
CC
+ 0.5 V
CC
Receiver Inputs (A, B) . . . . . . . . . . . . . . . . . –14 V to +14 V
Outputs
Driver Outputs . . . . . . . . . . . . . . . . . . . . –12.5 V to +12.5 V
Receiver Output . . . . . . . . . . . . . . . . . –0.5 V to V
+0.5 V
CC
ESD Rating: Air (Human Body Model) (A, B Pins) . . ± 15 kV
ESD Rating: Contact (Human Body Model)
(A, B Pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±8 kV
ESD Rating MIL-STD-883B Method 3015
(Except A, B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3.5 kV
EFT Rating (IEC1000-4-4) (A, B Pins) . . . . . . . . . . . . ±2 kV
EMI Immunity (IEC1000-4-3) . . . . . . . . . . . . . . . . . . 10 V/m
Power Dissipation 8-Pin DIP . . . . . . . . . . . . . . . . . . . 727 mW
θ
, Thermal Impedance . . . . . . . . . . . . . . . . . . +135°C/W
JA
Power Dissipation 8-Pin SOIC . . . . . . . . . . . . . . . . . 470 mW
θ
, Thermal Impedance . . . . . . . . . . . . . . . . . . +110°C/W
JA
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum ratings for extended periods may affect device reliability.
PIN FUNCTION DESCRIPTION
Pin Mnemonic Function
1 RO Receiver Output. When enabled if A > B by
200 mV, then RO = High. If A < B by
200 mV, then RO = Low.
2
RE Receiver Output Enable. A low level enables
the receiver output, RO. A high level places it
in a high impedance state.
3 DE Driver Output Enable. A high level enables
the driver differential outputs, A and B. A
low level places it in a high impedance state.
4 DI Driver Input. When the driver is enabled a
logic Low on DI forces A low and B high
while a logic High on DI forces A high and B
low.
5 GND Ground Connection, 0 V.
6 A Noninverting Receiver Input A/Driver
Output A.
7 B Inverting Receiver Input B/Driver Output B.
8V
CC
Power Supply, 5 V ± 10%.
PIN CONFIGURATION
ORDERING GUIDE
Model Temperature Range Package Option
ADM483EAN –40°C to +85°C N-8
ADM483EAR –40°C to +85°C SO-8
Table I. Selection Table
Part No. Duplex Data Rate Low Power Tx/Rx I
No of Tx/Rx ESD EFT EMI
CC
kb/s Shutdown Enable mA On Bus kV kV V/m
ADM483E Half 250 Yes Yes 36 32 ±15 ±210
REV. 0
–3–
Page 4
ADM483E
T
ZH
1.5VDE
1.5V
3V
0V
2.3V
T
HZ
V
OH
VOH – 0.5V
0V
A, B
V
OL
+ 0.5V
T
ZL
2.3V
T
LZ
V
OL
A, B
T
ZH
1.5V 1.5V
3V
0V
1.5V
T
HZ
V
OH
VOH – 0.5V
0V
R
V
OL
+ 0.5V
T
ZL
1.5V
T
LZ
V
OL
R
RE
O/P LOW
O/P HIGH
Test Circuits
V
CC
R
V
OD
R
V
OC
0V OR 3V
DE IN
A
DE
S1 S2
B
R
L
C
L
V
OUT
Figure 1. Driver Voltage Measurement Test Circuit
375Ω
V
OD3
60Ω
375Ω
V
TST
Figure 2. Driver Voltage Measurement Test Circuit 2
DI
D
Figure 5. Receiver Propagation Delay Test Circuit
Switching Characteristics
3V
VO
–VO
0V
B
VO
A
0V
1/2VO
90% POINT
10% POINT
T
1.5V
PLH
T
T
SKEW
R
1.5V
T
PHL
90% POINT
10% POINT
T
F
T
SKEW
Figure 3. Driver Enable/Disable Test Circuit
V
+15V
–15V
S1
RE IN
RE
R
C
L
V
OUT
CC
L
S2
Figure 4. Receiver Enable/Disable Test Circuit
A
C
L1
RL
DIFF
B
C
L2
RO
R
RE
Figure 6. Driver Propagation Delay, Rise/Fall Timing
0V
T
PHL
V
OH
V
OL
–4–
T
PLH
0V
1.5V 1.5V
A–B
RO
Figure 8. Receiver Propagation Delay
Figure 7. Driver Enable/Disable Timing
Figure 9. Receiver Enable/Disable Timing
REV. 0
Page 5
Typical Performance Characteristics–ADM483E
OUTPUT VOLTAGE – Volts
0
OUTPUT CURRENT – mA
0.5 3.01.0 1.5 2.0 2.5
90
80
0
40
30
20
10
70
50
60
10
0%
100
90
T
T
T
RO
DI
40
35
30
25
20
15
10
OUTPUT CURRENT – mA
5
0
0 0.5 2.51.0 1.5 2.0
OUTPUT VOLTAGE – Volts
Figure 11. Receiver Output Low
Voltage vs. Output Current
0
–10
–20
–30
–40
–50
–60
OUTPUT CURRENT – mA
–70
–80
–90
0
0.5 5.01.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
OUTPUT VOLTAGE – Volts
0
–5
–10
–15
OUTPUT CURRENT – mA
–20
3.4 3.6 5.03.8 4.0 4.2 4.4 4.6 4.8
OUTPUT VOLTAGE – Volts
Figure 12. Receiver Output High
Voltage vs. Output Current
80
70
60
50
40
30
20
OUTPUT CURRENT – mA
10
0
0 0.5 4.51.0 1.5 2.0 3.0 3.5 4.02.5
OUTPUT VOLTAGE – Volts
Figure 13. Driver Output Low
Voltage vs. Output Current
10dB/DIV
Figure 17. Driver Output Waveform
and FFT Plot Transmitting @ 150 kHz
REV. 0
Figure 14. Driver Output High
Voltage vs. Output Current
100
90
10
0%
500kHz/DIV0 5MHz
Figure 15. Driver Differential Output
Voltage vs. Output Current
80
70
60
50
40
dBµV
30
20
10
0
30 200
FREQUENCY – MHz
LIMIT
Figure 18. Radiated Emissions
–5–
Figure 16. ADM483E Driving
4000 ft. of Cable
80
70
60
50
40
dBµV
30
20
10
0
0.3 0.6
1361030
LOG FREQUENCY (0.15–30) – MHz
Figure 19. Conducted Emissions
LIMIT
Page 6
ADM483E
HIGH
VOLTAGE
GENERATOR
DEVICE
UNDER TEST
ESD Test Method R2 C1
Human Body Model 1.5K 100pF
C1
R2
GENERAL INFORMATION
The ADM483E is a ruggedized RS-485 transceiver that operates
from a single +5 V supply.
It contains protection against radiated and conducted interference, including high levels of electrostatic discharge.
It is ideally suited for operation in electrically harsh environments or where cables may be plugged/unplugged. It is also
immune to high RF field strengths without special shielding
precautions. It is intended for balanced data transmission and
complies with both EIA Standards RS-485 and RS-422. It contains a differential line driver and a differential line receiver, and
is suitable for half duplex data transmission as the driver and
receiver share the same differential pins.
The input impedance on the ADM483E is 12 kΩ, allowing up to
32 transceivers on the differential bus.
The ADM483E operates from a single +5 V ± 10% power
supply. Excessive power dissipation caused by bus contention or
by output shorting is prevented by a thermal shutdown circuit.
This feature forces the driver output into a high impedance state
if, during fault conditions, a significant temperature increase is
detected in the internal driver circuitry.
The receiver contains a fail-safe feature that results in a logic
high output state if the inputs are unconnected (floating).
A high level of robustness is achieved using internal protection
circuitry, eliminating the need for external protection components such as tranzorbs or surge suppressors.
Low electromagnetic emissions are achieved using slew limited
drivers, minimizing interference both conducted and radiated.
The ADM483 can transmit at data rates up to 250 kbps.
A typical application for the ADM483E is illustrated in Figure
20. This shows a half-duplex link where data may be transferred
at rates up to 250 kbps. A terminating resistor is shown at both
ends of the link. This termination is not critical since the slew
rate is controlled by the ADM483E and reflections are minimized.
The communications network may be extended to include
multipoint connections as shown in Figure 30. Up to 32
transceivers may be connected to the bus.
+5V +5V
0.1µF 0.1µF
GND
DE
V
CC
DI
RO
RE
V
RE
CC
RO
B
ADM483E ADM483E
DI
DE
A
RS485/RS-422 LINK
GND
B
A
Tables II and III show the truth tables for transmitting and
receiving.
Table II. Transmitting Truth Table
Inputs Outputs
RE DE DI B A
X1101
X1010
0 0 X Hi-Z Hi-Z
1 0 X Hi-Z Hi-Z
X = Don’t Care.
Table III. Receiving Truth Table
Inputs Outputs
RE DE A-B RO
00≥ +0.2 V 1
00≤ –0.2 V 0
0 0 Inputs O/C 1
1 0 X Hi-Z
X = Don’t Care.
ESD/EFT TRANSIENT PROTECTION SCHEME
The ADM483E uses protective clamping structures on its
inputs and outputs that clamp the voltage to a safe level and
dissipates the energy present in ESD (Electrostatic) and EFT
(Electrical Fast Transients) discharges.
The protection structure achieves ESD protection up to ± 15 kV
according to the Human Body Model, and EFT protection up
to ±2 kV on all I-O lines.
ESD TESTING
Two coupling methods are used for ESD testing, contact
discharge and air-gap discharge. Contact discharge calls for a
direct connection to the unit being tested. Air-gap discharge
uses a higher test voltage but does not make direct contact with
the unit under test. With air discharge, the discharge gun is
moved toward the unit under test, developing an arc across the
air gap, hence the term air-discharge. This method is influenced
by humidity, temperature, barometric pressure, distance and
rate of closure of the discharge gun. The contact-discharge
method, while less realistic, is more repeatable and is gaining
acceptance and preference over the air-gap method.
Although very little energy is contained within an ESD pulse,
the extremely fast rise time, coupled with high voltages, can
cause failures in unprotected semiconductors. Catastrophic
destruction can occur immediately as a result of arcing or
heating. Even if catastrophic failure does not occur immediately, the device may suffer from parametric degradation, which
may result in degraded performance. The cumulative effects of
continuous exposure can eventually lead to complete failure.
Figure 20. Typical Half-Duplex Link Application
–6–
Figure 21. ESD Generator
REV. 0
Page 7
I-O lines are particularly vulnerable to ESD damage. Simply
300ms 16ms
V
t
V
0.2/0.4ms
t
5ns
50ns
HIGH
VOLTAGE
SOURCE
R
C
R
M
C
C
Z
S
L
C
D
50Ω
OUTPUT
touching or plugging in an I-O cable can result in a static
discharge that can damage or completely destroy the interface
product connected to the I-O port.
It is, therefore, extremely important to have high levels of ESD
protection on the I-O lines.
It is possible that the ESD discharge could induce latchup in the
device under test. It is therefore important that ESD testing on
the I-O pins be carried out while device power is applied. This
type of testing is more representative of a real world I-O
discharge where the equipment is operating normally when the
discharge occurs.
100%
90%
PEAK
I
ADM483E
Figure 23. IEC1000-4-4 Fast Transient Waveform
Table V shows the peak voltages for each of the environments.
Table V.
36.8%
10%
t
RL
t
DL
TIME t
Figure 22. Human Body Model ESD Current Waveform
Table IV. ADM483E ESD Test Results
ESD Test Method I-O Pins Other Pins
Human Body Model: Air ±15 kV
Human Body Model: Contact ±8 kV ±3.5 V
FAST TRANSIENT BURST IMMUNITY (IEC1000-4-4)
IEC1000-4-4 (previously 801-4) covers electrical fast-transient/
burst (EFT) immunity. Electrical fast transients occur as a
result of arcing contacts in switches and relays. The tests
simulate the interference generated when, for example, a power
relay disconnects an inductive load. A spark is generated due to
the well known back EMF effect. In fact, the spark consists of a
burst of sparks as the relay contacts separate. The voltage
appearing on the line, therefore, consists of a burst of extremely
fast transient impulses. A similar effect occurs when switching
on fluorescent lights.
The fast transient burst test, defined in IEC1000-4-4, simulates
this arcing and its waveform is illustrated in Figure 23. It
consists of a burst of 2.5 kHz to 5 kHz transients repeating at
300 ms intervals. It is specified for both power and data lines.
Four severity levels are defined in terms of an open-circuit
voltage as a function of installation environment. The installation environments are defined as
1. Well-protected
2. Protected
3. Typical Industrial
4. Severe Industrial
REV. 0
Level V
(kV) V
PEAK
PEAK
(kV)
PSU I-O
1 0.5 0.25
2 1 0.5
32 1
44 2
A simplified circuit diagram of the actual EFT generator is
illustrated in Figure 24.
These transients are coupled onto the signal lines using an EFT
coupling clamp. The clamp is 1 m long and completely surrounds the cable, providing maximum coupling capacitance
(50 pF to 200 pF typ) between the clamp and the cable. High
energy transients are capacitively coupled onto the signal lines.
Fast rise times (5 ns) as specified by the standard result in very
effective coupling. This test is very severe since high voltages are
coupled onto the signal lines. The repetitive transients can often
cause problems, where single pulses do not. Destructive latchup
may be induced due to the high energy content of the transients.
Note that this stress is applied while the interface products are
powered up and are transmitting data. The EFT test applies
hundreds of pulses with higher energy than ESD. Worst case
transient current on an I-O line can be as high as 40 A.
Figure 24. EFT Generator
Test results are classified according to the following
1. Normal performance within specification limits.
2. Temporary degradation or loss of performance that is selfrecoverable.
3. Temporary degradation or loss of function or performance
that requires operator intervention or system reset.
4. Degradation or loss of function that is not recoverable due to
damage.
–7–
Page 8
ADM483E
SPECTRUM
ANALYSER
DUT
LISN PSU
The ADM483E has been tested under worst case conditions
using unshielded cables, and meets Classification 2 at severity
Level 4. Data transmission during the transient condition is
corrupted, but it may be resumed immediately following the
EFT event without user intervention.
RADIATED IMMUNITY (IEC1000-4-3)
IEC1000-4-3 (previously IEC801-3) describes the measurement
method and defines the levels of immunity to radiated electromagnetic fields. It was originally intended to simulate the electromagnetic fields generated by portable radio transceivers or any
other device that generates continuous wave radiated electromagnetic energy. Its scope has since been broadened to include
spurious EM energy, which can be radiated from fluorescent
lights, thyristor drives, inductive loads, etc.
Testing for immunity involves irradiating the device with an EM
field. There are various methods of achieving this including use
of anechoic chamber, stripline cell, TEM cell and GTEM cell.
These consist essentially of two parallel plates with an electric
field developed between them. The device under test is placed
between the plates and exposed to the electric field. There
are three severity levels having field strengths ranging from
1 V to 10 V/m. Results are classified in a similar fashion to those
for IEC1000-4-2.
1. Normal Operation.
2. Temporary Degradation or loss of function that is selfrecoverable when the interfering signal is removed.
3. Temporary degradation or loss of function that requires
operator intervention or system reset when the interfering
signal is removed.
4. Degradation or loss of function that is not recoverable due to
damage.
The ADM483E comfortably meets Classification 1 at the most
stringent (Level 3) requirement. In fact, field strengths up to
30 V/m showed no performance degradation and error-free data
transmission continued even during irradiation.
Table VI.
Level Field Strength
V/m
EMI EMISSIONS
The ADM483E contains internal slew rate limiting in order to
minimize the level of electromagnetic interference generated.
Figure 25 shows an FFT plot when transmitting a 150 kHz
data stream.
100
90
10dB/DIV
10
0%
500kHz/DIV0 5MHz
Figure 25. Driver Output Waveform and FFT Plot Transmitting @ 150 kHz
As may be seen, the slew limiting attenuates the high frequency
components. EMI is therefore reduced, as are reflections due to
improperly terminated cables.
EN55022, CISPR22 defines the permitted limits of radiated
and conducted interference from Information Technology
Equipment (ITE).
The objective is to control the level of emissions, both conducted and radiated.
For ease of measurement and analysis, conducted emissions are
assumed to predominate below 30 MHz, while radiated
emissions predominate above this frequency.
CONDUCTED EMISSIONS
This is a measure of noise that is conducted onto the mains
power supply. The noise is measured using a LISN (Linc
Impedance Stabilizing Network) and a spectrum analyzer. The
test setup is illustrated in Figure 26. The spectrum analyzer is
set to scan the spectrum from 0 MHz to 30 MHz. Figure 27
shows that the level of conducted emissions from the
ADM483E are well below the allowable limits.
11
23
310
–8–
Figure 26. Conducted Emissions Test Setup
REV. 0
Page 9
ADM483E
80
70
60
50
40
dBµV
30
20
10
0
0.3 0.6
1361030
LOG FREQUENCY (0.15–30) – MHz
LIMIT
Figure 27. Conducted Emissions
RADIATED EMISSIONS
Radiated emissions are measured at frequencies in excess of
30 MHz.
A typical test setup for monitoring radiated emissions is
illustrated in Figure 28.
RADIATED NOISE
OUT
TURNTABLE
ADJUSTABLE
ANTENNA
TO
RECEIVER
Figure 28. Radiated Emissions Test Setup
Figure 29 shows that the level of radiated emissions is also well
below the allowable limit.
80
70
60
50
40
dBµV
30
20
10
0
30 200
FREQUENCY – MHz
LIMIT
APPLICATIONS INFORMATION
Differential Data Transmission
Differential data transmission is used to reliably transmit data at
high rates over long distances and through noisy environments.
Differential transmission nullifies the effects of ground shifts
and noise signals that appear as common-mode voltages on the
line. There are two main standards approved by the Electronics Industries Association (EIA) that specify the electrical
characteristics of transceivers used in differential data transmission.
The RS-422 standard specifies data rates up to 10 MBaud and
line lengths up to 4000 ft. A single driver can drive a transmission line with up to 10 receivers.
In order to cater for true multipoint communications, the RS485 standard was defined. This standard meets or exceeds all
the requirements of RS-422, but also allows for up to 32 drivers
and 32 receivers to be connected to a single bus. An extended
common-mode range of –7 V to +12 V is defined. The most
significant difference between RS-422 and RS-485 is the fact
that the drivers may be disabled, thereby allowing more than
one (32 in fact) to be connected to a single line. Only one driver
should be enabled at a time, but the RS-485 standard contains
additional specifications to guarantee device safety in the event
of line contention.
Cable and Data Rate
The transmission line of choice for RS-485 communications is a
twisted pair. Twisted pair cable tends to cancel common-mode
noise and also causes cancellation of the magnetic fields
generated by the current flowing through each wire, thereby
reducing the effective inductance of the pair.
A typical application showing a multipoint transmission network
is illustrated in Figure 30. An RS-485 transmission line can have
as many as 32 transceivers on the bus. Only one driver can
transmit at a particular time, but multiple receivers may be
enabled simultaneously.
RT RT
D
R
D
R
D
R
D
R
REV. 0
Figure 29. Radiated Emissions
Figure 30. Typical RS-485 Network
–9–
Page 10
ADM483E
0.1574 (4.00)
0.1497 (3.80)
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead SOIC (SO-8)
0.1968 (5.00)
0.1890 (4.80)
8
5
0.2440 (6.20)
41
0.2284 (5.80)
0.0098 (0.25)
0.0040 (0.10)
SEATING
PLANE
0.210 (5.33)
MAX
0.160 (4.06)
0.115 (2.93)
0.022 (0.558)
0.014 (0.356)
PIN 1
0.0500
(1.27)
BSC
0.0688 (1.75)
0.0532 (1.35)
0.0192 (0.49)
0.0138 (0.35)
8-Pin Plastic DIP (N-8)
0.430 (10.92)
0.348 (8.84)
8
14
PIN 1
0.100
(2.54)
BSC
5
0.280 (7.11)
0.240 (6.10)
0.060 (1.52)
0.015 (0.38)
0.070 (1.77)
0.045 (1.15)
0.0098 (0.25)
0.0075 (0.19)
0.130
(3.30)
MIN
SEATING
PLANE
0.0196 (0.50)
0.0099 (0.25)
8°
0°
0.0500 (1.27)
0.0160 (0.41)
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
x 45°
0.195 (4.95)
0.115 (2.93)
–10–
REV. 0
Page 11
–11–
Page 12
C2934–12–1/97
–12–
PRINTED IN U.S.A.
Loading...