Datasheet ADM4210 Datasheet (ANALOG DEVICES)

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Hot Swap Controller

FEATURES

Controls supply rails from 2.7 V to 16.5 V
Allows protected board removal and insertion to a live

backplane

External sense resistor provides adjustable analog current

limit with circuit breaker
Peak fault current limited with fast response
Charge pumped gate drive for external N-FET switch
Automatic retry or latch-off during current fault
Undervoltage lockout
Low profile (1 mm), 6-lead, TSOT package
Pin compatible with LTC4210-1 and LTC4210-2

APPLICATIONS

Hot swap board insertion: line cards, raid systems
Industrial high-side switches/circuit breakers
Electronic circuit breakers

GENERAL DESCRIPTION

The ADM4210 is a hot swap controller that safely enables a
printed circuit board to be removed and inserted to a live
backplane. This is achieved using an external N-channel power
MOSFET with a current control loop that monitors the load
current through a sense resistor. An internal charge pump is
used to enhance the gate of the N-channel FET. When an
overcurrent condition is detected, the gate voltage of the FET is
reduced to limit the current flowing through the sense resistor.
During an overcurrent condition, the TIMER cap determines
the amount of time the FET remains at a current limiting mode

CLR

of operation until it is shut down. The ON (ON­enable input for the device and can be used to monitor the
input supply voltage. The ADM4210 operates with a supply
voltage ranging from 2.7 V to 16.5 V.

) pin is the

in 6-Lead TSOT Package

ADM4210

FUNCTIONAL BLOCK DIAGRAM

R

ON

C

TIMER

0.22µF

V

1.3V

CC

TIMER

SENSE

0.01Ω

SENSE

GATE
DRIVE/
LOGIC

ADM4210

GND

Q

GATE

V

ON

(2V/DIV)

V

TIMER

(1V/DIV)

V

OUT

(5V/DIV)

I

OUT

(0.5A/ DIV)

1

VIN = 5V V

GND GND

LONG

SHORT

LONG

R

ON1

20kΩ

R

ON2

10kΩ

C

TIMER

Figure 1.

C

= 470µF

LOAD

10ms/DIV

Figure 2. Start-Up Sequence

OUT

+

R

G

100Ω

R

C

100Ω

C

0.01µF

C
470µF

C

= 5V

LOAD

05132-050

05132-001

The ADM4210 is available in two options: the ADM4210-1 with
automatic retry for overcurrent fault and the ADM4210-2 with

CLR

latch off for an overcurrent fault. Toggling the ON (ON-

)
pin resets a latched fault. The ADM4210 is packaged in a
6-lead TSOT.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

ADM4210

TABLE OF CONTENTS

Features.............................................................................................. 1

UVLO........................................................................................... 11

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 4

Thermal Characteristics .............................................................. 4

ESD Caution.................................................................................. 4

Pin Configurations and Function Descriptions ........................... 5

Typical Performance Characteristics ............................................. 6

Theory of Operation ...................................................................... 11

Overview...................................................................................... 11

REVISION HISTORY

7/06—Revision 0: Initial Version

ON (ON-

GATE ........................................................................................... 11

Current Limit Function............................................................. 11

Calculating the Current Limit.................................................. 11

Circuit Breaker Function........................................................... 12

Timer Function........................................................................... 12

Power-Up Timing Cycle............................................................ 12

Circuit Breaker Timing Cycle................................................... 13

Automatic Retry or Latched Off............................................... 13

Outline Dimensions....................................................................... 14

Ordering Guide .......................................................................... 14

CLR

) Pin..................................................................... 11

Rev. 0 | Page 2 of 16

ADM4210

SPECIFICATIONS

VCC = 2.7 V to 16.5 V, TA = −40°C to +85°C, typical values at TA = 25°C, unless otherwise noted.

Table 1.

Parameter Symbol Min Typ Max Unit Conditions

VCC PIN

Operating Voltage Range VCC 2.7 16.5 V
Supply Current ICC 0.65 3.5 mA
Undervoltage Lockout V
Undervoltage Lockout Hysteresis V

ON (ON-CLR) PIN

Input Current
Threshold VON 1.22 1.3 1.38 V ON rising
Threshold Hysteresis V

SENSE PIN

Input Current
Circuit Breaker Limit Voltage VCB 44 50 56 mV VCB = (VCC− V

GATE PIN

Pull-Up Current I
Pull-Down Current I
V
V
Gate Drive Voltage

4.5 7.5 10 V V

5.0 8.5 12 V V

8.75 12 16 V V

7.6 12 16 V V

6.0 11 18 V V
TIMER PIN

Pull-Up Current I

−25 −60 −100 µA During current fault, V
Pull-Down Current
100 µA Normal operation, V
Threshold High V
Threshold Low V

t

OFF

Turn-Off Time (TIMER Rise to GATE Fall)
Turn-Off Time (ON (ON-CLR) Fall to GATE Fall)
Turn-Off Time (VCC Rise to IC Reset) t

2.2 2.5 2.65 V VCC rising

UVLO

100 mV

UVLOHYS

I

−10 0 +10 µA

INON

80 mV

ONHYST

I

−10 +5 +10 µA V

INSENSE

−5 −10 −15 µA V

GATEUP

25 mA V

GATEDN

V

GATE

−2 −5 −8.5 µA Initial cycle, V

TIMERUP

I

2 3.5 µA After current fault, V

TIMERDN

1.22 1.3 1.38 V TIMER rising

TIMERH

0.15 0.2 0.25 V TIMER falling

TIMERL

t

OFF(TMRHIGH)

t

OFF(ONLOW)

OFF(VCCLOW)

1 µs V

30 µs VON = 5 V to 0 V step, VCC = 5 V

30 µs VCC = 0 V to 2 V step, VON = 5 V

= VCC

SENSE

= 0 V

GATE

= 1.5 V, V

TIMER

= 0 V, V

ON

− V

CC

SENSE

− VCC, VCC = 3 V

GATE

− VCC, VCC = 3.3 V

GATE

− VCC, VCC = 5 V

GATE

− VCC, VCC = 12 V

GATE

− VCC, VCC = 15 V

GATE

= 0 V to 2 V step, VCC = VON = 5 V

TIMER

)

SENSE

= 3 V or

GATE

= 3 V or

GATE

= 100 mV, V

= 1 V

TIMER

TIMER

TIMER

GATE

TIMER

= 1 V
= 1 V

= 3 V

= 1 V

Rev. 0 | Page 3 of 16

ADM4210

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

VCC Pin −0.3 V to +20 V
SENSE Pin −0.3 V to +20 V
VCC − SENSE ±5 V
TIMER Pin −0.3 V to (VCC + 0.3 V)
ON (ON-CLR) Pin
GATE Pin −0.3 V to (VCC + 11 V)
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (10 sec) 300°C
Junction Temperature 150°C

−0.3 V to +20 V

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL CHARACTERISTICS

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 3. Thermal Resistance

Package Type θJA Unit

6-Lead TSOT 169.5 °C/W

Rev. 0 | Page 4 of 16

ADM4210

A

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

ADM4210-1AUJ

TIMER

GND

ON

1

TOP VIEW

2

(Not to Scale)

3

6

5

4

V

CC

SENSE

GATE

Figure 3. Pin Configuration, 1AUJ Model

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 TIMER

Timer Input Pin. The initial and circuit breaker timing cycles are set by this external capacitor. The initial timing
delay is 272.9 ms/F, and 21.7 ms/µF for a circuit breaker delay. When the TIMER pin is pulled beyond the upper

threshold, the GATE turns off.
2 GND Chip Ground Pin.
3

ON (ON-

CLR) Input Pin. The ON (ON-CLR) pin is an input to a comparator that has a low-to-high threshold of 1.3 V with 80 mV

hysteresis and a glitch filter. The ADM4210 is reset when the ON (ON-

high, the ADM4210 is enabled. A rising edge on this pin has the added function of clearing a fault and restarting

the device on the latched off model, the ADM4210-2.
4 GATE

Gate Output Pin. An internal charge pump provides a 12 µA pull-up current to drive the gate of an N-channel

MOSFET. In an overcurrent condition, the ADM4210 controls the external FET to maintain a constant load

current.
5 SENSE

Current Limit Sense Input Pin. The current limit is set via a sense resistor between the V

overcurrent condition, the gate of the FET is controlled to maintain the SENSE voltage at 50 mV. When this limit is

reached, the TIMER circuit breaker mode is activated. The circuit breaker limit can be disabled by connecting the

pin and SENSE pin together.

V

CC

6 VCC

Positive Supply Input Pin. The ADM4210 operates between 2.7 V to 16.5 V. An undervoltage lockout (UVLO)

circuit with a glitch filter resets the ADM4210 when the supply voltage drops below the specified UVLO limit.

DM4210-2AUJ

1

TIMER

GND 2

05132-006

ON-CLR

TOP VIEW

(Not to Scal e)

3

6

V

CC

SENSE5

GATE4

05132-007

Figure 4. Pin Configuration, 2AUJ Model

CLR) pin is low. When the ON (ON-

and SENSE pins. In an

CC

CLR

) pin is

Rev. 0 | Page 5 of 16

ADM4210

–

TYPICAL PERFORMANCE CHARACTERISTICS

4.0
TA = 25°C

3.5

3.0

25

20

2.5

2.0

1.5

SUPPLY CURRENT (mA)

1.0

0.5

0

01

246810121416

SUPPLY VOLTAGE (V)

8

05132-032

Figure 5. Supply Current vs. Supply Voltage

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

SUPPLY CURRENT (mA)

0.2

0.1

0

–25 0 25 50 75 100 125

–50 150

VCC = 12V

VCC = 5V

TEMPERATURE (° C)

VCC = 15V

VCC = 3V

05132-033

Figure 6. Supply Current vs. Temperature

15

10

GATE VOLTAGE (V)

5

0

018

246810121416

Figure 8. GATE Voltage vs. Supply Voltage

25

20

15

10

GATE VOLTAGE (V)

5

0

–25 0 25 50 75 100 125

–50 150

Figure 9. GATE Voltage vs. Temperature

SUPPLY VOLTAGE (V)

VCC = 15V

VCC = 12V

VCC = 5V

VCC = 3V

TEMPERATURE (° C)

05132-013

05132-015

2.65
VCC = 5V

2.63

2.61

2.59

2.57

2.55

2.53

2.51

UVLO THRESHO LD (V)

2.49

2.47

2.45

–25 0 25 50 75 100 125

–50 150

TEMPERATURE (° C)

VCC RISING

VCC FALLING

Figure 7. UVLO Threshold vs. Temperature

05132-046

8

–9

–10

–11

–12

GATE CURRENT (µA)

–13

–14

246810121416

01

SUPPLY VOLTAGE (V)

8

05132-009

Figure 10. GATE Current (up) vs. Supply Voltage

Rev. 0 | Page 6 of 16

ADM4210

–

–

11.0

–11.2

–11.4

–11.6

–11.8

–12.0

–12.2

GATE CURRENT (µ A)

–12.4

–12.6

–12.8

–13.0

VCC = 5V

VCC = 15V

–50 150

–25 0 25 50 75 100 125

TEMPERATURE (° C)

VCC = 3V

VCC = 12V

Figure 11. GATE Current (up) vs. Temperature

05132-017

0

TA = 25°C

–1

–2

–3

–4

(µA)

–5

–6

TIMERUP

I

–7

–8

–9

–10

01

246810121416

SUPPLY VOLTAGE (V)

Figure 14. I

(in Initial Cycle) vs. Supply Voltage

TIMERUP

8

05132-035

10

9

8

7

6

5

4

3

DELTA GATE VOLTAGE (V)

2

1

0

246810121416

01

SUPPLY VOLTAGE (V)

8

05132-014

Figure 12. Delta GATE Voltage vs. Supply Voltage

10

9

VCC = 12V

8

7

6

5

4

3

DELTA GATE VOLTAGE (V)

2

1

0

–25 0 25 50 75 100 125

–50 150

TEMPERATURE (° C)

VCC = 5V

VCC = 15V

VCC = 3V

05132-016

Figure 13. Delta GATE Voltage vs. Temperature

0

VCC = 5V

–1

–2

–3

–4

(µA)

–5

–6

TIMERUP

I

–7

–8

–9

–10

–50 150

–25 0 25 50 75 100 125

Figure 15. I

20

TA = 25°C

–30

–40

–50

(µA)

–60

TIMERUP

I

–70

–80

–90

–100

Figure 16. I

246810121416

01

TIMERUP

TEMPERATURE (° C)

(in Initial Cycle) vs. Temperature

TIMERUP

SUPPLY VOLTAGE (V)

(During Cct Breaker Delay) vs. Supply Voltage

05132-038

8

05132-036

Rev. 0 | Page 7 of 16

ADM4210

–

20

VCC = 5V

–30

1.38

1.36

TA = 25°C

–40

–50

(µA)

–60

TIMERUP

I

–70

–80

–90

–100

–50 150

–25 0 25 50 75 100 125

TEMPERATURE (° C)

Figure 17. I

3.0
TA = 25°C

2.8

2.6

2.4

2.2

(µA)

2.0

1.8

TIMERDN

I

1.6

1.4

1.2

1.0

01

Figure 18. I

(During Cct Breaker Delay) vs. Temperature

TIMERUP

246810121416

SUPPLY VOLTAGE (V)

(in Cool-Off Cycle) vs. Supply Voltage

TIMERDN

05132-039

8

05132-034

1.34

1.32

1.30

1.28

1.26

TIMER HIGH THRESHOLD (V)

1.24

1.22
01

246810121416

Figure 20. TIMER High Threshold vs. Supply Voltage

1.38

VCC = 5V

1.36

1.34

1.32

1.30

1.28

1.26

TIMER HIGH THRESHOLD (V)

1.24

1.22

–25 0 25 50 75 100 125

–50 150

Figure 21. TIMER High Threshold vs. Temperature

SUPPLY VOLTAGE (V)

TEMPERATURE (° C)

8

05132-042

05132-044

3.0
VCC = 5V

2.8

2.6

2.4

2.2

(µA)

2.0

1.8

TIMERDN

I

1.6

1.4

1.2

1.0

–50 150

–25 0 25 50 75 100 125

TEMPERATURE (° C)

Figure 19. I

(in Cool-Off Cycle) vs. Temperature

TIMERDN

05132-037

Rev. 0 | Page 8 of 16

0.24
TA = 25°C

0.23

0.22

0.21

0.20

0.19

0.18

TIMER LOW THRESHOLD (V)

0.17

0.16

246810121416

01

SUPPLY VOLTAGE (V)

8

05132-043

Figure 22. TIMER Low Threshold vs. Supply Voltage

ADM4210

0.24

0.23

VCC = 5V

1.45

1.40

VCC = 5V

0.22

0.21

0.20

0.19

0.18

TIMER LO W THRESHOL D (V)

0.17

0.16
–50 150

–25 0 25 50 75 100 125

TEMPERATURE (° C)

Figure 23. TIMER Low Threshold vs. Temperature

1.45

TA = 25°C

1.40

1.35

1.30

1.25

1.20

1.15

ON (ON- CLR) PI N THRESHOLD ( V)

1.10

HIGH THRESHOLD

LOW THRES HOLD

1.35

1.30

1.25

1.20

1.15

ON (ON-CLR) PI N THRESHOLD ( V)

1.10

1.05
–50 150

–25 0 25 50 75 100 125

05132-045

Figure 25. ON (ON-

80

TA = 25°C

70

60

50

(µs)

40

30

OFF(ONLOW)

t

20

10

HIGH THRESHOL D

LOW THRESHOLD

TEMPERATURE (° C)

CLR

) Pin Threshold vs. Temperature

05132-041

1.05
246810121416

01

SUPPLY VOLTAGE (V)

CLR

Figure 24. ON (ON-

) Pin Threshold vs. Supply Voltage

8

05132-040

0

246810121416

018

Figure 26. t

SUPPLY VOLTAGE (V)

vs. Supply Voltage

OFF(ONLOW)

05132-047

Rev. 0 | Page 9 of 16

ADM4210

80

70

60

50

(µs)

40

30

OFF(ONLOW)

t

20

10

0

–50 150

–25 0 25 50 75 100 125

VCC = 15V

VCC = 5V

VCC = 3V

Figure 27. t

VCC = 12V

TEMPERATURE (° C)

vs. Temperature

OFF(ONLOW)

50

45

40

35

30

(mV)

25

CB

V

20

15

10

5

0

–50 150

–25 0 25 50 75 100 125

05132-048

TEMPERATURE (° C)

05132-021

Figure 29. Cct Breaker Voltage vs. Temperature

50

49

48

47

46

(mV)

45

CB

V

44

43

42

41

40

01

246810121416

SUPPLY VOLTAGE (V)

8

05132-049

Figure 28. Cct Breaker Voltage vs. Supply Voltage

Rev. 0 | Page 10 of 16

ADM4210

THEORY OF OPERATION

Many systems require the insertion or removal of circuit boards
to live backplanes. During this event, the supply bypass and hold­up capacitors can require substantial transient currents from the
backplane power supply as they charge. These currents can
cause permanent damage to connector pins or undesirable glitches
and resets to the system.

The ADM4210 is intended to control the powering of a system
(on and off) in a controlled manner, allowing the board to be
removed from, or inserted into, a live backplane by protecting it
from excess currents. The ADM4210 can reside either on the
backplane or on the removable board.

OVERVIEW

The ADM4210 operates over a supply range of 2.7 V to 16.5 V.
As the supply voltage is coming up, an undervoltage lockout
circuit checks if sufficient supply voltage is present for proper
operation. During this period, the FET is held off by the GATE
pin being held to GND. When the supply voltage reaches a level

CLR

above UVLO and the ON (ON-

) pin is high, an initial timing
cycle ensures that the board is fully inserted in the backplane
before turning on the FET. The TIMER pin capacitor sets the
periods for all of the TIMER pin functions. After the initial
timing cycle, the ADM4210 monitors the inrush current
through an external sense resistor. Overcurrent conditions are
actively limited to 50 mV/R

for the circuit breaker timer

SENSE

limit. The ADM4210-1 automatically retries after a current
limit fault and the ADM4210-2 latches off. The retry duty cycle
on the ADM4210-1 timer function is limited to 3.8% for FET
cooling.

UVLO

If the VCC supply is too low for normal operation, an under­voltage lockout circuit holds the ADM4210 in reset. The GATE
pin is held to GND during this period. When the supply reaches
this UVLO voltage, the ADM4210 starts when the ON (ON-

CLR

)

pin condition is satisfied.

ON (ON-CLR) PIN

The ON (ON­comparator that has a low-to-high threshold of 1.3 V with 80 mV
hysteresis and a glitch filter. The ADM4210 is reset when the
ON (ON­the ADM4210 is enabled. A rising edge on this pin has the
added function of clearing a fault and restarting the device on
the latched off model, the ADM4210-2. A low input on the ON

CLR

(ON­pin to ground and resets the timer. An external resistor divider at
the ON (ON­lockout value higher than the internal UVLO circuit. There is a
glitch filter delay of approximately 3 μs on rising allowing the
addition of an RC filter at the ON (ON-

CLR

) pin is the enable pin. It is connected to a

CLR

) pin is low. When the ON (ON-

CLR

) pin is high,

) pin turns off the external FET by pulling the GATE

CLR

) pin can be used to program an undervoltage

CLR

) pin to increase the

delay time at card insertion. If using a short pin system to
enable the device, a pull-down resistor should be used to hold
the device prior to insertion.

GATE

Gate drive for the external N-channel MOSFET is achieved
using an internal charge pump. The gate driver consists of a
12 μA pull-up from the internal charge pump. There are various
pull-down devices on this pin. At a hot swap condition the board
is hot inserted to the supply bus. During this event, it is possible
for the external FET GATE capacitance to be charged up by the
sudden presence of the supply voltage. This can cause uncontrolled
inrush currents. An internal strong pull-down circuit holds
GATE low while in UVLO. This reduces current surges at inser­tion. After the initial timing cycle, the GATE is then pulled high.
During an overcurrent condition, the ADM4210 servos the
GATE pin in an attempt to maintain a constant current to the
load until the circuit breaker timeout completes. In the event of
a timeout, the GATE pin abruptly shuts down using the 4 mA
pull-down device. Care must be taken not to load the GATE pin
resistively because this reduces the gate drive capability.

CURRENT LIMIT FUNCTION

The ADM4210 features a fast response current control loop that
actively limits the current by reducing the gate voltage of the
external FET. This current is measured by monitoring the
voltage drop across an external sense resistor. The ADM4210
tries to regulate the gate of the FET to achieve a 50 mV voltage
drop across the sense resistor.

CALCULATING THE CURRENT LIMIT

The sense resistor connected between VCC and the SENSE pin is
used to determine the nominal fault current limit. This is given
by the following equation:

NOM

= VCB

ILIMIT

The minimum load current is given by Equation 2

MIN

= VCB

ILIMIT

The maximum load current is given by Equation 3

ILIMIT

MAX

= VCB

For proper operation, the minimum current limit must exceed
the circuit maximum operating load current with margin. The
sense resistor power rating must exceed

(VCB

)2/RSENSE

MAX

/RSENSE

NOM

/RSENSE

MIN

/RSENSE

MAX

MIN

(1)

NOM

(2)

MAX

(3)

MIN

Rev. 0 | Page 11 of 16

ADM4210

V

CIRCUIT BREAKER FUNCTION

When the supply experiences a sudden current surge, such as a
low impedance fault on load, the bus supply voltage can drop
significantly to a point where the power to an adjacent card is
affected, potentially causing system malfunctions. The
ADM4210 limits the current drawn by the fault by reducing the
gate voltage of the external FET. This minimizes the bus supply
voltage drop caused by the fault and protects neighboring cards.

This is the end of the first section of the initial cycle. The 100 µA
current source then pulls down the TIMER pin until it reaches

0.2 V at Time Point 4. The initial cycle delay (Time Point 2 to
Time Point 4) relates to C

= 1.3 × C

t

INITIAL

TIMER

by equation

TIMER

/5 µA (4)

When the initial cycle ends, a start-up cycle activates and the
GATE pin is pulled high; the TIMER pin continues to pull down.

As the voltage across the sense resistor approaches the current
limit, a timer activates. This timer resets again if the sense
voltage returns below this level. If the sense voltage is any
voltage below 44 mV, the timer is guaranteed to be off. Should
the current continue to increase, the ADM4210 tries to regulate
the gate of the FET to achieve a limit of 50 mV across the sense
resistor. However, if the device is unable to regulate the fault
current and the sense voltage further increases, a larger pull­down, in the order of milliamperes, is enabled to compensate
for fast current surges. If the sense voltage is any voltage greater
than 56 mV, this pull-down is guaranteed to be on. When the
timer expires, the GATE pin shuts down.

TIMER FUNCTION

The TIMER pin is responsible for several key functions on the
ADM4210. A capacitor controls the initial power on reset time
and the amount of time an overcurrent condition lasts before
the FET shuts down. On the ADM4210-1, the timer pin also
controls the time between auto retry pulses. There are pull-up
and pull-down currents internally available to control the timer
functions. The voltage on the TIMER pin is compared with two
threshold voltages: COMP1 (0.2 V) and COMP2 (1.3 V). The
four timing currents are listed in

Table 5.

Timing Current Level (μA)

Pull-up 5
Pull-up 60
Pull-down 2
Pull-down 100

Tabl e 5.

TIMER

V

GATE

V

V

TIMER

V

GATE

V

V

V

OUT

V

ON

V

OUT

IN

1

RESET

MODE

2

INITIAL
CYCLE

3

START-UP

CYCLE

4

NORMAL

CYCLE

05126-002

Figure 30. Power-Up Timing

IN

ON

5µA

60µA

2µA

100µA

POWER-UP TIMING CYCLE

I

The ADM4210 is in reset when the ON (ON-

CLR

) pin is held
low. The GATE pin is pulled low and the TIMER pin is pulled
low with a 100 µA pull-down. At Time Point 2 in
ON (ON-

CLR

) pin is pulled high. For the device to startup

Figure 30, the

correctly, the supply voltage must be above UVLO, the ON

CLR

(ON-

) pin must be above 1.3 V, and the TIMER pin voltage
must be less than 0.2 V. The initial timing cycle begins when these
three conditions are met, and the TIMER pin is pulled high with
5 µA. At Time Point 3, the TIMER reaches the COMP2 threshold.

Rev. 0 | Page 12 of 16

RSENSE

INITIAL

RESET

MODE

CYCLE

START-UP

CYCLE

Figure 31. Power-Up into Capacitor

NORMAL

CYCLE

05126-003

ADM4210

CIRCUIT BREAKER TIMING CYCLE AUTOMATIC RETRY OR LATCHED OFF

When the voltage across the sense resistor exceeds the circuit
breaker trip voltage, the 60 µA timer pull-up current is activated.
If the sense voltage falls below this level before the TIMER pin
reaches 1.3 V, the 60 µA pull-up is disabled and the 2 µA pull­down is enabled. This is likely to happen if the overcurrent fault
is only transient, such as an inrush current. This is shown in
Figure 31. However, if the overcurrent condition is continuous
and the sense voltage remains above the circuit breaker trip
voltage, the 60 µA pull-up remains active. This allows the TIMER
pin to reach the high trip point of 1.3 V and initiate the GATE
shutdown. On the ADM4210-2, the TIMER pin continues pulling
up but switches to the 5 µA pull-up when it reaches the 1.3 V
threshold. The device can be reset by toggling the ON-

CLR

pin
or by manually pulling the TIMER pin low. On the ADM4210-1,
the TIMER pin activates the 2 µA pull-down once the 1.3 V
threshold is reached, and continues to pull down until it reaches
the 0.2 V threshold. At this point, the 100 µA pull-down is
activated and the GATE pin is enabled. The device keeps
retrying in the manner as shown in

Figure 32.

The duty cycle of this automatic retry cycle is set to the ratio of
2 µA/60 µA, which approximates 3.8% on. The value of the
timer capacitor determines the on time of this cycle. This time
is calculated as follows:

= 1.3 × C

t

ON

t

= 1.1 × C

OFF

I

RSENSE

TIMER

TIMER

/60 A

/2 A

The ADM4210 is available in two models. The ADM4210-1
has an automatic retry system whereby when a current fault is
detected, the FET is shut down after a time determined by the
timer capacitor, and it is switched on again in a controlled con­tinuous cycle to determine if the fault remains (see

Figure 32
for details). The period of this cycle is determined by the timer
capacitor at a duty cycle of 3.8% on and 96.2% off.

The ADM4210-2 model has a latch off system whereby when a
current fault is detected, the GATE is switched off after a time
determined by the timer capacitor (see
Toggling the ON-

CLR

pin, or pulling the TIMER pin to GND

Figure 33 for details).

for a brief period, resets this condition.

I

RSENSE

5µA

V

TIMER

V

GSFET

V

OUT

Figure 33. ADM4210-2 Latch Off After Overcurrent Fault

60µA

SHORT­CIRCUIT
EVENT

COMP1COMP2

05126-005

2µA

V

V

GSFET

TIMER

V

OUT

60µA

SHORT­CIRCUIT
EVENT

FAULT
CYCLE

100µA

COMP1COMP2

FAULT
CYCLE

Figure 32. ADM4210-1 Automatic Retry During Overcurrent Fault

5126-004

Rev. 0 | Page 13 of 16

ADM4210

R

OUTLINE DIMENSIONS

2.90 BSC

4526

1.60 BSC

13

PIN 1

INDICATO

*

0.90

0.87

0.84

0.10 MAX

*

COMPLIANT TO JEDEC STANDARDS MO-193-AA WITH

THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.

1.90
BSC

0.50

0.30

Figure 34. 6-Lead Thin Small Outline Transistor Package [TSOT]

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

ADM4210-1AUJZ-RL7

ADM4210-2AUJZ-RL7

1

Z = Pb-free part.

1

1

−40°C to +85°C

−40°C to +85°C

2.80 BSC

0.95 BSC

*

1.00 MAX

SEATING
PLANE

0.20

0.08
8°

0.60

4°

0.45

0°

0.30

(UJ-6)

6-Lead TSOT UJ-6 M2P

6-Lead TSOT UJ-6 M2Q

Rev. 0 | Page 14 of 16

ADM4210

NOTES

Rev. 0 | Page 15 of 16

ADM4210

NOTES

©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05132-0-7/06(0)

Rev. 0 | Page 16 of 16