Datasheet ADM2490E Datasheet (ANALOG DEVICES)

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High Speed, ESD-Protected, Full-Duplex,
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FEATURES

Isolated, full-duplex RS-485/RS-422 transceiver ±8 kV ESD protection on RS-485 input/output pins 16 Mbps data rate Complies with ANSI TIA/EIA-485-A-1998 and
ISO 8482: 1987(E) Suitable for 5 V or 3 V operation (V High common-mode transient immunity: >25 kV/μs Receiver has open-circuit, fail-safe design 32 nodes on the bus Thermal shutdown protection Safety and regulatory approvals
UL recognition: 5000 V rms isolation voltage
for 1 minute per UL 1577
VDE certificate of conformity
DIN EN 60747-5-2 (VDE 0884-10 Part 2): 2003-01 DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000 V
= 848 V peak
IORM
Operating temperature range: −40°C to +105°C Wide body, 16-lead SOIC package
DD1
)
iCoupler Isolated RS-485 Transceiver
ADM2490E

FUNCTIONAL BLOCK DIAGRAM

DD2
ADM2490E
GND
2
Y
Z
A
B
05889-001
TxD
RxD
DD1
GND
GALVANIC ISOLATION
1
Figure 1.

APPLICATIONS

Isolated RS-485/RS-422 interfaces Industrial field networks INTERBUS Multipoint data transmission systems

GENERAL DESCRIPTION

The ADM2490E is an isolated data transceiver with ±8 kV ESD protection that is suitable for high speed, full-duplex communi­cation on multipoint transmission lines. It is designed for balanced transmission lines and complies with ANSI TIA/EIA-485-A-1998 and ISO 8482: 1987(E). The device employs Analog Devices, Inc., iCoupler® technology to combine a 2-channel isolator, a three­state differential line driver, and a differential input receiver into a single package.
The differential transmitter outputs and receiver inputs feature electrostatic discharge circuitry that provides protection to ±8 kV
using the human body model (HBM). The logic side of the device can be powered with either a 5 V or a 3 V supply, whereas the bus side requires an isolated 5 V supply.
The device has current-limiting and thermal shutdown features to protect against output short circuits and situations where bus contention could cause excessive power dissipation.
The ADM2490E is available in a wide body, 16-lead SOIC package and operates over the −40°C to +105°C temperature range.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006–2008 Analog Devices, Inc. All rights reserved.
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TABLE OF CONTENTS

Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Specifications .................................................................. 4
Package Characteristics ............................................................... 4
Regulatory Information ............................................................... 5
Insulation and Safety-Related Specifications ............................ 5
VDE 0884-10 Insulation Characteristics ................................... 5
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Test Circuits ....................................................................................... 8
Switching Characteristics .................................................................9
Typical Performance Characteristics ........................................... 10
Circuit Description......................................................................... 12
Electrical Isolation ...................................................................... 12
Truth Tables................................................................................. 12
Thermal Shutdown .................................................................... 13
Fail-Safe Receiver Inputs ........................................................... 13
Magnetic Field Immunity .......................................................... 13
Applications Information .............................................................. 14
Isolated Power Supply Circuit .................................................. 14
PCB Layout ................................................................................. 14
Typical Applications ................................................................... 15
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 16

REVISION HISTORY

8/08—Rev. 0 to Rev. A
Changes to Regulatory Approval Status Throughout .................. 1
Changed VDE 0884 to VDE 0884-10 Throughout ...................... 1
Changes to Table 5 ............................................................................ 5
Changes to Table 8 ............................................................................ 6
Changes to Figure 9 .......................................................................... 9
Changes to iCoupler Technology Section ................................... 12
Changes to Magnetic Field Immunity Section ........................... 13
Changes to Isolated Power Supply Circuit Section .................... 14
Changes to Figure 25 ...................................................................... 14
Added Typical Applications Section ............................................ 15
Updated Outline Dimensions ....................................................... 16
Changes to Ordering Guide .......................................................... 16
10/06—Revision 0: Initial Version
Rev. A | Page 2 of 16
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SPECIFICATIONS

All voltages are relative to their respective ground; 2.7 ≤ V over the entire recommended operation range, unless otherwise noted. All typical specifications are at T unless otherwise noted.
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions
SUPPLY CURRENT
Power Supply Current, Logic Side
TxD/RxD Data Rate < 2 Mbps I TxD/RxD Data Rate = 16 Mbps I
3.0 mA 2.7 V ≤ V
DD1
6 mA 100 Ω load between Y and Z
DD1
Power Supply Current, Bus Side
TxD/RxD Data Rate < 2 Mbps I TxD/RxD Data Rate = 16 Mbps I
4.0 mA 2.7 V ≤ V
DD2
60 mA 100 Ω load between Y and Z
DD2
DRIVER
Differential Outputs
Differential Output Voltage, Loaded |V
| 2.0 5.0 V RL = 50 Ω (RS-422), see Figure 3
OD2
1.5 5.0 V RL = 27 Ω (RS-485), see Figure 3 |V
| 1.5 5.0 V −7 V ≤ V
OD4
∆|VOD| for Complementary Output States ∆|VOD| 0.2 V RL = 54 Ω or 100 Ω, see Figure 3 Common-Mode Output Voltage VOC 3.0 V RL = 54 Ω or 100 Ω, see Figure 3 ∆|VOC| for Complementary Output States ∆|VOC| 0.2 V RL = 54 Ω or 100 Ω, see Figure 3 Short-Circuit Output Current IOS 200 mA
Logic Inputs
Input Threshold Low VIL 0.25 × V Input Threshold High VIH 0.7 × V TxD Input Current I
−10 +0.01 +10 μA
TxD
RECEIVER
Differential Inputs
Differential Input Threshold Voltage VTH −0.2 +0.2 V Input Voltage Hysteresis V
70 mV VOC = 0 V
HYS
Input Current (A, B) II 1.0 mA VOC = 12 V
−0.8 mA VOC = −7 V Line Input Resistance RIN 12
Logic Outputs
Output Voltage Low V Output Voltage High V
OLRxD
OHRxD
Short-Circuit Current 100 mA
COMMON-MODE TRANSIENT IMMUNITY
1
CM is the maximum common-mode voltage slew rate that can be sustained while maintaining specification-compliant operation. VCM is the common-mode potential
difference between the logic and bus sides. The transient magnitude is the range over which the common-mode is slewed. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
1
25 kV/μs
≤ 5.5 V, 4.5 V ≤ V
DD1
V
DD1
≤ 5.5 V. All minimum/maximum specifications apply
DD2
V
DD1
0.2 0.4 V I V
− 0.3 V
DD1
− 0.2 V I
DD1
= 25°C, V
A
DD1
= V
≤ 5.5 V, unloaded
DD1
≤ 5.5 V, unloaded
DD1
≤ +12 V, see Figure 4
TEST1
= 1.5 mA, VA − VB = −0.2 V
ORxD
= −1.5 mA, VA − VB = 0.2 V
ORxD
= 1 kV, transient
V
CM
magnitude = 800 V
= 5.0 V,
DD2
Rev. A | Page 3 of 16
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TIMING SPECIFICATIONS

TA = −40°C to +85°C.
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions
DRIVER
Maximum Data Rate 16 Mbps Propagation Delay t
Pulse Width Distortion,
PWD = |t
PYLH
|, PWD = |t
PYHL
PZLH
− t
PZHL
|
− t
Single-Ended Output Rise/Fall Times tR, tF 20 ns
RECEIVER
Propagation Delay t Pulse Width Distortion, PWD = |t
PLH
− t
| t
PHL
T
= −40°C to +105°C.
A
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions
DRIVER
Maximum Data Rate 10 Mbps Propagation Delay
Pulse Width Distortion,
PWD = |t
PYLH
|, PWD = |t
PYHL
PZLH
− t
PZHL
|
− t
Single-Ended Output Rise/Fall Time tR, tF 27 ns
RECEIVER
Propagation Delay t
Pulse Width Distortion, PWD = |t
PLH
− t
PHL
| t
, t
45 60 ns
PLH
PHL
, t
t
PWD
PLH
PWD
7 ns
PWD
, t
60 ns CL = 15 pF, see Figure 7 and Figure 9
PHL
10 ns CL = 15 pF, see Figure 7 and Figure 9
t t
t
PYLH
PZLH
PWD
, t
PYHL
, t
PZHL
, t
PWD
45 60 ns
,
9 ns
= 54 Ω, CL1 = C
R
L
= 100 pF,
L2
see Figure 6 and Figure 8
= 54 Ω, CL1 = CL2 = 100 pF,
R
L
see Figure 6 and Figure 8
= 54 Ω, CL1 = CL2 = 100 pF,
R
L
see Figure 6 and Figure 8
= 54 Ω, CL1 = CL2 = 100 pF,
R
L
see Figure 6 and Figure 8
= 54 Ω, CL1 = CL2 = 100 pF,
R
L
see Figure 6 and Figure 8
= 54 Ω, CL1 = CL2 = 100 pF,
R
L
see Figure 6 and Figure 8
, t
60 ns
PLH
PHL
10 ns
PWD
= 15 pF, see Figure 7 and
C
L
Figure 9 C
Figure 9
= 15 pF, see Figure 7 and
L

PACKAGE CHARACTERISTICS

Table 4.
Parameter Symbol Min Typ Max Unit Test Conditions
Resistance (Input to Output) Capacitance (Input to Output) Input Capacitance
2
C
Input IC Junction-to-Case Thermal Resistance θ
Output IC Junction-to-Case Thermal Resistance θ
1
Device considered a 2-terminal device: Pin 1, Pin 2, Pin 3, Pin 4, Pin 5, Pin 6, Pin 7, and Pin 8 are shorted together and Pin 9, Pin 10, Pin 11, Pin 12, Pin 13, Pin 14, Pin 15,
and Pin 16 are shorted together.
2
Input capacitance is from any input data pin to ground.
1
1
R
1012 Ω
I-O
C
3 pF f = 1 MHz
I-O
4 pF
I
33 °C/W
JCI
28 °C/W
JCO
Rev. A | Page 4 of 16
Thermocouple located at center of package underside
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REGULATORY INFORMATION

Table 5. ADM2490E Approvals
Organization Approval Type Notes
UL
VDE

INSULATION AND SAFETY-RELATED SPECIFICATIONS

Table 6.
Parameter Symbol Value Unit Conditions
Rated Dielectric Insulation Voltage 5000 V rms 1 minute duration Minimum External Air Gap (Clearance) L(I01) 7.45 mm min
Minimum External Tracking (Creepage) L(I02) 8.1 mm min
Minimum Internal Gap (Internal Clearance) 0.017 mm min Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1 Isolation Group IIIa Material Group (DIN VDE 0110, 1/89)
Recognized under the Component Recognition Program of Underwriters Laboratories, Inc.
Certified according to DIN EN 60747-5-2 (VDE 0884-10 Part 2): 2003-01, DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000
In accordance with UL 1577, each ADM2490E is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 10 μA).
In accordance with DIN EN 60747-5-2, each ADM2490E is proof tested by applying an insulation test voltage ≥ 1590 V peak for 1 second (partial discharge detection limit = 5 pC).
Measured from input terminals to output terminals, shortest distance through air
Measured from input terminals to output terminals, shortest distance along body

VDE 0884-10 INSULATION CHARACTERISTICS

This isolator is suitable for basic electrical isolation only within the safety limit data. Maintenance of the safety data must be ensured by means of protective circuits.
An asterisk (*) on a package denotes VDE 0884-10 approval for 848 V peak working voltage.
Table 7.
Description Symbol Characteristic Unit
Installation Classification per DIN VDE 0110 for Rated Mains Voltage
≤300 V rms I to IV ≤450 V rms I to II
≤600 V rms I to II Climatic Classification 40/105/21 Pollution Degree (DIN VDE 0110, see Table 1 ) 2 Maximum Working Insulation Voltage V Input-to-Output Test Voltage, Method b1 VPR 1590 V peak
V
× 1.875 = VPR, 100% Production Tested, tm = 1 sec, Partial Discharge < 5 pC
IORM
Input-to-Output Test Voltage, Method a
After Environmental Tests, Subgroup 1
V
× 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC 1357 V peak
IORM
After Input and/or Safety Test, Subgroup 2/3
V
× 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC VPR 1018 V peak
IORM
Highest Allowable Overvoltage (Transient Overvoltage, tTR = 10 sec) VTR 6000 V peak Safety-Limiting Values (Maximum Value Allowed in the Event of a Failure; see Figure 16)
Case Temperature TS 150 °C
Input Current I
Output Current I Insulation Resistance at TS, VIO = 500 V RS >109 Ω
848 V peak
IORM
265 mA
S, INPUT
335 mA
S, OUTPUT
Rev. A | Page 5 of 16
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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Each voltage is relative to its respective ground.
Table 8.
Parameter Rating
Storage Temperature Range −55°C to +150°C Ambient Operating Temperature Range −40°C to +105°C V
−0.5 V to +7 V
DD1
V
−0.5 V to +6 V
DD2
Logic Input Voltages −0.5 V to V Bus Terminal Voltages −9 V to +14 V Logic Output Voltages −0.5 V to V Average Output Current, per Pin ±35 mA ESD (Human Body Model)
on A, B, Y, and Z Pins
θJA Thermal Impedance 60°C/W
±8 kV
DD1
DD1
+ 0.5 V
+ 0.5 V
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Absolute maximum ratings apply individually only, not in combination.

ESD CAUTION

Rev. A | Page 6 of 16
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1
V
DD1
GND
2
1
RxD
3
4
NC
GND
5
1
TxD
6
7
NC
GND
8
1
NC = NO CONNECT
ADM2490E
TOP VIEW
(Not to Scale)
16
15
14
13
12
11
10
9
Figure 2. Pin Configuration
Table 9. Pin Function Descriptions
Pin No. Mnemonic Description
1 V
DD1
Power Supply (Logic Side). Decoupling capacitor to GND
0.01 μF and 0.1 μF. 2, 5, 8 GND1 Ground (Logic Side). 3 RxD Receiver Output. 4, 7, 12 NC No Connect. These pins must be left floating. 6 TxD Transmit Data. 9, 15 GND2 Ground (Bus Side). 10 Y Driver Noninverting Output. 11 Z Driver Inverting Output. 13 B Receiver Inverting Input. 14 A Receiver Noninverting Input. 16 V
DD2
Power Supply (Bus Side). Decoupling capacitor to GND
0.01 μF and 0.1 μF.
V
DD2
GND
A
B
NC
Z
Y
GND
2
2
05889-002
required; capacitor value should be between
1
required; capacitor value should be between
2
Rev. A | Page 7 of 16
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TEST CIRCUITS

R
V
OD
L
R
L
Figure 3. Driver Voltage Measurement
375
Y
V
OC
05889-003
Z
R
LDIFF
Figure 6. Driver Propagation Delay
C
L1
C
L2
05889-005
V
60
OD3
375
V
TEST
05889-004
Figure 4. Driver Voltage Measurement
DD2
TxD
RxD
V
DD1
GND
GALVANIC ISOLATION
1
V
GND
DD2
220
Y
100
Z
220
A
B
2
GND
2
05889-014
Figure 5. Supply-Current Measurement Test Circuit (See Figure 10 and Figure 11)
V
B
OUT
C
L
05889-006
Figure 7. Receiver Propagation Delay
Rev. A | Page 8 of 16
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SWITCHING CHARACTERISTICS

3
0V
Z
1/2VO
VO
Y
V
OH
, B
V
OL
90% POINT 90% POINT
10% POINT 10% POINT
Figure 8. Driver Propagation Delay, Rise/Fall Timing
A, B
RxD
1.5V
t
PLH
t
= |
t
PLH
t
PHL
PWD
t
R
0V 0V
t
PLH
1.5V 1.5V
1.5V
t
PHL
|
t
F
t
PHL
V
OH
5889-007
Figure 9. Receiver Propagation Delay
V
OL
05889-008
Rev. A | Page 9 of 16
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TYPICAL PERFORMANCE CHARACTERISTICS

3.00
60
2.95
2.90
(mA)
2.85
DD1
I
2.80
2.75
2.70 –40 –20 0 20 40 60 80 100
Figure 10. I
70
60
50
40
(mA)
DD2
30
I
20
Supply Current vs. Temperature (See Figure 5)
DD1
220-100-220 LOAD
100 LOAD
NO LOAD 100 LOAD 220-100-220 LOAD
TEMPERATURE (°C)
50
40
Y(ns)
30
DEL
20
10
0
–40 –20 0 20 40 60 80 100
05889-015
TEMPERATURE (°C)
t
PLH
t
PHL
05889-018
Figure 13. Receiver Propagation Delay vs. Temperature
TxD
1
Y AND Z OUTPUT S
2
RxD
10
0
–40 –20 0 20 40 60 80 100
Figure 11. I
60
50
40
Y (ns)
30
DEL
20
10
0
–40 –20 0 20 40 60 80 100
NO LOAD
TEMPERATURE (°C)
Supply Current vs. Temperature (See Figure 5)
DD2
TEMPERATURE (°C)
Figure 12. Driver Propagation Delay vs. Temperature
t
PZHL
t
PYLH
t
PZLH
t
PYHL
4
CH1 2V CH2 2V
05889-016
CH3 2V CH4 2V
M20ns A CH2 2.84V
T 44.2%
05889-019
Figure 14. Driver/Receiver Propagation Delay, Low to High
= 54 Ω, CL1 = CL2 = 100 pF)
(R
LDIFF
1
2
4
CH1 2V CH2 2V
05889-017
CH3 2V CH4 2V
M20ns A CH2 2.84V
T 44.2%
TxD
Y AND Z OUTPUTS
RxD
05889-020
Figure 15. Driver/Receiver Propagation Delay, High to Low
= 54 Ω, CL1 = CL2 = 100 pF)
(R
LDIFF
Rev. A | Page 10 of 16
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350
300
250
200
150
100
SAFETY-LIMITING CURRENT (mA)
50
0
0
SIDE 2
SIDE 1
50 100 150 200
CASE TEMPERATURE (°C)
05889-021
Figure 16. Thermal Derating Curve, Dependence of Safety-Limiting Values
with Case Temperature per VDE 0884-10
4.77
4.76
4.75
4.74
4.73
4.72
4.71
VOLTAGE (V)
4.70
4.69
4.68
4.67
4.66 –40 –20 0 20 40 60 80 100
TEMPERATURE (°C)
Figure 19. Receiver Output High Voltage vs. Temperature,
= −4 mA
I
RxD
05889-024
0
–2
–4
–6
–8
CURRENT (mA)
–10
–12
–14
4.0 4.2 4.4 4.6 4. 8 5. 0
VOLTAGE (V)
Figure 17. Output Current vs. Receiver Output High Voltage
16
14
12
10
8
0.35
0.30
0.25
0.20
0.15
VOLTAGE (V)
0.10
0.05
0
05889-022
–40 –20 0 20 40 60 80 100
TEMPERATURE (°C)
05889-025
Figure 20. Receiver Output Low Voltage vs. Temperature,
= –4 mA
I
RxD
6
CURRENT (mA)
4
2
0
0 0.2 0.4 0.6
VOLTAGE (V)
0.8 1.0 1.2
05889-023
Figure 18. Output Current vs. Receiver Output Low Voltage
Rev. A | Page 11 of 16
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CIRCUIT DESCRIPTION

ELECTRICAL ISOLATION

In the ADM2490E, electrical isolation is implemented on the logic side of the interface. Therefore, the part has two main sections: a digital isolation section and a transceiver section (see Figure 21). The driver input signal, which is applied to the TxD pin and referenced to logic ground (GND across an isolation barrier to appear at the transceiver section referenced to isolated ground (GND
). Similarly, the receiver
2
input, which is referenced to isolated ground in the transceiver section, is coupled across the isolation barrier to appear at the RxD pin referenced to logic ground.

iCoupler Technology

The digital signals transmit across the isolation barrier using iCoupler technology. This technique uses chip scale transformer windings to couple the digital signals magnetically from one side of the barrier to the other. Digital inputs are encoded into waveforms that are capable of exciting the primary transformer winding. At the secondary winding, the induced waveforms are decoded into the binary value that was originally transmitted.
Positive and negative logic transitions at the input cause narrow pulses (~1 ns) to be sent to the decoder via the transformer. The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than ~1 μs, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. If the decoder receives no internal pulses for more than about 5 μs, the input side is assumed to be unpowered or nonfunctional, in which case the output is forced to a default state (see Tab l e 1 2 ).
), is coupled
1
DD1
ISOLATION
BARRIER

TRUTH TABLES

The truth tables in this section use the abbreviations shown in Tabl e 10 .
Table 10. Truth Table Abbreviations
Abbreviation Description
H High level I Indeterminate L Low level X Irrelevant
Table 11. Transmitting
Supply Status Input Outputs
V
V
DD1
On On H H L On On L L H
Table 12. Receiving
Supply Status Inputs Output
V
V
DD1
On On >0.2 H On On <−0.2 L On On −0.2 < A − B < +0.2 I On On Inputs open H On Off X H Off On X H Off Off X L
V
DD2
TxD Y Z
DD2
A − B (V) RxD
DD2
TxD
RxD
ENCODE
DECODE
DIGITAL ISOLATION
GND
1
Figure 21. ADM2490E Digital Isolation and Transceiver Sections
DECODE
ENCODE
Rev. A | Page 12 of 16
TRANSCEIVER
GND
2
D
R
Y
Z
A
B
05889-009
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THERMAL SHUTDOWN

The ADM2490E contains thermal-shutdown circuitry that protects the part from excessive power dissipation during fault conditions. Shorting the driver outputs to a low impedance source can result in high driver currents. The thermal sensing circuitry detects the increase in die temperature under this condition and disables the driver outputs. This circuitry is designed to disable the driver outputs when a die temperature of 150°C is reached. As the device cools, the drivers are re-enabled at a temperature of 140°C.

FAIL-SAFE RECEIVER INPUTS

The receiver inputs include a fail-safe feature that guarantees a logic high on the RxD pin when the A and B inputs are floating or open-circuited.

MAGNETIC FIELD IMMUNITY

The limitation on the magnetic field immunity of the iCoupler is set by the condition in which an induced voltage in the receiv­ing coil of the transformer is large enough to either falsely set or reset the decoder. The following analysis defines the conditions under which this may occur. The 3 V operating condition of the ADM2490E is examined because it represents the most susceptible mode of operation.
The pulses at the transformer output have an amplitude greater than 1 V. The decoder has a sensing threshold of about 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated.
The voltage induced across the receiving coil is given by
=
V
dt
where:
β is the magnetic flux density (gauss). N is the number of turns in the receiving coil.
is the radius of the nth turn in the receiving coil (cm).
r
n
Given the geometry of the receiving coil and an imposed requirement that the induced voltage is, at most, 50% of the
0.5 V margin at the decoder, a maximum allowable magnetic field can be determined using Figure 22.
2
n
Nnr
,,2,1;
K=π
100
10
1
0.1
FLUX DE NSITY (kGAUSS)
0.01
MAXIMUM ALLOWABLE MAGNETIC
0.001 1k 10k 100k 100M1M 10M
Figure 22. Maximum Allowable External Magnetic Flux Density
MAGNETIC FIELD FREQUENCY (Hz)
5889-010
For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurs during a transmitted pulse and is the worst-case polarity, it reduces the received pulse from >1.0 V to 0.75 V, still well above the 0.5 V sensing threshold of the decoder.
Figure 23 shows the magnetic flux density values in terms of more familiar quantities, such as maximum allowable current flow at given distances away from the ADM2490E transformers.
1000
DISTANCE = 1m
100
DISTANCE = 5mm
10
1
0.1
MAXIMUM ALLOWABLE CURRENT (kA)
0.01
DISTANCE = 100mm
1k 10k 100k 100M1M 10M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 23. Maximum Allowable Current for
Various Current-to-ADM2490E Spacings
05889-011
With combinations of strong magnetic field and high frequency, any loops formed by PCB traces can induce error voltages large enough to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility.
Rev. A | Page 13 of 16
Page 14
ADM2490E
L
A
www.BDTIC.com/ADI

APPLICATIONS INFORMATION

ISOLATED POWER SUPPLY CIRCUIT

The ADM2490E requires isolated power capable of 5 V at up to approximately 65 mA (this current is dependent on the data rate and termination resistors used) to be supplied between the V
and the GND2 pins. A transformer driver circuit with a
DD2
center-tapped transformer and LDO can be used to generate the isolated 5 V supply, as shown in Figure 25. The center-tapped transformer provides electrical isolation of the 5 V power supply. The primary winding of the transformer is excited with a pair of square waveforms that are 180° out of phase with each other. A pair of Schottky diodes and a smoothing capacitor are used to create a rectified signal from the secondary winding. The ADP3330 linear voltage regulator provides a regulated power supply to the bus-side circuitry (V
) of the ADM2490E.
DD2

PCB LAYOUT

The ADM2490E isolated RS-485 transceiver requires no external interface circuitry for the logic interfaces. Power supply bypass­ing is required at the input and output supply pins (see Figure 24). Bypass capacitors are conveniently connected between Pin 1 and Pin 2 for V capacitor value should be between 0.01 μF and 0.1 μF. The total
and between Pin 15 and Pin 16 for V
DD1
V
CC
TRANSFORMER
DRIVER
DD2
V
CC
. The
ISO
BARRIER
78253
TION
lead length between both ends of the capacitor and the input power-supply pin should not exceed 20 mm. Bypassing between Pin 1 and Pin 8 and between Pin 9 and Pin 16 should also be considered unless the ground pair on each package side is connected close to the package.
V
DD1
GND
1
RxD
GND
TxD
GND
NC
1
NC
1
ADM2490E
NC = NO CONNECT
Figure 24. Recommended Printed Circuit Board Layout
V GND A B NC Z Y GND
In applications involving high common-mode transients, care should be taken to ensure that board coupling across the isola­tion barrier is minimized. Furthermore, the board layout should be designed such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this could cause voltage differentials between pins exceeding the absolute maximum ratings of the device, thereby leading to latch-up or permanent damage.
SD103C
SD103C
22µF
IN
ADP3330
SD GND ERR
OUT
5V
10µF
DD2
2
2
5889-013
V
CC
V
DD1
V
DD2
ADM2490E
GND
GND
1
Figure 25. Isolated Power-Supply Circuit
Rev. A | Page 14 of 16
2
05889-012
Page 15
ADM2490E
www.BDTIC.com/ADI

TYPICAL APPLICATIONS

The ADM2490E transceiver is designed for point-to-point transmission lines. Figure 26 shows a full-duplex point-to-point application. To minimize reflections, terminate the line at the receiver end with a termination resistor. The value of the termination resistor should be equal to the characteristic impedance of the cable.
RxO
A
R
R
T
B
Y
TxD
Z
D
Z
TxD
D
Y
ADM2490E
NOTES
IS EQUAL TO THE CHARACTERIST IC IMPEDANCE OF THE CABLE.
1. R
T
B
R
T
A
R
RxD
ADM2490E
05889-026
Figure 26. Full-Duplex Point-to-Point Application
Rev. A | Page 15 of 16
Page 16
ADM2490E
C
www.BDTIC.com/ADI

OUTLINE DIMENSIONS

10.50 (0.4134)
10.10 (0.3976)
BSC
9
7.60 (0.2992)
7.40 (0.2913)
8
10.65 (0.4193)
10.00 (0.3937)
2.65 (0.1043)
2.35 (0.0925)
SEATING PLANE
8° 0°
0.33 (0.0130)
0.20 (0.0079)
0 0
.
7
.
2
5
(
0
5
(
0
.
0
2
9
5
)
0
0
9
8
)
.
1.27 (0.0500)
0.40 (0.0157)
45°
032707-B
0.30 (0.0 118)
0.10 (0.0039)
OPLANARITY
0.10
16
1
1.27 (0.0500)
0.51 (0.0201)
0.31 (0.0122)
CONTROLL ING DIMENS IONS ARE IN MILLIM ETERS; INCH DI MENSIONS (IN PARENTHESES) ARE ROUNDED-O FF MIL LIMETE R EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRI ATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013- AA
Figure 27. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Model Temperature Range Package Description Package Option
ADM2490EBRWZ ADM2490EBRWZ-REEL7
1
Z = RoHS Compliant Part.
1
−40°C to +105°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
1
−40°C to +105°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
©2006–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05889-0-8/08(A)
Rev. A | Page 16 of 16
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