Datasheet ADM1177 Datasheet (ANALOG DEVICES)

V

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Hot Swap Controller and

Digital Power Monitor with Soft Start Pin

FEATURES

Allows safe board insertion and removal from a live

backplane
Controls supply voltages from 3.15 V to 16.5 V
Precision current sense amplifier
Precision voltage input
12-bit ADC for current and voltage readback
Charge pumped gate drive for external N-channel FET
Adjustable analog current limit with circuit breaker
±3% accurate hot swap current limit level
Fast response limits peak fault current
Automatic retry or latch-off on current fault
Programmable hot swap timing via TIMER pin
Soft start pin for reference adjustment and programming of

initial current ramp rate
Active-high ON pin

2

C® fast mode-compliant interface (400 kHz maximum)

I
10-lead MSOP

APPLICATIONS

Power monitoring/power budgeting
Central office equipment
Telecommunication and data communication equipment
PCs/servers

GENERAL DESCRIPTION

The ADM1177 is an integrated hot swap controller that offers
digital current and voltage monitoring via an on-chip, 12-bit
analog-to-digital converter (ADC), communicated through an

2

I

C interface.

VCC

SENSE

3.15V TO 16.5

FUNCTIONAL BLOCK DIAGRAM

ADM1177

MUX

V

AMPLIFIER

ON

1.3V
UV COMPARATOR

0

I

R

GND

1

SENSE

SENSEVCC

GATE

SDA

SCL

ADR

A

CURRENT

SENSE

GND

ADM1177

ON

SS
TIMER

Figure 2. Applications Diagram

12-BIT

ADC

FET DRIVE

CONTROLLER

TIMERSS

Figure 1.

N-CHANNEL FET

ADM1177

C

P = VI

SDA
SCL
ADR

GATE

2

I

CONTROLLER

SDA
SCL

06047-001

06047-002

An internal current sense amplifier senses voltage across the sense
resistor in the power path via the VCC pin and the SENSE pin.

The ADM1177 limits the current through this resistor by control­ling the gate voltage of an external N-channel FET in the power
path, via the GATE pin. The sense voltage (and, therefore, the
inrush current) is kept below a preset maximum.

The ADM1177 protects the external FET by limiting the time
that it spends with maximum current running through it. This
current limit period is set by the choice of capacitor attached to
the TIMER pin. Additionally, the device provides protection from
overcurrent events that may occur once the hot swap event is
complete. In the case of a short-circuit event, the current in the
sense resistor exceeds an overcurrent trip threshold, and the FET
is switched off immediately by pulling down the GATE pin.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

A soft start (SS) pin is also included. This gives the user control
over the reference on the current sense amplifier. An internal
current source charges a capacitor on this pin at startup, allowing
the user to set the profile of the initial current ramp. A voltage
can also be driven on this pin to alter the reference.

A 12-bit ADC can measure the current seen in the sense resistor,
as well as the supply voltage on the VCC pin. An industry-standard

2

I

C interface allows a controller to read current and voltage data

from the ADC. Measurements can be initiated by an I

2

Alternatively, the ADC can run continuously, and the user can
read the latest conversion data whenever it is required. Up to
four unique I

2

C addresses can be created, depending on the way

the ADR pin is connected.

The ADM1177 is packaged in a 10-lead MSOP.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

C command.

ADM1177

TABLE OF CONTENTS

Features.............................................................................................. 1

Initial Timing Cycle ................................................................... 14

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Overview of the Hot Swap Function............................................ 13

Undervoltage Lockout ............................................................... 13

ON Function ............................................................................... 13

TIMER Function ........................................................................13

GATE and TIMER Functions During a Hot Swap ................ 14

Calculating Current Limits and Fault Current Limit Time.. 14

Hot Swap Retry Cycle on the ADM1177-1............................. 15

Soft Start (SS Pin)....................................................................... 15

Voltage and Current Readback..................................................... 16

Serial Bus Interface..................................................................... 16

Identifying the ADM1177 on the I

General I

Write and Read Operations ...................................................... 18

Quick Command........................................................................ 18

Write Command Byte................................................................ 18

Write Extended Byte .................................................................. 19

Read Voltage and/or Current Data Bytes................................ 20

Applications Waveforms................................................................ 22

Kelvin Sense Resistor Connection ........................................... 23

Outline Dimensions....................................................................... 24

Ordering Guide .......................................................................... 24

2

C Timing.................................................................... 16

2

C Bus............................... 16

REVISION HISTORY

9/06—Revision 0: Initial Version

Rev. 0 | Page 2 of 24

ADM1177

SPECIFICATIONS

VCC = 3.15 V to 16.5 V; TA = −40°C to +85°C; typical values at TA = 25°C, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Conditions

VCC PIN

Operating Voltage Range, V
Supply Current, ICC 1.7 2.5 mA
Undervoltage Lockout, V
Undervoltage Lockout Hysteresis, V

ON PIN

Input Current, I

INON

−2 +2 μA
Rising Threshold, V

ONTH

Trip Threshold Hysteresis, V
Glitch Filter Time 3 μs

SS PIN

Pull-Up Current, I

ISSPU

Current Setting Gain, GAINSS 9.5 10 10.5 V/V VSS/VCB; VSS = 0.5 V to 1 V.
Soft Start Completion Voltage, SS
Pull-Down Current, I

ISSPD

SENSE PIN

Input Leakage, I

−1 +1 μA V

SENSE

Overcurrent Fault Timing Threshold, V

Overcurrent Limit Threshold, V

Fast Overcurrent Trip Threshold, V

GATE PIN

Drive Voltage, V

3 6 9 V V

GATE

Pull-Up Current 8 12.5 17 μA V
Pull-Down Current 1.5 mA V
5 mA V
7 mA V

TIMER PIN

Pull-Up Current (Power On Reset), I
Pull-Up Current (Fault Mode), I
Pull-Down Current (Retry Mode), I

Pull-Down Current, I
Trip Threshold Hig h, V
Trip Thresho ld Low, V

TIMERDN

TIMERH

TIMERL

ADR PIN

Set Address to 00, V
Set Address to 01, R

Set Address to 10, I

Set Address to 11, V

ADRLOWV

ADRLOWZ

ADRHIGHZ

ADRHIGHV

Input Current for 11 Decode, I
Input Current for 00 Decode, I

3.15 16.5 V

VCC

2.8 V VCC rising

UVLO

80 mV

UVLOHYST

−100

+100 nA ON < 1.5 V

1.26 1.3 1.34 V ON rising
35 50 65 mV

ONHYST

1 V SS continues to pull up beyond 1 V

HIGHV

10

μA VSS = 0 V to 1 V

70 μA Under fault

= V

92 mV

OCTIM

SENSE

V

OCTRIM

= (V

VCC

VCC

− V

), fault timing starts on the

SENSE

TIMER pin

97 100 103 mV

LIM

V

= (V

− V

LIM

VCC

), closed-loop regulation to a

SENSE

current limit

115 mV

OCFAST

V

OCFAST

= (V

VCC

− V

), gate pull-down current

SENSE

turned on

− V

, V

VCC

VCC

VCC

, V
, V

VCC

VCC

VCC

VCC

VCC

VCC

TIMER

= 3.15 V
= 5 V
= 16.5 V

= 3.15 V
= 5 V
= 16.5 V

= 1 V

TIMER

TIMER

= 1 V

= 1 V

TIMER

= 1 V

GATE

TIMERUPPOR

TIMERUPFAULT

TIMERDNRETRY

9 11 13 V V
7 10 13 V V

−3.5 −5 −6.5 μA Initial cycle, V

−40 −60 −80 μA During current fault, V
2 3 μA

− V

GATE

− V

GATE

= 0 V

GATE

= 3 V, V

GATE

= 3 V, V

GATE

= 3 V, V

GATE

After current fault and during a cool-down
period on a retry device, V

100 μA Normal operation, V

1.26 1.3 1.34 V TIMER rising

0.175 0.2 0.225 V TIMER falling

0 0.8 V Low state

135 150 165 kΩ

Resistor to ground state, load pin with specified
resistance for 01 decode

−1 +1 μA

Open state, maximum load allowed on ADR pin
for 10 decode

2 5.5 V High state

3 10 μA V

ADRLOW

−40 −22 μA V

ADRHIGH

= 2.0 V to 5.5 V

ADR

= 0 V to 0.8 V

ADR

Rev. 0 | Page 3 of 24

ADM1177

Parameter Min Typ Max Unit Conditions

MONITORING ACCURACY

Current Sense Absolute Accuracy −1.45

−1.8

−2.8

−5.7

−1.5

−1.8

−2.95

−6.1

−1.95

−2.45

−3.85

−6.7

V

for ADC Full Scale 105.84 mV

SENSE

Voltage Sense Accuracy −0.85

−0.9 +0.9 %

−0.85

−0.9 +0.9 %

−0.9

−1.15 +1.15 %

VCC for ADC Full Scale,
Low Range (VRANGE = 1)
VCC for ADC Full-Scale,
High Range (VRANGE = 0)

I2C TIMING

Low Level Input Voltage, V
High Level Input Voltage, V
Low Level Output Voltage on SDA, V
Output Fall Time on SDA from V

Maximum Width of Spikes Suppressed by
Input Filtering on SDA and SCL Pins

Input Current, II, on SDA/SCL When Not
Driving Out a Logic Low

Input Capacitance on SDA/SCL 5 pF

SCL Clock Frequency, f

Low Period of the SCL Clock 600 ns
High Period of the SCL Clock 1300 ns

1

+1.45 % V

+1.8 % V

+2.8 % V

+5.7 % V

+1.5 % V

+1.8 % V

+2.95 % V

+6.1 % V

+1.95 % V

+2.45 % V

+3.85 % V

+6.7 % V

SENSE

SENSE

SENSE

SENSE

SENSE

SENSE

SENSE

SENSE

SENSE

SENSE

SENSE

SENSE

This is an absolute value to be used when
converting ADC codes to current readings;
any inaccuracy in this value is factored into
absolute current accuracy values (see specs
for Current Sense Absolute Accuracy)

+0.85 %

VCC = 3 V minimum
(low range)

= 6 V minimum

V

CC

(high range)

+0.85 %

VCC = 3 V minimum
(low range)

= 6 V minimum

V

CC

(high range)

+0.9 %

VCC = 3 V minimum
(low range)

= 6 V minimum

V

CC

(high range)

6.65 V

These are absolute values to be used when
converting ADC codes to voltage readings;

26.35 V

any inaccuracy in these values is factored into
voltage accuracy values (see specs for Voltage
Accuracy)

0.3 V

IL

0.7 V

IH

0.4 V I

OL

to V

IHMIN

ILMAX

V

BUS

20 +

0.1 C

250 ns CB = bus capacitance from SDA to GND

B

V

BUS

= 3 mA

OL

50 250 ns

−10 +10 μA

400 kHz

SCL

= 75 mV 0°C to +70°C

= 50 mV 0°C to +70°C

= 25 mV 0°C to +70°C

= 12.5 mV 0°C to +70°C

= 75 mV 0°C to +85°C

= 50 mV 0°C to +85°C

= 25 mV 0°C to +85°C

= 12.5 mV 0°C to +85°C

= 75 mV −40°C to +85°C

= 50 mV −40°C to +85°C

= 25 mV −40°C to +85°C

= 12.5 mV −40°C to +85°C

0°C to +70°C

0°C to +70°C

0°C to +85°C

0°C to +85°C

−40°C to +85°C

−40°C to +85°C

Rev. 0 | Page 4 of 24

ADM1177

Parameter Min Typ Max Unit Conditions

Setup Time for a Repeated Start Condition,
t

SU;STA

SDA Output Data Hold Time, t
Setup Time for a Stop Condition, t

100 900 ns

HD;DAT

600 ns

SU;STO

Bus Free Time Between a Stop and a Start
Condition, t

BUF

Capacitive Load for Each Bus Line 400 pF

1

Monitoring accuracy is a measure of the error in a code that is read back for a particular voltage/current. This is a combination of amplifier error, reference error, ADC

error, and error in ADC full-scale code conversion factor.

600 ns

1300 ns

Rev. 0 | Page 5 of 24

ADM1177

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

VCC Pin 20 V
SENSE Pin 20 V
TIMER Pin −0.3 V to +6 V
ON Pin −0.3 V to +20 V
SS Pin −0.3 V to +6 V
GATE Pin 30 V
SDA Pin, SCL Pin −0.3 V to +7 V
ADR Pin −0.3 V to +6 V
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering, 10 sec) 300°C
Junction Temperature 150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Table 3. Thermal Resistance

Package Type θJA Unit

10-Lead MSOP 137.5 °C/W

ESD CAUTION

Rev. 0 | Page 6 of 24

ADM1177

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

VCC

SENSE

2

ADM1177

ON

3

TOP VIEW

(Not to S cale)

GND

4
5

TIMER

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 VCC

Positive Supply Input Pin. The operating supply voltage range is from 3.15 V to 16.5 V. An undervoltage
lockout (UVLO) circuit resets the ADM1175 when a low supply voltage is detected.

2 SENSE

Current Sense Input Pin. A sense resistor between the VCC pin and the SENSE pin sets the analog current
limit. The hot swap operation of the ADM1175 controls the external FET gate to maintain the (V
voltage at 100 mV or below.

3 ON

Undervoltage Input Pin. Active-high pin. An internal ON comparator has a trip threshold of 1.3 V, and the
output of this comparator is used as an enable for the hot swap operation. With an external resistor divider
from VCC to GND, this pin can be used to enable the hot swap operation on a specific voltage on VCC, giving

an undervoltage function.
4 GND Chip Ground Pin.
5 TIMER

Timer Pin. An external capacitor, C

, sets a 270 ms/μF initial timing cycle delay and a 21.7 ms/μF fault delay.

TIMER

The GATE pin turns off when the TIMER pin is pulled beyond the upper threshold. An overvoltage detection

with an external Zener can be used to force this pin high.
6 SCL I2C Clock Pin. Open-drain input requires an external resistive pull-up.
7 SDA I2C Data I/O Pin. Open-drain input/output. Requires an external resistive pull-up.
8 ADR

9 SS

2

C Address Pin. This pin can be tied low, tied high, left floating, or tied low through a resistor to set four

I

different I

2

C addresses.

Soft Start Pin. This pin controls the reference on the current sense amplifier. A 10 μA current source charges

this pin at startup. A capacitor on this pin then sets the slope of the initial current ramp. This pin can also be

driven to a voltage to alter the reference directly, thereby adjusting the current limit level with a gain of 10.
10 GATE

GATE Output Pin. This pin is the high-side gate drive of an external N-channel FET. This pin is driven by the

FET drive controller, which utilizes a charge pump to provide a 12.5 μA pull-up current to charge the FET

GATE pin. The FET drive controller regulates to a maximum load current (100 mV through the sense resistor)

by modulating the GATE pin.

10

GATE
SS

9

ADR

8

SDA

7
6

SCL

06047-003

− V

SENSE

)

VCC

Rev. 0 | Page 7 of 24

ADM1177

TYPICAL PERFORMANCE CHARACTERISTICS

2.0

1.8

1.6

1.4

1.2

1.0

(mA)

CC

I

0.8

0.6

0.4

0.2

0

024681014112 16

VCC (V)

Figure 4. Supply Current vs. Supply Voltage

8

06047-021

2.0

1.8

1.6

1.4

1.2

1.0

(mA)

CC

I

0.8

0.6

0.4

0.2

0

–40 806040200–20

TEMPERATURE (°C)

Figure 7. Supply Current vs. Temperature (Gate On)

06047-022

12

10

8

6

DRIVE VOLTAGE (V)

4

2

0

01

Figure 5. Drive Voltage (V

0

–2

–4

–6

(µA)

–8

GATE

I

–10

VCC (V)

− VCC) vs. Supply Voltage

GATE

8161412108642

06047-029

12

10

8

6

DRIVE VOLTAGE ( V)

4

2

0

–40 806040200–20

Figure 8. Drive Voltage (V

0

–2

–4

–6

(µA)

–8

GATE

I

–10

5V V

3.15V V

TEMPERATURE (°C)

− VCC) vs. Temperature

GATE

CC

CC

06047-030

–12

–14

01

VCC (V)

10 12 16148642

8

06047-027

Figure 6. Gate Pull-Up Current vs. Supply Voltage

–12

–14

–40 806040200–20

Figure 9. Gate Pull-Up Current vs. Temperature

Rev. 0 | Page 8 of 24

TEMPERATURE (°C)

06047-028

ADM1177

12

10

8

(mA)

6

GATE

I

4

2

0

01

Figure 10. Gate Pull-Down Current vs. V

VCC (V)

CC

at V

GATE

161412108642

8

06047-031

= 5 V

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

TIMER THRES HO LD (V)

0.4

0.2

0

01810 12 16148642

HIGH

LOW

VCC (V)

06047-038

Figure 13. Timer Threshold vs. Supply Voltage

2

0

–2

–4

(µA)

–6

GATE

I

–8

–10

–12

–14

01

V

GATE

(V)

Figure 11. Gate Pull-Up Current vs. Gate Voltage at V

20

15

(mA)

10

GATE

I

5

VCC = 3V

0

02

V

V

CC

GATE

V

CC

= 5V

= 12V

(V)

1412108642

6

06047-040

= 5 V

CC

2015105

5

06047-043

Figure 12. Gate Pull-Down Current vs. Gate Voltage

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

TIMER HIG H THRESHOLD (V )

0.4

0.2

0
–40 80

Figure 14. Timer Threshold vs. Temperature

100

90

80

70

60

50

40

GATE ON TIME (ms)

30

20

10

0

05.04.54.03.53.02.52.01.51.00.5

Figure 15. Current Limit On Time vs. Timer Capacitance

HIGH

LOW

TEMPERATURE (°C)

C

(µF)

TIMER

6040200–20

06047-039

06047-050

Rev. 0 | Page 9 of 24

ADM1177

0

0

–1

–2

(µA)

–3

TIMER

I

–4

–5

–6

018

VCC (V)

10 12 16148642

06047-032

Figure 16.Timer Pull-Up Current (Initial Cycle) vs. Supply Voltage

0

–10

–20

–30

(µA)

–40

TIMER

I

–50

–60

–1

–2

(µA)

–3

TIMER

I

–4

–5

–6

–40 806040200–20

Figure 19. Timer Pull-Up Current (Initial Cycle) vs. Temperature

0

–10

–20

–30

(µA)

–40

TIMER

I

–50

–60

TEMPERATURE (°C)

06047-033

–70

–80

018

VCC (V)

10 12 16148642

06047-034

Figure 17. Timer Pull-Up Current (C. B. Delay) vs. Supply Voltage

3.0

2.5

2.0

(µA)

1.5

TIMER

I

1.0

0.5

0

01810 12 16148642

VCC (V)

06047-036

Figure 18. Timer Pull-Down Current (Cool-Off Cycle) vs. Supply Voltage

–70

–80

–40 806040200–20

Figure 20. Timer Pull-Up Current (C. B. Delay) vs. Temperature

3.0

2.5

2.0

(µA)

1.5

TIMER

I

1.0

0.5

0

–40 806040200–20

Figure 21. Timer Pull-Down Current (Cool-Off Cycle) vs. Temperature

TEMPERATURE (°C)

TEMPERATURE (°C)

06047-035

06047-037

Rev. 0 | Page 10 of 24

ADM1177

120

115

110

105

(mV)

100

LIM

V

95

90

85

80

21

VCC (V)

8

16141210864

06047-041

Figure 22. Circuit Breaker Limit Voltage vs. Supply Voltage

110

108

106

104

102

100

V (mV)

98

96

94

92

90

–40 806040200–20

Figure 23. V

V

OCFAST

V

LIM

V

OCTIM

TEMPERATURE (°C)

, V

, V

OCTIM

LIM

OCFAST

vs. Temperature

06047-042

1000

900

800

700

600

500

400

300

HITS PER CO DE ( 1000 RE ADS)

200

100

0

2047 2048 2049 20502046

CODE

Figure 25. ADC Noise, Current Channel, Midcode Input, 1000 Reads

1000

900

800

700

600

500

400

300

HITS PER CO DE ( 1000 RE ADS)

200

100

0

780 781 782 783779

CODE

Figure 26. ADC Noise, 14:1 Voltage Channel, 5 V Input, 1000 Reads

06047-060

06047-061

11 DECODE 10 DECODE 01 DECODE 00 DECODE

3.2

3.0

2.8

2.6

2.4

2.2

2.0

1.8

1.6

1.4

V (A0/A1)

1.2

1.0

0.8

0.6

0.4

0.2
0

–35 –30 –25 –20 –15 –10 –5 0 5 10

I (A0/A1) (µA)

Figure 24. Address Pin Voltage vs. Address Pin Current

for Four Addressing Options

06047-026

Rev. 0 | Page 11 of 24

1000

900

800

700

600

500

400

300

HITS PER CO DE ( 1000 RE ADS)

200

100

0

3079 3080 3081 30823078

CODE

Figure 27. ADC Noise, 7:1 Voltage Channel, 5 V Input, 1000 Reads

06047-062

ADM1177

11.0

10.8

10.6

10.4

10.2

(µA)

10.0

9.8

SOFT_START

I

9.6

9.4

9.2

9.0
–40 806040200–20

VCC = 5V

VCC = 3.15V

TEMPERATURE (°C)

Figure 30. SS Pin Pull-Up Current vs. Temperature

06047-044

INL (LSB)

4

3

2

1

0

–1

–2

–3

–4

0 40002500 3000 3500200015001000500

CODE

Figure 28. INL for ADC

06047-023

(mV)

LIM

V

110
100

90
80
70
60
50
40
30
20
10

0

011.21.00.80.60.40.2
V

SOFT_START

Figure 31. V

LIM

(V)

vs. VSS

.4

06047-045

DNL (LSB)

4

3

2

1

0

–1

–2

–3

–4

0 40002500 3000 3500200015001000500

CODE

Figure 29. DNL for ADC

06047-024

Rev. 0 | Page 12 of 24

ADM1177

OVERVIEW OF THE HOT SWAP FUNCTION

When circuit boards are inserted into a live backplane, discharged
supply bypass capacitors draw large transient currents from the
backplane power bus as they charge. Such transient currents can
cause permanent damage to connector pins, as well as dips on
the backplane supply that can reset other boards in the system.
The ADM1177 is designed to turn a circuit board supply voltage
on and off in a controlled manner, allowing the circuit board to
be safely inserted into or removed from a live backplane. The
ADM1177 can reside either on the backplane or on the circuit
board itself.

The ADM1177 controls the inrush current to a fixed maximum
level by modulating the gate of an external N-channel FET placed
between the live supply rail and the load. This hot swap function
protects the card connectors and the FET itself from damage
and limits any problems that can be caused by the high current
loads on the live supply rail.

The ADM1177 holds the GATE pin down (and, thus, the FET is
held off) until a number of conditions are met. An undervoltage
lockout circuit ensures that the device is provided with an adequate
input supply voltage. Once the input supply voltage has been
successfully detected, the device goes through an initial timing
cycle to provide a delay before it attempts to hot swap. This delay
ensures that the board is fully seated in the backplane before
the board is powered up.

Once the initial timing cycle is complete, the hot swap function
is switched on under control of the ON pin. When the ON pin
is asserted high, the hot swap operation starts.

The ADM1177 charges up the gate of the FET to turn on the
load. It continues to charge up the GATE pin until the linear
current limit (set to 100 mV/R

) is reached. For some combi-

SENSE

nations of low load capacitance and high current limit, this limit
may not be reached before the load is fully charged up. If current
limit is reached, the ADM1177 regulates the GATE pin to keep
the current at this limit. For currents above the overcurrent
fault timing threshold, nominally 100 mV/R

, the current

SENSE

fault is timed by sourcing a current out to the TIMER pin. If the
load becomes fully charged before the fault current limit time is
reached (when the TIMER pin reaches 1.3 V), the current drops
below the overcurrent fault timing threshold. The ADM1177
then charges the GATE pin higher to fully enhance the FET for
lowest R

, and the TIMER pin is pulled down again.

ON

If the fault current limit time is reached before the load drops
below the current limit, a fault has been detected, and the hot
swap operation is aborted by pulling down on the GATE pin to
turn off the FET. The ADM1177-2 latches off at this point and
attempts to hot swap again only when the ON pin is deasserted
and then asserted again.

The ADM1177-1 retries the hot swap operation indefinitely,
keeping the FET in its safe operating area (SOA) by using the
TIMER pin to time a cool-down period between hot swap
attempts. The current and voltage threshold combinations on
the TIMER pin set the retry duty cycle to 3.8%.

The ADM1177 is designed to operate over a range of supplies
from 3.15 V to 16.5 V.

UNDERVOLTAGE LOCKOUT

An internal undervoltage lockout (UVLO) circuit resets the
ADM1177 if the VCC

supply is too low for normal operation.
The UVLO has a low-to-high threshold of 2.8 V, with 80 mV
hysteresis. Above 2.8 V supply voltage, the ADM1177 starts
the initial timing cycle.

ON FUNCTION

The ADM1177-1 has an active-high ON pin. The ON pin is the
input to a comparator that has a low-to-high threshold of 1.3 V,
a 50 mV hysteresis, and a glitch filter of 3 s. A low input on the
ON pin turns off the hot swap operation by pulling the GATE
pin to ground, turning off the external FET. The TIMER pin is
also reset by turning on a pull-down current on this pin. A low­to-high transition on the ON pin starts the hot swap operation.
A 10 k pull-up resistor connecting the ON pin to the supply is
recommended.

Alternatively, an external resistor divider at the ON pin can be
used to program an undervoltage lockout value higher than the
internal UVLO circuit, thereby setting a voltage level at the
VCC supply where the hot swap operation is to start. An RC
filter can be added at the ON pin to increase the delay time at
card insertion if the initial timing cycle delay is insufficient.

TIMER FUNCTION

The TIMER pin handles several timing functions with an
external capacitor, C
V

(0.2 V) and V

TIMERH

sources are a 5 µA pull-up, a 60 µA pull-up, a 2 µA pull-down,
and a 100 µA pull-down. The 100 µA pull-down is a non-ideal
current source, approximating a 7 k resistor below 0.4 V.

. There are two comparator thresholds:

TIMER

(1.3 V). The four timing current

TIMERL

These current and voltage levels, together with the value of
C

TIMER

time, the fault current limit time, and the hot swap retry duty cycle.

Rev. 0 | Page 13 of 24

chosen by the user, determine the initial timing cycle

ADM1177

GATE AND TIMER FUNCTIONS DURING A HOT
SWAP

During hot insertion of a board onto a live supply rail at VCC,
the abrupt application of supply voltage charges the external
FET drain/gate capacitance, which can cause an unwanted gate
voltage spike. An internal circuit holds GATE low before the
internal circuitry wakes up. This reduces the FET current surges
substantially at insertion. The GATE pin is also held low during
the initial timing cycle and until the ON pin has been taken
high to start the hot swap operation.

During hot swap operation, the GATE pin is first pulled up by
a 12 A current source. If the current through the sense resistor
reaches the overcurrent fault timing threshold, V
current of 60 µA on the TIMER pin, is turned on; and this pin
starts charging up. At a slightly higher voltage in the sense
resistor, the error amplifier servos the GATE pin to maintain
a constant current to the load by controlling the voltage across
the sense resistor to the linear current limit, V

A normal hot swap is complete when the board supply
capacitors near full charge, and the current through the sense
resistor drops to eventually reach the level of the board load
current. As soon as the current drops below the overcurrent
fault timing threshold, the current into the TIMER pin switches
from being a 60 A pull-up to a 100 A pull-down. The
ADM1177 then drives the GATE voltage as high as it can to
fully enhance the FET and reduce R

losses to a minimum.

ON

A hot swap fails if the load current does not drop below the
overcurrent fault timing threshold, V

, before the TIMER

OCTIM

pin has charged up to 1.3 V. In this case, the GATE pin is then
pulled down with a 2 mA current sink. The GATE pull-down
stays on until a hot swap retry starts, which can be forced by
deasserting and then reasserting the ON pin. On the ADM1177-1,
the device retries automatically after a cool-down period.

The ADM1177 also features a method of protection from
sudden load current surges, such as a low impedance fault,
when the current seen across the sense resistor can go well
beyond the linear current limit. If the fast overcurrent trip
threshold, V

, is exceeded, the 2 mA GATE pull-down is

OCFAST

turned on immediately. This pulls the GATE voltage down
quickly to enable the ADM1177 to limit the length of the
current spike that gets through and to bring the current through
the sense resistor back into linear regulation as quickly as
possible. This process protects the backplane supply from
sustained overcurrent conditions that may otherwise cause the
backplane supply to droop during the overcurrent event.

LIM

OCTIM

.

, a pull-up

CALCULATING CURRENT LIMITS AND FAULT
CURRENT LIMIT TIME

The nominal linear current limit is determined by a sense
resistor connected between the VCC pin and the SENSE pin,
as given by Equation 1.

I

LIMIT(NOM)

= V

LIM(NOM)/RSENSE

= 100 mV/R

SENSE

(1)

The minimum linear fault current is given by Equation 2.

I

LIMIT(MIN)

= V

LIM(MIN)/RSENSE(MAX)

= 90 mV/R

SENSE(MAX)

(2)

The maximum linear fault current is given by Equation 3.

I

LIMIT(MAX)

= V

LIM(MAX)/RSENSE(MIN)

= 110 mV/R

SENSE(MIN)

(3)

The power rating of the sense resistor should be rated at the
maximum linear fault current level.

The minimum overcurrent fault timing threshold current is
given by Equation 4.

I

OCTIM(MIN)

= V

OCTIM(MIN)/RSENSE(MAX)

= 85 mV/R

SENSE(MAX)

(4)

The maximum fast overcurrent trip threshold current is given
by Equation 5.

I

OCFAST(MAX)

= V

OCFAST(MAX)/RSENSE(MIN)

= 115 mV/R

SENSE(MIN)

(5)

The fault current limit time is the time that a device spends
timing an overcurrent fault, and is given by Equation 6.

t

FAULT

≈ 21.7 × C

ms/F (6)

TIMER

INITIAL TIMING CYCLE

When VCC is first connected to the backplane supply, the
internal supply (Time Point (1) in
must be charged up. A very short time later (significantly less
than 1 ms), the internal supply is fully up and, because the
undervoltage lockout voltage has been exceeded at VCC, the
device comes out of reset. During this first short reset period,
the GATE pin is held down with a 25 mA pull-down current,
and the TIMER pin is pulled down with a 100 A current sink.

The ADM1177 then goes through an initial timing cycle. At
Time Point (2) the TIMER pin is pulled high with 5 µA. At
Time Point (3), the TIMER reaches the V
the first portion of the initial cycle ends. The 100 µA current
source then pulls down the TIMER pin until it reaches 0.2 V at
Time Point (4). The initial cycle delay (Time Point (2) to Time
Point (4)) is related to C

≈ 270 × C

t

INITIAL

TIMER

ms/F (7)

TIMER

When the initial timing cycle terminates, the device is ready to
start a hot swap operation (assuming the ON pin is asserted).
In the example shown in

Figure 32, the ON pin is asserted at the
same time that VCC is applied, so the hot swap operation starts
immediately after Time Point (4).

Figure 32) of the ADM1177

threshold, and

TIMERL

by Equation 7.

Rev. 0 | Page 14 of 24

ADM1177

V

At this point, the FET gate is charged up with a 12 A current
source. At Time Point (5), the threshold voltage of the FET is
reached, and the load current begins to flow. The FET is
controlled to keep the sense voltage at 100 mV (this corresponds
to a maximum load current level defined by the value of R
At Time Point (6), V

GATE

and V

have reached their full

OUT

SENSE

potential, and the load current has settled to its nominal level.
Figure 33 illustrates the situation where the ON pin is asserted
after V

is applied.

VCC

V

VCC

(1)

(2) (3)(4)(5) (6)

).

HOT SWAP RETRY CYCLE ON THE ADM1177-1

With the ADM1177-1, the device turns off the FET after an
overcurrent fault and then uses the TIMER pin to time a delay
before automatically retrying to hot swap.

As with all ADM1177 devices, an overcurrent fault is timed by
charging the TIMER cap with a 60 A pull-up current. When
the TIMER pin reaches 1.3 V, the fault current limit time has
been reached and the GATE pin is pulled down. On the
ADM1177-1, the TIMER pin is then pulled down with a 2 A
current sink. When the TIMER pin reaches 0.2 V, it automatically
restarts the hot swap operation.

The cool-down period is related to C

by Equation 8.

TIMER

V

ON

V

TIMER

V

GATE

SENSE

V

OUT

INITIAL TIMING

CYCLE

Figure 32. Startup (ON Asserts as Power Is Applied)

(1) (2) (3)(4) (5)(6) (7)

V

VCC

V

ON

t

COOL

≈ 550 × C

ms/F (8)

TIMER

Thus, the retry duty cycle is given by Equation 9.

/(t

+ t

t

FAULT

COOL

) × 100% = 3.8% (9)

FAULT

SOFT START (SS PIN)

The SS pin is used to determine the inrush current profile.
A capacitor should be attached to this pin. When the FET is
requested to turn on, the SS pin is held at ground until the
SENSE pin reaches a few millivolts. A current source is then
turned on, which linearly ramps the capacitor up to 1.0 V. The
reference voltage for the GATE linear control amplifier is derived
from the soft start voltage, such that the inrush linear current
limit is defined as I

6047-004

This pin can also be driven to a voltage to alter the reference
directly, thereby adjusting the current limit level with a gain
of 10. See

Figure 31 for an illustration of this relationship.

= VSS/(20 × R

LIMIT

SENSE

).

V

TIMER

V

GATE

V

SENSE

V

OUT

INITIAL TIMING

CYCLE

06047-005

Figure 33. Startup (ON Asserts After Power Is Applied)

Rev. 0 | Page 15 of 24

ADM1177

VOLTAGE AND CURRENT READBACK

In addition to providing hot swap functionality, the ADM1177
also contains the components to allow voltage and current
readback over an Inter-IC (I

2

C) bus. The voltage output of the
current sense amplifier and the voltage on the VCC pin are fed
into a 12-bit ADC via a multiplexer. The device can be
instructed to convert voltage and/or current at any time during
operation via an I

2

C command. When all conversions are
complete, the voltage and/or current values can be read out to
12-bit accuracy in two or three bytes.

The peripheral whose address corresponds to the trans­mitted address responds by pulling the data line low during
the low period before the ninth clock pulse, known as the
acknowledge bit, and holding it low during the high period of
this clock pulse. All other devices on the bus now remain idle
while the selected device waits for data to be read from it or
written to it. If the R/
device. If the R/

W

bit is 0, the master writes to the slave

W

bit is 1, the master reads from the slave

device.

SERIAL BUS INTERFACE

Control of the ADM1177 is carried out via the I2C bus. This
interface is compatible with I
The ADM1177 is connected to this bus as a slave device under
the control of a master device.

2

C fast mode (400 kHz maximum).

IDENTIFYING THE ADM1177 ON THE I2C BUS

The ADM1177 has a 7-bit serial bus slave address. When the
device powers up, it does so with a default serial bus address.
The five MSBs of the address are set to 10110; the two LSBs are
determined by the state of the ADR pin. There are four different
configurations available on the ADR pin that correspond to four
different I
allows four ADM1177 devices to operate on a single I

Table 5. Setting I

ADR Configuration Address

Low state 0xB0
Resistor to GND 0xB2
Floating (unconnected) 0xB4
High state 0xB6

2

C addresses for the two LSBs (see Tabl e 5). This scheme

2

C Addresses via the ADR Pin

2

C bus.

GENERAL I2C TIMING

Figure 34 and Figure 35 show timing diagrams for general read
and write operations using the I
specific conditions for different types of read and write
operations, which are discussed later. The general I
operates as follows:

1. The master initiates data transfer by establishing a start

condition, defined as a high-to-low transition on the serial
data line, SDA, while the serial clock line SCL remains
high. This indicates that a data stream follows. All slave
peripherals connected to the serial bus respond to the start
condition and shift in the next eight bits, consisting of a 7-bit
slave address (MSB first), plus an R/
the direction of the data transfer, that is, whether data is
written to or read from the slave device (0 = write,
1 = read).

2

C. The I2C specification defines

2

C protocol

W

bit that determines

2. Data is sent over the serial bus in sequences of nine clock

pulses: eight bits of data followed by an acknowledge bit
from the slave device. Data transitions on the data line
must occur during the low period of the clock signal and
remain stable during the high period, because a low-to­high transition when the clock is high can be interpreted as
a stop signal.

If the operation is a write operation, the first data byte after
the slave address is a command byte. This tells the slave
device what to expect next. It can be an instruction, such
as telling the slave device to expect a block write; or it can
be a register address that tells the slave where subsequent
data is to be written.

Because data can flow in only one direction, as defined by

W

the R/

bit, it is not possible to send a command to a slave
device during a read operation. Before doing a read opera­tion, it may first be necessary to do a write operation to tell
the slave what sort of read operation to expect and/or the
address from which data is to be read.

3. When all data bytes have been read or written, stop conditions

are established. In write mode, the master pulls the data line
high during the 10th clock pulse to assert a stop condition. In
read mode, the master device releases the SDA line during the
low period before the ninth clock pulse, but the slave device
does not pull it low. This is known as a no acknowledge.
The master then takes the data line low during the low
period before the 10th clock pulse, then high during the
10th clock pulse to assert a stop condition.

Rev. 0 | Page 16 of 24

ADM1177

SCL

SDA

START BY MAST E R

SCL

(CONTINUED)

SDA

(CONTINUED)

(CONTINUED)

(CONTINUED)

1

0

1

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

1

SCL

SDA

START BY MAST E R

SCL

SDA

0

11

FRAME 1

SLAVE ADDRESS

FRAME 3

DATA BYTE

A1 A0 R/W

1

9

1

ACKNOWLEDG E BY

SLAVE

9

ACKNOWLEDGE BY

SLAVE

D6

D7

D4

D5

COMMAND CODE

1

D3

FRAME 2

D2 D1

FRAME N

DATA BYT E

9

D0

ACKNOWLEDGE BY

SLAVE

ACKNOWLEDG E BY

Figure 34. General I2C Write Timing Diagram

9

1

0

0

11

FRAME 1

SLAVE ADDRESS

1

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

A1 A0 R/W

1

FRAME 3

DATA BYTE

ACKNOWLEDG E BY

SLAVE

ACKNOWLEDGE BY

MASTER

Figure 35. General I

D6

D7

9

2

C Read Timing Diagram

D4

D5

DATA BYTE

1

D3

FRAME 2

D2 D1

FRAME N

DATA BYTE

9

D0

ACKNOWLEDGE BY

MASTER

9

STOP

SLAVE

NO ACKNOWLEDGE

BY
MASTER

9

06047-006

STOP
BY
MASTER

06047-007

t

SU;STA

t

HD;STA

t

SU;STO

P

06047-008

SCLSCL

SDA

t

LOW

t

HD;STA

t

BUF

S

P

t

t

HD;DAT

HIGH

t

F

t

SU;DAT

S

R

t

Figure 36. Serial Bus Timing Diagram

Rev. 0 | Page 17 of 24

ADM1177

WRITE AND READ OPERATIONS

The I2C specification defines several protocols for different
types of read and write operations. The operations used in the
ADM1177 are discussed in the sections that follow.

Tabl e 6

shows the abbreviations used in the command diagrams.

Table 6. I

2

C Abbreviations

Abbreviation Condition

S Start
P Stop
R Read
W Write
A Acknowledge
N No acknowledge

QUICK COMMAND

The quick command operation allows the master to check if the
slave is present on the bus, as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address, followed by the

write bit (low).

3. The addressed slave device asserts an acknowledge on SDA.

12 3

SLAVE

S

ADDRESS

Figure 37. Quick Command

Table 7. Command Byte Operations

Bit Default Name Function

C0 0 V_CONT

C1 0 V_ONCE

C2 0 I_CONT

C3 0 I_ONCE

C4 0 VRANGE

C5 0 N/A Unused.
C6 0 STATUS_RD

WA

06047-009

Set to convert voltage continuously. If readback is attempted before the first conversion is complete,
the ADM1177 asserts an acknowledge and returns all 0s in the returned data.

Set to convert voltage once. Self-clears. I
conversion is complete.

Set to convert voltage continuously. If readback is attempted before the first conversion is complete, the
ADM1177 asserts an acknowledge and returns all 0s in the returned data.

Set to convert current once. Self-clears. I
conversion is complete.

Selects different internal attenuation resistor networks for voltage readback. A 0 in C4 selects a 14:1 voltage
divider. A 1 in C4 selects a 7:2 voltage divider. With an ADC full scale of 1.902 V, the voltage at the VCC pin for
an ADC full-scale result is 26.35 V for VRANGE = 0 and 6.65 V for VRANGE = 1.

Status read. When this bit is set, the data byte read back from the ADM1177 is the STATUS byte. It contains
the status of the device alerts. See

Table 15 for full details of the STATUS byte.

WRITE COMMAND BYTE

In the write command byte operation, the master device sends
a command byte to the slave device, as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address, followed by the

write bit (low).

3. The addressed slave device asserts an acknowledge on SDA.

4. The master sends the command byte. The command byte

is identified by an MSB = 0. An MSB =1 indicates an extended
register write (see the

5. The slave asserts an acknowledge on SDA.

6. The master asserts a stop condition on SDA to end the

transaction.

12 3456

S

The seven LSBs of the command byte are used to configure and
control the ADM1177.
of each bit.

2

C asserts a no acknowledge on attempted reads until the ADC

2

C asserts a no acknowledge on attempted reads until the ADC

Write Extended Byte section).

SLAVE

ADDRESS

Figure 38. Write Command Byte

WA

COMMAND

BYTE

AP

06047-010

Tabl e 7 provides details of the function

Rev. 0 | Page 18 of 24

ADM1177

WRITE EXTENDED BYTE

In the write extended byte operation, the master device writes
to one of the three extended registers of the slave device, as
follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address, followed by the

write bit (low).

3. The addressed slave device asserts an acknowledge on SDA.

4. The master sends the register address byte. The MSB of

this byte is set to 1 to indicate an extended register write.
The two LSBs indicate which of the three extended
registers are to be written to (see

Table 8 ). All other bits

should be set to 0.

5. The slave asserts an acknowledge on SDA.

6. The master sends the command byte. The command byte

is identified by an MSB = 0. An MSB = 1 indicates an
extended register write.

Table 9. ALERT_EN Register Operations

Bit Default Name Function

0 0 EN_ADC_OC1

Enabled if a single ADC conversion on the I channel has exceeded the threshold set in the ALERT_TH
register.

1 0 EN_ADC_OC4

Enabled if four consecutive ADC conversions on the I channel have exceeded the threshold set in the
ALERT_TH register.

2 1 EN_HS_ALERT

Enabled if the hot swap has either latched off or entered a cool-down cycle because of an overcurrent
event.

3 0 EN_OFF_ALERT

Enables an alert if the HS operation is turned off by a transition that deasserts the ON pin or by an
operation that writes the SWOFF bit high.

4 0 CLEAR

Clears the ON_ALERT, HS_ALERT, and ADC_ALERT status bits in the STATUS register. These may
immediately reset if the source of the alert has not been cleared or disabled with the other bits in this
register. This bit self-clears to 0 after the STATUS register bits have been cleared.

Table 10. ALERT_TH Register Operations

Bit Default Function

7:0 FF

The ALERT_TH register sets the current level at which an alert occurs. Defaults to ADC full scale. The ALERT_TH 8-bit
number corresponds to the top eight bits of the current channel data.

Table 11. CONTROL Register Operations

Bit Default Name Function

0 0 SWOFF Forces hot swap off. Equivalent to deasserting the ON pin.

7. The slave asserts an acknowledge on SDA.

8. The master asserts a stop condition on SDA to end the

transaction.

12 345678

SLAVE

S

ADDRESS

REGISTER

WA

ADDRESS

Figure 39. Write Extended Byte

REGISTER

A

DATA

AP

06047-011

Tabl e 9 , Ta bl e 10 , and Tabl e 11 give details of each extended
register.

Table 8. Extended Register Addresses

A6 A5 A4 A3 A2 A1 A0 Extended Register

0 0 0 0 0 0 1 ALERT_EN
0 0 0 0 0 1 0 ALERT_TH
0 0 0 0 0 1 1 CONTROL

Rev. 0 | Page 19 of 24

ADM1177

READ VOLTAGE AND/OR CURRENT DATA BYTES

The ADM1177 can be set up to provide information in three
different ways (see the

Write Command Byte section). Depending
on how the device is configured, the following data can be read
out of the device after a conversion (or conversions).

Voltage and Current Readback

The ADM1177 digitizes both voltage and current. Three bytes
are read out of the device in the format shown in

Tabl e 12 .

Table 12. Voltage and Current Readback Format

Byte Contents B7 B6 B5 B4 B3 B2 B1 B0

1

Voltage

V11 V10 V9 V8 V7 V6 V5 V4

MSBs

2

Current

I11 I10 I9 I8 I7 I6 I5 I4

MSBs

3 LSBs V3 V2 V1 V0 I3 I2 I1 I0

Voltage Readback

The ADM1177 digitizes voltage only. Two bytes are read out of
the device in the format shown in

Tabl e 1 3 .

Table 13. Voltage Only Readback Format

Byte Contents B7 B6 B5 B4 B3 B2 B1 B0

1 Voltage MSBs V11 V10 V9 V8 V7 V6 V5 V4
2 Voltage LSBs V3 V2 V1 V0 0 0 0 0

Current Readback

The ADM1177 digitizes current only. Two bytes are read out of
the device in the format shown in

Tabl e 1 4 .

Table 14. Current Only Readback Format

Byte Contents B7 B6 B5 B4 B3 B2 B1 B0

1 Current MSBs I11 I10 I9 I8 I7 I6 I5 I4
2 Current LSBs I3 I2 I1 I0 0 0 0 0

The following series of events occurs when the master receives
three bytes (voltage and current data) from the slave device:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address, followed by the

read bit (high).

3. The addressed slave device asserts an acknowledge on SDA.

4. The master receives the first data byte.

5. The master asserts an acknowledge on SDA.

6. The master receives the second data byte.

7. The master asserts an acknowledge on SDA.

8. The master receives the third data byte.

9. The master asserts a no acknowledge on SDA.

10. The master asserts a stop condition on SDA, and the

transaction ends.

For cases where the master is reading voltage only or current
only, only two data bytes are read. Step 7 and Step 8 are not
required.

12 345678910

SLAVE

S

ADDRESS

RA

DATA 1 DATA 2 NPDATA 3AA

Figure 40. Three-Byte Read from ADM1175

05647-012

12 345678

SLAVE

S

ADDRESS

Figure 41. Two-Byte Read from ADM1175

RA

REGISTER
ADDRESS

REGISTER

A

DATA

NP

05647-013

Converting ADC Codes to Voltage and Current Readings

The following equations can be used to convert ADC codes
representing voltage and current from the ADM1175 12-bit
ADC into actual voltage and current values.

Voltage = (V

FULLSCALE

/4096) × Code

where:

V

= 6.65 (7:2 range) or 26.35 (14:1 range).

FULLSCALE

Code is the ADC voltage code read from the device (Bit V0

to

Bit V11).

Current = ((I

/4096) × Code)/Sense Resistor

FULLSCALE

where:

FULLSCALE

= 105.84 mV.

I
Code is the ADC current code read from the device (Bit I0 to

Bit I11).

Read Status Register

A single register of status data can also be read from the
ADM1177.

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the
read bit (high).

3. The addressed slave device asserts an acknowledge on SDA.

4. The master receives the status byte.

5. The master asserts an acknowledge on SDA.

12 345

SLAVE

S

ADDRESS

Figure 42. Status Read from ADM1175

RA

DATA 1 A

05647-014

Tabl e 1 5 shows the ADM1177 status registers in detail. Note
that Bit 1, Bit 3, and Bit 5 are cleared by writing to Bit 4 of the
ALERT_EN register (CLEAR).

Rev. 0 | Page 20 of 24

ADM1177

Table 15. Status Byte Operations

Bit Name Function

0 ADC_OC An ADC-based overcurrent comparison has been detected on the last three conversions
1 ADC_ALERT

2 HS_OC

3 HS_ALERT The hot swap has failed since the last time this was reset. Cleared by writing to Bit 4 of the ALERT_EN register.
4 OFF_STATUS

5 OFF_ALERT An alert has been caused by either the ON pin or the SWOFF bit. Cleared by writing to Bit 4 of the ALERT_EN register.

An ADC-based overcurrent trip has happened, which has caused the alert. Cleared by writing to Bit 4 of the ALERT_EN
register.

The hot swap is off due to an analog overcurrent event. On parts that latch off, this is the same as the HS_ALERT status
bit (if EN_HS_ALERT = 1). On the retry parts, this indicates the current state: a 0 can indicate that the data was read
during a period when the device was retrying, or that it has successfully hot swapped by retrying after at least one
overcurrent timeout.

The state of the ON pin. Set to 1 if the input pin is deasserted. Can also be set to 1 by writing to the SWOFF bit of the
CONTROL register.

Rev. 0 | Page 21 of 24

ADM1177

APPLICATIONS WAVEFORMS

1

2

3

4

CH1 1.5A CH2 1.00V
CH3 20.0V CH4 10.0V

M40.0ms

Figure 43. Inrush Current Control into 220 μF Load

LOAD

, CH2 = V

(CH1 = I

1

2

3

4

TIMER

, CH3 = V

GATE

, CH4 = V

OUT

1

2

3

4

CH1 1.5A CH2 1.00V

06047-070

CH3 20.0V CH4 10.0V

M10.0ms

06047-073

Figure 46. Overcurrent Condition During Operation (ADM1177-1 Model)

)

(CH1 = I

1

2

3

4

LOAD

, CH2 = V

TIMER

, CH3 = V

GATE

, CH4 = V

OUT

)

CH1 1.5A CH2 1.00V
CH3 20.0V CH4 10.0V

M10.0ms

Figure 44. Overcurrent Condition at Startup (ADM1177-1 Model)

(CH1 = I

LOAD

1

2

3

4

CH1 1.5A CH2 1.00V
CH3 20.0V CH4 10.0V

, CH2 = V

TIMER

, CH3 = V

M20.0ms

GATE

, CH4 = V

Figure 45. Overcurrent Condition at Startup (ADM1177-2 Model)

(CH1 = I

LOAD

, CH2 = V

TIMER

, CH3 = V

GATE

, CH4 = V

OUT

OUT

CH1 1.5A CH2 1.00V

06047-071

CH3 20.0V CH4 10.0V

M20.0ms

06047-074

Figure 47. Overcurrent Condition During Operation (ADM1177-2 Model)

)

06047-072

(CH1 = I

1

2

3

4

CH1 1.5A CH2 1.00V
CH3 20.0V CH4 10.0V

LOAD

, CH2 = V

TIMER

, CH3 = V

M20.0ms

GATE

, CH4 = V

OUT

)

06047-075

Figure 48. Inrush Current Control with Profiling of

)

Initial Current Edge via a Capacitor on the SS Pin

(CH1 = I

LOAD

, CH2 = V

TIMER

, CH3 = V

GATE

, CH4 = V

OUT

)

Rev. 0 | Page 22 of 24

ADM1177

KELVIN SENSE RESISTOR CONNECTION

When using a low value sense resistor for high current
measurement, the problem of parasitic series resistance may
arise. The lead resistance can be a substantial fraction of the
rated resistance, making the total resistance a function of lead
length. This problem can be avoided by using a Kelvin sense
connection. This type of connection separates the current path
through the resistor and the voltage drop across the resistor.
Figure 49 shows the correct way to connect the sense resistor
between the VCC pin and the SENSE pin of the ADM1177.

CURRENT
FLOW FROM
SUPPLY

KELVIN SENSE T RACE S

SENSE RESISTOR

VCC SENSE

ADM1177

Figure 49. Kelvin Sense Connections

CURRENT
FLOW TO
LOAD

06047-015

Rev. 0 | Page 23 of 24

ADM1177

OUTLINE DIMENSIONS

3.10

3.00

2.90

6

10

3.10

3.00

2.90

1

PIN 1

0.50 BSC

0.95

0.85

0.75

0.15

0.05

0.33

0.17

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-BA

Figure 50. 10-Lead Mini Small Outline Package [MSOP]

ORDERING GUIDE

Model Hot Swap Retry Option Temperature Range Package Description Package Option Branding

ADM1177-1ARMZ-R71 Automatic Retry Version −40°C to +85°C 10-Lead MSOP RM-10 M5Y
ADM1177-2ARMZ-R71 Latched Off Version −40°C to +85°C 10-Lead MSOP RM-10 M5Z
EVAL-ADM1177EBZ1 Evaluation Board

1

Z = Pb-free part.

5.15

4.90

4.65

5

1.10 MAX

SEATING
PLANE

0.23

0.08

8°
0°

(RM-10)

Dimensions shown in millimeters

0.80

0.60

0.40

Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I

©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06047-0-9/06(0)

2

C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

Rev. 0 | Page 24 of 24