Datasheet ADM1075 Datasheet (ANALOG DEVICES)

Page 1

−48 V Hot Swap Controller and Digital Power Monitor with PMBus Interface

Data Sheet

FEATURES

Constant power foldback for FET SOA protection Precision (<1.0%) current and voltage measurement Controls inrush and faults for negative supply voltages Suitable for wide input range due to internal shunt regulator 25 mV/50 mV full-scale sense voltage Fine tune current limit to allow use of standard sense resistor Soft start inrush current limit profiling 1% accurate UVH and OV pins, 1.5% accurate UVL pin PMBus interface for control, telemetry, and fault recording 28-lead TSSOP

−40°C to 105°C junction temperature (T

APPLICATIONS

Telecommunication and data communication equipment Central office switching

−48 V distributed power systems Negative power supply control High availability servers

) operating range

ADM1075

PRODUCT HIGHLIGHTS

1. Constant Power Foldback.

Maximum FET power set by a PLIM resistor divider. This eases complexity when designing to maintain FET SOA.

2. Adjustable Current Limit.

The current limit is adjustable via the ISET pin allowing for the use of a standard value sense resistor.

3. 12-Bit ADC.

Accurate voltage, current, and power measurements. Also enables calculation of energy consumption over time.

4. PMBus Interface.

PMBus fast mode compliant interface used to read back status and data registers and set warning and fault limits.

5. Fault Recording.

Latched status registers provide useful debugging information to help trace faults in high reliability systems.

6. Built-In Soft Start.

Soft start capacitor controls inrush current profile with di/dt control.

–48V RTN (0V)

VEE

UVH

UVL

ADC_V

VCAP

ISET

DROP

VIN

VCC AND REFERENCE GENERATOR

UNDERVOLTAG E

AND

OVERVOLTAGE

DETECTOR

SPLYGD

TIMER

FUNCTIONAL BLOCK DIAGRAM

SHDN

RESTART

POWER

ACCUMULATOR

POWER

MULTIPLIER

12-BIT ADC

FET POWER

FOLDBACK

CONTROL

FAULT TIMER

GATE CO NTROL

CURRENT LIMIT

VEE_G

DIGITAL

AND

PMBUS

VEE

LATCH GPO1/ALERT1/CONV

GPO2/ALERT2 SDAO

SDAI SCL

ADR

ADC_AUX

PWRGD

DRAIN

PLIM

VEE

GATE

SENSE+

SENSE–

LOAD

N-FET

SENSE

DC-TO-DC

CONVERTER

ADuM1250

12V

3.3V

2.8V

...etc.

GND

SDA_ISO

SCL_ISO

–48V

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

Figure 1.

09312-001

Page 2

ADM1075 Data Sheet

Features.............................................................................................. 1

Applications....................................................................................... 1

Product Highlights ........................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

General Description ......................................................................... 4

Specifications..................................................................................... 5

Serial Bus Timing ......................................................................... 9

Absolute Maximum Ratings.......................................................... 10

Thermal Resistance .................................................................... 10

ESD Caution................................................................................ 10

Pin Configuration and Function Description ............................11

Typical Performance Characteristic............................................. 13

Theory of Operation ...................................................................... 20

Powering the ADM1075............................................................ 20

Current Sense Inputs.................................................................. 21

Current Limit Reference............................................................ 21

Setting the Current Limit (ISET) ............................................. 22

Soft Start ...................................................................................... 22

Constant Power Foldback (PLIM) ........................................... 22

TIMER ......................................................................................... 23

Hot Swap Fault Retry ................................................................. 24

Fast Response to Severe Overcurrent ...................................... 24

UV and OV ................................................................................. 24

PWRGD

DRAIN......................................................................................... 25

SPLYGD

LATCH

SHDN

RESTART

FET Health ..................................................................................26

Power Monitor............................................................................ 26

Isolation ....................................................................................... 26

PMBus Interface .............................................................................28

Device Addressing...................................................................... 28

SMBus Protocol Usage............................................................... 28

Packet Error Checking............................................................... 28

SMBus Message Formats........................................................... 29

Group Commands...................................................................... 30

Hot Swap Control Commands ................................................. 31

....................................................................................... 25

......................................................................................... 25

........................................................................................... 25

..................................................................................... 25

Rev. 0 | Page 2 of 52

ADM1075 Information Commands........................................ 31

Status Commands ...................................................................... 31

GPO and Alert Pin Setup Commands .................................... 32

Power Monitor Commands ...................................................... 32

Warning Limit Setup Commands............................................ 33

PMBus Direct Format Conversion .......................................... 34

Voltage and Current Conversion Using LSB values .............. 35

ADM1075 Alert Pin Behavior ...................................................... 36

Faults and Warnings .................................................................. 36

Generating an Alert ................................................................... 36

Handling/Clearing an Alert...................................................... 36

SMBus Alert Response Address ............................................... 37

Example Use of SMBus Alert Response Address................... 37

Digital Comparator Mode......................................................... 37

PMBus Command Reference........................................................ 38

Operation Command Register ................................................. 39

Clear Faults Register .................................................................. 39

PMBus Capability Register ....................................................... 39

IOUT OC Warn Limit Register ................................................ 39

VIN OV Warn Limit Register................................................... 39

VIN UV Warn Limit Register................................................... 39

PIN OP Warn Limit Register .................................................... 40

Status Byte Register.................................................................... 40

Status Word Register.................................................................. 40

IOUT Status Register................................................................. 41

Input Status Register .................................................................. 41

Manufacturing Specific Status Register................................... 42

Read EIN Register ...................................................................... 43

Read VIN Register...................................................................... 43

Read IOUT Register................................................................... 43

Read PIN Register ...................................................................... 43

PMBus Revision Register .......................................................... 43

Manufacturing ID Register....................................................... 44

Manufacturing Model Register ................................................ 44

Manufacturing Revision Register............................................. 44

Peak IOUT Register ................................................................... 44

Peak VIN Register...................................................................... 45

Peak VAUX Register .................................................................. 45

Power Monitor Control Register.............................................. 45

Page 3

Data Sheet ADM1075

Power Monitor Configuration Register ...................................45

ALERT1 Configuration Register...............................................46

ALERT2 Configuration Register...............................................47

IOUT WARN2 Limit Register...................................................48

Device Configuration Register..................................................48

Power Cycle Register ..................................................................49

Peak PIN Register .......................................................................49

Read PIN_EXT Register.............................................................49

REVISION HISTORY

10/11—Revision 0: Initial Version

Read EIN_EXT Register ............................................................49

Read VAUX Register...................................................................50

VAUX OV Warn Limit Register................................................50

VAUX UV Warn Limit Register................................................50

VAUX Status Register.................................................................50

Outline Dimensions........................................................................51

Ordering Guide...........................................................................51

Rev. 0 | Page 3 of 52

Page 4

ADM1075 Data Sheet

GENERAL DESCRIPTION

The ADM1075 is a full feature, negative voltage, hot swap controller with constant power foldback and high accuracy digital current and voltage measurement that allows boards to be safely inserted and removed from a live −48 V backplane. The part provides precise and robust current limiting and protection against both transient and nontransient short circuits and overvoltage and undervoltage conditions. The ADM1075 typically operates from a negative voltage of −35 V to −80 V and, due to shunt regulation, has excellent voltage transient immunity. The operating range of the part is flexible due to the shunt regulator, and the part can be powered directly by a 10 V rail to save shunt power dissipation (see the Powering the ADM1075 section for more details).

A full-scale current limit of 25 mV or 50 mV can be selected by choosing the appropriate model. The maximum current limit is set by the combination of the sense resistor, R

, and the input

SENSE

voltage on the ISET pin, using external resistors. This allows fine tuning of the trip voltage so that standard sense resistors can be used. Inrush current is limited to this programmable value by controlling the gate drive of an external N-channel FET. A builtin soft start function allows control of the inrush current profile by an external capacitor on the soft start (SS) pin.

An external capacitor on the TIMER pin determines the maximum allowed on-time for when the system is in current limit. This is based on the safe operating area (SOA) limits of the MOSFET. A constant power foldback scheme is used to control the power dissipation in the MOSFET during power-up and fault conditions. The ADM1075 regulates the current dynamically to ensure that the power in the MOSFET is within SOA limits as V

changes. After the timer has expired, the device

shuts down the MOSFET. The level of this power, along with the TIMER regulation time, can be set to ensure that the MOSFET remains within the SOA limits.

The ADM1075 employs a limited consecutive retry scheme when the

LATCH

pin is tied to the

SHDN

pin. In this mode, if the load current reaches the limit, the FET gate is pulled low after the timer expires and retries after a cooling period for seven attempts only. If the fault remains, the device latches off, and the MOSFET is disabled until a manual restart is initiated. Alternatively, the can be set to retry only once by isolating the

ADM1075

LATCH

pin from the

SHDN

pin. The part can also be configured to retry an infinite number of times with a 10 second interval between restarts by connecting the GPO2 pin to the

RESTART

pin.

The ADM1075 has separate UVx and OV pins for undervoltage and overvoltage detection. The FET is turned off if a nontransient voltage less than the undervoltage threshold (typically −35 V) is detected on the UVx pins or if greater than the overvoltage threshold (typically −80 V) is detected on the OV pin. The operating voltage range of the ADM1075 is programmable via resistor networks on the UVx and OV pins. The hysteresis levels on the overvoltage detectors can also be altered by selecting the appropriate resistors. There are two separate UVx pins to allow accurate programming of hysteresis.

In the case of a short circuit, the ADM1075 has a fast response circuit to detect and respond adequately to this event. If the sense voltage exceeds 1.5 times the normal current limit, a high current (750 mA minimum) gate pull-down switch is activated to shut down the MOSFET as quickly as possible. There is a default internal glitch filter of 900 ns. If a longer filter time or different severe overcurrent limit is required, these parameters can be adjusted via the PMBus™ interface.

The ADM1075 also includes a 12-bit ADC to provide digital measurement of the voltage and load current. The current is measured at the output of the internal current sense amplifier and the voltage from the ADC_V input. This data can be read across the PMBus interface.

The PMBus interface allows a controller to read current, voltage, and power measurements from the ADC. Measurements can be initiated by a PMBus command or can be set up to run continuously. The user can read the latest conversion data whenever it is required. A power accumulator is also provided to report total power consumed in a user specified period (total energy). Up to four unique I

C addresses can be created, depending on

the configuration of the ADR pin.

The GPO1/

ALERT1

/CONV and GPO2/

ALERT2

outputs can be used as a flag to warn a microcontroller or FPGA of one or more fault/warning conditions becoming active. The fault type and level is programmed across the PMBus, and the user can select which faults/warnings activate the alert.

Other functions include

PWRGD

•

output, which can be used to enable a power module (the DRAIN and GATE pins are monitored to determine when the load capacitance is fully charged) SHDN

•

input to manually disable the GATE drive

RESTART

input to remotely initiate a 10 second shutdown

Rev. 0 | Page 4 of 52

Page 5

Data Sheet ADM1075

SPECIFICATIONS

VEE = −48 V, V

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

SYSTEM SUPPLY

Voltage Transient Immunity −200 V Typical Operating Voltage −80 −35 V Determined by external component, R

SHUNT REGULATOR

Operating Supply Voltage Range, VIN 11.5 12.3 13 V Shunt regulation voltage, IIN = 5.5 mA to 30 mA,

Quiescent Supply Current 5.5 mA VIN = 13 V Undervoltage Lockout, V Undervoltage Lockout Hysteresis 600 mV Power Directly Without Shunt 9.2 11.5 V

UV PINS—UNDERVOLTAGE DETECTION

Undervoltage Rising Threshold, V Undervoltage Falling Threshold, V Total Undervoltage Hysteresis 100 mV When UVL and UVH are tied together Undervoltage Fault Filter 3.5 7.5 µs UV Propagation Delay 5 8 µs UV low to GATE pull-down active UVL/UVH Input Current 1 50 nA

OV PIN—OVERVOLTAGE DETECTION

Overvoltage Rising Threshold, V Overvoltage Hysteresis Current 4.3 5 5.7 µA Overvoltage Fault Filter 1.75 3.75 µs OV Propagation Delay 2 4 µs OV high to GATE pull-down active OV Input Current 1 50 nA

GATE PIN

Gate Voltage High 11 12 13 V I Gate Voltage Low 10 100 mV I Pull-Up Current −50 −30 µA V Pull-Down Current (Regulation) 100 µA V Pull-Down Current (UV/OV/OC) 5 10 mA V Pull-Down Current (Severe OC) 750 1500 2000 mA V Pull-Down On-Time (Severe OC) 8 16 µs Gate Hold-Off Resistance 20 Ω 0 V ≤ VIN ≤ (V

SENSE+, SENSE−

SENSE+, SENSE− Input Current, I

SENSE+, SENSE− Input Imbalance, I

VCAP

Internally Regulated Voltage, V

ISET

ISET Reference Select Threshold, V ISET Internal Reference, V Gain of Current Sense Amplifier, AV ISET Input Current, I

ADM1075-1 ONLY (GAIN = 50)

Hot Swap Sense Voltage

Hot Swap Sense Voltage Current Limit,

SENSECL

24.5 25 25.5 mV V

19.5 20 20.5 mV V

14.5 15 15.5 mV V

SENSE

= (V

SENSE+

− V

) = 0 mV, shunt regulation current = 10 mA, TJ = −40°C to +105°C, unless otherwise noted.

SENSE−

maximum I

dependent on TA, θJA (see the Powering the

SHUNT

ADM1075 section)

9.2 V

UVLO_RISING

0.99 1.0 1.01 V

UVH

0.887 0.9 0.913 V

UVL

0.99 1.0 1.01 V

OVR

= −1.0 µA

GATE

= 100 µA

GATE

= 0 V to 8 V; VSS = 2 V

GATE

≥ 2 V

GATE

≥ 2 V

GATE

≥ 6 V

GATE

= 2 V)

GATE

100 A V

SENSEx

1 A I

∆SENSEx

2.66 2.7 2.74 V 0 ≤ I

VCAP

1.35 1.5 1.65 V If V

ISETRSTH

1 V Accuracies included in total sense voltage accuracies

CLREF

50/25 V/V Accuracies included in total sense voltage accuracies

CSAMP

100 nA V

ISET

19.4 20 20.6 mV V

≤ 65 mV for ADM1075-1, per individual pin;

SENSE

≤ 130 mV for ADM1075-2, per individual pin

SENSE

= I

− I

∆SENSEx

VCAP

> V

ISET

≤ VCAP

ISET

> 1.65 V; V

ISET

SENSE+

≤ 100 A; C

ISETRSTH

SENSE−

= 1 F

VCAP

an internal 1 V reference (V

GATE

= 3 V; I

= 0 A; VSS ≥ 2 V; V

GATE

CLREF

) is used

= 0 V

PLIM

= 1.25 V; V

ISET

= 1.0 V; V

ISET

= 0.75 V; V

ISET

GATE

= 3 V; I

= 0 A; VSS ≥ 2 V; V

GATE

= 0 A; VSS ≥ 2 V; V

GATE

= 0 A; VSS ≥ 2 V; V

GATE

PLIM

= 0 V

Rev. 0 | Page 5 of 52

Page 6

ADM1075 Data Sheet

Parameter Min Typ Max Unit Test Conditions/Comments

Constant Power Active 9.4 10 11.0 mV V

4.5 5 5.7 mV V

1.4 2 2.6 mV V Circuit Breaker Offset, V

0.6 0.75 0.95 mV Circuit breaker voltage, VCB = V

CBOS

Severe Overcurrent Activates high current gate pull-down

Voltage Threshold, V

23 25 27 mV V

SENSEOC

28 30 32 mV V 38 40 42 mV V 43 45 47 mV V

Response Time

Glitch Filter Duration 50 200 ns V

500 900 ns V

6.2 10.7 µs V

44 57 µs V

Total Response Time 180 300 ns V

610 950 ns V

7 13 µs V

45 60 µs V

ADM1075-2 ONLY (GAIN = 25)

Hot Swap Sense Voltage

Hot Swap Sense Voltage Current Limit,

SENSECL

39.2 40 40.8 mV V

49.2 50 50.8 mV V

39.2 40 40.8 mV V

29.2 30 30.8 mV V Constant Power Active 19 20 21.9 mV V

9.2 10 11.2 mV V 3 4 5.0 mV V

Circuit Breaker Offset, V

1.1 1.5 1.9 mV Circuit breaker voltage, VCB = V

CBOS

Severe Overcurrent Activates high current gate pull-down

Voltage Threshold, V

46 50 54 mV V

SENSEOC1

56 60 64 mV V 76 80 84 mV V

86 90 94 mV V

Response Time

Glitch Filter Duration 50 200 ns V

400 900 ns V

6.2 10.7 µs V

44 57 µs V

> 1.65 V; V

ISET

> 1.65 V; V

ISET

> 1.65 V; V

ISET

> 1.65 V; VSS ≥ 2 V; optional select through PMBus

ISET

> 1.65 V; VSS ≥ 2 V; default at power-up

ISET

> 1.65 V; VSS ≥ 2 V; optional select through PMBus

ISET

> 1.65 V; VSS ≥ 2 V; optional select through PMBus

ISET

> 1.65 V; VSS ≥ 2 V; V

ISET

GATE

= 3 V; I = 3 V; I = 3 V; I

= 0 A; VSS ≥ 2 V; V

GATE

= 0 A; VSS ≥ 2 V; V

GATE

= 0 A; VSS ≥ 2 V; V

GATE

− V

SENSECL

step from 18 mV to 52 mV;

SENSE

CBOS

optional select through PMBus

> 1.65 V; VSS ≥ 2 V; V

ISET

step from 18 mV to 52 mV;

SENSE

default at power-up

> 1.65 V; VSS ≥ 2 V; V

ISET

step from 18 mV to 52 mV;

SENSE

optional select through PMBus

> 1.65 V; VSS ≥ 2 V; V

ISET

step from 18 mV to 52 mV;

SENSE

optional select through PMBus

> 1.65 V; VSS ≥ 2 V; V

ISET

step from 18 mV to 52 mV;

SENSE

optional select through PMBus

> 1.65 V; VSS ≥ 2 V; V

ISET

step from 18 mV to 52 mV;

SENSE

default at power-up

> 1.65 V; VSS ≥ 2 V; V

ISET

step from 18 mV to 52 mV;

SENSE

optional select through PMBus

> 1.65 V; VSS ≥ 2 V; V

ISET

step from 18 mV to 52 mV;

SENSE

optional select through PMBus

> 1.65 V; V

ISET

= 1.25 V; V

ISET

= 1.0 V; V

ISET

= 0.75 V; V

ISET

> 1.65 V; V

ISET

> 1.65 V; V

ISET

> 1.65 V; V

ISET

> 1.65 V; VSS ≥ 2 V; optional select through PMBus

ISET

> 1.65 V; VSS ≥ 2 V; default at power-up

ISET

> 1.65 V; VSS ≥ 2 V; optional select through PMBus

ISET

> 1.65 V; VSS ≥ 2 V; optional select through PMBus

ISET

> 1.65 V; VSS ≥ 2 V; V

ISET

GATE

= 3 V; I

= 3 V; I = 3 V; I = 3 V; I = 3 V; I

= 0 A; VSS ≥ 2 V; V

GATE

= 0 A; VSS ≥ 2 V; V

GATE

= 0 A; VSS ≥ 2 V; V

GATE

= 0 A; VSS ≥ 2 V; V

GATE

= 0 A; VSS ≥ 2 V; V

GATE

= 0 A; VSS ≥ 2 V; V

GATE

= 0 A; VSS ≥ 2 V; V

GATE

− V

SENSECL

step from 36 mV to 104 mV;

SENSE

CBOS

optional select through PMBus

> 1.65 V; VSS ≥ 2 V; V

ISET

step from 36 mV to 104 mV;

SENSE

default at power-up

> 1.65 V; VSS ≥ 2 V; V

ISET

step from 36 mV to 104 mV;

SENSE

optional select through PMBus

> 1.65 V; VSS ≥ 2 V; V

ISET

step from 36 mV to 104 mV;

SENSE

optional select through PMBus

PLIM

= 0.2 V = 0.4 V = 1.2 V

= 0 V

= 0 V = 0.2 V = 0.4 V = 1.2 V

Rev. 0 | Page 6 of 52

Page 7

Data Sheet ADM1075

Parameter Min Typ Max Unit Test Conditions/Comments

Total Response Time 180 300 ns V

610 950 ns V

7 13 µs V

45 60 µs V

SOFT START

SS Pull-Up Current, ISS −11.5 −10 −8.5 µA VSS = 0V Default V

Limit 0.6 1.25 1.9 mV When V

SENSECL

1.2 2.5 3.8 mV When V

SS Pull-Down Current 100 µA VSS = 1 V

TIMER

Timer Pull-Up Current (POR), I Timer Pull-Up Current (OC Fault), I Timer Pull-Down Current (Retry), I

−4 −3 −2 µA Initial power-on reset; V

TIMERUPPOR

−63 −60 −57 µA Overcurrent fault; 0.05 V ≤ V

TIMERUPFLT

1.7 2 2.3 µA After a fault when GATE is off; V

TIMERDNRT

Timer Retry/OC Fault Current Ratio 3.33 % Defines the limits of the autoretry duty cycle Timer Pull-Down Current (Hold), I Timer High Threshold, V Timer Low Threshold, V

0.98 1.0 1.02 V

TIMERH

0.03 0.05 0.07 V

TIMERL

TIMERDNHOLD

100 µA Holds TIMER at 0 V when inactive; V

PLIM

PLIM Active Threshold 0.08 0.09 0.1 V V Input Current, I Minimum Current Clamp, V

100 nA V

PLIM

75 100 125 mV V

ICLAMP

DRAIN

DRAIN Voltage at Which

PWRGD

Asserts

1.9 2 2.1 V I

ADC_AUX/ADC_V

Input Current 100 nA 0 V ≤ V

SHDN

PIN Input High Voltage, VIH 1.1 V Input Low Voltage, VIL 0.8 V Glitch Filter 1 µs Internal Pull-Up Current 8 µA Pull-up to VIN

RESTART

PIN Input High Voltage, VIH 1.1 V Input Low Voltage, VIL 0.8 V Glitch Filter 1 µs Internal Pull-Up Current 8 µA Pull-up to VIN

SPLYGD

Output Low Voltage, V

0.4 V I

OL_LATCH

1.5 V I Leakage Current 100 nA

1 µA

LATCH

Output Low Voltage, V

0.4 V I

OL_LATCH

1.5 V I Leakage Current 100 nA 1 µA

ALERT1

GPO1/

/CONV PIN

Output Low Voltage, V

0.4 V I

OL_GPO1

1.5 V I

> 1.65 V; VSS ≥ 2 V; V

ISET

step from 36 mV to 104 mV;

SENSE

optional select through PMBus

> 1.65 V; VSS ≥ 2 V; V

ISET

step from 36 mV to 104 mV;

SENSE

default at power-up

> 1.65 V; VSS ≥ 2 V; V

ISET

step from 36 mV to 104 mV;

SENSE

optional select through PMBus

> 1.65 V; VSS ≥ 2 V; V

ISET

step from 36 mV to 104 mV;

SENSE

optional select through PMBus

reaches this level, ISS is enabled, ramping;

SENSE

= 0 V; ADM1075-1 only (gain = 50)

reaches this level, ISS is enabled, ramping;

SENSE

= 0 V; ADM1075-2 only (gain = 25)

= 0.5 V

TIMER

> 1.65 V

ISET

≤ 1 V

PLIM

= 1.2 V; V

PLIM

SENSE_IMIN

= (V

÷ gain) = minimum

ICLAMP

allowed current control

≤ 50 µA

DRAIN

≤ 1.5 V

ADC

= 1 mA

SPLYGD

= 5 mA

SPLYGD

≤ 2 V; ≤ 14 V;

= 1 mA = 5 mA

≤ 2 V; ≤ 14 V;

SPLYGD

LATCH

pin disabled

V V

LATCH

V V

GPO

SPLYGD

LATCH

= 1 mA = 5 mA

≤ 1 V

TIMER

= 0.5 V

TIMER

Rev. 0 | Page 7 of 52

Page 8

ADM1075 Data Sheet

Parameter Min Typ Max Unit Test Conditions/Comments

Leakage Current 100 nA V 1 µA V Input High Voltage, VIH 1.1 V Configured as CONV pin Input Low Voltage, VIL 0.8 V Configured as CONV pin Glitch Filter 1 µs Configured as CONV pin

ALERT2

GPO2/

Output Low Voltage, V

0.4 V I

OL_GPO2

1.5 V I Leakage Current 100 nA V 1 µA V

PWRGD

Output Low Voltage, V

0.4 V I

OL_PWRGD

1.5 V I VIN That Guarantees Valid Output 1 V I Leakage Current 100 nA

1 µA

CURRENT AND VOLTAGE MONITORING

Current Sense Absolute Error (ADM1075-1) 25 mV input range; 128 sample averaging (unless

−0.01 ±0.7 % V

0.05 ±0.85 % V

0.07 ±0.85 % V

0.04 ±2.8 % V ±1.0 % V ±1.4 % V ±2.7 % V ±5.9 % V Current Sense Absolute Error (ADM1075-2) 50 mV input range; 128 sample averaging (unless

−0.03 ±0.65 % V

−0.03 ±0.7 % V

−0.04 ±1.35 % V ±0.75 % V ±0.9 % V ±1.7 % V ±3.0 % V ADC_V/ADC_AUX Absolute Accuracy −0.8 +0.8 % 0.6 V ≤ V ADC Conversion Time 1 sample of voltage and current; from command

191 219 µs V 263 301 µs V

2.830 3.243 ms V

3.987 4.568 ms V 128 samples of voltage and current averaged; from

22.54 25.83 ms V

31.79 36.43 ms V Power Multiplication Time 14 µs

≤ 2 V; GPO disabled

GPO

= 14 V; GPO disabled

GPO

= 1 mA

GPO

= 5 mA

GPO

≤ 2 V; GPO disabled

GPO

= 14 V; GPO disabled

GPO

= 1 mA

PWRGD

= 5 mA

PWRGD

= 100 A; V

SINK

≤ 2 V;

PWRGD

= 14 V;

PWRGD

OL_PWRGD

PWRGD

= 0.4 V

active

otherwise noted)

= 25 mV

SENSE

= 20 mV

SENSE

= 20 mV; 16 sample averaging

SENSE

= 20 mV; 1 sample averaging

SENSE

= 15 mV

SENSE

= 10 mV

SENSE

= 5 mV

SENSE

= 2.5 mV

SENSE

otherwise noted)

= 50 mV

SENSE

= 40 mV

SENSE

= 40 mV; 16 sample averaging

SENSE

= 40 mV; 1 sample averaging

SENSE

= 30 mV

SENSE

= 20 mV

SENSE

= 10 mV

SENSE

= 5 mV

SENSE

≤ 1.5 V

ADC

received to valid data in register

disabled

AUX

enabled

AUX

16 samples of voltage and current averaged; from command received to valid data in register

disabled

AUX

enabled

AUX

command received to valid data in register

disabled (default on power-up)

AUX

enabled

AUX

Rev. 0 | Page 8 of 52

Page 9

Data Sheet ADM1075

Parameter Min Typ Max Unit Test Conditions/Comments

ADR PIN See Table 6

Address Set to 00 0 0.8 V Connect to VEE Input Current for Address 00 −40 −22 A V Address Set to 01 135 150 165 kΩ Resistor to VEE Address Set to 10 −1 +1 A No connect state; maximum leakage current allowed Address Set to 11 2.1 V Connect to VCAP Input Current for Address 11 3 10 A V

SERIAL BUS DIGITAL INPUTS (SDAI/SDAO, SCL)

Input High Voltage, VIH 1.1 V Input Low Voltage, VIL 0.8 V Output Low Voltage, VOL 0.4 V IOL = 4 mA, SDAO only Input Leakage, I

−10 +10 A

LEAK-PIN

−5 +5 A Device is not powered Nominal Bus Voltage, VDD 2.7 5.5 V 3 V to 5 V ±10% Capacitive Load per Bus Segment, C Capacitance for SDAI, SDAO, or SCL Pin, C

400 pF

BUS

5 pF

Input Glitch Filter, tSP 0 50 ns

SERIAL BUS TIMING

Table 2.

Parameter Description Min Typ Max Unit Test Conditions/Comments

Clock frequency 400 kHz

SCLK

Bus free time 1.3 µs

BUF

Start hold time 0.6 µs

HD;STA

Start setup time 0.6 µs

SU;STA

Stop setup time 0.6 µs

SU;STO

SDA1 hold time 300 900 ns

HD;DAT

SDA1 setup time 100 ns

SU;DAT

SCL low time 1.3 µs

LOW

SCL high time 0.6 µs

HIGH

SCL, SDA1 rise time 20 300 ns

tF SCL, SDA1 fall time 20 300 ns tOF SCL, SDA1 output fall time 20 + 0.1 × C

SDAI and SDAO tied together.

tR = (V

– 0.15) to (V

IL(MAX)

+ 0.15) and tF = 0.9 VDD to (V

IH3V3

– 0.15); where V

IL(MAX)

SCL

SDA

LOW

HD;STA

BUF

HD;DAT

250 ns

BUS

= 2.1 V, and VDD = 3.3 V.

IH3V3

HIGH

SU;STA

SU;DAT

Figure 2. Serial Bus Timing Diagram

= 0 V to 0.8 V

ADR

= 2.0 V to VCAP; must not exceed the maximum

ADR

allowable current draw from VCAP

SU;STO

PSSP

09312-002

Rev. 0 | Page 9 of 52

Page 10

ADM1075 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

VIN Pin to VEE −0.3 V to +14 V UVL Pin to VEE −0.3 V to +4 V UVH Pin to VEE −0.3 V to +4 V OV Pin to VEE −0.3 V to +4 V ADC_V Pin to VEE −0.3 V to +4 V ADC_AUX Pin to VEE −0.3 V to +4 V SS Pin to VEE −0.3 V to (VCAP + 0.3 V) TIMER Pin to VEE −0.3 V to (VCAP + 0.3 V) VCAP Pin to VEE −0.3 V to +4 V ISET Pin to VEE −0.3 V to +4 V SPLYGD Pin to VEE LATCH Pin to VEE RESTART Pin to VEE SHDN Pin to VEE PWRGD Pin to VEE DRAIN Pin to VEE −0.3 V to (VCAP + 0.3 V) SCL Pin to VEE −0.3 V to +6.5 V SDAI Pin to VEE −0.3 V to +6.5 V SDAO Pin to VEE −0.3 V to +6.5 V ADR Pin to VEE −0.3 V to (VCAP + 0.3 V) GPO1/

ALERT1

GPO2/

ALERT2

PLIM Pin to VEE −0.3 V to +4 V GATE Pin to VEE −0.3 V to +18 V SENSE+ Pin to VEE −0.3 V to +4 V SENSE− Pin to VEE −0.3 V to +0.3 V VEE to VEE_G −0.3 V to +0.3 V Continuous Current into Any Pin ±10 mA Storage Temperature Range −65°C to +125°C Operating Junction Temperature

Range Lead Temperature, Soldering (10 sec) 300°C Junction Temperature 150°C

/CONV Pin to VEE

Pin to VEE

−0.3 V to +18 V

−40°C to +105°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 4. Thermal Resistance

Package Type θ

28-Lead TSSOP 68 20 °C/W

Measured on JEDEC 4-layer board in still air.

θJC Unit

ESD CAUTION

Rev. 0 | Page 10 of 52

Page 11

Data Sheet ADM1075

PIN CONFIGURATION AND FUNCTION DESCRIPTION

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 DRAIN

Connect to the drain pin of the FET through a resistor. The current in this resistor is used to determine the VDS of the MOSFET. This is used for

2 VIN

Shunt Regulated Positive Supply to Chip. Connect to the positive supply rail via a shunt resistor. A 1 µF capacitor to VEE is recommended on the VIN pin.

3 UVH

Undervoltage Rising Input Pin. An external resistor divider is used from the supply to this pin to allow an internal comparator to detect if the supply is under the UVH limit.

4 UVL

Undervoltage Falling Input Pin. An external resistor divider is used from the supply to this pin to allow an internal comparator to detect if the supply is under the UVL limit.

5 OV

Overvoltage Input Pin. An external resistor divider is used from the supply to this pin to allow an internal comparator to detect if the supply is above the OV limit.

6 PLIM

The voltage on this pin is proportional to the V current limit automatically adjusts to maintain constant power across the FET.

7 VCAP

A capacitor with a value of 1 µF or greater should be placed on this pin to maintain good accuracy. This is an internal regulated supply. This pin can be used as a reference to program the ISET pin voltage.

8 ADC_V

This pin is used to read back the input voltage using the internal ADC. It can be connected to the OV string or a separate divider.

9 ISET

This pin allows the current limit threshold to be programmed. The default limit is set when this pin is connected directly to VCAP. Alternatively, using a resistor divider from VCAP, the current limit can be adjusted to achieve a user defined sense voltage. An external reference can also be used.

10 SS

A capacitor is used on this pin to set the inrush current soft start ramp profile. The voltage on the soft start pin controls the current sense voltage limit, allowing control over the inrush current profile.

11 TIMER

Timer Pin. An external capacitor, C turns off when the voltage on the TIMER pin exceeds the upper threshold.

LATCH

This pin signals the device latching off after an overcurrent fault. This pin is also used to configure the desired retry scheme. See the Hot Swap Fault Retry section for additional details.

13 ADR

PMBus Address Pin. This pin can be tied low, tied to VCAP, left floating, or tied low through a resistor to set four different PMBus addresses.

SHDN

Drive this pin low to shut down the gate. Internal weak pull-up to VIN. This pin is also used to configure the desired retry scheme. See the Hot Swap Fault Retry section for

additional details.

RESTART

Falling Edge Triggered 10 sec Automatic Restart. The gate remains off for 10 seconds, and then powers back up. Internal weak pull-up to VIN. This pin is also used to configure the desired retry scheme. See the Hot Swap Fault Retry section for additional details.

DRAIN

VIN

UVH

UVL

PLIM

VCAP

DC_V

ISET

TIMER

LATCH

ADR

SHDN

ADM1075

(Not to Scale)

TOP VIEW

Figure 3. Pin Configuration

VEE_G

GATE

SENSE+

SENSE–

VEE

SPLYGD

ADC_AUX

PWRGD

SCL

SDAI

SDAO

GPO2/ALERT2

GPO1/ALERT1/ CONV

RESTART

PWRGD

09312-004

voltage of the FET. As the PLIM voltage changes, the

, sets an initial timing cycle delay and a fault delay. The GATE pin

TIMER

Rev. 0 | Page 11 of 52

Page 12

ADM1075 Data Sheet

Pin No. Mnemonic Description

GPO1/

GPO2/

ALERT1

ALERT2

/CONV

18 SDAO PMBus Serial Data Output. This is a split version of the SDA for easy use with optocouplers. 19 SDAI PMBus Serial Data Input. This is a split version of the SDA for easy use with optocouplers. 20 SCL PMBus Clock Pin. Open-drain input requires an external resistive pull-up. 21

PWRGD

22 ADC_AUX This pin is used to read back a voltage using the internal ADC. 23

SPLYGD

24 VEE Chip Ground Pin. Must connect to –VIN rail (lowest potential). 25 SENSE−

26 SENSE+

27 GATE

28 VEE_G

General-Purpose Digital Output (GPO1). Alert (ALERT1

). This pin can be configured to generate an alert signal when one or more fault or warning conditions have been detected. Conversion (CONV). This pin can be used as an input signal to control when a power monitor ADC sampling cycle begins. This pin defaults to indicate FET health mode at power-up. There is no internal pull-up on this pin.

General-Purpose Digital Output (GPO2). Alert (ALERT2

). This pin can be configured to generate an alert signal when one or more fault or warning conditions have been detected. This pin is also used to configure the desired retry scheme. See the Hot Swap Fault Retry section for further details. This pin defaults to indicate a seven-attempt fail at power-up. There is no internal pull-up on this pin.

Power-Good Signal. This pin is used to indicate that the FET is no longer in the linear region and capacitors are fully charged. See the

PWRGD

section for details on assert and deassert.

This pin asserts low when the supply is within the UV and OV limits set by the UVx and OV pins.

Negative Current Sense Input Pin. A sense resistor between the SENSE+ pin and the SENSE− pin sets the analog current limit. The hot swap operation controls the external FET gate to maintain the (V

− V

) sense voltage. This pin also connects to the VEE node, but should be routed separately.

SENSE−

SENSE+

Positive Current Sense Input Pin. A sense resistor between the SENSE+ pin and the SENSE− pin sets the analog current limit. The hot swap operation controls the external FET gate to maintain the (V

− V

) sense voltage. This pin also connects to the FET source node.

SENSE−

SENSE+

Gate Output Pin. This pin is the gate drive of an external N-channel FET. It is driven by the FET drive controller. The FET drive controller regulates to a maximum load current by regulating the GATE pin. GATE is held low while the supply is out of the voltage range.

Chip Ground Pin. Must connect to –VIN rail (lowest potential). The PCB layout should configure this pin as the gate pull-down return.

Rev. 0 | Page 12 of 52

Page 13

Data Sheet ADM1075

TYPICAL PERFORMANCE CHARACTERISTIC

5.0

4.5

4.0

3.5

3.0

2.5

(mA)

2.0

1.5

1.0

0.5

–50–35–20–5 102540557085100115

TEMPERATURE (°C)

Figure 4. I

vs. Temperature

09312-005

10.0

9.5

9.0

8.5

8.0

UVLO (V )

7.5

7.0

6.5

6.0

–50 –35 –20 –5 10 25 40 55 70 85 100 115

RISING

FALLING

TEMPERATURE (° C)

Figure 7. UVLO vs. Temperature

09312-008

14.0

13.5

13.0

12.5

12.0

VIN (V)

11. 5

11. 0

10.5

10.0

–50–35–20–5 102540557085100115

IIN=30mA

=5.5mA

TEMPERATURE (° C)

Figure 5. VIN vs. Temperature

100

+105°C

+85°C +25°C

–40°C

(mA)

LOW (mV)

GATE

–50–35–20–5 102540557085100115

09312-006

Figure 8. V

HIGH (V)

GATE

0µA 5µA

TEMPERATURE (°C)

Low vs. Temperature (I

GATE

= 100 μA)

GATE

09312-009

0.1

12345678910111213

Figure 6. I

VIN (V)

vs. VIN

09312-007

Rev. 0 | Page 13 of 52

–40 –20 0 20 40 60 8 0 100 120

TEMPERATURE (°C)

Figure 9. V

High vs. Temperature

GATE

09312-010

Page 14

ADM1075 Data Sheet

PULL-DOWN (mA)

GATE

–50 –35 –20 –5 10 25 40 55 70 85 100 115

Figure 10. I

TEMPERATURE (°C)

Pull-Down vs. Temperature

GATE

09312-011

PULL-UP (µA)

GATE

0 2 4 6 8 101214

(V)

GATE

Figure 13. I

Pull-Up vs. V

GATE

09312-014

PULL-DOWN (mA)

GATE

0 2 4 6 8 10 12 14

Figure 11. I

–5

–10

–15

–20

–25

PULL-UP (µA)

–30

GATE

–35

–40

–45

–50

–50 –35 –20 –5 10 25 40 55 70 85 100 115

Figure 12. I

(V)

GATE

Pull-Down vs. V

GATE

TEMPERATURE (°C)

Pull-Up vs. Temperature

GATE

–2

–4

–6

–8

–10

–12

–14

SS PULL-UP CURRENT (µA)

–16

–18

–20

–50 –35 –20 –5 10 25 40 55 70 85 100 115

09312-012

TEMPERATURE (°C)

09312-015

Figure 14. SS Pull-Up Current vs. Temperature

–10

–20

–30

–40

PULL-UP (µA)

–50

TIMER

–60

–70

–80

–50–35–20–5 102540557085100115

09312-013

Figure 15. I

TEMPERATURE (°C)

Pull-Up vs. Temperature

TIMER

09312-016

Rev. 0 | Page 14 of 52

Page 15

Data Sheet ADM1075

–1

–2

–3

–4

–5

–6

POR PULL-UP (µA)

–7

TIMER

–8

–9

–10

–50–35–20–5 102540557085100115

Figure 16. I

RETRY PULL-DO WN (µA)

TIMER

–50–35–20–5 102540557085100115

Figure 17. I

TEMPERATURE (° C)

POR Pull-Up vs. Temperature

TIMER

TEMPERATURE (°C)

Retry Pull-Down vs. Temperature

TIMER

200

180

160

140

120

100

PLIM THRESHOLD (mV)

–50 –35 –20 –5 10 25 40 55 70 85 100 115

09312-017

TEMPERATURE (°C)

09312-020

Figure 19. PLIM Threshold vs. Temperature

200

180

160

140

120

100

PLIM CURRENT CLAMP (mV)

–50–35–20–5 102540557085100115

09312-018

TEMPERATURE (° C)

09312–021

Figure 20. PLIM Current Clamp vs. Temperature

1000

800

600

400

TIMER THRESHO LD (mV)

200

–50 –35 –20 –5 10 25 40 55 70 85 100 115

HIGH

LOW

TEMPERATURE (°C)

Figure 18. TIMER Threshold vs. Temperature

09312-019

Rev. 0 | Page 15 of 52

3.0

2.5

2.0

P (V)

1.5

1.0

0.5

–50 –35 –20 –5 10 25 40 55 70 85 100 115

TEMPERATURE (° C)

Figure 21. VCAP vs. Temperature (I

= 100 μA)

VCAP

09312-022

Page 16

ADM1075 Data Sheet

1000

800

UVH

UVL

600

400

UVx THRESHOL D (mV)

200

–50–35–20–5 102540557085100115

TEMPERATURE (°C)

Figure 22. UVx Threshold vs. Temperature

1000

800

600

400

OV THRES HOLD (mV)

200

–50 –35 –20 –5 10 25 40 55 70 85 100 115

TEMPERATURE (°C)

Figure 23. OV Threshold vs. Temperature

RESTART TIME (s)

09312-023

–40 –20 0 20 40 60 80 100 120

TEMPERATURE (°C)

09312-026

Figure 25. Restart Time vs. Temperature

1000

900

800

700

600

500

400

300

200

SEVERE OC RESPONSE TIME (ns)

100

09312-024

900ns GLI TCH FILTER

200ns GLI TCH FILTER

–50–35–20–5 102540557085100115

TEMPERATURE (°C)

09312-027

Figure 26. Severe OC Response vs. Temperature

100

(µA)

SENSE

–20

–40

–60

–80

–100

SENSE–

SENSE+

0 20 40 60 80 100 120

Figure 24. I

SENSE

(mV)

vs. V

SENSE

09312-025

Rev. 0 | Page 16 of 52

60000

57.5µs GLITCH FILTER

50000

40000

30000

20000

SEVERE OC RESPONSE TIME (ns)

10000

10.7µs GLITCH FILTER

–50 –35 –20 –5 10 25 40 55 70 85 100 115

TEMPERATURE (°C)

Figure 27. Severe OC Response vs. Temperature

09312-028

Page 17

Data Sheet ADM1075

(mV)

SENSECL

ADM1075-2 +85°C ADM1075-2 +25°C ADM1075-2 –40°C ADM1075-1 +85°C ADM1075-1 +25°C ADM1075-1 –40°C

Figure 31. V

SENSECL

PLIM

(V)

vs. PLIM

1.21. 11.00.90.80. 70. 60.50.40.30.20. 10

09312-032

2.0

1.8

(mV)

1.6

CBOS

1.4

1.2

1.0

0.8

0.6

0.4

CIRCUIT BREAKE R OFFSET,

0.2

–50 –35 –20 –5 10 25 40 55 70 85 100 115

TEMPERATURE (°C)

ISET = 1.65V ISET = 1.25V ISET = 1.0V ISET = 0.75V ISET = 0.25V ISET = 0.125V

Figure 28. Circuit Breaker Offset vs. Temperature, ADM1075-1

09312-029

2.0

1.8

(mV)

1.6

CBOS

1.4

1.2

1.0

0.8

0.6

0.4

CIRCUIT BREAKE R OFFSET,

0.2

–50 –35 –20 –5 10 25 40 55 70 85 100 115

TEMPERATURE (°C)

ISET = 1.65V ISET = 1.25V ISET = 1.0V ISET = 0.75V ISET = 0.25V ISET = 0.125V

Figure 29. Circuit Breaker Offset vs. Temperature, ADM1075-2

(mV)

SENSECL

0 –50 – 35 –20 –5 10 25 40 55 70 85 100 115

ADM1075-2

ADM1075-1

Figure 30. V

TEMPERATURE (°C)

vs. Temperature, ISET = 1.65 V

SENSECL

ACCURACY (%)

ADM1075 -2

00.5

09312-030

Figure 32. Worst-Case Hot Swap V

(mV)

SENSECL

09312-031

ADM1075-2

00.51.0

Figure 33. Typical Hot Swap V

ADM1075-1

ISET (V)

ADM1075-1

ISET (V)

1.0

Accuracy vs. ISET

SENSE

vs. ISET

SENSECL

1.5

09312-132

1.5

09312-133

Rev. 0 | Page 17 of 52

Page 18

ADM1075 Data Sheet

SEVERE OC THRESHOLD (mV)

–50–35–20–5 102540557085100115

225%

200%

150%

125%

TEMPERATURE (°C)

09312-035

Figure 34. Severe OC Threshold vs. Temperature, ADM1075-1, ISET = 1.65 V

140

120

100

SEVERE OC THRESHOLD (mV)

0.25 0.45 0.65 0.85 1.05 1.25 1. 45 1.65

225%

200%

150%

125%

ISET UNDEFINED

IN GREY AREA

ISET (V)

Figure 37. Severe OC Threshold vs. ISET, ADM1075-2

09312-237

100

SEVERE OC THRESHOLD (mV)

–50 – 35 –20 –5 10 25 40 55 70 85 100 115

225%

200%

150%

125%

TEMPERATURE (°C)

09312-036

Figure 35. Severe OC Threshold vs. Temperature, ADM1075-2, ISET = 1.65 V

SEVERE OC THRESHOLD (mV)

0.25 0.45 0.65 0.85 1.05 1.25 1. 45 1.65

225%

200%

150%

125%

ISET UNDEFINED

IN GREY AREA

ISET (V)

09312-136

Figure 36. Severe OC Threshold vs. ISET, ADM1075-1

ADM1075 -1

ACCURACY (%)

ADM1075 -2

0 102030405060

SENSE VOLTAGE (mV)

09312-138

Figure 38. Worst-Case Current Sense Power Monitor Error vs. Current Sense

Voltage (V

2.0

1.8

1.6

1.4

1.2

(V)

1.0

0.8

0.6

0.4

0.2

PWRGD GPO1 GPO2 LATCH SPLYGD

012345678910

Figure 39. V

SENSE

IOL (mA)

)

vs. IOL

09312-040

Rev. 0 | Page 18 of 52

Page 19

Data Sheet ADM1075

00 DECO DE 01 DECOD E 10 DECODE

3.0

2.5

2.0

(V)

1.5

ADR

1.0

0.5

–25 –20 –15 –10 –5 0 5

(µA)

ADR

Figure 40. V

ADR

vs. I

ADR

11 DECO DE

09312-041

Rev. 0 | Page 19 of 52

Page 20

ADM1075 Data Sheet







–

THEORY OF OPERATION

When circuit boards are inserted into a live backplane, discharged supply bypass capacitors draw large transient currents from the backplane power bus as they charge. Such transient currents can cause permanent damage to connector pins, as well as dips on the backplane supply that can reset other boards in the system.

The ADM1075 is intended to control the powering on and off of a board in a controlled manner, allowing the board to be removed from, or inserted into, a live backplane by protecting it from excess currents. The ADM1075 can reside either on the backplane or on the removable board.

A minimal load current requirement is assumed when charging the load capacitance. If the load current is too large relative to the regulation current, it may not be possible to charge the load capacitance. The

PWRGD

pin can be used to disable the load

until the load capacitance is fully charged.

POWERING THE ADM1075

The ADM1075 typically operates from a negative supply of

−35 V to −80 V and can tolerate transient voltages of up to

−200 V. The VIN chip ground. It is a current-driven supply and is shunt regulated to 12 V internally. It should be connected to the most positive supply terminal (usually −48 V RTN or 0 V) through a dropper resistor. The resistor should be chosen such that it always supplies enough current to overcome the maximum quiescent supply current of the chip while not exceeding the maximum allowable shunt current. After the system supply range has been established, an appropriate value for the dropper resistor can be calculated.

where:

and V

IN_MIN

80 V).

SHUNT_MIN

sheet specifications (see Table 1).

SHUNT_MIN

is the maximum quiescent supply current (minimum

shunt current).

SHUNT_MAX

is the maximum shunt input current.

can be calculated based on the maximum ambient temperature (T temperature (T from Table 4. Worst-case internal power is at VIN Tabl e 1 .

pin is a positive supply pin with respect to



MAXIN

MINSHUNT

MAXSHUNT

IN_MAX

and V

MAXSHUNT





MININ



are the supply voltage extremes (that is, 35 V,

SHUNT_MAX

A(MAX)

J(MAX)



are the shunt regulator voltage data

) in the application, the maximum junction

= 105°C), and the θJA value of the package



VIN





MAX

MINSHUNT

MAXSHUNT

MINSHUNT

)()(

MAXAMAXJ

)(

from

(MAX)

Rev. 0 | Page 20 of 52

For example, the maximum shunt current with a TSSOP device at 80°C maximum ambient can be calculated as



80105



MAXSHUNT





V13C/W68



mA28

Tolerance of supplies and resistors should also be accounted for to ensure that the shunt current is always within the desired range.

Care must be taken to ensure that the power rating of the shunt resistor is sufficient. The power may be as high as 2 W at extreme supply conditions. Multiple shunt resistors can be used in series or in parallel to share power between resistors.

IVVVIP 

MAXIN

SHUNTR

)(

MINSHUNT

MAX

where:

MAX



SHUNT

MINSHUNT

MAXIN

The power dissipation in the shunt resistor can be saved if a suitable voltage rail is available to power the chip directly. This voltage rail must be well regulated to ensure that it is always greater than the UVLO threshold but less than the minimum shunt regulation voltage. The power directly without shunt specification in Table 1 shows the limits this voltage rail must meet. Note that this voltage is referenced to VEE.

The VIN pin provides the majority of the bias current for the device. The remainder of the current needed to control the gate drive and to best regulate the V

voltage is supplied by the

SENSE± pins. The VEE and SENSE− pins are connected to the same voltage rail, although through separate traces to prevent accuracy loss in the sense voltage measurement (see Figure 41).

48V RTN

1µF

SHUNT

VIN

VEE

ADM1075

VEE

Figure 41. Powering the ADM1075

LOAD

GATE

SENSE+

SENSE–

SENSE

09312-042

The available shunt current range should be wide enough to accommodate most telecommunication input voltage ranges. In an application where a wider input voltage range is possible, some external circuitry may be required to meet the shunt regulation current specifications. The applications diagram in Figure 42 shows an example of such a circuit, using a Zener diode and a bipolar junction transistor (BJT) device as an external pre-regulator on the −48 V supply. This ensures that the shunt regulation current is always within specification even at the extremes of supply voltage.

Page 21

Data Sheet ADM1075

–

48V RTN

Rb1 = 100kΩ Rb2 = 640Ω

18V

Ib = 6µA TO 33µA

TO 75V

–48V

11V

1µF

VEE

10.3V (5.5mA TO 10mA)

= 15Ω

DROP

VIN

ADM1075

VEE

LOAD

GATE

SENSE+

SENSE–

SENSE

Figure 42. Wide Input Supply Range

CURRENT SENSE INPUTS

The load current is monitored by measuring the voltage drop across an external sense resistor, R sense amplifier provides a gain of 25 or 50 (depending on the model) to the voltage drop detected across R compared to an internal reference and detects when an overcurrent condition occurs.

VIN

ADM1075

OVERCURRENT

+ –

1V REF

VEE

×25/50

Figure 43. Hot-Swap Current Sense Amplifier

The SENSE± inputs can be connected to multiple parallel sense resistors, which can affect the voltage drop detected by the

ADM1075. The current flowing through the sense resistors

creates an offset, resulting in reduced accuracy. To achieve better accuracy, averaging resistors should be used to sum the sense nodes of each sense resistor, as shown in Figure 44. The typical value for the averaging resistors is 10 Ω. The value of the averaging resistors is chosen to be much greater than the trace resistance between the sense resistor terminals and the inputs to the ADM1075. This greatly reduces the effects of differences in the trace resistances.

. An internal current

SENSE

–

GATE

SENSE+

SENSE–

. The result is

SENSE

09312-043

Figure 44. Connection of Multiple Sense Resistors to SENSE± Pins

CURRENT LIMIT REFERENCE

The current limit reference voltage determines the load current level to which the ADM1075 limits the current during an

09312-137

overcurrent event. This is the reference voltage to which the gained up current sense voltage is compared to determine if the limit is reached. This current limit voltage, shown in Figure 45, is then converted to a gate current to regulate the GATE pin.

GATE

where g

, the gate transconductance, = 660 µs.

An internal current limit reference selector block continuously compares the ISET, soft start, and foldback (derived from PLIM) voltages, determines which is the lowest at any given time, and uses it as the current limit reference. This ensures that the programmed current limit, ISET, is used in normal operation and the soft start and foldback features reduce the current limit when required.

The foldback and soft start voltages change during different stages of operation and are clamped to a lower level of 100 mV (typical) to prevent zero current flow due to the current limit being too low.

ISET

VIN

ADM1075

LIMCURR

BIAS

CURRENT

VEE

gVI

GATE

SENSE+

SENSE–

ADM1075

GATE DRIVE LOGIC

VCAP

REF

SELECT

1.0V

CURRENT LIMIT

10µA

CURRENT

LIMIT

VOLTAGE

CURRENT

CONTROL

LIMIT

VEE

–

TIMEOUT

×25/50

FLB ( = 0.1/PLIM)

Figure 45. Current Limit Reference Selection

09312-044

PLIM

GATE

SENSE+

–

SENSE–

09312-045

Rev. 0 | Page 21 of 52

Page 22

ADM1075 Data Sheet

FLB

ISET1V

CURRENT LIMIT REFERENCE

.1V

09312-046

Figure 46. Interaction of Soft Start, Foldback, and ISET Current Limits

SETTING THE CURRENT LIMIT (ISET)

The maximum current limit is partially determined by selecting a sense resistor to match the current sense voltage limit on the controller for the desired load current. However, as currents become larger, the sense resistor value becomes smaller and resolution can be difficult to achieve when selecting the appropriate sense resistor value. The ADM1075 provides an adjustable sense voltage limit to deal with this issue. The device allows the user to program the required current sense voltage limit from 15 mV to 25 mV for the ADM1075-1 and from 30 mV to 50 mV for the ADM1075-2.

The default value of 20 mV/40 mV is achieved by connecting the ISET pin directly to the VCAP pin (VCAP > 1.65 V ISET reference select threshold). This configures the device to use an internal 1 V reference, which equates to 20 mV/40 mV at the sense inputs (see Figure 47(a)).

VCAP

ISET

ADM1075

(PARTIAL)

VEE

(B)

Rev. 0 | Page 22 of 52

VCAP

ISET

ADM1075

(PARTIAL)

VEE

(A)

Figure 47. (a) Fixed 20 mV/40 mV Current Sense Limit

(b) Adjustable 15 mV to 50 mV Current Sense Limit

C1 R1

To set the sense voltage in the 15 mV to 50 mV range, a resistor divider is used to apply a reference voltage to the ISET pin (see Figure 47(b)). The VCAP pin has a 2.7 V internally generated voltage that can be used to set a voltage at the ISET pin.

Assuming V divider should be sized to set the ISET voltage as follows:

ISET

where V be used as the pull-up supply for setting the I VCAP pin should not be used for any other purpose. To guarantee accuracy specifications, care must be taken to not load the VCAP pin by more than 100 µA.

SOFT START

A capacitor connected to the SS pin determines the inrush current profile. Before the FET is enabled, the output voltage of the current limit reference selector block is clamped at 100 mV. This, in turn, holds the current limit reference at approximately 2 mV for the ADM1075-1 or 4 mV for the ADM1075-2. When the FET is requested to turn on, the SS pin is held at ground until the voltage between the SENSE+ and SENSE− pins

) reaches the circuit breaker voltage, VCB.

SENSE

When the load current generates a sense voltage equal to V 10 µA current source is enabled, which charges the SS capacitor and results in a linear ramping voltage on the SS pin. The current limit reference also ramps up accordingly, allowing the regulated load current to ramp up, while avoiding sudden transients during power-up. The SS capacitor value is given by

C×=

where

For example, a 10 nF capacitor gives a soft start time of 1 ms.

Note that the SS voltage may intersect with the PLIM or foldback (FLB) voltage, and the current limit reference may change to follow PLIM (see Figure 46). This has minimal impact on startup because the output voltage rises at a similar rate to SS.

CONSTANT POWER FOLDBACK (PLIM)

Foldback is a method that actively reduces the current limit as the voltage drop across the FET increases. It keeps the power across the FET below the programmed value during power-up, overcurrent, or short-circuit events. This allows a smaller FET to be used, resulting in significant cost savings. The foldback

09312-047

method employed is a constant power foldback scheme, meaning power in the FET is held constant regardless of the V FET. This simplifies the task of ensuring that the FET is always operating within the SOA region.

The ADM1075 detects the voltage drop across the FET by monitoring the voltage on the drain of the FET (via the PLIM pin). The device relies on the principle that the source of the FET is at the most negative expected supply voltage, and the magnitude of the drain voltage is relative to that of the V the FET. Using a resistor divider from the drain of the FET to

equals the voltage on the ISET pin, the resistor

ISET

= (V

SENSE

= V

= 10 µA, and t is the SS ramp time.

× 50) for ADM1075-1 or

SENSE

× 25) for ADM1075-2

SENSE

is the sense voltage limit. The VCAP rail can also

C address. The

− V

SENSECL

ISET

CBOS

of the

, a

Page 23

Data Sheet ADM1075

the PLIM pin, the relationship of VDS to V The foldback voltage, V

, is the input to the current limit

FLB

can be controlled.

PLIM

reference selector block and is defined as

= 0.1/V

FLB

The resistor divider should be designed to generate a V voltage equal to I rises above the desired power level. If I be 0.1 V at the point where constant power takes over (V

). For example, to generate a 200 W constant power limit at

SET

10 A current limit, the maximum V

PLIM

when the VDS of the FET (and thus V

SET

= 1 V, V

SET

is required to be 20 V at

needs to

PLIM

FLB

PLIM

FLB

)

the current limit. Therefore, the resistor divider must be 200:1 to generate a 0.1 V PLIM voltage at V

= 20 V. As V

continues to increase, the current limit reference follows V

PLIM

FLB

because it is now the lowest voltage input to the current limit reference selector block. This results in a reduction of the current limit, and, therefore, the regulated load current. To prevent complete current flow restriction, a clamp becomes active when the current limit reference reaches 100 mV. The current limit cannot drop below this level. This 200 W constant power example is illustrated in terms of FET SOA and real scope plots in Figure 48 and Figure 49.

When V

has control of the current limit reference, the

FLB

regulation current through the FET is

= V

where

/(Gain × R

FLB

is the external FET drain current, and Gain is the sense

SENSE

)

amplifier gain.

= 0.1/(V

= 0.1/(VDS × D × Gain × R

D is the resistor divider factor on PLIM.

where

× Gain × R

PLIM

SENSE

)

SENSE

)

Therefore, the FET power is calculated as

FET

Because P

= ID × VDS = 0.1/(D × Gain × R

does not have any dependency on VDS, it remains

FET

SENSE

)

constant. Therefore, the FET power for a given system can be set by adjusting the divider (D) driving the PLIM pin.

> I

The limits to the constant power system are when V 1 V if V clamp on V

ISET

> V

CLREF

ISETRSTH

) or when V

). With an I

< 100 mV (100 mV max

FLB

voltage of 1 V, this gives a 10:1

SET

FLB

SET

(or

foldback current range.

Rev. 0 | Page 23 of 52

1000

1µs

10µs

100µs

1ms

10ms

1000

09312-143

(A)

100

0.1

MAX 200W

POWER

0.1

DISSIPATION

20V × 10A = 200W

60V × 3.33 A = 200W

10 100

(V)

Figure 48. FET SOA

CURRENT LIMI T ADJUSTING

GATE

3,4

VIN

200W CONSTANT POWER

1,2

Figure 49. 200 W Constant Power Scope Plot, CH1 = VIN; CH2 = V

09312-144

;

CH3 = GATE; CH4 = System Current; M1 = FET Power

TIMER

The TIMER pin handles several timing functions with an external capacitor, C

(1.0 V) and V

TIMERH

sources are a 3 A pull-up, a 60 A pull-up, a 2 A pull-down, and a 100 A pull-down.

These current and voltage levels, together with the value of

chosen by the user, determine the initial timing cycle

TIMER

time, the fault current limit time, and the hot swap retry duty cycle. The TIMER capacitor value is determined using the following equation:

= (tON × 60 A)/V

TIMER

where

is the time that the FET is allowed to spend in

regulation. The choice of C with the SOA requirements of the FET. Foldback can be used here to simplify selection.

When V

is connected to the backplane supply, the internal

supply of the ADM1075 must be charged up. A very short time later when the internal supply is fully up and above the undervoltage lockout voltage (UVLO), the device comes out of reset. During this first short reset period, the GATE and TIMER pins are both held low. The ADM1075 then goes through an initial

. There are two comparator thresholds:

TIMER

(0.05 V). The four timing current

TIMERL

TIMERH

is based on matching this time

TIMER

Page 24

ADM1075 Data Sheet

−

≈

timing cycle. The TIMER pin is pulled up with 3 A. When the TIMER reaches the V

threshold (1.0 V), the first portion

TIMERH

of the initial cycle is complete. The 100 A current source then pulls down the TIMER pin until it reaches V initial cycle duration is related to C

by the following

TIMER

(0.05 V). The

TIMERL

equation:

)(

CVVCV

INITIAL

A3

×−

TIMERTIMERLTIMERHTIMERTIMERH

A100

For example, a 470 nF capacitor results in a power-up delay of approximately 160 ms. Provided the UV and OV detectors are inactive when the initial timing cycle terminates, the device is ready to start a hot swap operation.

When the voltage across the sense resistor reaches the circuit breaker trip voltage, V

, the 60 µA timer pull-up current is

activated, and the gate begins to regulate the current at the current limit. This initiates a ramp-up on the TIMER pin. If the sense voltage falls below this circuit breaker trip voltage before the TIMER pin reaches V

(1.0 V), the 60 µA pull-up is

TIMERH

disabled, and the 2 µA pull-down is enabled.

The circuit breaker trip voltage is not the same as the hot swap sense voltage current limit. There is a small circuit breaker offset, V

, which means that the timer actually starts a short

CBOS

time before the current reaches the defined current limit.

However, if the overcurrent condition is continuous and the sense voltage remains above the circuit breaker trip voltage, the 60 µA pull-up remains active and the FET remains in regulation. This allows the TIMER pin to reach V GATE shutdown. The

LATCH

pin is pulled low immediately.

and initiate the

TIMERH

In latch-off mode, the TIMER pin is switched to the 2 µA pulldown when it reaches the V

threshold. The

TIMERH

LATCH

pin remains low. While the TIMER pin is being pulled down, the hot swap controller is kept off and cannot be turned back on.

When the voltage on the TIMER pin goes below the V

TIMERL

threshold, the hot swap controller can be reenabled by toggling the UVx pin or by using the PMBus OPERATION command to toggle the ON bit from on to off and then on again.

HOT SWAP FAULT RETRY

The ADM1075 turns off the FET after an overcurrent fault. With the default pin configuration, the part latches off after an

LATCH

overcurrent fault and can then be reset by either a power cycling event or a low signal

SHDN

to either the

input or reset by toggling the UVx pin, using the PMBus operation command or the PMBus power cycle command.

If the

LATCH

pin is connected to the makes seven attempts to hot swap before latching off. In this mode, the part uses the TIMER pin to time a delay between each attempt. In this way, a large load capacitance can be charged using consecutive current limit periods.

goes active low. This condition

RESTART

input. It can also be

SHDN

pin, the part

Rev. 0 | Page 24 of 52

The part can also be configured to autoretry an infinite number of times with a 10 second cooling period between each retry. Connecting

LATCH

RESTART

means that the part makes one hot swap attempt between each cooling period. Connecting LATCH

SHDN

and GPO2/

ALERT2

RESTART

means that the part makes seven hot swap attempts between each cooling period.

The duty cycle of the automatic retry cycle is set by the ratio of 2 µA/60 µA, which approximates to being on ~4% of the time. The value of the timer capacitor determines the on time of this cycle, which is calculated as follows:

= V

= (V

OFF

TIMERH

× (C

− V

TIMER

TIMERL

/60 A)

) × (C

TIMER

/2 A)

A 470 nF capacitor on the TIMER pin gives ~8 ms of on time (for example, to meet 10 ms SOA), and ~220 ms off time.

FAST RESPONSE TO SEVERE OVERCURRENT

The ADM1075 features a very fast detection circuit that quickly responds to severe overcurrent events such as short circuits. Such an event may cause catastrophic damage if not controlled very quickly. A fast response circuit ensures that the ADM1075 detects an overcurrent event at approximately 150% of the normal current limit (ISET) and responds and controls the current within 1 µs in most cases. The severe overcurrent threshold and glitch filter times are digitally programmable through the PMBus. The threshold can be selected as 125%, 150%, 200%, or 225% of the normal current limit, and the glitch filter time can be set to 200 ns, 900 ns, 10.7 s, or 57 s. This sets a maximum response time of 300 ns, 950 ns, 13 s, or 60 s.

UV AND OV

The ADM1075 monitors the supply voltage for undervoltage (UV) and overvoltage (OV) conditions. The OV pin is connected to the input of an internal voltage comparator, and its voltage level is internally compared with a 1 V voltage reference. The user can program the value of the OV hysteresis by varying the top resistor of the resistor divider on the pin. This impedance in combination with the 5 A OV hysteresis current (current turned on after OV trips) sets the OV hysteresis voltage.

BOTTOMTOP

RISING

OVOV

THRESHOLD

RISINGFALLING

×=

BOTTOM

ROVOV

TOP

The UV detector is split into two separate pins, UVH and UVL. The voltage on the UVH pin is compared internally to a 1 V reference, whereas the UVL pin is compared to a 0.9 V reference. Therefore, if the pins are tied together, the UV hysteresis is 100 mV. The hysteresis can be adjusted by placing a resistor between UVL and UVH.

Figure 50 illustrates the positive voltage monitoring input connection. An external resistor network divides the supply voltage for monitoring. An undervoltage event is detected when

)A5( ×

Page 25

Data Sheet ADM1075

–

the voltage connected to the UVL pin falls below 0.9 V, and the gate is shut down using the 10 mA pull-down device. The fault is cleared after UVH pin rises above 1.0 V.

Similarly, when an overvoltage event occurs and the voltage on the OV pin exceeds 1 V, the gate is shut down using the 10 mA pull-down device.

48V RTN (0V)

SHUNT

GATE

ENABLE

LOGIC

ADM1075

VEE

GATE

SENSE+

SENSE–

SENSE

09312-048

0.9V

VIN

+ –

– +

UVH

UVL

–48V

Figure 50. Undervoltage and Overvoltage Supply Monitoring

The maximum rating on the UVH pin is 4 V and the UVH threshold is 1 V. This limits the maximum input voltage to minimum input voltage ratio to 4:1. For example, if the UVH threshold is set at 20 V, the maximum input voltage is 80 V so as not to exceed the maximum ratings of the pin. If a wider input range is required, some protection circuitry is required on the UV pins to limit them to less than 4 V.

PWRGD

The As shown in , the Figure 51

output indicates the status of the output voltage.

PWRGD

output is derived from the DRAIN pin voltage. It is an open-drain output that pulls low when the voltage on DRAIN is less than 2 V and the GATE pin voltage is near its 12 V rail (power good). When a fault occurs or hot swap is turned off, the open-drain pull-down is disabled, allowing

PWRGD

to go high (power bad).

teed to be in a valid state for V

FET

DRAIN

50µA MAX

DRAIN

11V

GATE

HOT SWAP

DISABLE

SIGNAL

Figure 51. Generation of

≥ 1 V.

PWRGD

DIODE CLAMP S DRAIN TO 2V

PWRGD

Signal

SRQ

is guaran-

PWRGD

DRAIN

Because the source of the FET is always at or near the most negative system supply, the drain voltage is a close approximation to the V is less than 2 V, it is assumed the FET is turned on. The DRAIN

of the FET. When the voltage at the DRAIN pin

Rev. 0 | Page 25 of 52

09312-049

pin is used by the power-good circuitry to determine when PWRGD

can be asserted. A resistor is required on the DRAIN pin to limit current on the pin to 50 A. A 2 MΩ resistor is suitable to limit the current in most cases.

SPLYGD

The

output indicates when the input supply is within the programmed voltage window. This is an open-drain output. An external pull-up resistor is required on this pin.

LATCH

The

output signals that the device has latched off after an overcurrent fault. This pin is also used to configure the desired retry scheme. See the section for

Hot Swap Fault Retry

additional details.

SHDN

The

pin is a level-triggered input that allows the user to command a shutdown of the hot swap function. When this input is set low, the GATE output is switched to VEE to turn the FET off. This pin has an internal pull-up of approximately 8 µA, allowing it to be driven by an open-drain pull-down output or a push-pull output. The input threshold is ~1 V.

This pin is also used to configure the desired retry scheme. See the Hot Swap Fault Retry section for additional details.

SHDN

Care should be taken if using the Pulling the taking

SHDN

low always turns off the gate. However,

SHDN

high again turns on hot swap only if there have

pin as an on/off pin.

been less than seven faults/shutdown events within a 10 second period. The retry scheme is configured to set GPO2/ low after seven faults. The ALERT2

fault. The retry counter is cleared after 10 seconds of

SHDN

pin cannot clear the GPO2/

ALERT2

power good. Therefore, this is not an issue if there is never

SHDN

going to be more than seven

events within a 10 second

period.

The UVH or UVL pin may work better as a system on/off pin if required. Toggling the UVx pin clears any faults (including GPO2/

ALERT2

low after seven retry attempts). A switch

shorting UVH or UVL to VEE works as an on/off switch.

RESTART

The the user to command a 10 second automatic restart. When this input is set low, the gate turns off for 10 seconds, and then powers back up. The pin is falling edge triggered; therefore, holding RESTART restart. This pin has an internal pull-up of approximately 8 µA, allowing it to be driven by an open-drain pull-down output or a push-pull output. The input threshold is ~1 V.

This pin is also used to configure the desired retry scheme. See the Hot Swap Fault Retry section for additional details.

pin is a falling edge triggered input that allows

low for more than 10 seconds generates only one

Page 26

ADM1075 Data Sheet

FET HEALTH

The ADM1075 features a method of detecting a shorted pass FET. The FET health status can be used to generate an alert on the GPO1/

ALERT1

/CONV and GPO2/

at power-up, an alert is generated on GPO1/

ALERT2

pins. By default,

ALERT1

/CONV if the FET health status indicates a bad FET is present. FET health is considered bad if all of the following conditions are true:

• The ADM1075 is holding the FET off, for example, during

the initial power-on cycle time.

• V

> 2 mV for the ADM1075-1 and 4 mV for the

SENSE

ADM1075-2.

• V

GATE

< ~1 V.

POWER MONITOR

The ADM1075 features an integrated ADC that accurately measures the current sense voltage and the ADC_V voltage. It can also optionally monitor the ADC_AUX voltage. The measured input voltage (ADC_V) and the current being delivered to the load are multiplied to give a power value that can be read back. Each power value is also added to an accumulator that can be read back to allow an external device to calculate the energy consumption of the load.

The PEAK_IOUT, PEAK_VIN, and PEAK_VAUX commands can be used to read the highest peak current or voltage since the value was last cleared.

An averaging function is provided for voltage and current that allows a number of samples to be averaged by the ADM1075. This function reduces the need for postprocessing of sampled data by the host processor. The number of samples that can be averaged is 2

The power monitor current sense amplifier is bipolar and can measure both positive and negative currents. It has two input ranges and can be selected using the PMBus interface. The input ranges are ±25 mV and ±50 mV.

The two basic modes of operation for the power monitor are single shot and continuous. In single-shot mode, the power monitor samples the input voltage and current a number of times, depending on the averaging value selected by the user. The ADM1075 returns a single value corresponding to the average voltage and current measured. When configured for continuous mode, the power monitor continuously samples voltage and current, making the most recent sample available to be read. The ADC runs in continuous mode by default at power-up.

The single-shot mode can be triggered in a number of ways. The simplest is by selecting the single-shot mode using the PMON_CONFIG command and writing to the CONVERT bit using the PMON_CONTROL command. The CONVERT bit can also be written as part of a PMBus group command. Using a group command allows multiple devices to be written to as part of the same I

, where N is in the range of 0 to 7.

C bus transaction, with all devices executing the

command when the stop condition appears on the bus. In this way, several devices can be triggered to sample at the same time.

When the GPO1/

ALERT1

/CONV pin is set to the convert (CONV) mode, an external hardware signal can be used to trigger the single-shot sampling of one or more parts at the same time.

Each time a current sense and input voltage measurement is taken, a power calculation is performed, multiplying the two measurements together. This can be read from the device using the READ_PIN command, returning the input power.

At the same time, the calculated power value is added to a power accumulator register that may increment a rollover counter if the value exceeds the maximum accumulator value, and that also increments a power sample counter.

The power accumulator and power sample counter are read back using the same READ_EIN command to ensure that the accumulated value and sample count are from the same point in time. The bus host reading the data assigns a timestamp to show when the data is read. By calculating the time difference between consecutive uses of READ_EIN and determining the delta in power consumed, it is possible for the host to determine the total energy consumed over that period.

ISOLATION

Isolation is usually required in −48 V systems because there can be a large voltage difference between different ground planes in the system. The ADM1075 is referenced to −48 V, whereas the MCU is usually referenced to 0 V. In almost all cases, the I signals must be isolated. Any other ADM1075 digital input and output signals that go to or come from the MCU must also be isolated.

Analog Devices, Inc., provide a range of digital isolators using

iCoupler® technology. iCoupler technology is based on chip

scale transformers rather than the LEDs and photodiodes used

in optocouplers. The ADuM1250 is a dual I be used in conjunction with the ADM1075 for I

–48V SIDE

VDD1

100nF

–48V

(PRIMARY)

10kΩ

SDA

10kΩ

SCL

–48V

Figure 52. ADuM1250 I

ADuM1250

VDD1

VDD2

SDA2

SCL2

SCL1

GND2

GND1

SCL2

C isolator and can

ISOLATED SIDE

(SECONDARY)

SDA_ISO

SCL_ISO

GND_ISO

C Isolation

C isolation.

GND_ISO

In cases where more digital signals need to be isolated, the

ADuM3200 is a dual-channel digital isolator whereas the ADuM5404 is a quad-channel isolator with

isoPower®, an

integrated, isolated dc-to-dc converter.

The ADuM1250 and ADuM3200 must be powered from both the primary and secondary sides. The ADuM5404 only needs to

100nF

5V_ISO

09312-147

Rev. 0 | Page 26 of 52

Page 27

Data Sheet ADM1075

be powered from the secondary side and can provide power across the isolation barrier via the integrated dc-to-dc converter. Therefore, the ADuM5404 can be used to power the primary side of the ADuM1250 if both are used on the board. Some extra care is required if using the ADuM5404 to power the ADuM3200. If the power at the secondary side is enabled by the ADM1075, the

isoPower solution may not work. Because

isoPower is unpowered in this case, the ADuM3200 outputs are

SHDN

in an undefined state. If the

ADuM3200 ADM1075

, it may be held low, and the never turns

input comes from the

on the FET or enables power at the secondary side.

isoPower uses high frequency switching elements to transfer

power through its transformer. Special precautions must be taken during printed circuit board (PCB) layout to meet emissions standards. See the AN-0971 Application Note for board layout recommendations.

Powering the

iCouplers from the secondary side is usually

straightforward because there is often a suitable voltage rail available. However, there is not always a suitable voltage rail available on the primary side (−48 V side). If the ADuM5404 is not used on the system, the ADuM1250 can be powered on the primary side in a number of different ways.

If a voltage rail is available on the primary side (3.3 V or 5 V referenced to VEE), that can be used to power the chip directly. Otherwise, the ADM1075 shunt voltage and/or the −48 V supply can be regulated down to power the part. A simple emitter follower circuit achieves this, as shown in Figure 53.

12V (SHUNT)–48V RTN

–48V

1kΩ

0.33W

1µF

5V AUX

09312-148

20kΩ

20k

–48V

Figure 53. Powering iCoupler from −48 V Supply

Rev. 0 | Page 27 of 52

Page 28

ADM1075 Data Sheet

PMBus INTERFACE

The I2C bus is a common, simple serial bus used by many devices to communicate. It defines the electrical specifications, the bus timing, the physical layer, and some basic protocol rules.

SMBus is based on I fault-tolerant bus. Functions such as bus timeout and packet error checking are added to help achieve this robustness, along with more specific definitions of the bus messages used to read and write data to devices on the bus.

PMBus is layered on top of SMBus and, in turn, on I SMBus defined bus messages, PMBus defines a set of standard commands that can be used to control a device that is part of a power chain.

The ADM1075 command set is based upon the

System Management Protocol Specification

Revision 1.2. This version of the standard is intended to provide a common set of commands for communicating with dc-to-dc type devices. However, many of the standard PMBus commands can be mapped directly to the functions of a hot swap controller.

Part I and Part II of the PMBus standard describe the basic commands and how they can be used in a typical PMBus setup. The following sections describe how the PMBus standard and the ADM1075 specific commands are used.

C and aims to provide a more robust and

C. Using the

PMBus™ Power

, Part I and Part II,

DEVICE ADDRESSING

The ADM1075 is available in two models: the ADM1075-1 and

ADM1075-2. The PMBus address is seven bits in size. The

upper five bits (MSBs) of the address word are fixed and are different for each model, as follows:

• ADM1075-1: Base address is 00100xx (0x10)

• ADM1075-2: Base address is 00110xx (0x18)

The ADM1075-1 and ADM1075-2 have a single ADR pin that is used to select one of four possible addresses for a given model. The ADR pin connection selects the lowest two bits (LSBs) of the 7-bit address word (see Tab l e 6 ).

Table 6. PMBus Addresses and ADR Pin Connection

Value of Address LSBs ADR Pin Connection

00 Connect to VEE 01 150 kΩ resistor to VEE 10 No connection (floating) 11 Connect to VCAP

SMBus PROTOCOL USAGE

All I2C transactions on the ADM1075 are performed using SMBus defined bus protocols. The following SMBus protocols are implemented by the ADM1075:

• Send byte

• Receive byte

• Wr ite by te

• Read byte

• Write word

• Read word

• Block read

PACKET ERROR CHECKING

The ADM1075 PMBus interface supports the use of the packet error checking (PEC) byte that is defined in the SMBus standard. The PEC byte is transmitted by the ADM1075 during a read transaction or sent by the bus host to the ADM1075 during a write transaction. The ADM1075 supports the use of PEC with all the SMBus protocols that it implements.

The use of the PEC byte is optional. The bus host can decide whether to use the PEC byte with the ADM1075 on a messageby-message basis. There is no need to enable or disable PEC in the ADM1075.

The PEC byte is used by the bus host or the ADM1075 to detect errors during a bus transaction, depending on whether the transaction is a read or a write. If the host determines that the PEC byte read during a read transaction is incorrect, it can decide to repeat the read if necessary. If the ADM1075 determines that the PEC byte sent during a write transaction is incorrect, it ignores the command (does not execute it) and sets a status flag.

Within a group command, the host can choose to send or not send a PEC byte as part of the message to the ADM1075.

Rev. 0 | Page 28 of 52

Page 29

Data Sheet ADM1075

SMBus MESSAGE FORMATS

Figure 54 to Figure 62 show all the SMBus protocols supported by the ADM1075, along with the PEC variant. In these figures, unshaded cells indicate that the bus host is actively driving the bus; shaded cells indicate that the ADM1075 is driving the bus.

Figure 54 to Figure 62 use the following abbreviations: S = start condition Sr = repeated start condition P = stop condition

SPAAWSLAVE ADDRESS DATA BYTE

S PAAWSLAVE ADDRESS DATA BYTE P EC A

MASTER TO SLAVE SLAVE TO MASTER

Figure 54. Send Byte and Send Byte with PEC

SPAARSLAVE ADDRESS DATA BYTE

R = read bit W

= write bit A = acknowledge bit (0) A

= acknowledge bit (1)

“A” represents the ACK (acknowledge) bit. The ACK bit is typically active low (Logic 0) if the transmitted byte is successfully received by a device. However, when the receiving device is the bus master, the acknowledge bit for the last byte read is a Logic 1,

indicated by

09312-050

S PAARSLAVE ADDRESS DATA BYTE PEC

MASTER TO SLAVE SLAVE TO MASTER

Figure 55. Receive Byte and Receive Byte with PEC

SAAWSLAVE ADDRESS COMMAND CODE D ATA BYTE PA

SAAWSLAVE ADDRESS COMMAND CODE DATA BYTE

MASTER TO SLAVE SLAVE TO MASTER

Figure 56. Write Byte and Write Byte with PEC

SAAWSLAVE ADDRESS COMMA ND CODE SLAVE ADDRESS

MASTER TO SLAVE SLAVE TO MASTER

AWSLAVE ADDRESS COMMAND CODE

Figure 57. Read Byte and Read Byte with PEC

SAAWSLAVE ADDRESS COMMAND CODE DATA BYTE L OW

MASTER TO SLAVE SLAVE TO MASTER

Figure 58. Write Word and Write Word with PEC

SLAVE ADDRESS

SrA SLAVE ADDRESS ARSAWSLAVE ADDRESS COMMAND CODE

A A

ADATA BYTE HIGH

DATA BYTE

DATA BYTE HIGH

DATA BYTE LOW

09312-051

PA PEC A

09312-052

PRDATA BYTESrA

PEC

09312-053

09312-054

DATA BYTE HIG H

MASTER TO SLAVE SLAVE TO MASTER

SrA SLAVE ADDRESS ARSAWSLAVE ADDRESS COMMAND CODE

PEC

ADATA BYTE LOW

09312-055

Figure 59. Read Word and Read Word with PEC

Rev. 0 | Page 29 of 52

Page 30

ADM1075 Data Sheet

SrA SLAVE ADDRESS ARSAWSLAVE ADDRESS CO MMAND CODE

ABYTE COUNT = N

DATA BYTE 1

MASTER TO SLAVE SLAVE TO MASTER

DATA BYTE 2

PDATA BYTE NA

SrA SLAVE ADDRESS ARSAWSLAVE ADDRESS CO MMAND CODE

ADATA BYTE N PPECA

ABYTE COUNT = N

09312-056

Figure 60. Block Read and Block Read with PEC

ONE OR MORE DATA BYTES

MASTER TO SLAVE SLAVE TO MASTER

ALOW DATA BYTEASAWDEVI CE 1 ADDRESS COMMAND CODE 1

ALOW DATA BYTEASr AWDEVICE 2 ADDRESS COM MAND CODE 2

ALOW DATA BYTEASr AWDEVICE N ADDRESS COMMAND CODE N

Figure 61. Group Command

ONE OR MO RE DATA BYTES

A L OW DATA BY TE ASAWDEVICE 1 ADDRESS COMMAND CODE 1

ONE OR MO RE DATA BYTES

A L OW DATA BY TE ASr AWDEVICE 2 ADDRESS CO MMAND CODE 2

ONE OR MO RE DATA BYTES

A L OW DATA BY TE ASr AWDEVICE N ADDRESS COMMAND CODE N

ONE OR MORE DATA BYTES

AHIGH DATA BYTE

APHIGH DATA BYTE

PEC N

09312-057

APEC 1

APEC 2

MASTER TO SLAVE SLAVE TO MASTER

Figure 62. Group Command with PEC

GROUP COMMANDS

The PMBus standard defines what are known as group commands. Group commands are single bus transactions that send commands or data to more than one device at the same time. Each device is addressed separately, using its own address; there is no special group command address. A group command transaction can contain only write commands that send data to a device. It is not possible to use a group command to read data from devices.

From an I consists of the following:

• I

• Slave address bits and a write bit (followed by ACK from

• One or more data bytes (each of which is followed by ACK

• I

C protocol point of view, a normal write command

C start condition

the slave device)

from the slave device)

C stop condition to end the transaction

09312-058

A group command differs from a nongroup command in that, after the data is written to one slave device, a repeated start condition is put on the bus followed by the address of the next slave device and data. This continues until all the devices have been written to, at which point the stop condition is put on the bus by the master device.

The format of a group command and a group command with PEC is shown in Figure 62.

Each device that is written to as part of the group command does not immediately execute the command written. The device must wait until the stop condition appears on the bus. At that point, all devices execute their commands at the same time.

Using a group command, it is possible, for example, to turn multiple PMBus devices on or off at the same time. In the case of the ADM1075, it is also possible to issue a power monitor command that initiates a conversion, causing multiple ADM1075 devices to sample together at the same time. This is analogous to connecting the GPO1/

ALERT1

/CONV pins together and configuring the pin in the convert (CONV) mode to drive the power monitor sampling.

Rev. 0 | Page 30 of 52

Page 31

Data Sheet ADM1075

HOT SWAP CONTROL COMMANDS

OPERATION Command

The GATE pin that drives the FET is controlled by a dedicated hot swap state machine. The UVH, UVL, and OV input pins, along with the TIMER and SS pins and the current sense, all feed into the state machine and control when and how strongly the gate is turned off.

It is also possible to control the hot swap GATE output using commands over the PMBus interface. The OPERATION command can be used to request the hot swap output to turn on. However, if the UV pin indicates that the input supply is less than required, the hot swap output is not turned on, even if the OPERATION command indicates that the output should be enabled.

If the OPERATION command is used to disable the hot swap output, the GATE pin is held low, even if all hot swap state machine control inputs indicate that it can be enabled.

The default state of the OPERATION command ON bit is 1; therefore, the hot swap output is always enabled when the

ADM1075 comes out of UVLO. If the ON bit is never changed,

the UV input is the hot swap master on/off control signal.

By default, at power-up, the OPERATION command is disabled and must be enabled using the DEVICE_CONFIG command. This prevents inadvertent shutdowns of the hot swap controller by software.

If the ON bit is set to 0 while the UV signal is high, the hot swap output is turned off. If the UV signal is low or if the OV signal is high, the hot swap output is already off and the status of the ON bit has no effect.

If the ON bit is set to 1, the hot swap output is requested to turn on. If the UV signal is low or if the OV signal is high, setting the ON bit to 1 has no effect, and the hot swap output remains off.

It is possible to determine at any time whether the hot swap output is enabled using the STATUS_BYTE or the STATUS_WORD command (see the Status Commands section).

The OPERATION command can also be used to clear any latched faults in the status registers. To clear latched faults, set the ON bit to 0, and then reset it to 1.

DEVICE_CONFIG Command

The DEVICE_CONFIG command is used to configure certain settings within the ADM1075, for example, to modify the duration of the severe overcurrent glitch filter and to set the trip threshold. This command is also used to configure the polarity of the second IOUT current warnings.

At power-up, the OPERATION command is disabled, and the ADM1075 responds with a NACK if the OPERATION command is received. To allow use of the OPERATION command, the OPERATION_CMD_EN bit must be set using the DEVICE_CONFIG command.

POWER_CYCLE Command

The POWER_CYCLE command can be used to request that the ADM1075 be turned off for ~10 seconds and then back on. This command can be useful if the processor that controls the

ADM1075 is also powered off when the part is turned off. This

command allows the processor to request that the ADM1075 turn off and back on again as part of a single command.

ADM1075 INFORMATION COMMANDS

CAPABILITY Command

The CAPABILITY command can be used by host processors to determine the I The features reported are the maximum bus speed and whether the device supports the packet error checking (PEC) byte and the SMBAlert reporting function.

C bus features supported by the ADM1075.

PMBUS_REVISION Command

The PMBUS_REVISION command reports the version of Part I and Part II of the PMBus standard.

MFR_ID, MFR_MODEL, and MFR_REVISION Commands

The MFR_ID, MFR_MODEL, and MFR_REVISION commands return ASCII strings that can be used to facilitate detection and identification of the ADM1075 on the bus.

These commands are read using the SMBus block read message type. This message type requires that the ADM1075 return a byte count corresponding to the length of the string data that is to be read back.

STATUS COMMANDS

The ADM1075 provides a number of status bits that are used to report faults and warnings from the hot swap controller and the power monitor. These status bits are located in six different registers that are arranged in a hierarchy. The STATUS_BYTE and STATUS_WORD commands provide eight bits and 16 bits of high level information, respectively. The STATUS_BYTE and STATUS_WORD commands contain the most important status bits, as well as pointer bits that indicate whether any of the four other status registers need to be read for more detailed status information.

In the ADM1075, a particular distinction is made between faults and warnings. A fault is always generated by the hot swap controller and is defined by hardware component values. Three events can generate a fault.

• Overcurrent condition that causes the hot swap timer to

time out

• Overvoltage condition on the OV pin

• Undervoltage condition on the UVx pin

When a fault occurs, the hot swap controller always takes some action, usually to turn off the GATE pin, which is driving the FET. A fault can also generate an SMBAlert on one or both of the GPOx/

ALERTx

pins.

Rev. 0 | Page 31 of 52

Page 32

ADM1075 Data Sheet

All warnings in the ADM1075 are generated by the power monitor sampling voltage and current and then comparing these measurements to the threshold values set by the various limit commands. A warning has no effect on the hot swap controller, but it may generate an SMBAlert on one or both of the GPOx/

When a fault or warning status bit is set, it always means that the status condition—fault or warning—is active or was active at some point in the past. When a fault or warning bit is set, it is latched until it is explicitly cleared using either the OPERATION or the CLEAR_FAULTS command. Some other status bits are live, that is, they always reflect a status condition and are never latched.

ALERTx

output pins.

STATUS_BYTE and STATUS_WORD Commands

The STATUS_BYTE and STATUS_WORD commands can be used to obtain a snapshot of the overall part status. These commands indicate whether it is necessary to read more detailed information using the other status commands.

The low byte of the word returned by the STATUS_WORD command is the same byte returned by the STATUS_BYTE command. The high byte of the word returned by the STATUS_ WORD command provides a number of bits that can be used to determine which of the other status commands must be issued to obtain all active status bits.

STATUS_INPUT Command

The STATUS_INPUT command returns a number of bits relating to voltage faults and warnings and power warnings on the input supply.

STATUS_IOUT Command

The STATUS_IOUT command returns a number of bits relating to current faults and warnings on the output supply.

STATUS_VAUX Command

The STATUS_VAUX command returns a numb er of bits relating to current faults and warnings on the output supply.

STATUS_MFR_SPECIFIC Command

The STATUS_MFR_SPECIFIC command is a standard PMBus command, but the contents of the byte returned is specific to the ADM1075.

CLEAR_FAULTS Command

The CLEAR_FAULTS command is used to clear fault and warnings bits when they are set. Fault and warnings bits are latched when they are set. In this way, a host can read the bits any time after the fault or warning condition occurs and determine which problem actually occurred.

If the CLEAR_FAULTS command is issued and the fault or warning condition is no longer active, the status bit is cleared. If the condition is still active—for example, if an input voltage is below the undervoltage threshold of the UV pin—the CLEAR_FAULTS command attempts to clear the status bit, but that status bit is immediately set again.

Rev. 0 | Page 32 of 52

GPO AND ALERT PIN SETUP COMMANDS

Two multipurpose pins are provided on the ADM1075:

ALERT1

GPO1/

The GPO1/ two output modes of operation. These pins can be configured independently over the PMBus as general-purpose digital outputs. They can both be configured to generate an SMBAlert when one or more fault/warning status bits become active in the PMBus status registers. For an example of how to configure these pins to generate an SMBAlert and how to respond and clear the condition, see the Address

The GPO1/ input (CONV) to drive the power monitor in single-shot run mode and to control when a power monitor ADC sampling cycle begins. This function can be used to synchronize sampling across multiple devices, if required. ADM1075

/CONV and GPO2/

ALERT1

Example Use of SMBus Alert Response

section.

ALERT1

/CONV and GPO2/

/CONV pin can also be configured as an

ALERT2

pins have

ALERT1_CONFIG and ALERT2_CONFIG Commands

Using combinations of bit masks, the ALERT1_CONFIG and ALERT2_CONFIG commands can be used to select the status bits that, when set, generate an SMBAlert signal to a processor. They can also be used to set a GPO mode on the pin, so that it is under software control. If this mode is set, the SMBAlert masking bits are ignored.

On the ADM1075, one of the inputs can also be configured as a hardware-based convert control signal. If this mode is set, the GPO and SMBAlert masking bits are ignored.

POWER MONITOR COMMANDS

The ADM1075 provides a high accuracy, 12-bit current and voltage power monitor. The power monitor can be configured in a number of different modes of operation and can run in either continuous mode or single-shot mode with a number of different sample averaging options.

The power monitor can measure the following:

• Input voltage (VIN)

• Output current (IOUT)

• Auxiliary voltage (VAUX)

The following quantities are then calculated:

• Input power (PIN)

• Input energy (EIN)

PMON_CONFIG Command

The power monitor can run in a number of different modes with different input voltage range settings. The PMON_CONFIG command is used to set up the power monitor.

Page 33

Data Sheet ADM1075

The settings that can be configured are as follows:

• Single-shot or continuous sampling

• Enable VAUX sampling

• Current input range

• Current and voltage sample averaging

Modifying the power monitor settings while the power monitor is sampling is not recommended because it may cause spurious data or warnings to be generated.

PMON_CONTROL Command

Power monitor sampling can be initiated via software or via hardware, as follows:

• PMON_CONTROL command. This command can be

used with single-shot or continuous mode.

• GPO1/

ALERT1 convert mode, an external hardware signal can be used to take this pin high, triggering the single-shot sampling of one or more parts together.

/CONV pin. If this pin is configured for

READ_VIN, READ_VAUX, and READ_IOUT Commands

The ADM1075 power monitor measures the voltage developed across the sense resistor to provide a current measurement. The input voltage from the ADC_V pin is always measured, and the user can choose whether or not to measure the output voltage present on the ADC_AUX pin as well.

READ_PIN, READ_PIN_EXT, READ_EIN, and READ_EIN_EXT Commands

The VIN input voltage (12-bit) and IOUT current (12-bit) measurement values are multiplied by the ADM1075 to give the input power value. This is done using fixed point arithmetic and produces a 24-bit value. It is assumed that the numbers are of the 12.0 format, meaning there is no fractional part. It should be noted that only positive IOUT values are used to avoid returning a negative power.

This 24-bit value can be read from the ADM1075 using the READ_PIN_EXT command, where the most significant bit (MSB) is always a zero because PIN_EXT is a twos complement binary value that is always positive.

The 16 most significant bits of the 24-bit value are used as the value for input power (PIN). The MSB of the 16-bit PIN word is always zero because PIN is a twos complement binary value that is always positive.

Each time a power calculation is performed, the 24-bit power value is added to a 24-bit energy accumulator register. This is a twos complement representation as well; therefore, the MSB is always zero. Each time this energy accumulator register rolls over from 0x7FFFFF to 0x000000, a 16-bit rollover counter is incremented. The rollover counter is straight binary, with a maximum value of 0xFFFF before it rolls over.

There is also a 24-bit straight binary power sample counter that is incremented by one each time a power value is calculated and added to the energy accumulator.

Rev. 0 | Page 33 of 52

These registers can be read back using one of two commands, depending on the level of accuracy required for the energy accumulator and the desire to limit the frequency of reads from the ADM1075.

A bus host can read these values, and, using some difference calculations, determine the amount of energy consumed since the last read and the number of samples in that time. The bus host, using an external real-time clock, can then determine the power used in the last time period.

To avoid the loss of data, the bus host must read at a rate that ensures the rollover counter does not wrap around more than once and, if it does wrap around, that the next rollover value is less than the previous one.

The READ_EIN command returns the top 16 bits of the energy accumulator, the lower eight bits of the rollover counter, and the full 24 bits of the sample counter.

The READ_EIN_EXT command returns the full 24 bits of the energy accumulator, the full 16 bits of the rollover counter, and the full 24 bits of the sample counter. The use of the longer rollover counter means that the time interval between reads of the part to ensure that no data is lost can be increased from seconds to minutes.

PEAK_IOUT, PEAK_VIN, PEAK_VAUX, and PEAK_PIN Commands

In addition to the standard PMBus commands for reading voltage and current, the ADM1075 provides commands that can report the maximum peak voltage, current, or power value since the peak value was last cleared.

The peak values are updated only after the power monitor has sampled and averaged the current and voltage measurements. Individual peak values are cleared by writing a 0 value with the corresponding commands.

WARNING LIMIT SETUP COMMANDS

The ADM1075 power monitor can monitor a number of different warning conditions simultaneously and report any current or voltage values that exceed the user-defined thresholds using the status commands.

All comparisons performed by the power monitor require the measured voltage or current value to be strictly greater or less than the threshold value.

At power-up, all threshold limits are set to either minimum scale (for undervoltage or undercurrent conditions) or to maximum scale (for overvoltage, overcurrent or overpower conditions). This effectively disables the generation of any status warnings by default; warning bits are not set in the status registers until the user explicitly sets the threshold values.

VIN_OV_WARN_LIMIT and VIN_UV_WARN_LIMIT Commands

The VIN_OV_WARN_LIMIT and VIN_UV_WARN_LIMIT commands are used to set the OV and UV thresholds on the input voltage, as measured at the ADC_V pin.

Page 34

ADM1075 Data Sheet

VAUX_OV_WARN_LIMIT and VAUX_UV_WARN_LIMIT Commands

Th e VA U X_ O V_ WAR N _L I MI T and VAU X _U V _WA R N_ LIMIT commands are used to set the OV and UV thresholds on the output voltage, as measured at the ADC_VAUX pin on the ADM1075.

PIN_OP_WARN_LIMIT Command

The PIN_OP_WARN_LIMIT command is used to set the overpower (OP) threshold for the power measurement register.

IOUT_OC_WARN_LIMIT Command

The IOUT_OC_WARN_LIMIT command is used to set the overcurrent (OC) threshold for the current flowing through the sense resistor.

IOUT_WARN2_LIMIT Command

The IOUT_WARN2_LIMIT command provides a second current warning threshold that can be programmed. The polarity of this warning can be set to overcurrent or undercurrent using the DEVICE_CONFIG command.

PMBus DIRECT FORMAT CONVERSION

The ADM1075 uses the PMBus direct format internally to represent real-world quantities such as voltage, current, and power values. A direct format number takes the form of a 2-byte, twos complement binary integer value.

It is possible to convert between direct format value and real-world quantities using the following equations. Equation 1 converts from real-world quantities to PMBus direct values, and Equation 2 converts PMBus direct format values to real-world values.

Y = (mX + b) × 10

X = 1/m × (Y × 10

where:

Y is the value in PMBus direct format. X is the real-world value. m is the slope coefficient, a 2-byte, twos complement integer. b is the offset, a 2-byte, twos complement integer. R is a scaling exponent, a 1-byte, twos complement integer.

The same equations are used for voltage, current, and power conversions, the only difference being the values of the m, b, and R coefficients used.

Tabl e 7 lists all the coefficients required for the ADM1075. The coefficients shown are dependent on the value of the external sense resistor used in a given application. This means that an additional calculation must be performed to take the sense resistor value into account to obtain the coefficients for a specific sense resistor value. The resistor divider scaling factor on VIN/VAUX also needs to be taken into account when performing a voltage or power calculation (see Example 4).

(1)

−R

− b) (2)

The sense resistor value used in the calculations to obtain the coefficients is expressed in milliohms. The m coefficients are defined as 2-byte twos complement numbers in the PMBus standard; therefore, the maximum positive value that can be represented is 32,767. If the m value is greater than that, and is to be stored in PMBus standard form, the m coefficients should be divided by 10, and the R coefficient increased by a value of 1. For example, if performing a power calculation on the ADM1075-1 with a 10 m sense resistor, the m coefficient is 8549, and the R coefficient is 0.

Example 1

IOUT_OC_WARN_LIMIT requires a current limit value expressed in direct format.

If the required current limit is 10 A, and the sense resistor is 2 m, the first step is to determine the voltage coefficient. For an ADM1075-1, this is simply m = 806 × 2, giving 1612.

Using Equation 1, and expressing X, in units of amps,

Y = ((1612 × 10) + 20,475) × 10

−1

Y = 3659.5 = 3660 (rounded up to integer form)

Writing a value of 3660 with the IOUT_OC_WARN_LIMIT command sets an overcurrent warning at 10 A.

Example 2

The READ_IOUT command returns a direct format value of 3341, representing the current flowing through a sense resistor of 1 m.

To convert this value to the current flowing, use Equation 2,

m = 806 × 1 (for the ADM1075-1):

with

X = 1/806 × (3341 × 10

– 20,475)

X = 16.05 A

This means that when READ_IOUT returns a value of 3341,

16.05 A is flowing in the sense resistor.

Note the following:

• The same calculations that are used to convert power

values also apply to the energy accumulator value returned by the READ_EIN command because the energy accumulator is a summation of multiple power values.

• The READ_PIN_EXT and READ_EIN_EXT commands

return 24-bit extended precision versions of the 16-bit values returned by READ_PIN and READ_EIN. The direct format values must be divided by 256 prior to being converted with the coefficients shown in Ta ble 7.

Rev. 0 | Page 34 of 52

Page 35

Data Sheet ADM1075

Table 7. PMBus Conversion to Real-World Coefficients

Current (A) Power (W)—Resistor Scaled

Coefficient Voltage (V)

m 27,169 806 × R b 0 20,475 20,475 0 0 R −1 −1 −1 −1 −1

Example 3

The READ_VIN command returns a direct format value of 1726. The ADC_V pin is shorted to the OV pin, which is connected to the input supply via an 820 kΩ/11 kΩ resistor divider.

To convert this value to the input voltage, use Equation 2

X = 1/27,169 × (1726 × 10

– 0)

X = 0.635 V

This corresponds to 0.635 V at the ADC_V pin. To obtain the input voltage, this must be amplified by the resistor divider ratio,

X = 0.635 V × (820 kΩ + 11 kΩ)/11 kΩ = 47.99 V

Example 4

The PIN_OP_WARN_LIMIT command requires a power limit value expressed in direct format.

If the required power limit is 350 W and the sense resistor is 1 m, the first step is to determine the m coefficient. Assuming an ADM1075-1 device,

m = 8549 × 1 = 8549. The resistor

divider on VIN scales down the power limit referenced to the ADC input. Assuming a 49 k and 1 k resistor divider on VIN, this gives a scaling factor of 0.02.

Using Equation 1,

Y = (8549 × (350 × 0.02)) × 10

−1

Y = 5984.3 = 5984 (rounded to the nearest integer)

Writing a value of 5984 with the PIN_OP_WARN_LIMIT command sets an overpower warning at 350 W.

VOLTAGE AND CURRENT CONVERSION USING LSB VALUES

The direct format voltage and current values returned by the READ_VIN, READ_VOUT, and READ_IOUT commands, and the corresponding peak versions are the actual data output directly from the ADM1075 ADC. Because the voltages and currents are a 12-bit ADC output code, they can also be converted to real-world values with knowledge of the size of the LSB on the ADC.

The m, b, and R coefficients defined for the PMBus conversion are required to be whole integers by the standard and have therefore been rounded off slightly. Using this alternative method, with the exact LSB values, can provide slightly more accurate numerical conversions.

ADM1075-1 ADM1075-2 ADM1075-1 ADM1075-2

404 × R

SENSE

8549 × R

SENSE

4279 × R

SENSE

To convert an ADC code to current in amperes, the following formulas can be used:

OUT

SENSE

= LSB

= V

SENSE

xmV

/(R

× (I

SENSE

− 2048)

ADC

× 0.001)

where:

= (V

SENSE

LSB

= 12.4 µV.

25mV

LSB

= 24.77 µV.

50mV

is the 12-bit ADC code.

ADC

is the measured current value in amperes.

OUT

is the value of the sense resistor in milliohms.

SENSE

SENSE+

) − (V

SENSE−

To convert an ADC code to a voltage, the following formula can be used:

VM = LSB

INPUTV

× (V

ADC

+ 0.5)

where:

is the measured value in volts.

is the 12-bit ADC code.

ADC

LSB

INPUTV

= 368 V.

To convert a current in amperes to a 12-bit value, the following formulas can be used (round the result to the nearest integer):

= I

× R

= 2048 + (V

CODE

SENSE

× 0.001

/LSB

SENSE

xmV

)

where:

= (V

SENSE

is the current value in amperes.

is the value of the sense resistor in milliohms.

SENSE

is the 12-bit ADC code.

CODE

LSB

= 12.4 µV.

25mV

LSB

= 24.77 µV.

50mV

SENSE+

) − (V

SENSE−

To convert a voltage to a 12-bit value, the following formula can be used (round the result to the nearest integer):

= (VA/LSB

CODE

INPUTV

) − 0.5

where:

is the 12-bit ADC code.

CODE

is the voltage value in volts.

LSB

INPUTV

= 368 V.

SENSE

Rev. 0 | Page 35 of 52

Page 36

ADM1075 Data Sheet

ADM1075 ALERT PIN BEHAVIOR

The ADM1075 provides a very flexible alert system, whereby one or more fault/warning conditions can be indicated to an external device.

FAULTS AND WARNINGS

A PMBus fault on the ADM1075 is always generated due to an analog event and causes a change in state in the hot swap output, turning it off. The three defined fault sources are as follows:

• Undervoltage (UV) event detected on the UVH and UVL

pins

• Overvoltage (OV) event detected on the OV pin

• Overcurrent (OC) event that causes a hot swap timeout

Faults are continuously monitored, and, as long as power is applied to the device, they cannot be disabled. When a fault occurs, a corresponding status bit is set in one or more STATUS_xxx registers.

A value of 1 in a status register bit field always indicates a fault or warning condition. Fault and warning bits in the status registers are latched when set to 1. To clear a latched bit to 0— provided that the fault condition is no longer active—use the CLEAR_FAULTS command or use the OPERATION command to turn the hot swap output off and then on again.

The latched status registers provide fault recording functionality. In the event of a fault, the HS_SHUTDOWN_CAUSE bits in the manufacturing specific status register (0x80) can be used to identify the fault source (UV, OV, or OC). Other status registers can also be checked for more fault and warning information.

A warning is less severe than a fault and never causes a change in the state of the hot swap controller. The eight sources of a warning are defined as follows:

• CML: a communications error occurred on the I

• HS timer was active (HSTA): the current regulation was

active but does not necessarily shut the system down

• IOUT OC warning from the ADC

• IOUT Warning 2 from the ADC

• VIN UV warning from the ADC

• VIN OV warning from the ADC

• VAUX UV warning from the ADC

• VAUX OV warning from the ADC

• PIN OP warning from the ADC

C bus

GENERATING AN ALERT

A host device can periodically poll the ADM1075 using the status commands to determine whether a fault/warning is active. However, this polling is very inefficient in terms of software and processor resources. The ADM1075 has two

ALERTx

GPOx/ interrupts to a host processor, GPO1/

ALERT2

GPO2/

output pins that can be used to generate

ALERT1

/CONV and

By default, at power-up, the open-drain GPOx/ outputs are high impedance; therefore, the pins can be pulled high through resistors. No faults or warnings are enabled on the

ALERT2

GPO2/ the faults or warnings to be monitored. The FET health bad warning is active by default on the GPO1/ at power-up.

Any one or more of the faults and warnings listed in the Faults and Warnings section can be enabled and cause an alert, making the corresponding GPOx/

active state of a GPOx/

For example, to use GPO1/ IOUT OC warning from the ADC, the followings steps must be performed:

Set a threshold level with the IOUT_OC_WARN_LIMIT

1. command.

Set the IOUT_OC_WARN_EN1 bit in the

2. ALERT1_CONFIG register

Start the power monitor sampling on IOUT.

If an IOUT sample is taken that is above the configured IOUT OC value, the GPO1/ low, signaling an interrupt to a processor.

pin at power-up; the user must explicitly enable

ALERTx

pin active. By default, the

pin is low.

ALERT1

/CONV to monitor the

ALERT1

/CONV pin is taken

HANDLING/CLEARING AN ALERT

When faults/warnings are configured on the GPOx/ the pins become active to signal an interrupt to the processor. (These pins are active low, unless inversion is enabled.) The

ALERTx

GPOx/

Note that the GPOx/ dently of each other, but they are always made inactive together.

A processor can respond to the interrupt in one of two basic ways:

• If there is only one device on the bus, the processor can

simply read the status bytes and issue a CLEAR_FAULTS command to clear all the status bits, which causes the deassertion of the GPOx/ fault—for example, an undervoltage on the input—the status bits remain set after the CLEAR_FAULTS command is executed because the fault has not been removed. However, the GPOx/ warning becomes active. If the cause of the SMBAlert is a power monitor generated warning and the power monitor is running continuously, the next sample generates a new SMBAlert after the CLEAR_FAULTS command is issued.

• If there are many devices on the bus, the processor can issue

an SMBus alert response address command to find out which device asserted the SMBAlert line. The processor can read the status bytes from that device and issue a CLEAR_FAULTS command.

signal performs the function of an SMBAlert.

ALERTx

pins can become active indepen-

ALERTx

line is not pulled low unless a new fault/

line. If there is a persistent

ALERTx

ALERT1

/CONV pin

ALERTx

pins,

Rev. 0 | Page 36 of 52

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Data Sheet ADM1075

SMBus ALERT RESPONSE ADDRESS

The SMBus alert response address (ARA) is a special address that can be used by the bus host to locate any devices that need to talk to it. A host typically uses a hardware interrupt pin to monitor the SMBus alert pins of a number of devices. When the host interrupt occurs, the host issues a message on the bus using the SMBus receive byte or receive byte with PEC protocol.

The special address used by the host is 0x0C. Any devices that have an SMBAlert signal return their own 7-bit address as the seven MSBs of the data byte. The LSB value is not used and can be either 1 or 0. The host reads the device address from the received data byte and proceeds to handle the alert condition.

More than one device may have an active SMBAlert signal and attempt to communicate with the host. In this case, the device with the lowest address dominates the bus and succeeds in transmitting its address to the host. The device that succeeds disables its SMBusAlert signal. If the host sees that the SMBus alert signal is still low, it continues to read addresses until all devices that need to talk to it have successfully transmitted their addresses.

EXAMPLE USE OF SMBus ALERT RESPONSE ADDRESS

The full sequence of steps that occurs when an SMBAlert is generated and cleared is as follows:

A fault or warning is enabled using the ALERT1_CONFIG

command, and the corresponding status bit for the fault or warning goes from 0 to 1, indicating that the fault/warning has just become active.

The GPO1/

2. becomes active (low) to signal that an SMBAlert is active.

The host processor issues an SMBus alert response address

to determine which device has an active alert.

ALERT1

/CONV or GPO2/

ALERT2

If there are no other active alerts from devices with lower

C addresses, this device makes the GPO1/

I or GPO2/ bit period after it sends its address to the host processor.

If the GPO1/

5. low, the host processor must continue to issue SMBus alert response address commands to devices to find out the addresses of all devices whose status it must check.

The ADM1075 continues to operate with the GPO1/

6. CONV or GPO2/ the status bytes unchanged until the host reads the status

bytes and clears them, or until a new fault occurs. That is, if a status bit for a fault/warning that is enabled on the GPO1/ was not already active (equal to 1) goes from 0 to 1, a new alert is generated, causing the GPO1/ GPO2/

ALERT2

ALERT1

ALERT2

pin inactive (high) during the NACK

/CONV or GPO2/

ALERT2

/CONV or GPO2/

pin to become active again.

pin inactive and the contents of

ALERT2

ALERT1

/CONV

pin stays

ALERT1

pin and that

/CONV or

DIGITAL COMPARATOR MODE

The GPO1/ configured to indicate if a user defined threshold for voltage, current, or power is being exceeded. In this mode, the output pin is live and is not latched when a warning threshold is exceeded. In effect, the pin acts as a digital comparator where the threshold is set using the warning limit threshold commands.

The ALERTx_CONFIG command is used, as for the SMBAlert configuration, to select the specific warning threshold to be monitored. The GPO1/ then indicates if the measured value is above or below the threshold.

ALERT1

/CONV and GPO2/

ALERT1

/CONV or GPO2/

ALERT2

pins can be

ALERT2

Rev. 0 | Page 37 of 52

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ADM1075 Data Sheet

PMBus COMMAND REFERENCE

Table 8. PMBus Command Summary

Command Code Command Name SMBus Transaction Type Number of Data Bytes Reset 0x01 OPERATION Read/write byte 1 0x00 0x03 CLEAR_FAULTS Send byte 0 Not applicable 0x19 CAPABILITY Read byte 1 0xB0 0x4A IOUT_OC_WARN_LIMIT Read/write word 2 0x0FFF 0x57 VIN_OV_WARN_LIMIT Read/write word 2 0x0FFF 0x58 VIN_UV_WARN_LIMIT Read/write word 2 0x0000 0x6B PIN_OP_WARN_LIMIT Read/write word 2 0x7FFF 0x78 STATUS_BYTE Read byte 1 0x00 0x79 STATUS_WORD Read word 2 0x0000 0x7B STATUS_IOUT Read byte 1 0x00 0x7C STATUS_INPUT Read byte 1 0x00 0x80 STATUS_MFR_SPECIFIC Read byte 1 0x00 0x86 READ_EIN Block read 1 (byte count) + 6 (data) 0x06000000000000 0x88 READ_VIN Read word 2 0x0000 0x8C READ_IOUT Read word 2 0x0000 0x97 READ_PIN Read word 2 0x0000 0x98 PMBUS_REVISION Read byte 1 0x22 0x99 MFR_ID Block read 1 (byte count) + 3 (data) 0x03 + ASCII “ADI” 0x9A MFR_MODEL Block read 1 (byte count) + 9 (data) 0x09 + ASCII “ADM1075-1” or “ADM1075-2” 0x9B MFR_REVISION Block read 1 (byte count) + 1 (data) 0x01 + ASCII “1” 0xD0 PEAK_IOUT Read/write word 2 0x0000 0xD1 PEAK_VIN Read/write word 2 0x0000 0xD2 PEAK_VAUX Read/write word 2 0x0000 0xD3 PMON_CONTROL Read/write byte 1 0x01 0xD4 PMON_CONFIG Read/write byte 1 0x8F 0xD5 ALERT1_CONFIG Read/write word 2 0x8000 0xD6 ALERT2_CONFIG Read/write word 2 0x0004 0xD7 IOUT_WARN2_LIMIT Read/write word 2 0x0000 0xD8 DEVICE_CONFIG Read/write byte 1 0x00 0xD9 POWER_CYCLE Send byte 0 Not applicable 0xDA PEAK_PIN Read/write word 2 0x0000 0xDB READ_PIN_EXT Block read 1 (byte count) + 3 (data) 0x03000000 0xDC READ_EIN_EXT Block read 1 (byte count) + 8 (data) 0x080000000000000000 0xDD READ_VAUX Read word 2 0x0000 0xDE VAUX_OV_WARN_LIMIT Read/write word 2 0x0FFF 0xDF VAUX_UV_WARN_LIMIT Read/write word 2 0x0000 0xF6 STATUS_VAUX Read byte 1 0x00

Rev. 0 | Page 38 of 52

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Data Sheet ADM1075

REGISTER DETAILS

OPERATION COMMAND REGISTER

Address: 0x01, Reset: 0x00, Name: OPERATION

Table 9. Bit Descriptions for OPERATION

Bits Bit Name Settings Description Reset Access 7 ON Hot swap enable. 0x0 RW 0 Hot swap output disabled. 1 Hot swap output enabled. [6:0] RESERVED Always reads as 0000000. 0x0 R

CLEAR FAULTS REGISTER

Address: 0x03, Send Byte, No Data, Name: CLEAR_FAULTS

PMBUS CAPABILITY REGISTER

Address: 0x19, Reset: 0xB0, Name: CAPABILITY

Table 10. Bit Descriptions for CAPABILITY

Bits Bit Name Settings Description Reset Access 7 PEC_SUPPORT Always reads as 1. Packet error checking (PEC) is supported. 0x1 R [6:5] MAX_BUS_SPEED Always reads as 01. Maximum supported bus speed is 400 kHz. 0x01 R 4 SMBALERT_SUPPORT

[3:0] RESERVED Always reads as 0000. 0x0000 R

Always reads as 1. Device supports SMBAlert and alert response address (ARA).

0x1 R

IOUT OC WARN LIMIT REGISTER

Address: 0x4A, Reset: 0x0FFF, Name: IOUT_OC_WARN_LIMIT

Table 11. Bit Descriptions for IOUT_OC_WARN_LIMIT

Bits Bit Name Settings Description Reset Access [15:12] RESERVED Always reads as 0000. 0x0 R [11:0] IOUT_OC_WARN_LIMIT

Overcurrent threshold for the IOUT measurement through the sense resistor, expressed in ADC codes.

0xFFF RW

VIN OV WARN LIMIT REGISTER

Address: 0x57, Reset: 0x0FFF, Name: VIN_OV_WARN_LIMIT

Table 12. Bit Descriptions for VIN_OV_WARN_LIMIT

Bits Bit Name Settings Description Reset Access [15:12] RESERVED Always reads as 0000. 0x0 R [11:0] VIN_OV_WARN_LIMIT

Overvoltage threshold for the ADC_V pin measurement, expressed in ADC codes.

0xFFF RW

VIN UV WARN LIMIT REGISTER

Address: 0x58, Reset: 0x0000, Name: VIN_UV_WARN_LIMIT

Table 13. Bit Descriptions for VIN_UV_WARN_LIMIT

Bits Bit Name Settings Description Reset Access [15:12] RESERVED Always reads as 0000. 0x0 R [11:0] VIN_UV_WARN_LIMIT

Undervoltage threshold for the ADC_V pin measurement, expressed in ADC codes.

0x0 RW

Rev. 0 | Page 39 of 52

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ADM1075 Data Sheet

PIN OP WARN LIMIT REGISTER

Address: 0x6B, Reset: 0x7FFF, Name: PIN_OP_WARN_LIMIT

Table 14. Bit Descriptions for PIN_OP_WARN_LIMIT

Bits Bit Name Settings Description Reset Access 15 RESERVED Always reads as 0. 0x0 R [14:0] PIN_OP_WARN_LIMIT

Overpower threshold for the PMBus power measurement, expressed in ADC codes.

STATUS BYTE REGISTER

Address: 0x78, Reset: 0x00, Name: STATUS_BYTE

Table 15. Bit Descriptions for STATUS_BYTE

Bits Bit Name Settings Description Reset Access 7 RESERVED Always reads as 0. 0x0 R 6 HOTSWAP_OFF Live register. 0x0 R 0 The hot swap gate drive output is enabled. 1

5 RESERVED Always reads as 0. 0x0 R 4 IOUT_OC_FAULT Latched register. 0x0 R 0 No overcurrent output fault detected. 1

3 VIN_UV_FAULT Latched register. 0x0 R 0 No undervoltage input fault detected on the UVH/UVL pins. 1 An undervoltage input fault was detected on the UVH/UVL pins. 2 RESERVED Always reads as 0. 0x0 R 1 CML_FAULT Latched register. 0x0 R 0 No communications error detected on the I2C/PMBus interface. 1

0 NONE_OF_THE_ABOVE Live register. 0x0 R 0

The hot swap gate drive output is disabled, and the GATE pin is pulled down. This can be due to, for example, an overcurrent fault that causes the ADM1075 to latch off, an undervoltage condition on the UVx pin, or the use of the OPERATION command to turn the output off.

The hot swap controller detected an overcurrent condition and the time limit set by the capacitor on the TIMER pin has elapsed, causing the hot swap gate drive to shut down.

An error was detected on the I are unsupported command, invalid PEC byte, and incorrectly structured message.

No other active status bit to be reported by any other status command.

Active status bits are waiting to be read by one or more status commands.

C/PMBus interface. Errors detected

0x7FFF RW

STATUS WORD REGISTER

Address: 0x79, Reset: 0x0000, Name: STATUS_WORD

Table 16. Bit Descriptions for STATUS_WORD

Bits Bit Name Settings Description Reset Access 15 RESERVED Always reads as 0. 0x0 R 14 IOUTPOUT_STATUS Live register. 0x0 R 0 There are no active status bits to be read by STATUS_IOUT. 1 There are one or more active status bits to be read by STATUS_IOUT.

Rev. 0 | Page 40 of 52

Page 41

Data Sheet ADM1075

Bits Bit Name Settings Description Reset Access 13 INPUT_STATUS Live register. 0x0 R 0 There are no active status bits to be read by STATUS_INPUT. 1 There are one or more active status bits to be read by STATUS_INPUT. 12 MFR_STATUS Live register. 0x0 R 0 There are no active status bits to be read by STATUS_MFR_SPECIFIC. 1

11 PGB_STATUS Live register. 0x0 R 0

[10:8] RESERVED Always reads as 000. 0x0 R [7:0] STATUS_BYTE

There are one or more active status bits to be read by STATUS_MFR_SPECIFIC.

The voltage on the DRAIN pin is above the required threshold, indicating that output power is considered good. This bit is the

PWRGD

logical inversion of the The voltage on the DRAIN pin is below the required threshold,

indicating that output power is considered bad.

This byte is the same as the byte returned by the STATUS_BYTE command.

pin on the part.

IOUT STATUS REGISTER

Address: 0x7B, Reset: 0x00, Name: STATUS_IOUT

Table 17. Bit Descriptions for STATUS_IOUT

Bits Bit Name Settings Description Reset Access 7 IOUT_OC_FAULT Latched register. 0x0 R 0 No overcurrent output fault detected. 1

6 RESERVED Always reads as 0. 0x0 R 5 IOUT_OC_WARN Latched register. 0x0 R 0

[4:0] RESERVED Always reads as 00000. 0x0 R

The hot swap controller detected an overcurrent condition and the time limit set by the capacitor on the TIMER pin has elapsed, causing the hot swap gate drive to shut down.

No overcurrent condition on the output supply detected by the power monitor using the IOUT_OC_WARN_LIMIT command.

An overcurrent condition was detected by the power monitor using the IOUT_OC_WARN_LIMIT command.

0x0 R

INPUT STATUS REGISTER

Address: 0x7C, Reset: 0x00, Name: STATUS_INPUT

Table 18. Bit Descriptions for STATUS_INPUT

Bits Bit Name Settings Description Reset Access 7 VIN_OV_FAULT Latched register. 0x0 R 0 No overvoltage detected on the OV pin. 1 An overvoltage was detected on the OV pin. 6 VIN_OV_WARN Latched register. 0x0 R 0

5 VIN_UV_WARN Latched register. 0x0 R 0

No overvoltage condition on the input supply detected by the power monitor.

An overvoltage condition on the input supply was detected by the power monitor.

No undervoltage condition on the input supply detected by the power monitor.

An undervoltage condition on the input supply was detected by the power monitor.

Rev. 0 | Page 41 of 52

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ADM1075 Data Sheet

Bits Bit Name Settings Description Reset Access 4 VIN_UV_FAULT Latched register. 0x0 R 0 No undervoltage detected on the UVx pin. 1 An undervoltage was detected on the UVx pin. [3:1] RESERVED Always reads as 000. 0x0 R 0 PIN_OP_WARN Latched register. 0x0 R 0

No overpower condition on the input supply detected by the power monitor.

An overpower condition on the input supply was detected by the power monitor.

MANUFACTURING SPECIFIC STATUS REGISTER

Address: 0x80, Reset: 0x00, Name: STATUS_MFR_SPECIFIC

Table 19. Bit Descriptions for STATUS_MFR_SPECIFIC

Bits Bit Name Settings Description Reset Access 7 FET_HEALTH_BAD Latched register. 0x0 R 0 FET behavior appears to be as expected. 1 FET behavior suggests that the FET may be shorted. 6 UV_CMP_OUT Live register. 0x0 R 0 Input voltage to UVx pin is above threshold. 1 Input voltage to UVx pin is below threshold. 5 OV_CMP_OUT Live register. 0x0 R 0 Input voltage to OV pin is below threshold. 1 Input voltage to OV pin is above threshold. 4 VAUX_STATUS Latched register. 0x0 R 0 There are no active status bits to be read by STATUS_VAUX. 1 There are one or more active status bits to be read by STATUS_VAUX. 3 HS_INLIM_FAULT Latched register. 0x0 R 0 The ADM1075 has not actively limited the current into the load. 1

[2:1] HS_SHUTDOWN_CAUSE Latched register. 0x0 R 00

0 IOUT_WARN2 Latched register. 0x0 R 0

The ADM1075 has actively limited current into the load. This bit differs from the IOUT_OC_FAULT bit in that the HS_INLIM bit is set immediately, whereas the IOUT_OC_FAULT bit is not set unless the time limit set by the capacitor on the TIMER pin elapses.

The ADM1075 is either enabled and working correctly, or has been shut down using the OPERATION command.

An IOUT_OC_FAULT condition occurred that caused the ADM1075 to shut down.

A VIN_UV_FAULT condition occurred that caused the ADM1075 to shut down.

A VIN_OV_FAULT condition occurred that caused the ADM1075 to shut down.

No overcurrent condition on the output supply detected by the power monitor using the IOUT_WARN2_LIMIT command.

An undercurrent or overcurrent condition on the output supply was detected by the power monitor using the IOUT_WARN2_LIMIT command. The polarity of the threshold condition is set by the IOUT_WARN2_OC_SELECT bit using the DEVICE_CONFIG command.

Rev. 0 | Page 42 of 52

Page 43

Data Sheet ADM1075

READ EIN REGISTER

Address: 0x86, Reset: 0x06000000000000, Name: READ_EIN

Table 20. Bit Descriptions for READ_EIN

Bits Bit Name Settings Description Reset Access [55:48] BYTE_COUNT

[47:32] ENERGY_COUNT

[31:24] ROLLOVER_COUNT

[23:0] SAMPLE_COUNT

Always reads as 0x06, the number of data bytes that the block read command should expect to read.

Energy accumulator value in direct format. Byte 2 is the high byte, and Byte 1 is the low byte. Internally, the energy accumulator is a 24-bit value, but only the most significant 16 bits are returned with this command. Use the READ_EIN_EXT to access the nontruncated version.

Number of times that the energy count has rolled over, from 0x7FFF to 0x0000. This is a straight 8-bit binary value.

This is the total number of PIN samples acquired and accumulated in the energy count accumulator. Byte 6 is the high byte, Byte 5 is the middle byte, and Byte 4 is the low byte.

READ VIN REGISTER

Address: 0x88, Reset: 0x0000, Name: READ_VIN

Table 21. Bit Descriptions for READ_VIN

Bits Bit Name Settings Description Reset Access [15:12] RESERVED Always reads as 0000. 0x0 R [11:0] READ_VIN

Input voltage from the ADC_V pin measurement, expressed in ADC codes.

0x6 R

0x0 R

READ IOUT REGISTER

Address: 0x8C, Reset: 0x0000, Name: READ_IOUT

Table 22. Bit Descriptions for READ_IOUT

Bits Bit Name Settings Description Reset Access [15:12] RESERVED Always reads as 0000. 0x0 R [11:0] READ_IOUT Output current measurement through the sense resistor. 0x0 R

READ PIN REGISTER

Address: 0x97, Reset: 0x0000, Name: READ_PIN

Table 23. Bit Descriptions for READ_PIN

Bits Bit Name Settings Description Reset Access [15:0] READ_PIN Input power from the VIN × IOUT calculation. 0x0 R

PMBus REVISION REGISTER

Address: 0x98, Reset: 0x22, Name: PMBUS_REVISION

Table 24. Bit Descriptions for PMBUS_REVISION

Bits Bit Name Settings Description Reset Access [7:4] PMBUS_P1_REVISION Always reads as 0010, PMBus Specification Part I, Revision 1.2. 0x2 R [3:0] PMBUS_P2_REVISION Always reads as 0010, PMBus Specification Part II, Revision 1.2. 0x2 R 0000 Rev1.0. 0001 Rev1.1. 0010 Rev1.2.

Rev. 0 | Page 43 of 52

Page 44

ADM1075 Data Sheet

MANUFACTURING ID REGISTER

Address: 0x99, Reset: 0x03414449, Name: MFR_ID

Table 25. Bit Descriptions for MFR_ID

Bits Bit Name Settings Description Reset Access [31:24] BYTE_COUNT

[23:16] CHARACTER1 Always reads as 0x41 = “A”. 0x41 R [15:8] CHARACTER2 Always reads as 0x44 = “D”. 0x44 R [7:0] CHARACTER3 Always reads as 0x49 = “I”. 0x49 R

Always reads as 0x03, the number of data bytes that the block read command should expect to read.

MANUFACTURING MODEL REGISTER

Address: 0x9A, Reset: 0x0941444D313037352D31, Name: MFR_MODEL

Table 26. Bit Descriptions for MFR_MODEL

Bits Bit Name Settings Description Reset Access [79:72] BYTE_COUNT

[71:64] CHARACTER1 Always reads as 0x41 = “A”. 0x41 R [63:56] CHARACTER2 Always reads as 0x44 = “D”. 0x44 R [55:48] CHARACTER3 Always reads as 0x4D = “M”. 0x4D R [47:40] CHARACTER4 Always reads as 0x31 = “1”. 0x31 R [39:32] CHARACTER5 Always reads as 0x30 = “0”. 0x30 R [31:24] CHARACTER6 Always reads as 0x37 = “7”. 0x37 R [23:16] CHARACTER7 Always reads as 0x35 = “5”. 0x35 R [15:8] CHARACTER8 Always reads as 0x2D = “-”. 0x2D R [7:0] CHARACTER9

Always reads as 0x03, the number of data bytes that the block read command should expect to read.

Always reads as 0x31 = “1” for ADM1075-1. Always reads as 0x32 = “2” for ADM1075-2.

0x3 R

0x9 R

0x31 or 0x32

MANUFACTURING REVISION REGISTER

Address: 0x9B, Reset: 0x0131, Name: MFR_REVISION

Table 27. Bit Descriptions for MFR_REVISION

Bits Bit Name Settings Description Reset Access [15:8] BYTE_COUNT

[7:0] CHARACTER1 Always reads as 0x31, Revision 1 of ADM1075. 0x31 R

Always reads as 0x01, the number of data bytes that the block read command should expect to read.

0x1 R

PEAK IOUT REGISTER

Address: 0xD0, Reset: 0x0000, Name: PEAK_IOUT (writing 0x0000 clears the peak value)

Table 28. Bit Descriptions for PEAK_IOUT

Bits Bit Name Settings Description Reset Access [15:12] RESERVED Always reads as 0000. 0x0 R [11:0] PEAK_IOUT Returns the peak IOUT current since the register was last cleared. 0x0 R

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Page 45

Data Sheet ADM1075

PEAK VIN REGISTER

Address: 0xD1, Reset: 0x0000, Name: PEAK_VIN (writing 0x0000 clears the peak value)

Table 29. Bit Descriptions for PEAK_VIN

Bits Bit Name Settings Description Reset Access [15:12] RESERVED Always reads as 0000. 0x0 R [11:0] PEAK_VIN Returns the peak VIN voltage since the register was last cleared. 0x0 R

PEAK VAUX REGISTER

Address: 0xD2, Reset: 0x0000, Name: PEAK_VAUX (writing 0x0000 clears the peak value)

Table 30. Bit Descriptions for PEAK_VAUX

Bits Bit Name Settings Description Reset Access [15:12] RESERVED Always reads as 0000. 0x0 R [11:0] PEAK_VAUX Returns the peak VAUX voltage since the register was last cleared. 0x0 R

POWER MONITOR CONTROL REGISTER

Address: 0xD3, Reset: 0x01, Name: PMON_CONTROL

Table 31. Bit Descriptions for PMON_CONTROL

Bits Bit Name Settings Description Reset Access [7:1] RESERVED Always reads as 0000000. 0x0 R 0 CONVERT 0x1 RW 0 Power monitor is not running. 1

Default. Starts the sampling of current and voltage with the power monitor. In single-shot mode, this bit clears itself after one complete cycle. In continuous mode, this bit must be written to 0 to stop sampling.

POWER MONITOR CONFIGURATION REGISTER

Address: 0xD4, Reset: 0x8F, Name: PMON_CONFIG

Table 32. Bit Descriptions for PMON_CONFIG

Bits Bit Name Settings Description Reset Access 7 PMON_MODE 0x1 RW 0 This setting selects single-shot sampling mode. 1 Default. This setting selects continuous sampling mode. 6 VAUX_ENABLE 0x0 RW 0

1 The power monitor also samples the voltage on the ADC_AUX pin. 5 RESERVED Always reads as 0. 0x0 R [4:3] IRANGE 0x1 RW 00 Reserved. 01 Sets current sense range to 25 mV. Default for ADM1075-1. 10 Sets current sense range to 50 mV. Default for ADM1075-2. 11 Reserved. [2:0] AVERAGING 0x7 RW 000 Disables sample averaging for current and voltage. 001 Sets sample averaging for current and voltage to two samples. 010 Sets sample averaging for current and voltage to four samples. 011 Sets sample averaging for current and voltage to eight samples. 100 Sets sample averaging for current and voltage to 16 samples. 101 Sets sample averaging for current and voltage to 32 samples. 110 Sets sample averaging for current and voltage to 64 samples. 111 Default. Sets sample averaging for current and voltage to 128 samples.

Default. The power monitor samples the input voltage on ADC_V and IOUT.

Rev. 0 | Page 45 of 52

Page 46

ADM1075 Data Sheet

ALERT1 CONFIGURATION REGISTER

Address: 0xD5, Reset: 0x8000, Name: ALERT1_CONFIG

Table 33. Bit Descriptions for ALERT1_CONFIG

Bits Bit Name Settings Description Reset Access 15 FET_HEALTH_BAD_EN1 0x1 RW 0

14 IOUT_OC_FAULT_EN1 0x0 RW 0

1 Generates SMBAlert when the IOUT_OC_FAULT bit is set. 13 VIN_OV_FAULT_EN1 0x0 RW 0

1 Generates SMBAlert when the VIN_OV_FAULT bit is set. 12 VIN_UV_FAULT_EN1 0x0 RW 0

1 Generates SMBAlert when the VIN_UV_FAULT bit is set. 11 CML_ERROR_EN1 0x0 RW 0

1 Generates SMBAlert when the CML_ FAULT bit is set. 10 IOUT_OC_WARN_EN1 0x0 RW 0

1 Generates SMBAlert when the IOUT_OC_WARN bit is set. 9 IOUT_WARN2_EN1 0x0 RW 0

1 Generates SMBAlert when the IOUT_WARN2 bit is set. 8 VIN_OV_WARN_EN1 0x0 RW 0

1 Generates SMBAlert when the VIN_OV_WARN bit is set. 7 VIN_UV_WARN_EN1 0x0 RW 0

1 Generates SMBAlert when the VIN_UV_WARN bit is set. 6 VAUX_OV_WARN_EN1 0x0 RW 0

1 Generates SMBAlert when the VAUX_OV_WARN bit is set. 5 VAUX_UV_WARN_EN1 0x0 RW 0

1 Generates SMBAlert when the VAUX_UV_WARN bit is set. 4 HS_INLIM_EN1 0x0 RW 0

1 Generates SMBAlert when the HS_INLIM_FAULT bit is set.

Disables generation of SMBAlert when the FET_HEALTH_BAD bit is set.

Default. Generates SMBAlert when the FET_HEALTH_BAD bit is set. This bit is active from power-up so that a FET problem can be detected and flagged immediately without the need for software to set this bit.

Default. Disables generation of SMBAlert when the IOUT_OC_FAULT bit is set.

Default. Disables generation of SMBAlert when the VIN_OV_FAULT bit is set.

Default. Disables generation of SMBAlert when the VIN_UV_FAULT bit is set.

Default. Disables generation of SMBAlert when the CML_FAULT bit is set.

Default. Disables generation of SMBAlert when the IOUT_OC_WARN bit is set.

Default. Disables generation of SMBAlert when the IOUT_WARN2 bit is set.

Default. Disables generation of SMBAlert when the VIN_OV_WARN bit is set.

Default. Disables generation of SMBAlert when the VIN_UV_WARN bit is set.

Default. Disables generation of SMBAlert when the VAUX_OV_WARN bit is set.

Default. Disables generation of SMBAlert when the VAUX_UV_WARN bit is set.

Default. Disables generation of SMBAlert when the HS_INLIM_FAULT bit is set.

Rev. 0 | Page 46 of 52

Page 47

Data Sheet ADM1075

Bits Bit Name Settings Description Reset Access 3 PIN_OP_WARN_EN1 0x0 RW 0

1 Generates SMBAlert when the PIN_OP_WARN bit is set. [2:1] GPO1_MODE 0x0 RW 00 Default. GPO1 is configured to generate SMBAlerts. 01

10 GPO1 is configured as a convert (CONV) input pin. 11

0 GPO1_INVERT 0x0 RW 0 Default. In GPO mode, the GPO1 pin is active low. 1 In GPO mode, the GPO1 pin is active high.

Default. Disables generation of SMBAlert when the PIN_OP_WARN bit is set.

GPO1 can be used a general-purpose digital output pin. The GPO1_INVERT bit is used to change the output state.

This is digital comparator mode. The output pin now reflects the live status of the warning or fault bit selected for the output. In effect, this is a nonlatched SMBAlert.

ALERT2 CONFIGURATION REGISTER

Address: 0xD6, Reset: 0x0004, Name: ALERT2_CONFIG

Table 34. Bit Descriptions for ALERT2_CONFIG

Bits Bit Name Settings Description Reset Access 15 FET_HEALTH_BAD_EN2 0x0 RW 0

14 IOUT_OC_FAULT_EN2 0x0 RW 0

1 Generates SMBAlert when the IOUT_OC_FAULT bit is set. 13 VIN_OV_FAULT_EN2 0x0 RW 0

1 Generates SMBAlert when the VIN_OV_FAULT bit is set. 12 VIN_UV_FAULT_EN2 0x0 RW 0

1 Generates SMBAlert when the VIN_UV_FAULT bit is set. 11 CML_ERROR_EN2 0x0 RW 0

1 Generates SMBAlert when the CML_ FAULT bit is set. 10 IOUT_OC_WARN_EN2 0x0 RW 0

1 Generates SMBAlert when the IOUT_OC_WARN bit is set. 9 IOUT_WARN2_EN2 0x0 RW 0

1 Generates SMBAlert when the IOUT_WARN2 bit is set. 8 VIN_OV_WARN_EN2 0x0 RW 0

1 Generates SMBAlert when the VIN_OV_WARN bit is set.

Default. Disables generation of SMBAlert when the FET_HEALTH_BAD bit is set.

Generates SMBAlert when the FET_HEALTH_BAD bit is set. This bit is active from power-up so that a FET problem can be detected and flagged immediately without the need for software to set this bit.

Default. Disables generation of SMBAlert when the IOUT_OC_FAULT bit is set.

Default. Disables generation of SMBAlert when the VIN_OV_FAULT bit is set.

Default. Disables generation of SMBAlert when the VIN_UV_FAULT bit is set.

Default. Disables generation of SMBAlert when the CML_FAULT bit is set.

Default. Disables generation of SMBAlert when the IOUT_OC_WARN bit is set.

Default. Disables generation of SMBAlert when the IOUT_WARN2 bit is set.

Default. Disables generation of SMBAlert when the VIN_OV_WARN bit is set.

Rev. 0 | Page 47 of 52

Page 48

ADM1075 Data Sheet

Bits Bit Name Settings Description Reset Access 7 VIN_UV_WARN_EN2 0x0 RW 0

1 Generates SMBAlert when the VIN_UV_WARN bit is set. 6 VAUX_OV_WARN_EN2 0x0 RW 0

1 Generates SMBAlert when the VAUX_OV_WARN bit is set. 5 VAUX_UV_WARN_EN2 0x0 RW 0

1 Generates SMBAlert when the VAUX_UV_WARN bit is set. 4 HS_INLIM_EN2 0x0 RW 0

1 Generates SMBAlert when the HS_INLIM_FAULT bit is set. 3 PIN_OP_WARN_EN2 0x0 RW 0

1 Generates SMBAlert when the PIN_OP_WARN bit is set. [2:1] GPO2_MODE 0x2 RW 00 GPO2 is configured to generate SMBAlerts. 01

10 Default. GPO2 is configured as a retry fail output. 11

0 GPO2_INVERT 0x0 RW 0 Default. In GPO mode, the GPO2 pin is active low. 1 In GPO mode, the GPO2 pin is active high.

Default. Disables generation of SMBAlert when the VIN_UV_WARN bit is set.

Default. Disables generation of SMBAlert when the VAUX_OV_WARN bit is set.

Default. Disables generation of SMBAlert when the VAUX_UV_WARN bit is set.

Default. Disables generation of SMBAlert when the HS_INLIM_FAULT bit is set.

Default. Disables generation of SMBAlert when the PIN_OP_WARN bit is set.

GPO2 can be used a general-purpose digital output pin. The GPO2_INVERT bit is used to change the output state.

This is digital comparator mode. The output pin now reflects the live status of the warning or fault bit selected for the output. In effect, this is a nonlatched SMBAlert.

IOUT WARN2 LIMIT REGISTER

Address: 0xD7, Reset: 0x0000, Name: IOUT_WARN2_LIMIT

Table 35. Bit Descriptions for IOUT_WARN2_LIMIT

Bits Bit Name Settings Description Reset Access [15:12] RESERVED Always reads as 0000. 0x0 R [11:0] IOUT_WARN2_LIMIT

Threshold for the IOUT measurement through the sense resistor, expressed in ADC codes. This value can be either an undercurrent or overcurrent, depending on the state of the IOUT_WARN2_OC_SELECT bit set using the DEVICE_CONFIG command.

0x0 RW

DEVICE CONFIGURATION REGISTER

Address: 0xD8, Reset: 0x00, Name: DEVICE_CONFIG

Table 36. Bit Descriptions for DEVICE_CONFIG

Bits Bit Name Settings Description Reset Access [7:6] RESERVED Always reads as 00. 0x00 R 5 OPERATION_CMD_ENABLE Enable operation command. 0x0 RW 0

The OPERATION command is disabled, and the ADM1075 issues a NACK if the command is received. This setting provides some protection against a card accidentally turning itself off

The OPERATION command is enabled, and the ADM1075 responds to it.

Rev. 0 | Page 48 of 52

Page 49

Data Sheet ADM1075

Bits Bit Name Settings Description Reset Access 4 IOUT_WARN2_OC_SELECT Sets IOUT Warning 2 limit to OC or UC. 0x0 RW 0 Configures IOUT_WARN2_LIMIT as an undercurrent threshold 1 Configured IOUT_WARN2_LIMIT as an overcurrent threshold [3:2] OC_TRIP_SELECT Sets severe OC trip threshold. 0x0 RW 00 125%. 01 150%. Default. 10 200%. 11 225%. [1:0] OC_FILT_SELECT Sets severe OC filter time. 0x0 RW 00 200 ns. 01 900 ns. Default. 10 10.7 µs. 11 57 µs.

POWER CYCLE REGISTER

Address: 0xD9, Send Byte, No Data, Name: POWER_CYCLE

PEAK PIN REGISTER

Address: 0xDA, Reset: 0x0000, Name: PEAK_PIN (writing 0x0000 clears the peak value)

Table 37. Bit Descriptions for PEAK_PIN

Bits Bit Name Settings Description Reset Access [15:0] PEAK_PIN Returns the peak input power since the register was last cleared. 0x0 R

READ PIN_EXT REGISTER

Address: 0xDB, Reset: 0x03000000, Name: READ_PIN_EXT

Table 38. Bit Descriptions for READ_PIN_EXT

Bits Bit Name Settings Description Reset Access [31:24] BYTE_COUNT

[23:0] READ_PIN_EXT

Always reads as 0x03, the number of data bytes that the block read command should expect to read.

This is the result of the VIN × IOUT calculation that has not been truncated. Byte 3 is the high byte, Byte 2 is the middle byte, and Byte 1 is the low byte.

0x3 R

0x0 R

READ EIN_EXT REGISTER

Address: 0xDC, Reset: 0x080000000000000000, Name: READ_EIN_EXT

Table 39. Bit Descriptions for READ_EIN_EXT

Bits Bit Name Settings Description Reset Access [71:64] BYTE_COUNT

[63:40] ENERGY_EXT

[39:24] ROLLOVER_EXT

[23:0] SAMPLE_COUNT

Always reads as 0x08, the number of data bytes that the block read command should expect to read.

This is the 24-bit energy accumulator in direct format. Byte 3 is the high byte, Byte 2 is the middle byte, and Byte 1 is the low byte.

Number of times that the energy count has rolled over, from 0x7FFF to 0x0000. This is a straight 16-bit binary value. Byte 5 is the high byte, Byte 4 is the low byte.

This is the total number of PIN samples acquired and accumulated in the energy count accumulator. Byte 8 is the high byte, Byte 7 is the middle byte, and Byte 6 is the low byte.

0x8 R

0x0 R

Rev. 0 | Page 49 of 52

Page 50

ADM1075 Data Sheet

READ VAUX REGISTER

Address: 0xDD, Reset: 0x0000, Name: READ_VAUX

Table 40. Bit Descriptions for READ_VAUX

Bits Bit Name Settings Description Reset Access [15:12] RESERVED Always reads as 0000. 0x0 R [11:0] READ_VAUX

Output voltage from the ADC_AUX pin measurement, expressed in ADC codes.

VAUX OV WARN LIMIT REGISTER

Address: 0xDE, Reset: 0x0FFF, Name: VAUX_OV_WARN_LIMIT

Table 41. Bit Descriptions for VAUX_OV_WARN_LIMIT

Bits Bit Name Settings Description Reset Access [15:12] RESERVED Always reads as 0000. 0x0 R [11:0] VAUX_OV_WARN_LIMIT

Overvoltage threshold for the ADC_AUX pin measurement, expressed in ADC codes.

VAUX UV WARN LIMIT REGISTER

Address: 0xDF, Reset: 0x0000, Name: VAUX_UV_WARN_LIMIT

0x0 R

0xFFF RW

Table 42. Bit Descriptions for VAUX_UV_WARN_LIMIT

Bits Bit Name Settings Description Reset Access [15:12] RESERVED Always reads as 0000. 0x0 R [11:0] VAUX_UV_WARN_LIMIT

Undervoltage threshold for the ADC_AUX pin measurement, expressed in ADC codes.

0x0 RW

VAUX STATUS REGISTER

Address: 0xF6, Reset: 0x00, Name: STATUS_VAUX

Table 43. Bit Descriptions for STATUS_VAUX

Bits Bit Name Settings Description Reset Access 7 VAUX_OV_WARN Latched register. 0x0 R 0

6 VAUX_UV_WARN Latched register. 0x0 R 0

[5:0] RESERVED Always reads as 000000. 0x0 R

No overvoltage condition was detected on the ADC_AUX pin by the power monitor using the VAUX_OV_WARN_LIMIT command.

An overvoltage condition was detected on the ADC_AUX pin by the power monitor using the VAUX_OV_WARN_LIMIT command.

No undervoltage condition was detected on the ADC_AUX pin by the power monitor using the VAUX_UV_WARN_LIMIT command.

An undervoltage condition was detected on the ADC_AUX pin by the power monitor using the VAUX_UV_WARN_LIMIT command.

Rev. 0 | Page 50 of 52

Page 51

Data Sheet ADM1075

OUTLINE DIMENSIONS

9.80

9.70

9.60

PIN 1

0.15

0.05

OPLANARIT

0.10

0.65 BSC

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153-AE

1.20 MAX

SEATING

PLANE

4.50

4.40

4.30

0.20

0.09

6.40 BSC

8° 0°

0.75

0.60

0.45

141

Figure 63. 28-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-28)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range2 Package Description Package Option

ADM1075-1ARUZ −40°C to +85°C 28-Lead TSSOP RU-28 ADM1075-1ARUZ-RL7 −40°C to +85°C 28-Lead TSSOP RU-28 ADM1075-2ARUZ −40°C to +85°C 28-Lead TSSOP ADM1075-2ARUZ-RL7 −40°C to +85°C 28-Lead TSSOP EVAL-ADM1075EBZ Evaluation Board

Z = RoHS Compliant Part.

Operating junction temperature is −40°C to +105°C.

RU-28 RU-28

Rev. 0 | Page 51 of 52

Page 52

ADM1075 Data Sheet

NOTES

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

Rev. 0 | Page 52 of 52

Datasheet ADM1075 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

PRODUCT HIGHLIGHTS

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

GENERAL DESCRIPTION

SPECIFICATIONS

SERIAL BUS TIMING

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTION

TYPICAL PERFORMANCE CHARACTERISTIC

THEORY OF OPERATION

POWERING THE ADM1075

CURRENT SENSE INPUTS

CURRENT LIMIT REFERENCE

SETTING THE CURRENT LIMIT (ISET)

SOFT START

CONSTANT POWER FOLDBACK (PLIM)

TIMER

HOT SWAP FAULT RETRY

FAST RESPONSE TO SEVERE OVERCURRENT

UV AND OV

DRAIN

FET HEALTH

POWER MONITOR

ISOLATION

PMBus INTERFACE

DEVICE ADDRESSING

SMBus PROTOCOL USAGE

PACKET ERROR CHECKING

SMBus MESSAGE FORMATS

GROUP COMMANDS

HOT SWAP CONTROL COMMANDS

OPERATION Command

DEVICE_CONFIG Command

POWER_CYCLE Command

ADM1075 INFORMATION COMMANDS

CAPABILITY Command

PMBUS_REVISION Command

MFR_ID, MFR_MODEL, and MFR_REVISION Commands

STATUS COMMANDS

STATUS_BYTE and STATUS_WORD Commands

STATUS_INPUT Command

STATUS_IOUT Command

STATUS_VAUX Command

STATUS_MFR_SPECIFIC Command

CLEAR_FAULTS Command

GPO AND ALERT PIN SETUP COMMANDS

ALERT1_CONFIG and ALERT2_CONFIG Commands

POWER MONITOR COMMANDS

PMON_CONFIG Command

PMON_CONTROL Command

READ_VIN, READ_VAUX, and READ_IOUT Commands

READ_PIN, READ_PIN_EXT, READ_EIN, and READ_EIN_EXT Commands

PEAK_IOUT, PEAK_VIN, PEAK_VAUX, and PEAK_PIN Commands

WARNING LIMIT SETUP COMMANDS

VIN_OV_WARN_LIMIT and VIN_UV_WARN_LIMIT Commands

VAUX_OV_WARN_LIMIT and VAUX_UV_WARN_LIMIT Commands

PIN_OP_WARN_LIMIT Command

IOUT_OC_WARN_LIMIT Command

IOUT_WARN2_LIMIT Command

PMBus DIRECT FORMAT CONVERSION

Example 1

Example 2

Example 3

Example 4

VOLTAGE AND CURRENT CONVERSION USING LSB VALUES

ADM1075 ALERT PIN BEHAVIOR

FAULTS AND WARNINGS

GENERATING AN ALERT

HANDLING/CLEARING AN ALERT

SMBus ALERT RESPONSE ADDRESS

EXAMPLE USE OF SMBus ALERT RESPONSE ADDRESS