Page 1
a
–48 V Hot Swap Controller
ADM1070
FEATURES
Allows Safe Board Insertion and Removal from a Live
–48 V Backplane
Typically Operates from –36 V to –80 V
Tolerates Transients up to –200 V (Limited by External
Components)
Accurate Programmable Linear Current Limit for
In-Rush Control and Short Circuit Protection
Programmable Timeout in Current Limit
Limited Consecutive Retry:
Auto-Restart after Current Limit Timeout
Shutdown after Seven Consecutive Auto Restarts
Provides Immunity from Step Induced Current Spikes
Default Timing Provided with no TIMER Capacitor
Single Pin Undervoltage/Overvoltage Detection
Programmable Operating Voltage Window
Programmable Undervoltage/Overvoltage Time Filter
Small 6-Lead SOT-23 Package
APPLICATIONS
Central Office Switching
–48 V Distributed Power Systems
Negative Power Supply Control
Hot Board Insertion
Electronic Circuit Breaker
High Availability Servers
Programmable Current Limiting Circuit
–48 V Power Supply Modules
0V
V
DD
R1
R2
–48V
V
EE
FUNCTIONAL BLOCK DIAGRAM
16k⍀
R
DROP
V
IN
VCC AND
REFERENCE
GENERATOR
100mV
ADM1070
UV/OV
TIMER
()*
12V
OVER-UNDER
VOLTAGE DETECTION
CIRCUIT
FAULT TIMER AND
CONTROL
OSCILLATOR
*OPTIONAL TIMER CAPACITOR
EN
C
V
CC
V
REF
V
IN
45A
GATE
SENSE
V
EE
LOAD
Q1
R
SENSE
V
OUT
GENERAL DESCRIPTION
The ADM1070 is a negative voltage hot swap controller that
allows a board to be safely inserted and removed from a live
–48 V backplane. The part achieves this by providing robust
current limiting, protection against transient and nontransient
short circuits and overvoltage and undervoltage conditions. The
ADM1070 typically operates from a negative voltage of up to
–80 V and can tolerate transient voltages of up to –200 V.
In-rush current is limited to a programmable value by controlling the gate drive of an external N-channel FET. The current
limit can be controlled by the choice of the sense resistor,
R
. Added control of the in-rush current is provided by an
SENSE
on-chip timer that uses pulsewidth modulation to allow the
maximum current to flow for only 3% of the time. An autorestart
occurs after a current limit timeout. After seven successive
autorestarts, the fault will be latched and the part goes into
shutdown with the result that the external FET is disabled until
the power is reset.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
The ADM1070 also features single-pin undervoltage and overvoltage detection. The FET is turned off if a nontransient
voltage less than the undervoltage threshold, typically –36 V, or
greater than the overvoltage threshold, typically –77 V, is detected
on the UV/OV Pin. The operating voltage window of the
ADM1070 is programmable and is determined by the ratio R1/R2.
Time filtering on the undervoltage and overvoltage detection
and current limiting is programmable via the TIMER Pin. An
external capacitor connected between the TIMER Pin and V
EE
determines the undervoltage/overvoltage time filter and the
timeout in current limit. If the pin is tied to V
, the time filter
EE
values and the current limit timeout revert to default figures.
The ADM1070 is fabricated using BiCMOS technology for minimal power consumption. The part is available in a small
6-Lead SOT-23 package.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2002
Page 2
ADM1070–SPECIFICATIONS
(VDD = 0 V, VEE = –48 V, R
wise noted.)
= 16 k⍀, TA = –40ⴗC to +85ⴗC, unless other-
DROP
Parameter Min Typ Max Unit Test Conditions
BOARD SUPPLY
(not connected directly to device)
Maximum Voltage Range –200 –48 –20 V Limited by Voltage Capability of
External Components*
Typical Operating Voltage Range –77 –48 –36 V R
= 16 kΩ, R1/R2 = 40*
DROP
VIN PIN––SHUNT REGULATOR
Operating Supply Voltage Range, V
Quiescent Supply Current, I
Maximum Shunt Supply Voltage, V
Undervoltage Lockout, V
LKO
SS
SS
SS
11.5 12.3 13 V ISS = 1.5 mA to 4.25 mA
0.4 0.85 1.3 mA VSS = 11.5 V
12.5 14 V ISS = 20 mA
7 8.5 10.5 V
UV/OV PIN––UNDERVOLTAGE AND
OVERVOLTAGE DETECTION
Undervoltage Falling Threshold, V
Undervoltage Rising Threshold, V
Undervoltage Hysteresis, V
UVH
Overvoltage Falling Threshold, V
Overvoltage Rising Threshold, V
Overvoltage Hysteresis V
Power-On Reset Delay, t
Voltage Fault Filter Time (UV/OV Out of
Voltage
Input Current, I
Window), t
VMON
OVH
POR
FLT
UVF
UVR
OVF
OVR
0.81 0.86 0.91 V
0.86 0.91 0.96 V
45 mV
1.85 1.93 2.01 V
1.89 1.97 2.05 V
–45 mV
1.10 1.70 2.30 ms TIMER Pin Tied to V
(V
< UV/OV < V
0.90 1.21 1.51 ms C
UVR
= 470 pF
TIMER
(V
< UV/OV < V
UVR
OVF
OVF
1.10 1.70 2.30 ms TIMER Pin Tied to V
(V
< UV/OV < V
0.90 1.21 1.51 ms C
UVR
= 470 pF
TIMER
< UV/OV < V
(V
UVR
OVF
OVF
1.0 µA
EE
)
)
EE
)
)*
GATE PIN––FET DRIVER
Maximum Gate Voltage, V
Minimum Gate Voltage, V
Pull-Up Current, I
GUP
Pull-Down Current, I
Hold-off Impedance, R
GMAX
GMIN
GDP
GOFF
11 12 13 V I
050mVI
–20 –40 –55 µAV
10 30 mA V
10 k⍀ V
30 k⍀ V
= –1 µA
GATE
= 1 µA
GATE
= 0 V to 9 V, V
GATE
= V
GATE
GATE
GATE
SS
< 2 V, VSS > 11 V
< 2 V, VSS > 2 V
SENSE
= 0
SENSE PIN––CURRENT SENSE
Analog Current Limit Voltage (Rising),V
LIM
90 100 110 mV I
= 0 µA to –15 µA
GATE
Circuit Breaker Limit Voltage (Rising) 75 88 100 mV
Circuit Breaker Limit Voltage (Rising) –12 mV
(With Respect to V
LIM
), V
LIMITON
Circuit Breaker Limit Voltage (Falling) 60 79 95 mV
Circuit Breaker Limit Voltage (Falling) –21 mV
(With Respect to V
LIM
), V
LIMITOFF
Fast Current Limit Voltage 107 126 145 mV
Fast Current Limit Voltage 26 mV
(With Respect to V
Control Loop Transconductance, 1.5 2.75 4 µA/mV I
/dV
(dI
GATE
SENSE
Maximum Current Limit On Time, t
Current Limit PWM Off Time 320 450 580 ms TIMER Pin Tied to V
)
LIM
< ⫾30 µA, TA = 25°C
GATE
)
LIMITON
10 14 18 ms TIMER Pin Tied to V
(V
< UV/OV < V
7.4 9.9 12.4 ms C
240 320 400 ms C
UVR
= 470 pF
TIMER
(V
< UV/OV < V
UVR
(V
< UV/OV < V
UVR
= 470 pF
TIMER
(V
< UV/OV < V
UVR
OVF
OVF
OVF
OVF
EE
)
)*
EE
)*
)*
Current Limit PWM Duty Cycle 3 % (Typical Only)
Number of Consecutive PWM Retry Cycles 7 (Typical Only)
REV. 0–2–
Page 3
Parameter Min Typ Max Unit Test Conditions
WARNING!
ESD SENSITIVE DEVICE
SENSE PIN––CURRENT SENSE (continued)
Continuous Short Circuit Time before Latched 2100 2800 3500 ms TIMER Pin Tied to V
Shutdown, t
SHORT
Operating Sense Voltage Range, V
Input Current, I
TIMER PIN
SENSE
––
TIMING CONTROL
SOP
1500 2000 2500 ms C
0 0.11 V
–500 +500 µAV
(V
< UV/OV < V
UVR
= 470 pF
TIMER
(V
< UV/OV < V
UVR
= –2 V to +2 V
SENSE
Internal Oscillator Default Frequency, 9.0 kHz TIMER Pin Tied to V
f
TIMERINT
External/Internal Selection Threshold, V
High Trip Threshold, V
Low Trip Threshold, V
Pull-Down Current, I
Pull-Up Current, I
Start-Up Current, I
*Not production tested. Guaranteed by design.
Specifications subject to change without notice.
(Not Seen at Pin)
TIMERTHH
TIMERTHL
TIMERDN
TIMERUP
TIMERSTART
TIMERTHEI
0.3 0.45 0.6 V
3.0 3.5 4.0 V
1.2 1.5 1.8 V
15 24 31 µAV
–15 –24 –31 µAV
–12 –19 –26 µAV
TIMER
TIMERTHEI
< V
TIMER
> V
TIMERTHH
< V
TIMERTHEI
TIMER
ADM1070
EE
)
OVF
)*
OVF
EE
< V
TIMERTHL
ABSOLUTE MAXIMUM RATINGS*
(All voltages referred to VEE, unless otherwise noted. TA = 25°C, unless other-
wise noted.)
Supply Voltage (VDD–VEE) . . . . . . . . . . . . . –0.3 V to –200.0 V
Maximum Shunt Supply Voltage, V
. . . . . . . . . . . . . . . 16 V
SS
SENSE Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . –2 V to +16 V
GATE Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +16 V
UV/OV Pin . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +15 V
TIMER Pin . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +10 V
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125°C
Temperature Range . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Continuous Power Dissipation . . . . . . . . . . . . . . . . . 282 mW
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
*This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods of time may affect reliability.
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
ADM1070ART –40ºC to +85ºC 6-Lead RT-6
THERMAL CHARACTERISTICS
6-Lead SOT-23 Package:
= 226.6°C/W, JC = 91.99°C/W
JA
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADM1070 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. 0
–3–
Page 4
ADM1070
PIN CONFIGURATION
SENSE
V
EE
V
1
ADM1070ART
2
3
IN
TOP VIEW
(Not to Scale)
6
5
4
GATE
UV/OV
TIMER
PIN FUNCTION DESCRIPTION
Pin No. Mnemonic Function
1 SENSE Connection to External FET Source Voltage. A sense resistor is connected in the supply path
between the SENSE Pin and V
, and the voltage across this resistor is monitored to detect current
EE
faults. This voltage is fed as an input to the linear current regulator. When it reaches 100 mV for
a specified period, t
, the regulator reduces the gate voltage and drives the FET as a linear pass
ON
device. If current monitoring is not required, this feature can be turned off by shorting the
SENSE Pin and VEE together.
2V
EE
Device Negative Supply Voltage. This pin should be connected to the lower potential of the
power supply.
3V
IN
Shunt Regulated On-Chip Supply, Nominally V
EE
+ 12.3 V. This pin should be current fed
through a dropper resistor that is connected to the higher potential of the power supply inputs.
4TIMER
Allows User Control over Timing Functions by Determining Frequency of Oscillator. Frequency set by connecting external capacitor to VEE. Tying pin directly to VEE causes oscillator to
default to internally set value.
5 UV/OV Input Pin for Overvoltage and Undervoltage Detection Circuitry. The voltage appearing on the
UV/OV Pin is proportional to board supply and is determined by external resistors. When the
voltage on UV/OV falls below the undervoltage threshold of 0.86 V, the GATE Pin is driven low.
When the voltage appearing at the UV/OV Pin rises above the overvoltage threshold of 1.97 V,
the GATE Pin is also driven low. If the external resistor ratio of R1/R2 = 40 is used, then this
gives an operating range of –36 V to –77 V.
6 GATE Output to External FET Gate Drive. Controlled by linear current regulator. The gate is driven
low if an overvoltage or undervoltage fault occurs or if a current fault lasts for longer than the
time, t
. When in linear regulation, the GATE Pin voltage is controlled as part of the servo loop.
ON
No external compensation is required. When the FET is fully enhanced and the load capacitance
has been charged, the GATE Pin reaches a high level of typically 12 V.
REV. 0–4–
Page 5
2.0
TEMPERATURE – ⴗC
–45
V
Z
– V
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
–35 –25 –15 –5 5 15 25 35 45 55 65 75 85
1.8
1.6
1.4
1.2
1.0
– mA
IN
I
0.8
0.6
0.4
0.2
0
–50 –35
Typical Performance Characteristics–
–20 –5 10 25 40 55 70
TEMPERATURE – ⴗC
ADM1070
85
1000
100
– mA
IN
I
10
1
0.1
10
9
8
TPC 1. IIN vs. Temperature
+85ⴗC
+25ⴗC
02
4681012 14
VIN – V
TPC 2. IIN vs. V
TPC 4. VZ vs. Temperature
12
11
10
– V
9
LKO
V
8
–40ⴗC
16
IN
7
6
–50
–35 –20 –5 10 25 40 55 70 85
TEMPERATURE – ⴗC
TPC 5. Undervoltage Lockout, V
100
95
90
vs. Temperature
LKO
RISING
7
– V
6
Z
R
5
4
REV. 0
3
2
–45
–35 –25 –15 –5 5 15 25 35 45 55 65 75 85
TPC 3. RZ vs. Temperature
TEMPERATURE – ⴗC
–5–
85
– mV
80
CB
V
75
70
65
60
–35 –20 –5 10 25 40 55 70 85
–50
TEMPERATURE – ⴗC
FALLING
TPC 6. Circuit Breaker Current Limit Voltage,
vs. Temperature
V
CB
Page 6
ADM1070
120
115
110
105
– mV
100
ACL
V
95
90
85
80
–35 –20 –5 10 25 40 55 70 85
–50
TEMPERATURE – ⴗC
TPC 7. Analog Current Limit Voltage, V
Temperature
150
145
140
135
130
– mV
125
FCL
V
120
115
110
105
100
–50 –35
–20 –5 10 25 40 55 70
TEMPERATURE – ⴗC
ACL
vs.
60
50
40
– mA
30
GATE
I
20
10
0
–50
–35 –20 –5 10 25 40 55 70 85
TPC 10. I
14.0
13.5
13.0
12.5
– V
12.0
GATE
V
11.5
11.0
10.5
85
10.0
(FCL, Sink) vs. Temperature (V
GATE
–35 –20 –5 10 25 40 55 70 85
–50
TEMPERATURE – ⴗC
TEMPERATURE – ⴗC
GATE
= 9 V)
TPC 8. Fast Current Limit Voltage, V
60
55
50
– A
45
GATE
I
40
35
30
–50 –35
TPC 9. I
–10 5 25 405570
TEMPERATURE – ⴗC
(Source) vs. Temperature
GATE
vs. Temperature
FCL
TPC 11. V
50
40
30
– mV
GATEL
20
V
10
0
–40
85
–30 –20 –10 0 10 20 30 40 50 60 70 80 90
TPC 12. V
vs. Temperature
GATE
TEMPERATURE – ⴗC
vs. Temperature
GATEL
REV. 0–6–
Page 7
50
TEMPERATURE – ⴗC
–50
V
OV
– V
2.05
2.00
1.95
1.90
1.80
–35 –20 –5 10 25 40 55 70 85
1.85
OV HIGH
OV LOW
45
40
35
30
– mA
25
GATE
I
20
15
10
5
0
01
23
45678910 11 12
V
– V
GATE
TPC 13. I
GATE
vs. V
GATE
ADM1070
TPC 16. OV Threshold vs. Temperature
4.0
3.5
3.0
2.5
2.0
1.5
TIMER THRESHOLD – V
1.0
0.5
0
–50 –35
–20 –5 10 25 40 55
TEMPERATURE – ⴗC
HIGH
LOW
70
85
TPC 14. High and Low Timer Thresholds vs. Temperature
1.00
0.95
UV HIGH
0.90
– V
UV
V
0.85
0.80
0.75
–50
–35 –20 –5 10 25 40 55 70 85
TPC 15. UV Threshold vs. Temperature
TEMPERATURE – ⴗC
UV LOW
10
9
8
7
6
– A
5
SENSE
I
4
3
2
1
0
–50 –35
TPC 17. I
–60
–40
–20
–2.0 –1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2
0
20
– A
40
SENSE
I
60
80
100
120
–20 –5 10 25 40 55 70
TEMPERATURE – ⴗC
vs. Temperature (V
SENSE
V
– V
SENSE
TPC 18. I
SENSE
vs. (V
EE
SENSE
SENSE
– VEE)
85
= 50 mV)
2.0
1.6
REV. 0
–7–
Page 8
ADM1070
4.0
3.5
3.0
2.5
– ms
2.0
POR
T
1.5
1.0
0.5
0
–50 –35
–20 –5 10 25 40 55
TEMPERATURE – ⴗC
TIMER –> V
TIMER –> 470pF
EE
70
85
TPC 19. POR Delay vs. Temperature
4.0
3.5
3.0
2.5
– ms
-
2.0
FLT
T
1.5
1.0
0.5
0
–50 –35
–20 –5 10 25 40 55 70 85
TEMPERATURE – ⴗC
TIMER –> V
TIMER –> 470pF
EE
TPC 20. Voltage Fault Filter Time vs. Temperature
5.0
4.5
4.0
3.5
3.0
– SEC
2.5
SHORT
2.0
T
1.5
1.0
0.5
0
–50 –35
–20 –5 10 25 40 55 70
TEMPERATURE – ⴗC
TIMER –> V
TIMER –> 470pF
EE
85
TPC 22. Continuous Short Circuit Time before Shutdown
vs. Temperature
5.0
4.5
4.0
3.5
3.0
2.5
PWM – %
2.0
1.5
1.0
0.5
0
–50 –35
–20 –5 10 25 40 55 70
TEMPERATURE – ⴗC
85
TPC 23. Current Limit PWM vs. Temperature
20
18
16
14
12
– ms
10
ON
T
8
6
4
2
0
–50 –35
–20 –5 10 25 40 55 70
TEMPERATURE – ⴗC
TIMER –> V
TIMER –> 470pF
EE
TPC 21. Maximum Current Limit On Time vs.
Temperature
85
REV. 0–8–
Page 9
ADM1070
FUNCTIONAL DESCRIPTION
HOT CIRCUIT INSERTION
Inserting circuit boards into a live –48 V backplane can cause large
transient currents to be drawn as the board capacitance charges up.
These transient currents can cause glitches on the system power
supply and can permanently damage components on the board.
The ADM1070 is designed to control the manner in which a
board’s supply voltage is applied so that harmful transient currents
do not occur and the board can be safely inserted or removed from
a live backplane. Undervoltage, overvoltage, and overcurrent protection are other features of the part. The ADM1070 ensures that
the input voltage is stable and within tolerance before being applied
to the dc-to-dc converter, which generates the low voltage levels
required to power the on-board logic. One such converter is the
Artesyn EXQ50. Go to www.artesyn.com for more information.
PLUG-IN BOARD
ARTESYN
EXQ50
C
LOAD
VIN+
V
IN
V
+
OUT
V
–
OU
T
TRIM
–
0V
LIVE
BACKPLANE
–48V
R1
R2
ADM1070
R
FET
SENSE
Figure 1. Topology
INITIAL STARTUP
The ADM1070 hot swap controller normally resides on a removable circuit board and controls the manner in which power is
applied to the board upon connection. This is achieved using a
FET, Q1, in the power path. By controlling the gate voltage of
the FET, the surge of current to charge load capacitance can be
limited to a safe value when the board makes connection. Note
that the ADM1070 can also reside on the backplane itself, and
perform the same function from there.
0V
LIVE
BACKPLANE
R
16k⍀
DROP
V
R1
R2
IN
ADM1070
UV/OV
TMER
GATE
SENSE
C
LOAD
V
EE
Q1
R
SENSE
V
OUT
Figure 2 shows how a plug-in module containing the ADM1070
makes connection to the backplane supply. When the board is
inserted, the –48 V and 0 V lines connect. This powers up the
device with the voltage on V
IN
exceeding V
LKO
.
When the voltage at the UV/OV Pin exceeds undervoltage rising
threshold (V
) of 0.91 V, it is now inside the operating volt-
UVR
age window. It must stay inside this window for the duration of
the power-on reset delay time, t
value of C
.
T
, which is dependent on the
POR
When the device detects that the supply voltage is valid, it ramps
up the gate voltage until the FET turns on and the load current
increases. The ADM1070 monitors the level of the current flowing
through the FET by sensing the voltage across the external
sense resistor, R
. When the sense voltage reaches 100 mV,
SENSE
the GATE Pin is actively controlled, limiting the load current.
In this way, the maximum current permitted to flow through the
load is set by the choice of R
SENSE
.
If a change in the level of the supply voltage causes UV/OV to
fall below the undervoltage falling threshold of V
above the overvoltage rising threshold of V
OVR
, or rise
UVF
, then the gate
drive will be disabled.
BOARD REMOVAL
If the board is removed from a card cage, the voltage at the
UV/OV pin falls to zero (i.e., outside operating range) and the
gate drive is deasserted, turning off the FET.
CONTROLLING THE CURRENT
The ADM1070 features a current limiting function that protects
against short circuits or excessive supply currents. The flow of
current through the load is monitored by measuring the voltage
across the sense resistor, which is connected between the SENSE
Pins. There are three different types of protection offered:
and V
EE
1. If the voltage across the sense resistor exceeds the circuit
breaker limit voltage of 88 mV (rising) for the current limit
on time (t
), then a current fault has occurred and the
LIMITON
PWM cycle begins. The FET current is linearly controlled at
a maximum of 100 mV/R
t
duration t
given by t
(see next section). The gate is then disabled for the
LIMITON
. This PWM ratio, which will always be 3%, is
OFF
.
ON/tOFF
(via the gate drive) during
SENSE
A unique feature of the ADM1070 is the limited consecutive
retry function. An internal fault counter keeps track of the
number of successive PWM cycles that occur. The fault
counter is incremented after every fault is detected. If the
ADM1070 detects seven consecutive current faults, it is apparent that the fault is not a temporary one and the device
latches itself off. The fault counter is cleared if a new t
timeout does not occur within 2 ⫻ t
t
LIMITON
timeout.
of the previous
OFF
ON
–48V
REV. 0
Figure 2. Circuit Board Connection
–9–
Page 10
ADM1070
2. If a voltage between the SENSE and VEE Pins increases to
100 mV (the analog current limit voltage) during t
LIMITON
,
then the ADM1070 takes action to reduce this current to a
safer level. The internal analog current limit loop dynamically adjusts the gate drive, keeping the load current at the
100 mV/R
level. The FET now acts as a current
SENSE
source, limiting the load current to the level set by the value
of the sense resistor.
The sense voltage is also above the circuit breaker limit voltage,
so the limited consecutive retry function is still operational. If
the current fault is not cleared (sense resistor voltage brought
below 79 mV) after seven consecutive faults, then the device
is latched off.
3. If a serious short circuit occurs on the load side, the –48 V
supply can cause massive currents to flow very quickly.
Because of this, the gate voltage must be reduced quickly to
prevent a catastrophic failure. If the ADM1070 detects a
voltage greater than the fast current limit voltage (126 mV)
across the sense resistor, it is apparent that a serious short
circuit is present and the load current must be reduced as
quickly as possible. The fast current limit loop takes over and
pulls gate low much faster than in the previous case.
SENSE RESISTOR
The ADM1070’s current limiting function can operate at different current levels. The sense resistor is inserted between the V
EE
and sense pins, and a current fault occurs whenever the voltage
across the sense resistor is greater than 100 mV for longer than
the on time, t
tion of the sense resistor, R
maximum allowable load current (I
mum and maximum in-rush currents (I
are related to the value of R
Table I. I
for Different Values of R
R
SENSE
. The current limit is determined by selec-
LIMITON
LOAD(MAX)
I
LOAD(MAX)
. Table I shows how the
SENSE
LOAD(MAX)
LIMIT(MIN)
.
SENSE
, I
LIMIT(MIN)
, and I
SENSE
I
LIMIT(MIN)
) and the mini-
) and I
LIMIT(MAX)
LIMIT(MAX)
I
LIMIT(MAX)
)
(m⍀) (A) (A) (A)
5 12.0 18.0 22.0
10 6.0 9.0 11.0
15 4.0 6.0 7.3
18 3.3 5.0 6.1
22 2.7 4.1 5.0
33 1.8 2.7 3.3
47 1.3 1.9 2.3
51 1.2 1.7 2.2
68 0.9 1.3 1.6
75 0.8 1.2 1.5
90 0.7 1.0 1.2
SHUNT REGULATOR
A shunt regulator shunts the ADM1070 VIN Pin. Power is
derived from the –48 V supply through the combination of an
internal Zener diode and an external shunt resistor, R
DROP
.
Table II shows the operational voltage range and power dissipation for different values of R
value for R
DROP
.
. Note that 16 kΩ is the default
DROP
Table II. Minimum and Maximum Allowable Operating
Voltages for Different Values of R
Min Allowable Max Allowable P
DROP
DROP
VDD Voltage VDD Voltage @ 48 V
R
DROP
10 kΩ (0.25 W)
(V) (V) (W)
26 61 0.13
12 kΩ 28.6 65.8 0.11
14 kΩ 31.2 70.2 0.09
16 kΩ 33.8 74.2 0.08
18 kΩ 36.4 78.1 0.07
20 kΩ 39 81.7 0.065
22 kΩ 41.6 85.2 0.06
10 kΩ (0.5 W) 26 81.7 0.13
12 kΩ 28.6 88.5 0.11
14 kΩ 31.2 94.7 0.09
16 kΩ 33.8 100.4 0.08
18 kΩ 36.4 105.9 0.07
20 kΩ 39 111 0.065
22 kΩ 41.6 115.9 0.06
INTERNAL UNDERVOLTAGE LOCKOUT
The VIN Pin is monitored for undervoltage lockout. When the
voltage at V
is above 8.5 V (V
IN
), the device is enabled. If
LKO
this voltage drops below 8.5 V, the device is disabled and gate is
pulled low. Note that this is unrelated to the undervoltage
and overvoltage functions performed at the UV/OV Pin.
TIMER
The TIMER Pin on the ADM1070 gives the user control over
the timing functions on the part. By connecting an external
capacitor between the TIMER Pin and V
UV/OV glitch filter time, t
t
, the maximum current on time, tON, the current limit time
POR
out, t
shutdown, t
, and the continuous short circuit time before latched
OFF
(see Table III). Note that all times are scaled
SHORT
, the power-on reset delay time,
FLT
, the user can set the
EE
relative to each other and cannot be altered individually (without
changing the other times). The default values for these times are
selected by tying the TIMER Pin directly to V
EE
.
Table III. Timer Capacitor Values and Timing Values
C
TIMER
t
FLT
t
PORtLIMITONtPWMOFFtSHORT
(pF) (ms) (ms) (ms) (ms) (ms)
220 0.58 0.58 4.8 150 1000
330 0.85 0.85 7.1 230 1400
470 1.21 1.21 9.9 320 2000
Tied to V
1.55 1.55 12.8 410 2600
EE
680 1.74 1.74 14.2 450 2800
1000 2.54 2.54 20.8 660 4100
2200 5.64 5.64 46.2 1465 9113
REV. 0–10–
Page 11
ADM1070
UNDERVOLTAGE/OVERVOLTAGE DETECTION
The ADM1070 incorporates single-pin overvoltage and
undervoltage detection with a programmable operating voltage
window. When
the voltage on the
UV/OV pin rises above the
OV rising threshold or falls below the UV falling threshold, a
fault signal is generated that disables the linear current regulator
and results in the GATE Pin being pulled low. The voltage fault
signal is time filtered so that faults of duration less than the UV/
OV glitch filter time, t
, do not force the gate drive low (t
FLT
FLT
is set by the choice of external capacitor CT, see Table III). The
filter operates only on
low transition on the
the “faulting” edge (i.e., on a high to
undervoltage monitor and on a low to
high transition on the overvoltage monitor). The analog comparators have some hysteresis to provide smooth switching of
the comparator inputs.
If the voltage on UV/OV goes out of range (i.e., below 0.86 V
above 1.97 V) gate is pulled low. If
or
subse
quently re-enters the operating voltage window, the
ADM1070
will
restore the gate drive.
the UV/OV voltage
The overvoltage and undervoltage thresholds are:
UV turning on = 0.91 V
UV turning off = 0.86 V
OV turning on = 1.97 V
OV turning off = 1.93 V
The undervoltage/overvoltage levels are determined by selection
of the resistor ratio R1/R2, (see Table I). These two resistors
form a resistor divider that generates the voltage; at the UV/OV
Pin, which
this ratio
is proportional to the supply voltage. By choosing
carefully, the ADM1070 can be programmed to apply
the supply voltage to the load only when it is within specific
thresholds.
For example, for R1 = 39 kΩ and R2 = 1 kΩ the
typical operating range is 36.4 V to 76.8 V. The undervoltage
overvoltage
and
for this resistor
shutdown thresholds are 34.4 V and 77.2 V
ratio. 1% resistors should be used to maintain
the accuracy of these threshold levels.
Voltage Divider:
V
= VSS(R2/(R1 + R2))
UV/OV
For R2 = 1 kΩ:
V
SS
= V
UV/OV
(R1 + 1)
And for R1 = 39 kΩ:
V
= 40 V
SS
UV/OV
Operating Range:
UV => 40(0.91) = 36.4 V
OV => 40(1.93) = 77.2 V
UV/OV Shutdown Levels:
UV => 40(0.86) = 34.4 V
OV => 40(1.97) = 78.8 V
120
100
80
60
40
OPERATING VOLTAGE – V
20
0
30 47 5133 4339
36
R1 – k⍀ (FOR R2 = 1k⍀)
+
R1
V
SS
––
+
R2
V
UV/OV
Figure 3. Voltage Divider
Resistor Ratio Undervoltage Overvoltage
R1 (for R2 = 1 k⍀)V
k⍀
30
33
36
39
43
47
51
REV. 0
Figure 4. Operating Voltage Window vs. Resistance Ratio
Ta b le IV. Resistance Ratios and Operating Voltage Windows
(Falling) VUV (Rising) VOV (Falling) VOV (Rising)
UV
V
26.7
29.2
31.8
34.4
37.8
41.3
44.7
V
28.2
31.0
33.7
36.4
40.0
43.7
46.4
V
59.8
65.6
71.4
77.2
84.9
92.6
100.4
102.4
–11–
V
61.0
67.0
72.9
78.8
86.7
94.6
Page 12
ADM1070
FUNCTIONALITY AND TIMING
Live Insertion
The timing waveforms associated with the live insertion of a
plug-in board using the ADM1070 are shown in the following
figures. When the board connects the GND-VEE potential
climbs to 48 V. As this voltage is applied, the voltage at the V
Pin ramps above the undervoltage lockout (V
) of 8.5 V to a
LKO
IN
constant 12.3 V and is held at this level with the shunt resistor
and external resistor combination at the V
IN
Pin.
When UV/OV crosses the undervoltage rising threshold of
0.91 V, it is now inside the operating voltage window and the
–48 V supply must be applied to the load. After a time delay,
t
, the ADM1070 begins to ramp up the gate drive. When the
POR
voltage on the SENSE Pin reaches 100 mV (the analog current
limit) the gate drive is held constant. When the board capacitance is fully charged, the sense voltage begins to drop below
the analog current limit voltage and the gate voltage is free to
ramp up further. The gate voltage eventually reaches its maximum value of 12.3 V (as set by V
GND-V
EE
V
UV/OV
GATE
SENSE
IN
V
LKO
).
IN
V
UVR
OVERVOLTAGE AND UNDERVOLTAGE
The waveforms for an overvoltage glitch are shown below.
When UV/OV glitches above the overvoltage rising threshold of
1.97 V, an overvoltage condition is detected and the gate voltage is pulled low. UV/OV begins to drop a back toward the
operating voltage window and the gate drive is restored when
the overvoltage falling threshold of 1.93 V is reached. Figure 7
illustrates the ADM1070’s operation in an overvoltage situation.
GATE
SENSE
V
UV/OV
T
T
CH210.00VCH1
1.00VCH3
100mV M 200s CH3 1.96V
Figure 7. Timing Waveforms Associated with an
Overvoltage Glitch
An undervoltage glitch is dealt with in a similar way. When
V
falls below the undervoltage falling threshold of 0.86 V,
UV/OV
the gate voltage is pulled low. If UO/UV subsequently rises
back above the undervoltage rising threshold of 0.91 V, then the
gate voltage is restored. Figure 8 illustrates the ADM1070’s
operation in an undervoltage situation.
V
OUT
t
POR
Figure 5. Timing Waveforms Associated with a
Live Insertion Event
SENSE
GATE
V
OUT
10.00VCH3
T
T
CH25.00VCH1
100mV M 500s CH1 2.8V
Figure 6. Start-Up Sequence
GATE
SENSE
V
UV/OV
CH210.0VCH1
1.00VCH3
100mV M 200ms
Figure 8. Timing Waveforms Associated with an
Undervoltage Glitch
REV. 0–12–
Page 13
ADM1070
GATE
SENSE
5.00V
CH2
1.00VCH3
100mV M 100ms
CH1
t
ON
t
OFF
CURRENT FAULT PLOTS
Some timing waveforms associated with current over faults are
shown in the following figures. Figure 9 shows how a current
glitch (of approximately 500 µs) is dealt with when the output is
shorted after power-up. The gate voltage is at a constant 12.3 V
before the glitch occurs. When the short circuit occurs, the
sense voltage rises sharply as the load current ramps up quickly.
When the sense voltage reaches 100 mV (V
), the ADM1070
ACL
reduces the gate voltage to stop the load current from increasing
any further. When V
drops back below V
SENSE
, the gate
ACL
voltage is increased again.
SENSE
GATE
V
OUT
CH3
10.00VCH1
20.00V
CH2
T
T
T
100mV M 500s CH2
34mV
Figure 11 shows a current fault on a wider timebase. The first
spike on the sense line represents the first current fault. The
sense voltage is allowed to ramp up to 100 mV before the gate
voltage is reduced to compensate. The gate and sense voltages
remain at these levels until the t
time has expired. A current
ON
fault is then registered and the gate voltage, and therefore the
sense voltage, are then both held low for the time period t
Note that the PWM ratio (t
) is equal to 3%. The cycle
ON/tOFF
OFF
.
then restarts and the sense voltage is free to ramp up to 100 mV
again (it will if the fault is still present). This cycle repeats itself
a total of seven times. Figure 12 shows the seven consecutive
faults occurring on an even wider timebase. If the ADM1070
detects seven consecutive current faults, the part then latches off
(after a total time t
SHORT
).
Figure 9. Timing Waveforms Associated with a
Current Glitch
The plots shown illustrate the operation of the ADM1070’s
unique limited consecutive retry function. Figure 10 highlights
what happens when a current fault occurs for more than 14 ms
(default t
fault is registered. In this case, gate is previously low and
part is being powered up into a current fault situation
when TIMER Pin tied to VEE) and a current
LIMITON
the
(shorted
load). When power is applied, gate is allowed to ramp until
sense reaches 100 mV. gate is then held constant to keep sense
at this level. After tON, the PWM cycle begins and gate is
reduced to zero.
14ms
GATE
SENSE
Figure 10. Timing Waveforms Associated with a
5.00V CH2 100mV
M 5.00s
CH1 1.4VCH1
Current Fault
Figure 11. Illustration of the PWM Ratio (tON/t
t
SHORT
GATE
SENSE
CH2
CH1
5.00V
1.00VCH3
100mV M 100ms
OFF
Figure 12. Illustration of the Limited Consecutive
Retry Function (Seven Retries and Latch Off)
)
REV. 0
–13–
Page 14
ADM1070
Figure 13 shows the behavior of ADM1070 when a temporary
current fault occurs followed by a permanent current fault.
When the first overcurrent fault occurs, the first 100 mV spike
on the sense line can be seen. During the t
time, this current
OFF
fault corrects itself. After this time period, a no fault condition is
detected and the limited consecutive counter is reset. GATE is
reasserted. When the overcurrent fault returns permanently, the
limited consecutive retry counter detects seven consecutive
faults and the part latches off.
SENSE
CH1
T
B
N
5.00VCH2100mV M 500ms
OFF
)
GATE
Figure 13. Illustration of the PWM Ratio (tON/t
In this way, the ADM1070 prevents nuisance shutdowns from
transient shorts of up to three seconds (typically), but will provide
latched shut-down protection from permanently shorted loads.
UV/OV AS ENABLE PIN
Connecting an open collector output to the UV/OV Pin means
that a TTL signal can be used to disable the part. In Figure 15,
the open collector output connects to EN. Driving the base of
the open collector device high enough to cause the UV/OV Pin
to be pulled below the undervoltage falling threshold of 0.86 V
typical will cause the pass transistor Q1 to be turned off.
0V
C
EN
R
DROP
R1
R2
V
UV/OV
TIMER
IN
GATE
SENSE
V
EE
LOAD
Q1
R
SENSE
V
OUT
ADM1070
–48V
Figure 15. UV/OV Used as Enable Input
KELVIN SENSE RESISTOR CONNECTION
When using a low value sense resistor for high current measurement, the problem of parasitic series resistance can arise. The
lead resistance can be a substantial fraction of the rated resistance, making the total resistance a function of lead length. This
problem can be avoided by using a Kelvin sense connec
This type of connection separates the current path
tion.
through
the resistor and the voltage drop across the resistor. Figure 14
shows the correct way to connect the sense resistor between the
SENSE and V
KELVIN SENSE TRACES
Pins of the ADM1070.
EE
SENSE RESISTOR
CURRENT
FLOW FROM
LOAD
SENSE V
ADM1070
CURRENT
FLOW TO –48V
BACKPLANE
EE
Figure 14. Kelvin Sensing with the ADM1070
REV. 0–14–
Page 15
OUTLINE DIMENSIONS
6-Lead Plastic Surface-Mount Package [SOT-23]
(RT-6)
Dimensions shown in millimeters
2.90 BSC
ADM1070
1.60 BSC
1.30
1.15
0.90
0.15 MAX
1.90
BSC
0.50
0.30
4 5
2.80 BSC
2
0.95 BSC
1.45 MAX
SEATING
PLANE
6
1 3
PIN 1
COMPLIANT TO JEDEC STANDARDS MO-178AB
0.22
0.08
10ⴗ
0.60
0ⴗ
0.45
0.30
REV. 0
–15–
Page 16
C02843–0–9/02(0)
–16–
PRINTED IN U.S.A.
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