Datasheet ADM1062 Datasheet (ANALOG DEVICES)

查询ADM1062供应商

Super Sequencer™ with Margining Control

FEATURES

Complete supervisory and sequencing solution for up to

10 supplies

10 supply fault detectors enable supervision of supplies to

better than 1% accuracy

5 selectable input attenuators allow supervision of

supplies up to

14.4 V on VH
6 V on VP1 to VP4

5 dual-function inputs, VX1 to VX5:

High impedance input to supply fault detector with

thresholds between 0.573 V and 1.375 V

General-purpose logic input

10 programmable output drivers, PDO1 to PDO10

Open collector with external pull-up
Push/pull output, driven to VDDCAP or VPn
Open collector with weak pull-up to VDDCAP or VPn
Internally charge-pumped high drive for use with external

N-FET (PDO1 to PDO6 only)

Sequencing engine (SE) implements state machine control of

PDO outputs

State changes conditional on input events
Enables complex control of boards
Power-up and power-down sequence control
Fault event handling
Interrupt generation on warnings
Watchdog function can be integrated in SE

Program software control of sequencing through SMBus
Complete voltage margining solution for 6 voltage rails
6 voltage output, 8-bit DACs (0.300 V to 1.551 V) allow voltage

adjustment via dc-to-dc converter trim/feedback node
12-bit ADC for readback of all supervised voltages
Internal and external temperature sensors
Reference input, REFIN, has 2 input options

Driven directly from 2.048 V (±0.25%) REFOUT pin

More accurate external reference for improved

ADC performance

Device powered by the highest of VP1 to VP4, VH for

improved redundancy
User EEPROM: 256 bytes
Industry-standard, 2-wire bus interface (SMBus)
Guaranteed PDO low with VH, VPn = 1.2 V
40-lead, 6 mm × 6 mm LFCSP and

48-lead, 7 mm × 7 mm TQFP packages

and Temperature Monitoring

ADM1062

FUNCTIONAL BLOCK DIAGRAM

V

OUT

DAC

DAC6

SDA SCL A1 A0

SMBus

INTERFACE

EEPROM

CONFIGURABLE

OUTPUT

DRIVERS

(HV CAPABLE

OF DRIVING

GATES OF

N-CHANNEL FET)

CONFIGURABLE

OUTPUT

DRIVERS

(LV CAPABLE

OF DRIVING

LOGIC SIGNALS)

VDD

ARBITRATOR

VCCP

GND

PDO1
PDO2
PDO3
PDO4
PDO5
PDO6

PDO7

PDO8

PDO9

PDO10
PDOGND
VDDCAP

REFOUTREFINDNDP REFGND

ADM1062

SEQUENCING

V

OUT

DAC

ENGINE

V

OUT

DAC

DAC5

VREF

VX1
VX2
VX3
VX4
VX5

VP1
VP2
VP3
VP4

AGND

TEMP

SENSOR

VH

INTERNAL

DIODE

MUX

CLOSED-LOOP
MARGINING SYSTEM

DUAL-

FUNCTION

INPUTS

(LOGIC INPUTS

OR

SFDs)

PROGRAMMABLE

RESET

GENERATORS

(SFDs)

V

V

OUT

OUT

DAC

DAC

DAC1

DAC2

DAC3

SAR ADC

V

OUT

DAC

12-BIT

DAC4

Figure 1.

APPLICATIONS

Central office systems
Servers/routers
Multivoltage system line cards
DSP/FPGA supply sequencing
In-circuit testing of margined supplies

GENERAL DESCRIPTION

The ADM1062 is a configurable supervisory/sequencing device
that offers a single-chip solution for supply monitoring and
sequencing in multiple supply systems. In addition to these
functions, the ADM1062 integrates a 12-bit ADC and six 8-bit
voltage output DACs. These circuits can be used to implement a
closed-loop margining system, which enables supply adjustment
by altering either the feedback node or reference of a dc-to-dc
converter using the DAC outputs.

04433-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

(continued on Page 3)

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

ADM1062

TABLE OF CONTENTS

General Description ......................................................................... 3

Fault Reporting........................................................................... 19

Specifications..................................................................................... 4

Pin Configurations and Function Descriptions ........................... 7

Absolute Maximum Ratings............................................................ 8

Thermal Characteristics .............................................................. 8

ESD Caution.................................................................................. 8

Typical Performance Characteristics ............................................. 9

Powering the ADM1062................................................................ 12

Inputs................................................................................................ 13

Supply Supervision..................................................................... 13

Programming the Supply Fault Detectors............................... 13

Input Comparator Hysteresis.................................................... 14

Input Glitch Filtering ................................................................. 14

Supply Supervision with VXn Inputs ...................................... 14

VXn Pins as Digital Inputs........................................................ 15

Outputs ............................................................................................ 16

Voltage Readback............................................................................ 20

Supply Supervision with the ADC........................................... 20

Supply Margining........................................................................... 21

Overview ..................................................................................... 21

Open-Loop Margining .............................................................. 21

Closed-Loop Supply Margining............................................... 21

Writing to the DACs .................................................................. 22

Choosing the Size of the Attenuation Resistor....................... 22

DAC Limiting and Other Safety Features............................... 22

Temperature Measurement System.............................................. 23

Remote Temperature Measurement ........................................ 23

Applications Diagram .................................................................... 25

Communicating with the ADM1062........................................... 26

Configuration Download at Power-Up................................... 26

Updating the Configuration ..................................................... 26

Supply Sequencing Through Configurable

Output Drivers............................................................................ 16

Sequencing Engine .........................................................................17

Overview...................................................................................... 17

Warnings...................................................................................... 17

SMBus Jump (Unconditional Jump)........................................ 17

Sequencing Engine Application Example............................... 18

Sequence Detector...................................................................... 19

Monitoring Fault Detector ........................................................ 19

Timeout Detector ....................................................................... 19

REVISION HISTORY

4/05—Revision 0: Initial Version

Updating the Sequencing Engine............................................. 27

Internal Registers........................................................................ 27

EEPROM ..................................................................................... 27

Serial Bus Interface..................................................................... 27

SMBus Protocols for RAM and EEPROM.............................. 29

Write Operations........................................................................ 29

Read Operations......................................................................... 31

Outline Dimensions....................................................................... 33

Ordering Guide .......................................................................... 34

Rev. 0 | Page 2 of 36

ADM1062

GENERAL DESCRIPTION

(continued from Page 1)

Supply margining can be performed with a minimum of
external components. The margining loop can be used for
in-circuit testing of a board during production (for example, to
verify the board’s functionality at −5% of nominal supplies),
or it can be used dynamically to accurately control the output
voltage of a dc-to-dc converter.

The device also provides up to 10 programmable inputs for
monitoring under, over, or out-of-window faults on up to 10
supplies. In addition, 10 programmable outputs can be used as
logic enables. Six of these programmable outputs can also provide
up to a 12 V output for driving the gate of an N-channel FET,
which can be placed in the path of a supply.

DNDP

VX1

VX2
VX3
VX4

VX5

TEMP

SENSOR

INTERNAL

DIODE

ADM1062

SAR ADC

GPI SIGNAL

CONDITIONING

GPI SIGNAL

CONDITIONING

12-BIT

Temperature measurement is possible with the ADM1062. The
device contains one internal temperature sensor and a differen­tial input for a remote thermal diode. These are measured by
the 12-bit ADC.

The logical core of the device is a sequencing engine. This state­machine-based construction provides up to 63 different states.
This design enables very flexible sequencing of the outputs,
based on the condition of the inputs.

The device is controlled via configuration data that can be
programmed into an EEPROM. The entire configuration can
be programmed using an intuitive GUI-based software package
provided by ADI.

REFOUTREFIN REFGND

VREF

SFD

SFD

SDA SCL A1 A0

CONTROLLER

SEQUENCING

ENGINE

SMBus

INTERFACE

DEVICE

CONFIGURABLE

CONFIGURABLE

EEPROM

O/P DRIVER

(HV)

O/P DRIVER

(HV)

OSC

PDO1

PDO2
PDO3
PDO4
PDO5

PDO6

VP1

VP2
VP3
VP4

VH

AGND

VDDCAP

SELECTABLE
ATTENUATOR

SELECTABLE
ATTENUATOR

VDD

ARBITRATOR

SFD

SFD

REG 5.25V

CHARGE PUMP

GND DAC2 DAC3 DAC4 DAC5

VCCP

V

OUT

DAC

DAC1

CONFIGURABLE

O/P DRIVER

(LV)

CONFIGURABLE

O/P DRIVER

(LV)

V

OUT

DAC

DAC6

PDO7

PDO8
PDO9

PDO10

PDOGND

04433-002

Figure 2. Detailed Block Diagram

Rev. 0 | Page 3 of 36

ADM1062

SPECIFICATIONS

VH = 3.0 V to 14.4 V1, VPn = 3.0 V to 6.0 V1, TA = −40°C to +85°C, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

POWER SUPPLY ARBITRATION

VH, VPn 3.0 V Minimum supply required on one of VH, VPn.
VP 6.0 V Maximum VDDCAP = 5.1 V, typical.
VH 14.4 V VDDCAP = 4.75 V.
VDDCAP 2.7 4.75 5.4 V Regulated LDO output.
C

10 µF Minimum recommended decoupling capacitance.

VDDCAP

POWER SUPPLY

Supply Current, IVH, I

Additional Currents

All PDO FET Drivers On 1 mA

Current Available from VDDCAP 2 mA

DACs Supply Current 2.2 mA Six DACs on with 100 µA maximum load on each.
ADC Supply Current 1 mA Running round-robin loop.
EEPROM Erase Current 10 mA 1 ms duration only, VDDCAP = 3 V.

SUPPLY FAULT DETECTORS

VH Pin

Input Attenuator Error ±0.05 % Midrange and high range.
Detection Ranges

High Range 6 14.4 V
Midrange 2.5 6 V

VPn Pins

Input Attenuator Error ±0.05 % Low range and midrange.
Detection Ranges

Midrange 2.5 6 V
Low Range 1.25 3 V
Ultralow Range 0.573 1.375 V No input attenuation error.

VXn Pins

Input Impedance 1 MΩ
Detection Range

Ultralow Range 0.573 1.375 V No input attenuation error.

Absolute Accuracy ±1 %

Threshold Resolution 8 Bits
Digital Glitch Filter 0 µs Minimum programmable filter length.
100 µs Maximum programmable filter length.

ANALOG-TO-DIGITAL CONVERTER

Signal Range 0 V

Input Reference Voltage on REFIN Pin, V
Resolution 12 Bits
INL ±2.5 LSB Endpoint corrected, V
Gain Error ±0.05 % V

4.2 6 mA

VPn

VDDCAP = 4.75 V, PDO1 to PDO10 off, DACs off,
ADC off.

VDDCAP = 4.75 V, PDO1 to PDO6 loaded with 1 µA
each, PDO7 to PDO10 off.

Maximum additional load that can be drawn from
all PDO pull-ups to VDDCAP.

VREF error + DAC nonlinearity + comparator offset
error + input attenuation error.

V

REFIN

The ADC can convert signals presented to the VH,
VPn, and VXn pins. VPn and VH input signals are
attenuated depending on selected range. A signal
at the pin corresponding to the selected range is
from 0.573 V to 1.375 V at the ADC input.

2.048 V

REFIN

= 2.048 V.

REFIN

= 2.048 V.

REFIN

Rev. 0 | Page 4 of 36

ADM1062

Parameter Min Typ Max Unit Test Conditions/Comments

Conversion Time 0.44 ms One conversion on one channel
84 ms All 12 channels selected, 16x averaging enabled
Offset Error ±2 LSB V
Input Noise 0.25 LSB

Direct input (no attenuator)

rms

TEMPERATURE SENSOR2

Local Sensor Accuracy ±3 °C VDDCAP = 4.75 V
Local Sensor Supply Voltage Coefficient −1.7 °C/V
Remote Sensor Accuracy ±3 °C VDDCAP = 4.75 V
Remote Sensor Supply Voltage Coefficient −3 °C
Remote Sensor Current Source 200 µA High level
12 µA Low level
Temperature for Code 0x800 0 °C VDDCAP = 4.75 V
Temperature for Code 0xC00 128 °C VDDCAP = 4.75 V
Temperature Resolution per Code 0.125 °C

BUFFERED VOLTAGE OUTPUT DACs

Resolution 8 Bits
Code 0x80 Output Voltage

Range 1 0.592 0.6 0.603 V
Range 2 0.796 0.8 0.803 V
Range 3 0.996 1 1.003 V

Range 4 1.246 1.25 1.253 V
Output Voltage Range 601.25 mV Same range, independent of center point
LSB Step Size 2.36 mV
INL ±0.75 LSB Endpoint corrected
DNL ±0.4 LSB
Gain Error 1 %
Load Regulation −4 mV Sourcing current, I
2 mV Sinking current, I
Maximum Load Capacitance 50 pF
Settling Time to 50 pF Load 2 µs
Load Regulation 2.5 mV Per mA
PSRR 60 dB DC

40 dB 100 mV step in 20 ns with 50 pF load
REFERENCE OUTPUT

Reference Output Voltage 2.043 2.048 2.053 V No load
Load Regulation −0.25 mV Sourcing current, I

0.25 mV Sinking current, I
Minimum Load Capacitance 1 µF Capacitor required for decoupling, stability
Load Regulation 2 mV Per 100 µA
PSRR 60 dB DC

PROGRAMMABLE DRIVER OUTPUTS

High Voltage (Charge-Pump) Mode

(PDO1 to PDO6)

Output Impedance 500 kΩ

VOH 11 12.5 14 V IOH = 0

10.5 12 13.5 V IOH = 1 µA

I

20 µA 2 V < V

OUTAVG

= 2.048 V

REFIN

Six DACs are individually selectable for centering
on one of four output voltage ranges

= −200 µA

REFOUTMAX

= 100 µA

REFOUTMAX

= −100 µA

DACnMAX

= 100 µA

DACnMAX

< 7 V

OH

Rev. 0 | Page 5 of 36

ADM1062

Parameter Min Typ Max Unit Test Conditions/Comments

Standard (Digital Output) Mode

(PDO1 to PDO10)
VOH 2.4 V VPU (pull-up to VDDCAP or VPn) = 2.7 V, IOH = 0.5 mA

4.5 V VPU to VPn = 6.0 V, IOH = 0 mA
V

VOL 0 0.50 V IOL = 20 mA

3

I

20 mA Maximum sink current per PDO pin

OL

3

I

60 mA Maximum total sink for all PDO pins

SINK

R

20 kΩ Internal pull-up

PULL-UP

I

(VPn)3 2 mA

SOURCE

Three-State Output Leakage Current 10 µA V
Oscillator Frequency 90 100 110 kHz All on-chip time delays derived from this clock

DIGITAL INPUTS (VXn, A0, A1)

Input High Voltage, VIH 2.0 V Maximum VIN = 5.5 V
Input Low Voltage, VIL 0.8 V Maximum VIN = 5.5 V
Input High Current, IIH −1 µA VIN = 5.5 V
Input Low Current, IIL 1 µA VIN = 0
Input Capacitance 5 pF
Programmable Pull-Down Current,

PULL-DOWN

I

SERIAL BUS DIGITAL INPUTS (SDA, SCL)

Input High Voltage, VIH 2.0 V
Input Low Voltage, VIL 0.8 V
Output Low Voltage, V

3

0.4 V I

OL

SERIAL BUS TIMING

Clock Frequency, f
Bus Free Time, t
Start Setup Time, t
Start Hold Time, t
SCL Low Time, t
SCL High Time, t

400 kHz

SCLK

4.7 µs

BUF

4.7 µs

SU;STA

4 µs

HD;STA

4.7 µs

LOW

4 µs

HIGH

SCL, SDA Rise Time, tr 1000 µs
SCL, SDA Fall Time, tf 300 µs
Data Setup Time, t
Data Hold Time, t

250 ns

SU;DAT

5 ns

HD;DAT

Input Low Current, IIL 1 µA VIN = 0

SEQUENCING ENGINE TIMING

State Change Time 10 µs

1

At least one of the VH, VP1 to VP4 pins must be ≥3.0 V to maintain the device supply on VDDCAP.

2

All temperature sensor measurements are taken with round-robin loop enabled and at least one other voltage input being measured.

3

Specification is not production tested, but is supported by characterization data at initial product release.

− 0.3 V VPU ≤ 2.7 V, IOH = 0.5 mA

PU

Current load on any VPn pull-ups, that is, total
source current available through any number of
PDO pull-up switches configured onto any one

= 14.4 V

PDO

20 µA

VDDCAP = 4.75, T
required

= −3.0 mA

OUT

= 25°C if known logic state is

A

Rev. 0 | Page 6 of 36

ADM1062

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

NC48GND47VDDCAP46DP45DN44SDA43SCL42A141A040VCCP39PDOGND38NC

VH

GND40VDDCAP39DP38DN37SDA36SCL35A134A033VCCP32PDOGND

X1

1

PIN 1
INDICATOR

2

X2

3

X3
X4

4

X5

5

P1

6
7

P2

8

P3
P4

9

10

11

AGND

12

REFGND

ADM1062

TOP VIEW

(Not to Scale)

13

14

DAC115DAC216DAC317DAC418DAC519DAC6

REFIN

REFOUT

Figure 3. LFCSP Pin Configuration

31

PDO1

30
29

PDO2

28

PDO3
PDO4

27

PDO5

26

PDO6

25
24

PDO7

23

PDO8
PDO9

22

PDO10

21

20

04433-003

NC

1

X1
X2
X3
X4
X5
P1
P2
P3

P4
VH
NC

NC = NO CONNECT

PIN 1

2

INDICATOR
3
4
5
6
7
8
9

10
11
12

13

14

NC

AGND

Figure 4. TQFP Pin Configuration

15

REFGND

ADM1062

TOP VIEW

(Not to Scale)

16

17

DAC118DAC219DAC320DAC421DAC522DAC6

REFIN

REFOUT

Table 2. Pin Function Descriptions

Pin No.

LFCSP TQFP

1, 12,

Mnemonic Description

NC No Connection.
13, 24,
25, 36,
37, 48

1 to 5 2 to 6 VX1 to VX5

High Impedance Inputs to Supply Fault Detectors. Fault thresholds can be set from 0.573 V to 1.375 V.
Alternatively, these pins can be used as general-purpose digital inputs.

6 to 9 7 to 10 VP1 to VP4

Low Voltage Inputs to Supply Fault Detectors. Three input ranges can be set by altering the input
attenuation on a potential divider connected to these pins, the output of which connects to a supply
fault detector. These pins allow thresholds from 2.5 V to 6.0 V, 1.25 V to 3.00 V, and 0.573 V to 1.375 V.

10 11 VH

High Voltage Input to Supply Fault Detectors. Two input ranges can be set by altering the input
attenuation on a potential divider connected to this pin, the output of which connects to a supply

fault detector. This pin allows thresholds from 6.0 V to 14.4 V and 2.5 V to 6.0 V.
11 14 AGND Ground Return for Input Attenuators.
12 15 REFGND Ground Return for On-Chip Reference Circuits.
13 16 REFIN Reference Input for ADC. Nominally, 2.048 V.
14 17 REFOUT Reference Output, 2.048 V.
15 to 20 18 to 23 DAC1 to DAC6 Voltage Output DACs. These pins default to high impedance at power-up.
21 to 30 26 to 35 PDO10 to PDO1 Programmable Output Drivers.
31 38 PDOGND Ground Return for Output Drivers.
32 39 VCCP

Central Charge-Pump Voltage of 5.25 V. A reservoir capacitor must be connected between this pin

and GND.
33 40 A0 Logic Input. This pin sets the seventh bit of the SMBus interface address.
34 41 A1 Logic Input. This pin sets the sixth bit of the SMBus interface address.
35 42 SCL SMBus Clock Pin. Open-drain output requires external resistive pull-up.
36 43 SDA SMBus Data I/O Pin. Open-drain output requires external resistive pull-up.
37 44 DN External Temperature Sensor Cathode Connection.
38 45 DP External Temperature Sensor Anode Connection.
39 46 VDDCAP

Device Supply Voltage. Linearly regulated from the highest voltage on the VP1 to VP4 and VH pins

to a typical voltage of 4.75 V.
40 47 GND Ground Supply.

23NC24

37

NC

36

PDO1

35

PDO2

34

PDO3

33
32

PDO4

31

PDO5

30

PDO6

29

PDO7

28

PDO8

27

PDO9

26

PDO10
NC

25

04433-004

Rev. 0 | Page 7 of 36

ADM1062

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Voltage on VH Pin 16 V
Voltage on VP Pins 7 V
Voltage on VX Pins −0.3 V to +6.5 V
Voltage on D1N, D1P, and REFIN Pins −0.3 V to +5 V
Input Current at Any Pin ±5 mA
Package Input Current ±20 mA
Maximum Junction Temperature (TJ max) 150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature, Soldering

Vapor Phase, 60 sec 215°C

ESD Rating, All Pins 2000 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL CHARACTERISTICS

40-lead LFCSP package: θJA = 25°C/W.

48-lead TQFP package: θ

= 14.8°C/W.

JA

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 8 of 36

ADM1062

TYPICAL PERFORMANCE CHARACTERISTICS

(V)

VDDCAP

V

6

5

4

3

2

1

0

0654321

Figure 5. V

V

VP1

VDDCAP

(V)

vs. V

04609-050

VP1

180

160

140

120

100

(µA)

80

VP1

I

60

40

20

0

0123456

Figure 8. I

V

(V)

VP1

vs. V

VP1

(VP1 Not as Supply)

VP1

04609-053

6

5

4

(V)

3

VDDCAP

V

2

1

0

0161412108642

Figure 6. V

5.0

4.5

4.0

3.5

3.0

2.5

(mA)

VP1

I

2.0

1.5

1.0

0.5

0

0123456

Figure 7. I

VVH (V)

vs. VVH

VDDCAP

V

(V)

VP1

vs. V

VP1

(VP1 as Supply)

VP1

04609-051

04609-052

(mA)

VH

I

350

300

250

200

(µA)

VH

150

I

100

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

0161412108642

50

0

0654321

Figure 9. I

Figure 10. I

VVH (V)

vs. VVH (VH as Supply)

VH

VVH (V)

vs. V

(VH Not as Supply)

VH

VH

04609-054

04609-055

Rev. 0 | Page 9 of 36

ADM1062

14

12

(V)

10

PDO1

8

6

4

CHARGE-PUMPED V

2

0

0 15.012.510.07.55.02.5

Figure 11. Charge-Pumped V

I

(µA)

LOAD

(FET Drive Mode) vs. I

PDO1

LOAD

1.0

0.8

0.6

0.4

0.2

0

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

04433-056

–1.0

CODE

Figure 14. DNL for ADC

04609-066

40001000 2000 30000

5.0

4.5

4.0

3.5

3.0

(V)

2.5

PDO1

V

2.0

1.5

1.0

0.5

4.5

4.0

3.5

3.0

2.5

(V)

2.0

PDO1

V

1.5

1.0

0.5

0

0654321

Figure 12. V

0

0605040302010

Figure 13. V

VP1 = 3V

I

(mA)

LOAD

(Strong Pull-Up to VP) vs. I

PDO1

VP1 = 5V

VP1 = 3V

I

(µA)

LOAD

(Weak Pull-Up to VP) vs. I

PDO1

VP1 = 5V

LOAD

LOAD

04609-057

04609-058

1.0

0.8

0.6

0.4

0.2

0

INL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 4000300020001000

CODE

Figure 15. INL for ADC

12000

10000

8000

6000

HITS PER CODE

4000

2000

0

25

9894

CODE

Figure 16. ADC Noise, Midcode Input, 10,000 Reads

04609-063

81

204920482047

04609-064

Rev. 0 | Page 10 of 36

ADM1062

1.005

1.004

1.003

1.002

DAC

20kΩ
BUFFER
OUTPUT

47pF

1

CH1 200mV M1.00µs CH1 756mV

Figure 17. Transient Response of DAC Code Change into Typical Load

DAC
BUFFER
OUTPUT

PROBE
POINT

100kΩ

PROBE
POINT

1.001

1.000

0.999

DAC OUTPUT

0.998

0.997

0.996

0.995

04609-059

–40 –20 0 20 40 60 10080

VP1 = 4.75V

TEMPERATURE (°C)

Figure 19. DAC Output vs. Temperature

2.058

2.053

2.048

1V

REFOUT (V)

2.043

VP1 = 3.0V

04609-065

VP1 = 3.0V

VP1 = 4.75V

1

CH1 200mV M1.00µs CH1 944mV

Figure 18. Transient Response of DAC to Turn-On from HI-Z State

2.038

04609-060

–40 –20 0 20 40 60 10080

TEMPERATURE (°C)

04609-061

Figure 20. REFOUT vs. Temperature

Rev. 0 | Page 11 of 36

ADM1062

POWERING THE ADM1062

The ADM1062 is powered from the highest voltage input on
either the positive-only supply inputs (VPn) or the high voltage
supply input (VH). This technique offers improved redundancy,
because the device is not dependent on any particular voltage
rail to keep it operational. The same pins are used for supply
fault detection (discussed in the Programming the Supply Fault
Detectors section). A V
which supply to use. The arbitrator can be considered an OR’ing
of five LDOs together.
A supply comparator determines which of the inputs is highest
and selects it to provide the on-chip supply. There is minimal
switching loss with this architecture (~0.2 V), resulting in the
ability to power the ADM1062 from a supply as low as 3.0 V.
Note that the supply on the VXn pins cannot be used to power
the device.

An external capacitor to GND is required to decouple the on-chip
supply from noise. This capacitor should be connected to the
VDDCAP pin, as shown in Figure 21. The capacitor has another
use during brownouts (momentary loss of power). Under these
conditions, when the input supply (VPn or VH) dips transiently
below V

, the synchronous rectifier switch immediately turns

DD

off so that it does not pull V
act as a reservoir to keep the device active until the next highest
supply takes over the powering of the device. For this reservoir/
decoupling function, 10 µF is recommended.

arbitrator on the device chooses

DD

down. The VDDCAP can then

DD

VP1

VP2

VP3

VP4

VH

SUPPLY

COMPARATOR

Figure 21. V

INENOUT

4.75V
LDO

INENOUT

4.75V
LDO

INENOUT

4.75V
LDO

INENOUT

4.75V
LDO

INENOUT

4.75V
LDO

Arbitrator Operation

DD

VDDCAP

INTERNAL
DEVICE
SUPPLY

4609-022

Note that when two or more supplies are within 100 mV of each
other, the supply that takes control of V
For example, if VP1 is connected to a 3.3 V supply, then V

first keeps control.

DD

DD

powers up to approximately 3.1 V through VP1. If VP2 is then
connected to another 3.3 V supply, VP1 still powers the device,
unless VP2 goes 100 mV higher than VP1.

Rev. 0 | Page 12 of 36

ADM1062

E

INPUTS

SUPPLY SUPERVISION

The ADM1062 has 10 programmable inputs. Five of these are
dedicated supply fault detectors (SFDs). These dedicated inputs
are called VH and VP1 to VP4 by default. The other five inputs
are labeled VX1 to VX5 and have dual functionality. They can
be used as either SFDs with similar functionality to VH and
VP1 to VP4, or CMOS-/TTL-compatible logic inputs to the
devices. Therefore, the ADM1062 can have up to 10 analog
inputs, a minimum of five analog inputs and five digital inputs,
or a combination. If an input is used as an analog input, it
cannot be used as a digital input. Therefore, a configuration
requiring 10 analog inputs has no digital inputs available.
Table 5 shows the details of each of the inputs.

RANG

SELECT

VPn

ULTRA

LOW

LOW

MID

VREF

Figure 22. Supply Fault Detector Block

COMPARATOR

+

–

+

–

COMPARATOR

OV

GLITCH

FILTER

UV

FAULT TYPE

SELECT

FAULT
OUTPUT

PROGRAMMING THE SUPPLY FAULT DETECTORS

The ADM1062 can have up to 10 SFDs on its 10 input
channels. These highly programmable reset generators enable
the supervision of up to 10 supply voltages. The supplies can be
as low as 0.573 V and as high as 14.4 V. The inputs can be
configured to detect an undervoltage fault (the input voltage
drops below a preprogrammed value), an overvoltage fault (the
input voltage rises above a preprogrammed value), or an out-of­window fault (an undervoltage or overvoltage). The thresholds
can be programmed to an 8-bit resolution in registers provided
in the ADM1062. This translates to a voltage resolution that is
dependent on the range selected.

04609-023

The resolution is given by

Step Size = Threshold Range/255

Therefore, if the high range is selected on VH, the step size can
be calculated as follows:

(14.4 V − 4.8 V)/255 = 37.6 mV

Table 4 lists the upper and lower limits of each available range,
the bottom of each range (V

), and the range itself (VR).

B

Table 4. Voltage Range Limits

Voltage Range (V) VB (V) VR (V)

0.573 to 1.375 0.573 0.802

1.25 to 3.00 1.25 1.75

2.5 to 6.0 2.5 3.5

4.8 to 14.4 4.8 9.6

The threshold value required is given by

= (VR × N)/255 + VB

V

T

where:

is the desired threshold voltage (UV or OV).

V

T

is the voltage range.

V

R

N is the decimal value of the 8-bit code.

is the bottom of the range.

V

B

Reversing the equation, the code for a desired threshold is given by

N = 255 × (V

− VB)/VR

T

For example, if the user wants to set a 5 V OV threshold on
VP1, the code to be programmed in the PS1OVTH register
(discussed in the AN-698 application note) is given by

N = 255 × (5 − 2.5)/3.5

Therefore, N = 182 (1011 0110 or 0xB6).

Table 5. Input Functions, Thresholds, and Ranges

Input Function Voltage Range (V) Maximum Hysteresis Voltage Resolution (mV) Glitch Filter (µs)

VH High V analog input 2.5 to 6.0 425 mV 13.7 0 to 100

4.8 to 14.4 1.16 V 37.6 0 to 100
VPn Positive analog input 0.573 to 1.375 97.5 mV 3.14 0 to 100

1.25 to 3.00 212 mV 6.8 0 to 100

2.5 to 6.0 425 mV 13.7 0 to 100
VXn High Z analog input 0.573 to 1.375 97.5 mV 3.14 0 to 100
Digital input 0 to 5 N/A N/A 0 to 100

Rev. 0 | Page 13 of 36

ADM1062

T

T

INPUT COMPARATOR HYSTERESIS

The UV and OV comparators shown in Figure 22 are always
looking at VPn. To avoid chattering (multiple transitions when
the input is very close to the set threshold level), these compara­tors have digitally programmable hysteresis. The hysteresis can
be programmed up to the values shown in Table 5.

The hysteresis is added after a supply voltage goes out of
tolerance. Therefore, the user can program the amount above
the UV threshold that the input must rise to before a UV fault is
deasserted. Similarly, the user can program the amount below
the OV threshold that an input must fall to before an OV fault
is deasserted.

The hysteresis figure is given by

V

HYST

= VR × N

THRESH

/255

where:

is the desired hysteresis voltage.

V

HYST

N

is the decimal value of the 5-bit hysteresis code.

THRESH

Note that N

has a maximum value of 31. The maximum

THRESH

hysteresis for the ranges is listed in Table 5.

INPUT GLITCH FILTERING

The final stage of the SFDs is a glitch filter. This block provides
time-domain filtering on the output of the SFD comparators.
This allows the user to remove any spurious transitions, such as
supply bounce at turn-on. The glitch filter function is additional
to the digitally programmable hysteresis of the SFD comparators.
The glitch filter timeout is programmable up to 100 µs.

For example, when the glitch filter timeout is 100 µs, any pulse
appearing on the input of the glitch filter block that is less than
100 µs in duration is prevented from appearing on the output of
the glitch filter block. Any input pulse that is longer than 100 µs
does appear on the output of the glitch filter block. The output
is delayed with respect to the input by 100 µs. The filtering
process is shown in Figure 23.

INPUT PULSE SHORTER

THAN GLITCH FILTER TIMEOUT

PROGRAMMED

TIMEOUT

INPUT

0

0

T

GF

OUTPUT

T

GF

Figure 23. Input Glitch Filter Function

INPUT PULSE LONGER

THAN GLITCH FILTER TIMEOUT

PROGRAMMED

TIMEOUT

INPUT

T

T

T

0

0

T

GF

OUTPUT

GF

04609-024

SUPPLY SUPERVISION WITH VXn INPUTS

The VXn inputs have two functions. They can be used as either
supply fault detectors or digital logic inputs. When selected as an
analog (SFD) input, the VXn pins function similarly to the VH
and VPn pins. The primary difference is that the VXn pins have
only one input range: 0.573 V to 1.375 V. Therefore, these inputs
can directly supervise only the very low supplies. However, the
input impedance of the VXn pins is high, allowing an external
resistor divide network to be connected to the pin. Thus,
potentially any supply can be divided down into the input range
of the VXn pin and supervised. This enables the ADM1062 to
monitor other supplies such as +24 V, +48 V, and −5 V.

An additional supply supervision function is available when the
VXn pins are selected as digital inputs. In this case, the analog
function is available as a second detector on each of the dedi­cated analog inputs, VP1 to VP4 and VH. The analog function
of VX1 is mapped to VP1, VX2 is mapped to VP2, and so on;
VX5 is mapped to VH. In this case, these SFDs can be viewed as
a secondary or warning SFD.

The secondary SFDs are fixed to the same input range as the
primary SFD. They are used to indicate warning levels rather
than failure levels. This allows faults and warnings to be gener­ated on a single supply using only one pin. For example, if VP1
is set to output a fault when a 3.3 V supply drops to 3.0 V, VX1
can be set to output a warning at 3.1 V. Warning outputs are
available for readback from the status registers. They are also
OR’ed together and fed into the SE, allowing warnings to generate
interrupts on the PDOs. Therefore, in the previous example, if
the supply drops to 3.1 V, a warning is generated and remedial
action can be taken before the supply drops out of tolerance.

Rev. 0 | Page 14 of 36

ADM1062

VXn PINS AS DIGITAL INPUTS

As discussed in the Supply Supervision with VXn Inputs
section, the VXn input pins on the ADM1062 have dual
functionality. The second function is as a digital input to the
device. Therefore, the ADM1062 can be configured for up to five
digital inputs. These inputs are TTL-/CMOS-compatible.
Standard logic signals can be applied to the pins: RESET from
reset generators, POWER_GOOD signals, fault flags, manual
resets, and so on. These signals are available as inputs to the SE
and, therefore, can be used to control the status of the PDOs. The
inputs can be configured to detect either a change in level or
an edge.

When configured for level detection, the output of the digital
block is a buffered version of the input. When configured for
edge detection, a pulse of programmable width is output from
the digital block once the logic transition is detected. The width
is programmable from 0 µs to 100 µs.

The digital blocks feature the same glitch filter function that is
available on the SFDs. This enables the user to ignore spurious
transitions on the inputs. For example, the filter can be used to
debounce a manual reset switch.

When configured as digital inputs, each of the VXn pins has a
weak (10 µA) pull-down current source available for placing the
input into a known condition, even if left floating. The current
source, if selected, weakly pulls the input to GND.

(DIGITAL INPUT)

VXn

+

DETECTOR

–

VREF = 1.4V

Figure 24. VXn Digital Input Function

GLITCH

FILTER

TO
SEQUENCING
ENGINE

04609-027

Rev. 0 | Page 15 of 36

ADM1062

S

A

V

OUTPUTS

SUPPLY SEQUENCING THROUGH
CONFIGURABLE OUTPUT DRIVERS

Supply sequencing is achieved with the ADM1062 using the
programmable driver outputs (PDOs) on the device as control
signals for supplies. The output drivers can be used as logic
enables or as FET drivers.

The sequence in which the PDOs are asserted (and, therefore,
the supplies are turned on) is controlled by the sequencing
engine (SE). The SE determines what action is taken with the
PDOs based on the condition of the inputs of the ADM1062.
Therefore, the PDOs can be set up to assert when the SFDs are
in tolerance, the correct input signals are received on the VXn
digital pins, no warnings are received from any of the inputs of
the device, and so on. The PDOs can be used for a variety of
functions. The primary function is to provide enable signals for
LDOs or dc-to-dc converters, which generate supplies locally on
a board. The PDOs can also be used to provide a
POWER_GOOD signal when all the SFDs are in tolerance, or a
RESET output if one of the SFDs goes out of specification (this
can be used as a status signal for a DSP, FPGA, or other
microcontroller).

The PDOs can be programmed to pull up to a number of
different options. The outputs can be programmed as follows:

• Open-drain (allowing the user to connect an external pull-

up resistor)

• Open-drain with weak pull-up to V

• Push/pull to V

DD

• Open-drain with weak pull-up to VPn

• Push/pull to VPn

• Strong pull-down to GND

• Internally charge-pumped high drive (12 V, PDO1 to

PDO6 only)

The last option (available only on PDO1 to PDO6) allows the
user to directly drive a voltage high enough to fully enhance an

DD

CFG4 CFG5 CFG6

SEL

external N-channel FET, which is used to isolate, for example, a
card-side voltage from a backplane supply (a PDO can sustain
greater than 10.5 V into a 1 µA load). The pull-down switches
can also be used to drive status LEDs directly.

The data driving each of the PDOs can come from one of three
sources. The source can be enabled in the PDOnCFG con­figuration register (see the AN-698 application note for details).

The data sources are as follows:

• Output from the SE.

• Directly from the SMBus. A PDO can be configured so that

the SMBus has direct control over it. This enables software
control of the PDOs. Therefore, a microcontroller can be
used to initiate a software power-up/power-down sequence.

• On-Chip Clock. A 100 kHz clock is generated on the

device. This clock can be made available on any of the
PDOs. It can be used, for example, to clock an external
device such as an LED.

By default, the PDOs are pulled to GND by a weak (20 kΩ) on­chip, pull-down resistor. This is the case upon power-up until
the configuration is downloaded from EEPROM and the
programmed setup is latched. The outputs are actively pulled
low once a supply of 1 V or greater is on VPn or VH. The
outputs remain high impedance prior to 1 V appearing on VPn
or VH. This provides a known condition for the PDOs during
power-up. The internal pull-down can be overdriven with an
external pull-up of suitable value tied from the PDO pin to the
required pull-up voltage. The 20 kΩ resistor must be accounted
for in calculating a suitable value. For example, if PDOn must be
pulled up to 3.3 V and 5 V is available as an external supply, the
pull-up resistor value is given by

3.3 V = 5 V × 20 kΩ/(R

+ 20 kΩ)

UP

Therefore,

= (100 kΩ − 66 kΩ)/3.3 = 10 kΩ

R

UP

FET (PDO1 TO PDO6 ONLY)

V

DD

VP1

VP4

10Ω

20kΩ

SE DATA

MBus DAT

CLK DATA

Figure 25. Programmable Driver Output

Rev. 0 | Page 16 of 36

10Ω

10Ω

20kΩ

20kΩ

PDO

20kΩ

04433-028

ADM1062

SEQUENCING ENGINE

OVERVIEW

The ADM1062 sequencing engine (SE) provides the user with
powerful and flexible control of sequencing. The SE implements
a state machine control of the PDO outputs, with state changes
conditional on input events. SE programs can enable complex
control of boards such as power-up and power-down sequence
control, fault event handling, interrupt generation on warnings,
and so on. A watchdog function that verifies the continued
operation of a processor clock can be integrated into the SE
program. The SE can also be controlled via the SMBus, giving
software or firmware control of the board sequencing.

The SE state machine comprises 63 state cells. Each state has the
following attributes:

• Monitors signals indicating the status of the 10 input pins,

VP1 to VP4, VH, and VX1 to VX5.

• Can be entered from any other state.

• Three exit routes move the state machine onto a next state:

sequence detection, fault monitoring, and timeout.

• Delay timers for the sequence and timeout blocks can be

programmed independently and changed with each state
change. The range of timeouts is from 0 ms to 400 ms.

• Output condition of the 10 PDO pins is defined and fixed

within a state.

The ADM1062 offers up to 63 state definitions. The signals
monitored to indicate the status of the input pins are the
outputs of the SFDs.

WARNINGS

The SE also monitors warnings. These warnings can be
generated when the ADC readings violate their limit register
value or when the secondary voltage monitors detect a warning
on VP1 to VP4 and VH. The warnings are OR’ed together and
available as a single warning input to each of the three blocks
that enable exiting a state.

SMBus JUMP (UNCONDITIONAL JUMP)

The SE can be forced to advance to the next state uncondition­ally. This enables the user to force the SE to advance. Examples
of where this might be used include moving to a margining
state or debugging a sequence. The SMBus jump or go-to
command can be seen as another input to sequence and
timeout blocks, which provide an exit from each state.

MONITOR

FAULT

STATE

SEQUENCE

Figure 26. State Cell

TIMEOUT

04609-029

• Transition from one state to the next is made in less than

20 µs, which is the time needed to download a state definition
from EEPROM to the SE.

Table 6. Sample Sequence State Entries

State Sequence Timeout Monitor

IDLE1 If VX1 is low , go to state IDLE2.
IDLE2 If VP1 is okay, go to state EN3V3.
EN3V3 If VP2 is okay, go to state EN2V5.

DIS3V3 If VX1 is high, go to state IDLE1.
EN2V5 If VP3 is okay, go to state PWRGD.

DIS2V5 If VX1 is high, go to state IDLE1.
FSEL1 If VP3 is not okay, go to state DIS2V5. If VP1 or VP2 is not okay, go to state FSEL2.
FSEL2 If VP2 is not okay, go to state DIS3V3. If VP1 is not okay, go to state IDLE1.
PWRGD If VX1 is high, go to state DIS2V5. If VP1, VP2, or VP3 is not okay, go to state FSEL1.

If VP2 is not okay after 10 ms, go to
state DIS3V3.

If VP3 is not okay after 20 ms, go to
state DIS2V5.

If VP1 is not okay, go to state IDLE1.

If VP1 or VP2 is not okay, go to state FSEL2.

Rev. 0 | Page 17 of 36

ADM1062

SEQUENCING ENGINE APPLICATION EXAMPLE

The application in this section demonstrates the operation of
the SE. Figure 27 shows how the simple building block of a
single SE state can be used to build a power-up sequence for a
3-supply system.

Table 7 lists the PDO outputs for each state in the same SE
implementation. In this system, the triggers required to start a
power-up sequence are the presence of a good 5 V supply on VP1
and the VX1 pin held low. The sequence intends to turn on the

3.3 V supply next, then the 2.5 V supply (assuming successful
turn-on of the 3.3 V supply). Once all three supplies are good,
the POWER_GOOD state is entered, where the SE remains until
a fault occurs on one of the three supplies, or until it is instructed
to go through a power-down sequence by VX1 going high.

Faults are dealt with throughout the power-up sequence on a
case-by-case basis. The following sections, which describe the
individual blocks, use this sample application to demonstrate
the state machine’s actions.

VP1 = 0

MONITOR FAULT

STATES

(VP1 + VP2) = 0

(VP1 + VP2 + VP3) = 0

FSEL1

(VP1 +

VP2) = 0

FSEL2

VP2 = 0

VP1 = 0

VP3 = 0

SEQUENCE

STATES

IDLE1

VX1 = 0

IDLE2

VP1 = 1

EN3V3

VP2 = 1

EN2V5

VP3 = 1

VX1 = 1

10ms

20ms

VP2 = 0

TIMEOUT

STATES

DIS3V3

DIS2V5PWRGD

VX1 = 1

VX1 = 1

04609-030

Figure 27. Sample Application Flow Diagram

Table 7. PDO Outputs for Each State

PDO Outputs IDLE1 IDLE2 EN3V3 EN2V5 DIS3V3 DIS2V5 PWRGD FSEL1 FSEL2

PDO1 = 3V3ON 0 0 1 1 0 1 1 1 1
PDO2 = 2V5ON 0 0 0 1 1 0 1 1 1
PDO3 = FAULT 0 0 0 0 1 1 0 1 1

Rev. 0 | Page 18 of 36

ADM1062

VP1V

SEQUENCE DETECTOR

The sequence detector block is used to detect when a step in a
sequence has been completed. It looks for one of the inputs to
the SE to change state and is most often used as the gate for
successful progress through a power-up or power-down
sequence. A timer block is included in this detector, which can
insert delays into a power-up or power-down sequence if
required. Timer delays can be set from 10 µs to 400 ms.
Figure 28 is a block diagram of the sequence detector.

VP1

VX5

SUPPLY FAULT

DETECTION

LOGIC INPUT CHANGE
OR FAULT DETECTION

WARNINGS

FORCE FLOW

(UNCONDITIONAL JUMP)

Figure 28. Sequence Detector Block Diagram

INVERT

SELECT

SEQUENCE
DETECTOR

TIMER

04609-032

The sequence detector can also help to identify monitoring
faults. In the sample application shown in Figure 27, the FSEL1
and FSEL2 states identify which of the VP1,VP2, or VP3 pins
has faulted, and then they take the appropriate action.

MONITORING FAULT DETECTOR

The monitoring fault detector block is used to detect a failure
on an input. The logical function implementing this is a wide
OR gate, which can detect when an input deviates from its
expected condition. The clearest demonstration of the use of
this block is in the POWER_GOOD state, where the monitor
block indicates that a failure on one or more of the VP1,VP2, or
VP3 inputs has occurred.

No programmable delay is available in this block, because the
triggering of a fault condition is likely to be caused when a supply
falls out of tolerance. In this situation, the user should react as
quickly as possible. Some latency occurs when moving out of
this state, because it takes a finite amount of time (~20 µs) for the
state configuration to download from EEPROM into the SE.
Figure 29 is a block diagram of the monitoring fault detector.

MONITORING FAULT
DETECTOR

1-BIT FAULT
DETECTOR

FAULT

FAULT

FAULT

LOGIC INPUT CHANGE

X5

OR FAULT DETECTION

Figure 29. Monitoring Fault Detector Block Diagram

SUPPLY FAULT

DETECTION

WARNINGS

MASK
SENSE

1-BIT FAULT
DETECTOR

MASK
SENSE

1-BIT FAULT
DETECTOR

MASK

TIMEOUT DETECTOR

The timeout detector allows the user to trap a failure,
thus ensuring proper progress through a power-up or power­down sequence.

In the sample application shown in Figure 27, the timeout next­state transition is from the EN3V3 and EN2V5 states. For the
EN3V3 state, the signal 3V3ON is asserted on the PDO1 output
pin upon entry to this state to turn on a 3.3 V supply. This supply
rail is connected to the VP2 pin, and the sequence detector looks
for the VP2 pin to go above its UV threshold, which is set in the
supply fault detector (SFD) attached to that pin.

The power-up sequence progresses when this change is detected.
If, however, the supply fails (perhaps due to a short circuit over­loading this supply), the timeout block traps the problem. In this
example, if the 3.3 V supply fails within 10 ms, the SE moves to
the DIS3V3 state and turns off this supply by bringing PDO1
low. It also indicates that a fault has occurred by taking PDO3
high. Timeout delays of 100 µs to 400 ms can be programmed.

FAULT REPORTING

The ADM1062 has a fault latch for recording faults. Two registers
are set aside for this purpose. A single bit is assigned to each
input of the device, and a fault on that input sets the relevant
bit. The contents of the fault register can be read out over the
SMBus to determine which input(s) faulted. The fault register
can be enabled/disabled in each state. This ensures that only
real faults are captured and not, for example, undervoltage trips
when the SE is executing a power-down sequence.

04609-033

Rev. 0 | Page 19 of 36

ADM1062

V

K

V

VOLTAGE READBACK

The ADM1062 has an on-board, 12-bit, accurate ADC for
voltage readback over the SMBus. The ADC has a 12-channel
analog mux on the front end. The 12 channels consist of the
10 SFD inputs (VH, VP1 to VP4, and VX1 to VX5) plus two
channels for temperature readback (discussed in the Remote
Temperature Measurement section). Any or all of these inputs
can be selected to be read, in turn, by the ADC. The circuit
controlling this operation is called the round-robin circuit. The
round-robin circuit can be selected to run through its loop of
conversions once or continuously. Averaging is also provided
for each channel. In this case, the round-robin circuit runs
through its loop of conversions 16 times before returning a
result for each channel. At the end of this cycle, the results are
written to the output registers.

The ADC samples single-sided inputs with respect to the AGND
pin. A 0 V input gives out Code 0, and an input equal to the
voltage on REFIN gives out full code (4095 decimal).

The inputs to the ADC come directly from the VXn pins and
from the back of the input attenuators on the VPn and VH pins,
as shown in Figure 30 and Figure 31.

12-BIT

ADC

2.048V VREF

DIGITIZED
VOLTAGE

READING

12-BIT

ADC

04609-025

DIGITIZED

VOLTAGE
READING

04609-026

NO ATTENUATION

Xn

2.048V VREF

Figure 30. ADC Reading on VXn Pins

Pn/VH

ATTENUATION NETWOR
(DEPENDS ON RANGE SELECTED)

Figure 31. ADC Reading on VPn/VH Pins

The voltage at the input pin can be derived from the following
equation:

CodeADC

V =

4095

× Attenuation Factor × 2.048 V

The ADC input voltage ranges for the SFD input ranges are
listed in Table 8.

Table 8. ADC Input Voltage Ranges

SFD Input
Range (V) Attenuation Factor

ADC Input Voltage
Range (V)

0.573 to 1.375 1 0 to 2.048

1.25 to 3 2.181 0 to 4.46

2.5 to 6 4.363 0 to 6.01

4.8 to 14.4 10.472 0 to 14.41

1

The upper limit is the absolute maximum allowed voltage on these pins.

The normal way to supply the reference to the ADC on the
REFIN pin is to simply connect the REFOUT pin to the REFIN
pin. REFOUT provides a 2.048 V reference. As such, the
supervising range covers less than half of the normal ADC
range. It is possible, however, to provide the ADC with a more
accurate external reference for improved readback accuracy.

Supplies can also be connected to the input pins purely for ADC
readback, even though they might go above the expected super­visory range limits (as long as they are not above 6 V, because
this violates the absolute maximum ratings on these pins). For
instance, a 1.5 V supply connected to the VX1 pin can be correctly
read out as an ADC code of approximately 3/4 full scale, but it
always sits above any supervisory limits that can be set on that
pin. The maximum setting for the REFIN pin is 2.048 V.

SUPPLY SUPERVISION WITH THE ADC

In addition to the readback capability, a further level of supervi­sion is provided by the on-chip, 12-bit ADC. The ADM1062 has
limit registers on which the user can program a maximum or
minimum allowable threshold. Exceeding the threshold generates
a warning that can either be read back from the status registers
or input into the SE to determine what sequencing action the
ADM1062 should take. Only one register is provided for each
input channel; therefore, either a UV or OV threshold (but not
both) can be set for a given channel. The round-robin circuit
can be enabled via an SMBus write, or it can be programmed to
turn on in any state in the SE program. For example, it can be
set to start once a power-up sequence is complete and all
supplies are known to be within expected tolerance limits.

Note that a latency is built into this supervision, dictated by the
conversion time of the ADC. With all 12 channels selected, the
total time for the round-robin operation (averaging off) is
approximately 6 ms (500 µs per channel selected). Supervision
using the ADC, therefore, does not provide the same real time
response as the SFDs.

Rev. 0 | Page 20 of 36

ADM1062

SUPPLY MARGINING

OVERVIEW

It is often necessary for the system designer to adjust supplies,
either to optimize their level or force them away from nominal
values to characterize the system performance under these
conditions. This is a function typically performed during an in­circuit test (ICT), such as when the manufacturer wants to
guarantee that a product under test functions correctly at
nominal supplies −10%.

OPEN-LOOP MARGINING

The simplest method of margining a supply is to implement an
open-loop technique. A popular method for this is to switch extra
resistors into the feedback node of a power module, such as a
dc-to-dc converter or low dropout regulator (LDO). The extra
resistor alters the voltage at the feedback or trim node and forces
the output voltage to margin up or down by a certain amount.

The ADM1062 can perform open-loop margining for up to six
supplies. The six on-board voltage DACs (DAC1 to DAC6) can
drive into the feedback pins of the power modules to be
margined. The simplest circuit to implement this function is an
attenuation resistor, which connects the DACn pin to the
feedback node of a dc-to-dc converter. When the DACn output
voltage is set equal to the feedback voltage, no current flows in
the attenuation resistor, and the dc-to-dc output voltage does
not change. Taking DACn above the feedback voltage forces
current into the feedback node, and the output of the dc-to-dc
converter is forced to fall to compensate for this. The dc-to-dc
output can be forced high by setting the DACn output voltage
lower than the feedback node voltage. The series resistor can be
split in two, and the node between them decoupled with a
capacitor to ground. This can help to decouple any noise picked
up from the board. Decoupling to a ground local to the dc-to­dc converter is recommended.

VIN

V

OUTPUT

DC/DC

CONVERTER

FEEDBACK

GND

OUT

ATTENUATION

RESISTOR

DACOUTn

PCB
TRACE NOISE
DECOUPLING
CAPACITOR

ADM1062

Figure 32. Open-Loop Margining System Using the ADM1062

The ADM1062 can be commanded to margin a supply up or
down over the SMBus by updating the values on the relevant
DAC output.

DAC

µCONTROLLER

DEVICE

CONTROLLER

(SMBus)

Rev. 0 | Page 21 of 36

04433-067

CLOSED-LOOP SUPPLY MARGINING

A much more accurate and comprehensive method of margining
is to implement a closed-loop system. With this technique, the
voltage of a rail is read back so that it can be accurately margined
to the target voltage. The ADM1062 incorporates all the circuits
required to do this, with the 12-bit successive approximation
ADC used to read back the level of the supervised voltages, and
the six voltage output DACs, implemented as described in the
Open-Loop Margining section, used to adjust supply levels.
These circuits can be used along with other intelligence such as
a microcontroller to implement a closed-loop margining system
that allows any dc-to-dc or LDO supply to be set to any voltage,
accuracy to within ±0.5% of the target.

ADC

DAC

µCONTROLLER

DEVICE

CONTROLLER

(SMBus)

VIN

ADM1062

DC/DC

CONVERTER

OUTPUT

FEEDBACK

GND

R1

R2

ATTENUATION
RESISTOR, R3

VH/VPn/VXn

DACOUTn

PCB
TRACE NOISE
DECOUPLING
CAPACITOR

MUX

Figure 33. Closed-Loop Margining System Using the ADM1062

To implement closed-loop margining:

1. Disable the six DACn outputs.

2. Set the DAC output voltage equal to the voltage on the
feedback node.

3. Enable the DAC.

4. Read the voltage at the dc-to-dc output, which is connected
to one of the VP1 to VP4, VH, or VX1 to VX5 pins.

5. If necessary, modify the DACn output code up or down to
adjust the dc-to-dc output voltage; otherwise, stop because
the target voltage has been reached.

6. Set the DAC output voltage to a value that alters the supply
output by the required amount (for example, ±5%).

7. Repeat from Step 4.

Step 1 to Step 3 ensure that when the DACn output buffer is
turned on, it has little effect on the dc-to-dc output. The DAC
output buffer is designed to power up without glitching by first
powering up the buffer to follow the pin voltage. It does not
drive out onto the pin at this time. Once the output buffer is
properly enabled, the buffer input is switched over to the DAC
and the output stage of the buffer is turned on. Output glitching
is negligible.

04433-034

ADM1062

WRITING TO THE DACs

Four DAC ranges are offered. They can be placed with midcode
(Code 0x7F) at 0.6 V, 0.8 V, 1.0 V, and 1.25 V. These voltages are
placed to correspond to the most common feedback voltages.
Centering the DAC outputs in this way provides the best use of
the DAC resolution. For most supplies, it is possible to place the
DAC midcode at the point where the dc-to-dc output is not
modified, thereby giving half of the DAC range to margin up
and the other half to margin down.

The DAC output voltage is set by the code written to the DACn
register. The voltage is linear with the unsigned binary number
in this register. Code 0x7F is placed at the midcode voltage, as
described previously. The output voltage is given by the
following equation:

DAC Output = (DACn − 0x7F)/255 × 0.6015 + V

where V

is one of the four offset voltages.

OFF

There are 256 DAC settings available. The midcode value is
located at DAC Code 0x7F, as close as possible to the middle
of the 256 code range. The full output swing of the DACs is
+302 mV (+128 codes) and −300 mV (−127 codes) around the
selected midcode voltage. The voltage range for each midcode
voltage is shown in Table 9.

Table 9. Ranges for Midcode Voltages

Midcode
Voltage (V)

0.6 0.300 0.902

0.8 0.500 1.102

1.0 0.700 1.302

1.25 0.950 1.552

Minimum Voltage
Output (V)

Maximum Voltage
Output (V)

CHOOSING THE SIZE OF THE ATTENUATION
RESISTOR

The degree to which the DAC voltage swing affects the output
voltage of the dc-to-dc converter that is being margined is
determined by the size of the attenuation resistor, R3 (see
Figure 33).

Because the voltage at the feedback pin remains constant, the
current flowing from the feedback node to GND via R2 is
constant. Also, the feedback node itself is high impedance. This

OFF

means that the current flowing through R1 is the same as the
current flowing through R3. Therefore, a direct relationship
exists between the extra voltage drop across R1 during
margining and the voltage drop across R3.

This relationship is given by the following equation:

∂V

OUT

R3

(VFB − V

DACOUT

)

R1

=

where:

V

is the change in V

∂

OUT

V

is the voltage at the feedback node of the dc-to-dc converter.

FB

V

is the voltage output of the margining DAC.

DACOUT

OUT

.

This equation demonstrates that if the user wants the output
voltage to change by ±300 mV, then R1 = R3. If the user wants the
output voltage to change by ±600 mV, then R1 = 2 × R3, and so on.

It is best to use the full DAC output range to margin a supply.
Choosing the attenuation resistor in this way provides the most
resolution from the DAC. In other words, with one DAC code
change, the smallest effect on the dc-to-dc output voltage is
induced. If the resistor is sized up to use a code such as 27 (dec)
to 227 (dec) to move the dc-to-dc output by ±5%, then it takes
100 codes to move 5% (each code moves the output by 0.05%).
This is beyond the readback accuracy of the ADC, but should not
prevent the user from building a circuit to use the most resolution.

DAC LIMITING AND OTHER SAFETY FEATURES

Limit registers (called DPLIMn and DNLIMn) on the device
offer the user some protection from firmware bugs, which can
cause catastrophic board problems by forcing supplies beyond
their allowable output ranges. Essentially, the DAC code written
into the DACn register is clipped such that the code used to set
the DAC voltage is actually given by

DAC Code
= DACn, DACn ≥ DNLIMn and DACn ≤ DPLIMn
= DNLIMn, DACn < DNLIMn
= DPLIMn, DACn > DPLIMn

In addition, the DAC output buffer is three-stated if DNLIMn >
DPLIMn. By programming the limit registers in this way, the
user can make it very difficult for the DAC output buffers to be
turned on during normal system operation (these are among
the registers downloaded from EEPROM at startup).

Rev. 0 | Page 22 of 36

ADM1062

TEMPERATURE MEASUREMENT SYSTEM

The ADM1062 contains an on-chip, band gap temperature
sensor, whose output is digitized by the on-chip, 12-bit ADC.
Theoretically, the temperature sensor and ADC can measure
temperatures from −128°C to +127°C with a resolution of

0.125°C. Because this exceeds the operating temperature range
of the device, local temperature measurements outside this
range are not possible. Temperature measurements from

−128°C to +127°C are possible using a remote sensor. The
output code is in offset binary format, with −128°C given by
Code 0x400, 0°C given by Code 0x800, and +127°C given by
Code 0xC00.

If a discrete transistor is used, the collector is not grounded and
should be linked to the base. If a PNP transistor is used, the
base is connected to the DN input and the emitter is connected
to the DP input. If an NPN transistor is used, the emitter is
connected to the DN input and the base is connected to the DP
input. Figure 35 and Figure 36 show how to connect the
ADM1062 to an NPN or PNP transistor for temperature
measurement. To prevent ground noise from interfering with
the measurement, the more negative terminal of the sensor is
not referenced to ground, but is biased above ground by an
internal diode at the DN input.

As with the other analog inputs to the ADC, a limit register is
provided for each of the temperature input channels. Therefore,
a temperature limit can be set such that if it is exceeded, a warning
is generated and available as an input to the sequencing engine.
This enables users to control their sequence or monitor functions
based on an overtemperature or undertemperature event.

REMOTE TEMPERATURE MEASUREMENT

The ADM1062 can measure the temperature of a remote diode
sensor or diode-connected transistor connected to Pin DN and
Pin DP (Pin 37 and Pin 38 on the LFCSP package, and Pin 44
and Pin 45 on the TQFP package).

The forward voltage of a diode or diode-connected transistor
operated at a constant current exhibits a negative temperature
coefficient of about −2 mV/°C. Unfortunately, the absolute
value of V
calibration is required to null this, making the technique
unsuitable for mass production. The technique used in the
ADM1062 is to measure the change in V
operated at two different currents.

This is given by

where:

k is Boltzmann’s constant.
q is charge on the carrier.
T is absolute temperature in Kelvin.
N is ratio of the two currents.

Figure 34 shows the input signal conditioning used to measure the
output of a remote temperature sensor. This figure shows the
external sensor as a substrate transistor provided for temperature
monitoring on some microprocessors, but it could equally be a
discrete transistor such as a 2N3904 or 2N3906.

varies from device to device, and individual

be

∆

V

= kT/q × ln(N)

be

when the device is

be

To me as u re ∆ V

, the sensor is switched between operating

be

currents of I and N × I. The resulting waveform is passed
through a 65 kHz low-pass filter to remove noise and through a
chopper-stabilized amplifier that amplifies and rectifies the
waveform to produce a dc voltage proportional to ∆V

. This

be

voltage is measured by the ADC to produce a temperature
output in 12-bit offset binary. To further reduce the effects of
noise, digital filtering is performed by averaging the results of
16 measurement cycles. A remote temperature measurement
takes nominally 600 ms. The results of remote temperature
measurements are stored in 12-bit, offset binary format, as
shown in Table 10. This provides temperature readings with a
resolution of 0.125°C.

Table 10. Temperature Data Format

Temperature Digital Output (Hex) Digital Output (Bin)

−128 °C 400 010000000000

−125 °C 418 010000011000

−100 °C 4E0 010011100000

−75 °C 5A8 010110101000

−50 °C 600 011000000000

−25 °C 670 011001110000

−10 °C 7B0 011110110000

0 °C 800 100000000000
+10.25 °C 852 100001010010
+25.5 °C 8CC 100011001100
+50.75 °C 996 100110010110
+75 °C A58 101001011000
+100 °C B48 101101001000
+125 °C BE8 101111101000
+128 °C C00 110000000000

Rev. 0 | Page 23 of 36

ADM1062

CPU

REMOTE

SENSING

TRANSISTOR

Figure 34. Signal Conditioning for Remote Diode Temperature Sensors

ADM1062

2N3904

NPN

DP

DN

Figure 35. Measuring Temperature Using an NPN Transistor

THERM DA
THERM DCDPDN

04433-070

I N× I

BIAS

DIODE

V

DD

I

BIAS

LOW-PASS FILTER

f

= 65kHz

C

V

OUT+

TO ADC

V

OUT–

04433-069

ADM1062

DP

2N3906

PNP

DN

04433-071

Figure 36. Measuring Temperature Using a PNP Transistor

Rev. 0 | Page 24 of 36

ADM1062

APPLICATIONS DIAGRAM

12V IN

5V IN

3V IN

VH

5V OUT
3V OUT VP2

3.3V OUT VP3

2.5V OUT VP4

1.8V OUT VX1

1.2V OUT VX2

0.9V OUT VX3

POWER_ON

RESET_L

*ONLY ONE MARGINING CIRCUIT
SHOWN FOR CLARITY. DAC1 TO DAC6
WILL ALLOW MARGINING FOR UP TO
SIX VOLTAGE RAILS.

3.3V OUT

2.5V OUT

VP1

VX4

VX5

REFOUT

REFIN

10µF

ADM1062

VCCP

10µF

TEMPERATURE

PDO1
PDO2

PDO3
PDO4
PDO5

POWER_GOOD

PDO6

SIGNAL_VALID

PDO7

SYSTEM RESET

PDO8

PDO9
PDO10
DAC1*

DP
DN

GND

VDDCAP

10µF

DIODE

µP

Figure 37. Applications Diagram

3.3V OUT

IN

OUT

EN TRIM

DC-DC4

IN

DC-DC1

EN OUT

IN

DC-DC2

EN OUT

IN

DC-DC3

EN OUT

3.3V OUT

IN

LDO

EN OUT

12V OUT

5V OUT

3V OUT

3.3V OUT

2.5V OUT

1.8V OUT

0.9V OUT

1.2V OUT

04433-068

Rev. 0 | Page 25 of 36

ADM1062

COMMUNICATING WITH THE ADM1062

CONFIGURATION DOWNLOAD AT POWER-UP

The configuration of the ADM1062 (UV/OV thresholds, glitch
filter timeouts, PDO configurations, and so on) is dictated by
the contents of RAM. The RAM is comprised of digital latches
that are local to each of the functions on the device. The latches
are double-buffered and have two identical latches, Latch A and
Latch B. Therefore, when an update to a function occurs, the
contents of Latch A are updated first, and then the contents of
Latch B are updated with identical data. The advantages of this
architecture are explained in detail in the Updating the
Configuration section.

The ADM1062 provides several options that allow the user to
update the configuration over the SMBus interface. The
following options are controlled in the UPDCFG register:

Update the configuration in real time. The user writes

1.
to RAM across the SMBus and the configuration is
updated immediately.

2.

Update the Latch As without updating the Latch Bs. With

this method, the configuration of the ADM1062 remains
unchanged and continues to operate in the original setup
until the instruction is given to update the Latch Bs.

The latches are volatile memory and lose their contents at
power-down. Therefore, the configuration in the RAM must be
restored at power-up by downloading the contents of the
EEPROM (nonvolatile memory) to the local latches. This
download occurs in steps, as follows:

1.

With no power applied to the device, the PDOs are all

high impedance.

2.

When 1 V appears on any of the inputs connected to the

V

arbitrator (VH or VPn), the PDOs are all weakly

DD

pulled to GND with a 20 kΩ impedance.

3.

When the supply rises above the undervoltage lockout of

the device (UVLO is 2.5 V), the EEPROM starts to
download to the RAM.

4.

The EEPROM downloads its contents to all Latch As.

5.

Once the contents of the EEPROM are completely down-

loaded to the Latch As, the device controller signals all
Latch As to download to all Latch Bs simultaneously,
completing the configuration download.

6.

At 0.5 ms after the configuration download completes, the

first state definition is downloaded from EEPROM into
the SE.

Note that any attempt to communicate with the device prior to
the completion of the download causes the ADM1062 to issue
a no acknowledge (NACK).

UPDATING THE CONFIGURATION

After power-up, with all the configuration settings loaded from
EEPROM into the RAM registers, the user might need to alter
the configuration of functions on the ADM1062, such as changing
the UV or OV limit of an SFD, changing the fault output of an
SFD, or adjusting the rise time delay of one of the PDOs.

3.

Change EEPROM register contents without changing the

RAM contents, and then download the revised EEPROM
contents to the RAM registers. With this method, the
configuration of the ADM1062 remains unchanged and
continues to operate in the original setup until the
instruction is given to update the RAM.

The instruction to download from the EEPROM in Option 3 is
also a useful way to restore the original EEPROM contents, if
revisions to the configuration are unsatisfactory. For example, if
the user needs to alter an OV threshold, this can be done by
updating the RAM register as described in Option 1. However,
if the user is not satisfied with the change and wants to revert to
the original programmed value, then the device controller can
issue a command to download the EEPROM contents to the
RAM again, as described in Option 3, restoring the ADM1062
to its original configuration.

The topology of the ADM1062 makes this type of operation
possible. The local, volatile registers (RAM) are all double­buffered latches. Setting Bit 0 of the UPDCFG register to 1
leaves the double-buffered latches open at all times. If Bit 0 is set
to 0, then, when a RAM write occurs across the SMBus, only
the first side of the double-buffered latch is written to. The user
must then write a 1 to Bit 1 of the UPDCFG register. This
generates a pulse to update all the second latches at once.
EEPROM writes occur in a similar way.

The final bit in this register can enable or disable EEPROM
page erasure. If this bit is set high, the contents of an EEPROM
page can all be set to 1. If low, then the contents of a page
cannot be erased, even if the command code for page erasure is
programmed across the SMBus. The bit map for the UPDCFG
register is shown in the AN-698 application note. A flow diagram
for download at power-up and subsequent configuration updates
is shown in Figure 38.

Rev. 0 | Page 26 of 36

ADM1062

SMBus

POWER-UP

> 2.5V)

(V

CC

EEPROM

E
E
P
R

O

M

L
D

DEVICE

CONTROLLER

D
A
T
A

LATCH A LATCH B

Figure 38. Configuration Update Flow Diagram

UPDATING THE SEQUENCING ENGINE

Sequencing engine (SE) functions are not updated in the same way
as regular configuration latches. The SE has its own dedicated
512-byte EEPROM for storing state definitions, providing 63
individual states, each with a 64-bit word (one state is reserved).
At power-up, the first state is loaded from the SE EEPROM into
the engine itself. When the conditions of this state are met, the
next state is loaded from EEPROM into the engine, and so on.
The loading of each new state takes approximately 10 µs.

To alter a state, the required changes must be made directly
to EEPROM. RAM for each state does not exist. The relevant
alterations must be made to the 64-bit word, which is then
uploaded directly to EEPROM.

INTERNAL REGISTERS

The ADM1062 contains a large number of data registers. The
principal registers are the address pointer register and the
configuration registers.

Address Pointer Register

This register contains the address that selects one of the other
internal registers. When writing to the ADM1062, the first byte
of data is always a register address, which is written to the
address pointer register.

Configuration Registers

These registers provide control and configuration for various
operating parameters of the ADM1062.

EEPROM

The ADM1062 has two 512-byte cells of nonvolatile, electrically
erasable, programmable, read-only memory (EEPROM) from
Register Address 0xF800 to Register Address 0xFBFF. The
EEPROM is used for permanent storage of data that is not lost
when the ADM1062 is powered down. One EEPROM cell
contains the configuration data of the device; the other contains
the state definitions for the SE. Although referred to as read-only
memory, the EEPROM can be written to, as well as read from,
via the serial bus in exactly the same way as the other registers.

R

U

A

P

M

D
L
D

FUNCTION

(OV THRESHOLD

ON VP1)

04609-035

The major differences between the EEPROM and other
registers are as follows:

• An EEPROM location must be blank before it can be

written to. If it contains data, it must first be erased.

• Writing to EEPROM is slower than writing to RAM.

• Writing to the EEPROM should be restricted, because it

has a limited write/cycle life of typically 10,000 write
operations due to the usual EEPROM wear-out
mechanisms.

The first EEPROM is split into 16 (0 to 15) pages of 32 bytes
each. Pages 0 to 6, starting at Address 0xF800, hold the config­uration data for the applications on the ADM1062 (the SFDs,
PDOs, and so on). These EEPROM addresses are the same as
the RAM register addresses, prefixed by F8. Page 7 is reserved.
Page 8 to Page 15 are for customer use.

Data can be downloaded from EEPROM to RAM in one of the
following ways:

• At power-up when Page 0 to Page 6 are downloaded.

• By setting Bit 0 of the UDOWNLD register (0xD8), which

performs a user download of Page 0 to Page 6.

SERIAL BUS INTERFACE

The ADM1062 is controlled via the serial system management
bus (SMBus). The ADM1062 is connected to this bus as a slave
device, under the control of a master device. It takes approxi­mately 1 ms after power-up for the ADM1062 to download
from its EEPROM. Therefore, access to the ADM1062 is
restricted until the download is completed.

Identifying the ADM1062 on the SMBus

The ADM1060 has a 7-bit serial bus slave address. The device is
powered up with a default serial bus address. The 5 MSBs of the
address are set to 01101, and the 2 LSBs are determined by the
logical states of Pin A1 and Pin A0. This allows the connection
of four ADM1062s to one SMBus.

Rev. 0 | Page 27 of 36

ADM1062

The device also has several identification registers (read-only),
which can be read across the SMBus. Table 11 lists these registers
with their values and functions.

Table 11. Identification Register Values and Functions

Name Address Value Function

MANID 0xF4 0x41

REVID 0xF5 0x02 Silicon revision
MARK1 0xF6 0x00 Software brand
MARK2 0xF7 0x00 Software brand

General SMBus Timing

Figure 39, Figure 40, and Figure 41 are timing diagrams for
general read and write operations using the SMBus. The SMBus
specification defines specific conditions for different types of
read and write operations, which are discussed in the Write
Operations and Read Operations sections.

The general SMBus protocol operates as follows:

1.

The master initiates data transfer by establishing a start

condition, defined as a high-to-low transition on the serial
data-line SDA while the serial clock-line SCL remains high.
This indicates that a data stream follows. All slave periph­erals connected to the serial bus respond to the start
condition and shift in the next eight bits, consisting of a 7­bit slave address (MSB first) plus an R/

determines the direction of the data transfer, that is,
whether data is written to or read from the slave device (0
= write, 1 = read).

The peripheral whose address corresponds to the trans­mitted address responds by pulling the data line low during
the low period before the ninth clock pulse, known as the
acknowledge bit, and holding it low during the high period
of this clock pulse.

Manufacturer ID for Analog
Devices

bit. This bit

W

All other devices on the bus remain idle while the selected
device waits for data to be read from or written to it. If the

bit is a 0, the master writes to the slave device. If the

R/

W

bit is a 1, the master reads from the slave device.

R/

W

Data is sent over the serial bus in sequences of nine clock

2.
pulses—eight bits of data followed by an acknowledge bit
from the slave device. Data transitions on the data line
must occur during the low period of the clock signal and
remain stable during the high period, because a low-to­high transition when the clock is high might be interpreted
as a stop signal. If the operation is a write operation, the
first data byte after the slave address is a command byte.
This tells the slave device what to expect next. It might be
an instruction telling the slave device to expect a block
write, or it might simply be a register address that tells the
slave where subsequent data is to be written. Because data
can flow in only one direction, as defined by the R/

W

sending a command to a slave device during a read
operation is not possible. Before a read operation, it might
be necessary to perform a write operation to tell the slave
what sort of read operation to expect and/or from which
address to read data.

3.

When all data bytes have been read or written, stop condi-

tions are established. In write mode, the master pulls the
data line high during the 10th clock pulse to assert a stop
condition. In read mode, the master device releases the
SDA line during the low period before the ninth clock
pulse, but the slave device does not pull it low. This is
known as a no acknowledge. The master then takes the
data line low during the low period before the 10th clock
pulse, then high during the 10th clock pulse to assert a
stop condition.

bit,

SCL

SDA

(CONTINUED)

(CONTINUED)

19 91

START BY

MASTER

SCL

SDA

19 91

FRAME 1

SLAVE ADDRESS

D7 D6 D5 D4 D3 D2 D1

FRAME 3

DATA BYTE

Figure 39. General SMBus Write Timing Diagram

R/W

ACK. BY

SLAVE

D7A0A11110 0 D6 D5 D4 D3 D2 D1 D0

FRAME 2

COMMAND CODE

D0

ACK. BY

SLAVE

D7 D6 D5 D4 D3 D2 D1 D0

DATA BYTE

FRAME N

ACK. BY

SLAVE

ACK. BY

SLAVE

STOP

BY

MASTER

04609-036

Rev. 0 | Page 28 of 36

ADM1062

SCL

SDA

(CONTINUED)

(CONTINUED)

19 91

START BY

MASTER

SCL

SDA

19 91

FRAME 1

SLAVE ADDRESS

D7 D6 D5 D4 D3 D2 D1

FRAME 3

DATA BYTE

R/W

ACK. BY

SLAVE

D7A0A11110 0 D6 D5 D4 D3 D2 D1 D0

FRAME 2

DATA BYTE

D0

ACK. BY
MASTER

D7 D6 D5 D4 D3 D2 D1 D0

FRAME N

DATA BYTE

ACK. BY
MASTER

NO ACK.

STOP

BY

MASTER

04609-037

Figure 40. General SMBus Read Timing Diagram

t

R

t

SCL

SDA

t

BUF

PS S P

LOW

t

HD;STA

t

HD;DAT

Figure 41. Serial Bus Timing Diagram

t

SU;DAT

t

HIGH

t

F

t

SU;STA

t

HD;STA

t

SU;STO

04609-038

SMBus PROTOCOLS FOR RAM AND EEPROM

The ADM1062 contains volatile registers (RAM) and nonvola­tile registers (EEPROM). User RAM occupies address locations
from 0x00 to 0xDF; EEPROM occupies addresses from 0xF800
to 0xFBFF.

Data can be written to and read from both RAM and EEPROM
as single data bytes. Data can be written only to unprogrammed
EEPROM locations. To write new data to a programmed location,
the location’s contents must first be erased. EEPROM erasure
cannot be done at the byte level. The EEPROM is arranged as
32 pages of 32 bytes each, and an entire page must be erased.

Page erasure is enabled by setting Bit 2 in the UPDCFG register
(Address 0x90) to 1. If this bit is not set, page erasure cannot
occur, even if the command byte (0xFE) is programmed across
the SMBus.

WRITE OPERATIONS

The SMBus specification defines several protocols for different
types of read and write operations. The following abbreviations
are used in the diagrams:

S = Start
P = Stop
R = Read
W = Write
A = Acknowledge

= No acknowledge

A

The ADM1062 uses the following SMBus write protocols.

Send Byte

In a send byte operation, the master device sends a single
command byte to a slave device, as follows:

1.

The master device asserts a start condition on SDA.

2.

The master sends the 7-bit slave address followed by the

write bit (low).

3.

The addressed slave device asserts ACK on SDA.

4.

The master sends a command code.

5.

The slave asserts ACK on SDA.

6.

The master asserts a stop condition on SDA, and the

transaction ends.

In the ADM1062, the send byte protocol is used for two
purposes:

• To write a register address to RAM for a subsequent single

byte read from the same address, or for a block read or a
block write starting at that address, as shown in Figure 42.

2413 56

SLAVE

SWA AP

ADDRESS

Figure 42. Setting a RAM Address for Subsequent Read

RAM

ADDRESS

(0x00 TO 0xDF)

04609-039

Rev. 0 | Page 29 of 36

ADM1062

• To erase a page of EEPROM memory. EEPROM memory

can be written to only if it is unprogrammed. Before
writing to one or more EEPROM memory locations that
are already programmed, the page(s) containing those
locations must first be erased. EEPROM memory is erased
by writing a command byte.

The master sends a command code that tells the slave
device to erase the page. The ADM1062 command code for
a page erasure is 0xFE (1111 1110). Note that, for a page
erasure to take place, the page address must be given in the
previous write word transaction (see the Write Byte/Word
section). Also, Bit 2 in the UPDCFG register (Address
0x90) must be set to 1.

2413 56

SLAVE

SWA AP

ADDRESS

Figure 43. EEPROM Page Erasure

As soon as the ADM1062 receives the command byte, page
erasure begins. The master device can send a stop
command as soon as it sends the command byte. Page
erasure takes approximately 20 ms. If the ADM1062 is
accessed before erasure is complete, it responds with a no
acknowledge (NACK).

Write Byte/Word

In a write byte/word operation, the master device sends a
command byte and one or two data bytes to the slave device, as
follows:

1.

The master device asserts a start condition on SDA.

2.

The master sends the 7-bit slave address followed by the

write bit (low).

3.

The addressed slave device asserts ACK on SDA.

4.

The master sends a command code.

5.

The slave asserts ACK on SDA.

6.

The master sends a data byte.

7.

The slave asserts ACK on SDA.

8.

The master sends a data byte or asserts a stop condition.

9.

The slave asserts ACK on SDA.

10.

The master asserts a stop condition on SDA to end

the transaction.

COMMAND

BYTE

(0xFE)

04609-040

In the ADM1062, the write byte/word protocol is used for three
purposes:

• To write a single byte of data to RAM. In this case, the

command byte is the RAM addresses from 0x00 to 0xDF
and the only data byte is the actual data, as shown in
Figure 44.

2413 5876

SLAVE

S W A DATAAPA

ADDRESS

Figure 44. Single Byte Write to RAM

RAM

ADDRESS

(0x00 TO 0xDF)

04609-041

• To set up a 2-byte EEPROM address for a subsequent read,

write, block read, block write, or page erase. In this case,
the command byte is the high byte of the EEPROM
addresses from 0xF8 to 0xFB. The only data byte is the low
byte of the EEPROM address, as shown in Figure 45.

2413 5 876

SLAVE

SWA

ADDRESS

Figure 45. Setting an EEPROM Address

EEPROM

ADDRESS

HIGH BYTE

(0xF8 TO 0xFB)

EEPROM

ADDRESS

APA

LOW BYTE

(0x00 TO 0xFF)

04609-042

Note that for page erasure, because a page consists of
32 bytes, only the 3 MSBs of the address low byte are
important. The lower five bits of the EEPROM address low
byte specify the addresses within a page and are ignored
during an erase operation.

• To write a single byte of data to EEPROM. In this case, the

command byte is the high byte of the EEPROM addresses
from 0xF8 to 0xFB. The first data byte is the low byte of the
EEPROM address, and the second data byte is the actual
data, as shown in Figure 46.

2413 5 107

SLAVE

SWA

ADDRESS

EEPROM

ADDRESS

HIGH BYTE

(0xF8 TO 0xFB)

Figure 46. Single Byte Write to EEPROM

APA

(0x00 TO 0xFF)

EEPROM

ADDRESS

LOW BYTE

86

DATA

9

A

04609-043

Block Write

In a block write operation, the master device writes a block of
data to a slave device. The start address for a block write must
have been set previously. In the ADM1062, a send byte opera­tion sets a RAM address, and a write byte/word operation sets
an EEPROM address, as follows:

1.

The master device asserts a start condition on SDA.

2.

The master sends the 7-bit slave address followed by

the write bit (low).

3.

The addressed slave device asserts ACK on SDA.

Rev. 0 | Page 30 of 36

ADM1062

4. The master sends a command code that tells the slave

device to expect a block write. The ADM1062 command
code for a block write is 0xFC (1111 1100).

5.

The slave asserts ACK on SDA.

6.

The master sends a data byte that tells the slave device how

many data bytes are being sent. The SMBus specification
allows a maximum of 32 data bytes in a block write.

7.

The slave asserts ACK on SDA.

8.

The master sends N data bytes.

9.

The slave asserts ACK on SDA after each data byte.

10.

The master asserts a stop condition on SDA to end the

transaction.

2

SLAVE

SWA

ADDRESS

413A5

COMMAND 0xFC

(BLOCK WRITE)

Figure 47. Block Write to EEPROM or RAM

6

BYTE

COUNT

8

7

910

DATA

A

A

1

DATA

2

DATA

N

A PA

Unlike some EEPROM devices that limit block writes to within
a page boundary, there is no limitation on the start address
when performing a block write to EEPROM, except

• There must be at least N locations from the start address to

the highest EEPROM address (0xFBFF) to avoid writing to
invalid addresses.

04609-044

The master asserts a no acknowledge on SDA.

5.

6.

The master asserts a stop condition on SDA, and the

transaction ends.

In the ADM1062, the receive byte protocol is used to read a
single byte of data from a RAM or EEPROM location whose
address has previously been set by a send byte or write
byte/word operation, as shown in Figure 48.

231465

SLAVE

S R DATA PA

ADDRESS

Figure 48. Single Byte Read from EEPROM or RAM

A

04609-045

Block Read

In a block read operation, the master device reads a block of
data from a slave device. The start address for a block read must
have been set previously. In the ADM1062, this is done by a
send byte operation to set a RAM address, or a write byte/word
operation to set an EEPROM address. The block read operation
itself consists of a send byte operation that sends a block read
command to the slave, immediately followed by a repeated start
and a read operation that reads out multiple data bytes, as follows:

1.

The master device asserts a start condition on SDA.

2.

The master sends the 7-bit slave address followed by the

write bit (low).

3.

The addressed slave device asserts ACK on SDA.

• If the addresses cross a page boundary, both pages must be

erased before programming.

Note that the ADM1062 features a clock extend function for
writes to EEPROM. Programming an EEPROM byte takes
approximately 250 µs, which would limit the SMBus clock for
repeated or block write operations. The ADM1062 pulls SCL
low and extends the clock pulse when it cannot accept any
more data.

READ OPERATIONS

The ADM1062 uses the following SMBus read protocols.

Receive Byte

In a receive byte operation, the master device receives a single
byte from a slave device, as follows:

1.

The master device asserts a start condition on SDA.

2.

The master sends the 7-bit slave address followed by the

read bit (high).

3.

The addressed slave device asserts ACK on SDA.

4.

The master receives a data byte.

4.

The master sends a command code that tells the slave

device to expect a block read. The ADM1062 command
code for a block read is 0xFD (1111 1101).

5.

The slave asserts ACK on SDA.

6.

The master asserts a repeat start condition on SDA.

7.

The master sends the 7-bit slave address followed by the

read bit (high).

8.

The slave asserts ACK on SDA.

9.

The ADM1062 sends a byte-count data byte that tells the

master how many data bytes to expect. The ADM1062
always returns 32 data bytes (0x20), which is the maximum
allowed by the SMBus 1.1 specification.

10.

The master asserts ACK on SDA.

11.

The master receives 32 data bytes.

12.

The master asserts ACK on SDA after each data byte.

13.

The master asserts a stop condition on SDA to end

the transaction.

Rev. 0 | Page 31 of 36

ADM1062

2

SLAVE

SWA

ADDRESS

Error Correction

The ADM1062 provides the option of issuing a packet error
correction (PEC) byte after a write to RAM, a write to EEPROM,
a block write to RAM/EEPROM, or a block read from RAM/
EEPROM. This enables the user to verify that the data received
by or sent from the ADM1062 is correct. The PEC byte is an
optional byte sent after that last data byte has been written to
or read from the ADM1062. The protocol is as follows:

413A5S6

COMMAND 0xFD

(BLOCK READ)

7

SLAVE

ADDRESS

8

BYTE

COUNT

910 1211

Figure 49. Block Read from EEPROM or RAM

DATA

ARA

A

1

13A14

DATA

P

32

04609-046

Note that the PEC byte is calculated using CRC-8. The frame
check sequence (FCS) conforms to CRC-8 by the polynomial

C(x) = x

8

+ x2 + x1 + 1

See the SMBus 1.1 specification for details.

An example of a block read with the optional PEC byte is shown
in Figure 50.

2

SLAVE

SWA

ADDRESS

Figure 50. Block Read from EEPROM or RAM with PEC

413A5S6

COMMAND 0xFD

(BLOCK READ)

7

SLAVE

ADDRESS

8

COUNT

910 1211

BYTE

DATA

32

A

DATA

1

A13PEC

ARA

14A15

P

04609-047

1.

The ADM1062 issues a PEC byte to the master. The master

checks the PEC byte and issues another block read if the
PEC byte is incorrect.

2.

A no acknowledge (NACK) is generated after the PEC byte

to signal the end of the read.

Rev. 0 | Page 32 of 36

ADM1062

OUTLINE DIMENSIONS

PIN 1

INDICATOR

1.00

0.85

0.80

12° MAX

SEATING
PLANE

6.00

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

0.30

0.23

0.18

COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2

5.75

BCS SQ

0.20 REF

0.05 MAX

0.02 NOM

COPLANARITY

0.60 MAX

0.50
BSC

0.50

0.40

0.30

0.08

0.60 MAX

31

30

EXPOSED

(BOTTOM VIEW)

21

20

PAD

4.50
REF

PIN 1

40

11

INDICATOR

1

4.25

4.10 SQ

3.95

10

0.25 MIN

Figure 51. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

6 × 6 Body, Very Thin Quad

(CP-40)

Dimensions shown in millimeters

1.05

1.00

0.95

0.15

SEATING

0.05

PLANE

VIEW A

ROTATED 90° CCW

Figure 52. 48-Lead Thin Plastic Quad Flat Package [TQFP]

1.20

0.75

MAX

0.60

0.45

0° MIN

0.20

0.09
7°

3.5°
0°

0.08 MAX
COPLANARITY

COMPLIANT TO JEDEC STANDARDS MS-026ABC

VIEW A

(SU-48)

Dimensions shown in millimeters

48

1

12

13

LEAD PITCH

9.00

BSC SQ

PIN 1

TOP VIEW

(PINS DOWN)

0.50
BSC

0.27

0.22

0.17

37

36

7.00

BSC SQ

25

24

Rev. 0 | Page 33 of 36

ADM1062

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADM1062ACP −40°C to +85°C 40-Lead LFCSP_VQ CP-40
ADM1062ACP-REEL7 −40°C to +85°C 40-Lead LFCSP_VQ CP-40
ADM1062ACPZ1 −40°C to +85°C 40-Lead LFCSP_VQ CP-40
ADM1062ACPZ-REEL71 −40°C to +85°C 40-Lead LFCSP_VQ CP-40
ADM1062ASU −40°C to +85°C 48-Lead TQFP SU-48
ADM1062ASU-REEL7 −40°C to +85°C 48-Lead TQFP SU-48
ADM1062ASUZ1 −40°C to +85°C 48-Lead TQFP SU-48
ADM1062ASUZ-REEL71 −40°C to +85°C 48-Lead TQFP SU-48
EVAL-ADM1062LFEB ADM1062 Evaluation Kit (LFCSP Version)
EVAL-ADM1062TQEB ADM1062 Evaluation Kit (TQFP Version)

1

Z = Pb-free part.

Rev. 0 | Page 34 of 36

ADM1062

NOTES

Rev. 0 | Page 35 of 36

ADM1062

NOTES

© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

D04433–0–4/05(0)

Rev. 0 | Page 36 of 36