Datasheet ADM1052JR Datasheet (Analog Devices)

Precision Dual Voltage

a

FEATURES
Two Independent Controllers on One Chip
Two 2.525 V Outputs
Shutdown Inputs to Control Each Channel
2.5% Accuracy Over Line, Load, and Temperature
Low Quiescent Current
Low Shutdown Current
Works with External N-Channel MOSFETs for Low Cost
“Hiccup Mode” Fault Protection
No External Voltage or Current Setting Resistors
Small, 8-Lead SO Package

APPLICATIONS
Desktop Computers
Servers
Workstations

FUNCTIONAL BLOCK DIAGRAM

V

ADM1052

V

CC

50A

BANDGAP

REFERENCE

Regulator Controller

ADM1052

GENERAL DESCRIPTION

The ADM1052 is a dual, precision, voltage regulator controller
intended for power rail generation and active bus termination
on personal computer motherboards. It contains a precision

1.2 V bandgap reference and two channels consisting of con­trol amplifiers driving external power devices. Each channel has a
shutdown input to turn off amplifier output and “Hiccup Mode”
protection circuitry for the external power device.

The ADM1052 operates from a 12 V supply. This gives suffi­cient headroom for the amplifiers to drive external N-channel
MOSFETs, operating as source-followers, as the external series
pass devices. This has the advantage that N-channel devices are
cheaper than P-channel devices of similar performance, and the
circuit is easier to stabilize than one using P-channel devices in
a common-source configuration.

3.3V

CC

CONTROL

AMPLIFIER

FORCE 1

SENSE 1

100F

V

OUT1

2  100F

SHDN1

SHDN2

V

CC

50A

V

CC

POWER-ON

RESET

SHUTDOWN

CONTROL

SHUTDOWN

CONTROL

CLK/DELAY

GENERATOR

GND

COMPARATOR

COMPARATOR

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

HICCUP

CONTROL

AMPLIFIER

FORCE 2

SENSE 2

HICCUP

CLOCK

OSCILLATOR

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

3.3V

100F

V

OUT2

2  100F

(VCC = 12 V  6%, VIN = 3.3 V, TA = 0C to 70C, both channels, unless otherwise

ADM1052–SPECIFICATIONS

Parameter Min Typ Max Unit Test Conditions/Comments

OUTPUT VOLTAGE

Channel 1, Channel 2 2.525 V SHDN1, SHDN2 Floating

OUTPUT VOLTAGE ACCURACY –2.5 +2.5 % V

Load Regulation –5 +5 mV V
Line Regulation –5 +5 mV V

CONTROL AMPLIFIER

Control Amplifier Open-Loop Gain 100 dB
Control Amplifier Slew Rate 3 V/µs
Closed-Loop Settling Time 5 µsI
Turn-On Time 5 µs To 90% of Force High Output Level (C
Sense Input Impedance
Force Output Voltage Swing, V
Force Output Voltage Swing, VF (Low) 2 V RL = 10 kΩ to V

HICCUP MODE

Hiccup Mode Hold-Off Time 30 60 90 ms Figure 2
Hiccup Mode Threshold 0.8 × V
Hiccup Comparator Glitch Immunity 100 µs
Hiccup Mode On-Time 0.5 1.0 1.5 ms
Hiccup Mode Off-Time 20 40 60 ms
Power-On Reset Threshold 6 9 V

SHUTDOWN, SHDN1, SHDN2

Shutdown Input Low Voltage, V
Shutdown Input High Voltage, V
Supply Current, Normal Operation 2.4 4.0 mA Shutdown Inputs Floating
Supply Current, Shutdown Mode 600 1000 µA Both Channels Shut Dow

NOTES

1

Guaranteed by design.

Specifications subject to change without notice.

1

(High) 10 V RL = 10 kΩ to GND

F

IL

IH

2.0 V

noted. See Test Circuit.)

50 kΩ

V

OUT

0.8 V

= 3.0 V to 3.6 V, I

IN

= 3.3 V, I

IN

= 3.0 V to 3.6 V, I

IN

= 10 mA to 2 A

O

OUT

CC

= 10 mA to 1 A

OUT

= 10 mA to 1 A

OUT

= 1 A

1

n

1

= 470 pF)

L

–2–

REV. A

ADM1052

TOP VIEW

(Not to Scale)

8

7

6

5

1

2

3

4

FORCE 2

SENSE 2

SHDN2

GND

V

CC

FORCE 1

SENSE 1

SHDN1

ADM1052

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

(TA = 25°C unless otherwise noted)

VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 V

SHDN1, SHDN2 to GND . . . . . . . . –0.3 V to (V

+ 0.3 V)

CC

SENSE1, SENSE2 to GND . . . . . . . . . . . . –0.3 V to +5.5 V

FORCE1, FORCE2 . . . . . . . . Short-Circuit to GND or V

CC

Continuous Power Dissipation (TA = 70°C) . . . . . . . 650 mW

°

8-Lead SOIC . . . . . . . . . . . . (Derate 8.3 mW/

C above 70°C)

Operating Temperature Range

Commercial (J Version) . . . . . . . . . . . . . . . . . . 0°C to 70°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C

*This is a stress rating only and functional operation of the device at these or any

other conditions above those indicated in the operation sections of this specifica­tion is not implied. Exposure to absolute maximum rating conditions for extended
periods of time may affect reliability.

THERMAL CHARACTERISTICS

8-Lead Small Outline Package: ␪JA = 150°C/W

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

ADM1052JR 0°C to 70°C 8-Lead SOIC SO-8

PIN FUNCTION DESCRIPTIONS

Pin
No. Mnemonic Function

1 FORCE 2 Output of Channel 2 control amplifier to

gate of external N-channel MOSFET.

2 SENSE 2 Input from source of external MOSFET to

inverting input of Channel 2 control
amplifier, via output voltage-setting feed­back resistor network.

3 SHDN2 Digital Input. Active-low shutdown control

with 50 µA internal pull-up. The output
of Channel 2 control amplifier goes to
ground when SHDN2 is taken low.

4 GND Device Ground Pin.
5 SHDN1 Digital Input. Active-low shutdown control

with 50 µA internal pull-up. The output
of Channel 1 control amplifier goes to
ground when SHDN1 is taken low.

6 SENSE 1 Input from source of external MOSFET

to inverting input of Channel 1 control
amplifier, via output voltage-setting
feedback resistor network.

7 FORCE 1 Output of Channel 2 control amplifier to

gate of external N-channel MOSFET.

8V

CC

12 V Supply.

LEAVE OPEN OR

CONNECT TO

LOGIC SIGNALS

IF SHUTDOWN

REQUIRED

SHDN1

SHDN2

12V

V

CC

ADM1052

GND

1F

FORCE 2

SENSE 2

PHD55N03LT

FORCE 1

SENSE 1

MTD3055VL

3.3V

3.3V

100F

V

OUT1

2  100F

100F

V

OUT2

2  100F

PIN CONFIGURATION

Figure 1. Test Circuit

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADM1052 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

REV. A

–3–

ADM1052

Tek Stop: 25.0MS/s 56Acqs

Stop:

–Typical Performance Characteristics

[]

T

T

2.55

2.54

2.53

T

2

v

T

3

v

1

t

Ch1 500mV Ch2 20.0mV M 2.00s Ch1 3.53V

Ch1

Ch3 20.0mV

B

W

B

W

B

W

TPC 1. Line Transient Response, Channel 1 and Channel 2

2.536

2.535

2.534

2.533

– V

OUT

V

2.532

2.531

2.530

2.529

2.9

3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7
VIN – V

TPC 2. Line Regulation, Channel 1

2.52

OUTPUT – V

2.51

2.50

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

0

CURRENT – A

TPC 4. Load Regulation, Channel 1

2.55

2.54

2.53

2.52

OUTPUT – V

2.51

2.50

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

0

CURRENT – A

TPC 5. Load Regulation, Channel 2

2.542

2.541

2.540

2.539

– V

OUT

V

2.538

2.537

2.536

2.535

2.9

3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7
VIN – V

TPC 3. Line Regulation, Channel 2

–4–

0

–10

–20

–30

–40

–50

RIPPLE REJECTION – dB

–60

–70

100 1k 10k 100k 1M 10M

10

FREQUENCY – Hz

TPC 6. VCC Supply Ripple Rejection

REV. A

OUTPUT – V

2.544

2.542

2.540

2.538

2.536

2.534

Tek Stop: Single Seq 50.0MS/s

Stop:

1

t

[]

T

T

ADM1052

2.532

2.530

2.528
10 20 30 40 50 60 70 80 90

0

TEMPERATURE – C

TPC 7. Regulator Output Voltage vs. Temperature

Tek Stop: Single Seq 50.0MS/s

Stop:

1

t

[]

T

T

t

Ch1 20.0mV M 1.00s Ch1 –45.0mV

Ch1

B

W

t

Ch1 20.0mV M 1.00s Ch1 –40mV

Ch1

B

W

TPC 10. Transient Response Channel 2, 10 mA to 2 A
Output Load Step

Tek Stop: Single Seq 50.0MS/s

Stop:

[]

T

t

1

T

t

Ch1 20.0mV M 1.00s Ch1 37.6mV

Ch1

B

W

TPC 8. Transient Response Channel 1, 10 mA to 2 A
Output Load Step

Tek Stop: Single Seq 50.0MS/s

Stop:

1

t

Ch1 20.0mV M 1.00s Ch1 5.2mV

Ch1

[]

T

T

B

W

TPC 9. Transient Response Channel 1, 2 A to 10 mA
Output Load Step

REV. A

TPC 11. Transient Response Channel 2, 2 A to 10 mA
Output Load Step

Tek Stop: 10.0kS/s 0Acqs

Stop:

t

1

t

Ch1 10.0mV M 5.00s Ch1 800mV

Ch1

[]

T

T

B

W

t

TPC 12. Force Output In Hiccup Mode, Channel 1

–5–

ADM1052

GENERAL DESCRIPTION

The ADM1052 is a dual, precision, voltage regulator controller
intended for power rail generation and active bus termination on
personal computer motherboards. It contains a precision 1.2 V
bandgap reference and two channels consisting of control amp­lifiers driving external power devices. Both channels have an
output of nominally 2.525 V. Each channel has a shutdown
input to turn off amplifier output and protection circuitry for
the external power device.

The ADM1052 operates from a 12 V V
disabled until V

climbs above the reset threshold (6 V–9 V). The

CC

supply. The output is

CC

output from the ADM1052 is used to drive external N-channel
MOSFETs, operating as source-followers. This has the advan­tage that N-channel devices are cheaper than P-channel devices
of similar performance, and the circuit is easier to stabilize than
one using P-channel devices in a common-source configuration.

The external power devices are protected by a “Hiccup Mode”
circuit that operates if the circuit goes out of regulation due to
an output short-circuit. In this case the power device is pulsed
on/off with a 1:40 duty cycle to limit the power dissipation until
the fault condition is removed.

CIRCUIT DESCRIPTION

CONTROL AMPLIFIERS

The reference voltage is amplified and buffered by the control
amplifiers and external MOSFETs, the output voltage of each
channel being determined by the feedback resistor network
between the sense input and the inverting input of the con­trol amplifier.

A power-on reset circuit disables the amplifier output until V

CC

has risen above the reset threshold (6 V–9 V).

Each amplifier output drives the gate of an N-channel power
MOSFET, whose drain is connected to the unregulated supply
input and whose source is the regulated output voltage, which is
also fed back to the appropriate sense input of the ADM1052.
The control amplifiers have high current-drive capability so that
they can quickly charge and discharge the gate capacitance of
the external MOSFET, thus giving good transient response to
changes in load or input voltage.

SHUTDOWN INPUTS

Each channel has a separate shutdown input, which may be
controlled by a logic signal and allows the output of the regula­tor to be turned on or off. If the shutdown input is held high or
not connected, the regulator operates normally. If the shutdown
input is held low, the enable input of the control amplifier is turned
off and the amplifier output goes low, turning off the regulator.

“HICCUP MODE” FAULT PROTECTION

Hiccup mode fault protection is a simple method of protecting
the external power device without the added cost of external
sense resistors or a current sense pin on the ADM1052. In the
event of a short-circuit condition at the output, the output
voltage will fall. When the output voltage of a channel falls 20%
below the nominal voltage, this is sensed by the hiccup com­parator and the channel will go into hiccup mode, where the
enable signal to the control amplifier is pulsed on and off with a
1:40 duty cycle.

To prevent the device inadvertently going into hiccup mode
during power-up or during channel enabling, the hiccup mode is
held off for approximately 60 ms on both channels. By this time
the output voltage should have reached its correct value. In the
case of power-up, the hold-off period starts when V

reaches the

CC

power-on reset threshold of 6 V–9 V. In the case of channel
enabling, the hold-off period starts when SHDN is taken high.
Note that the hold-off timeout applies to both channels even if
only one channel is disabled/enabled.

As the 3.3 V input to the drain of the MOSFET is not moni­tored, it should ideally rise at the same or a faster rate than V
At the very least it must be available in time for V

to reach its

OUT

CC

.

final value before the end of the power-on delay. If the output
voltage is still less than 80% of the correct value after the power­on delay, the device will go into hiccup mode until the output
voltage exceeds 80% of the correct value during a hiccup mode
on-period. Of course, if there is a fault condition at the output
during power-up, the device will go into hiccup mode after
the power-up delay and remain there until the fault condition
is removed.

The effect of power-on delay is illustrated in Figure 2, which
shows an ADM1052 being powered up with a fault condition.
The output current rises to a very high value during the power­on delay, the device goes into hiccup mode, and the output is
pulsed on and off at 1:40 duty cycle. When the fault condition is
removed, the output voltage recovers to its normal value at the
end of the hiccup mode off period.

The load current at which the ADM1052 will go into hiccup
mode is determined by three factors:

• The input voltage to the drain of the MOSFET, V

• The output voltage V

• The on-resistance of the MOSFET, R

I

HICCUP

(–20%)

OUT

= (VIN – (0.8 × V

ON

OUT

))/R

IN

ON

It should be emphasized that the hiccup mode is not intended as
a precise current limit but as a simple method of protecting the
external MOSFET against catastrophic fault conditions such as
output short circuits.

–6–

REV. A

12V SUPPLY

3.3V SUPPLY

TO EXTERNAL

MOSFET DRAIN

GATE DRIVE TO

EXTERNAL MOSFET

CHANNEL 1

OR CHANNEL 2

OUTPUT VOLTAGE

POR THRESHOLD

6V – 9V

V

TURN-ON

REF

THRESHOLD

MOSFET GATE

THRESHOLD

NORMAL OUTPUT VOLTAGE

HICCUP MODE

HOLD-OFF TIME

OUTPUT < 0.8  V

DEVICE

ENTERS

HICCUP MODE

REG

FAULT

CURRENT

ADM1052

FAULT
REMOVED

CHANNEL 1

OR CHANNEL 2

OUTPUT CURRENT

2 AMPS

Figure 2. Power-On Reset and Hiccup Mode

APPLICATIONS INFORMATION

PCB LAYOUT

For optimum voltage regulation, the loads should be placed as
close as possible to the source of the output MOSFETs and
feedback to the sense inputs should be taken from a point as
close to the loads as possible. The PCB tracks from the loads
back to the sense inputs should be separate from the output
tracks and not carry any load current.

12V

V

CC

FORCE 1

SENSE 1

V

3.3V

IN

FORCE 2

SENSE 2

GND

I

1

V

OUT1

LOAD 1 LOAD 2

I

2

V

OUT2

V

3.3V

IN

OFF ON

1:40 DUTY CYCLE

Similarly, the ground connection to the ADM1052 should be
made as close as possible to the ground of the loads, and the
ground track from the loads to the ADM1052 should not carry
load current. Correct and incorrect layout practice is illustrated
in Figure 3.

12V

V

CC

FORCE 1

SENSE 1

FORCE 2

SENSE 2

GND

I1 + I

LOAD 1

2

V

OUT1

V

OUT2

I

1

I

2

LOAD 2

VOLTAGE DROP
BETWEEN OUTPUT
AND LOAD

REV. A

CORRECT

VOLTAGE DROP

IN GROUND LEAD

INCORRECT

Figure 3. Correct and Incorrect Layout Practice

–7–

ADM1052

LEAVE OPEN OR

CONNECT TO

LOGIC SIGNALS

IF SHUTDOWN

REQUIRED

SHDN1

SHDN2

12V

V

CC

ADM1052

GND

1F

FORCE 1

SENSE 1

FORCE 2

SENSE 2

3.3V

3.3V

100F

V

OUT1

2  100F

100F

V

OUT2

2  100F

Figure 4. Typical Application Circuit

SUPPLY DECOUPLING

The supply to the drain of an external MOSFET should be decoupled
as close as possible to the drain pin of the device, with a 100 µF
capacitor to ground. The output from the source of the MOSFET
should be decoupled as close as possible to the source pin of the
device. Decoupling capacitors should be chosen to have a low
Equivalent Series Resistance (ESR). With the MOSFETs specified
and two 100 µF capacitors in parallel, the circuit will be stable for
load currents up to 2 A. The V

pin of the ADM1052 should be

CC

decoupled with a 1 µF capacitor to ground, connected as close as
possible to the V

and GND pins.

CC

In practice, the amount of decoupling required will depend on
the application. PC motherboards are notoriously noisy environ­ments, and it may be necessary to employ distributed decoupling
to achieve acceptable noise levels on the supply rails.

CHOICE OF MOSFET

As previously discussed, the load current at which an output
goes into hiccup mode depends on the on-resistance of the
external MOSFET. If the on-resistance is too low this current
may be very high. While the Test Circuit (Figure 1) shows the
use of the lower resistance PHD55N03LT from Philips on
Channel 1 and the use of the higher resistance MTD3055VL
from Motorola on Channel 2, the MTD3055VL is, in fact,
suitable for both channels. Similarly, the PHB11N06LT from
Philips is also suitable for both channels.

THERMAL CONSIDERATIONS

Heat generated in the external MOSFET must be dissipated
and the junction temperature of the device kept within accept­able limits. The power dissipated in the device is, of course, the
drain-source voltage multiplied by the load current. The required
thermal resistance to ambient is given by

␪

JA

= T

J(MAX)

– T

AMB(MAX)

/(V

DS(MAX)

× I

OUT(MAX)

)

Surface-mount MOSFETs such as those specified must rely on
heat conduction through the device leads and the PCB. One
square inch of copper (645 sq. mm) gives a thermal resistance of
around 60°C/W for a SOT-223 surface-mount package and
80°C/W for a SO-8 surface-mount package.

For higher power dissipation than can be accommodated by a
surface-mount package D

2

PAK or TO-220 devices are recom­mended. These should be mounted on a heatsink with a thermal
resistance low enough to maintain the required maximum junc­tion temperature.

C02127–0–1/01 (rev. A)

0.1574 (4.00)

0.1497 (3.80)

PIN 1

0.0098 (0.25)

0.0040 (0.10)

SEATING

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

8-Lead Small Outline Package

(Narrow Body, SO-8)

0.1968 (5.00)

0.1890 (4.80)

85

0.0500 (1.27)

PLANE

0.2440 (6.20)

0.2284 (5.80)

41

BSC

0.0192 (0.49)

0.0138 (0.35)

0.0688 (1.75)

0.0532 (1.35)

0.0098 (0.25)

0.0075 (0.19)

–8–

0.0196 (0.50)

0.0099 (0.25)

8

0.0500 (1.27)

0

0.0160 (0.41)

PRINTED IN U.S.A.

 45

REV. A