Datasheet ADM1028ARQ Datasheet (Analog Devices)

Remote Thermal Diode

a

FEATURES
On-Chip Temperature Sensor
External Temperature Measurement with Remote Diode
Interrupt and Over-Temperature Outputs
Fault-Tolerant Fan Control with Auto Hardware Trip Point
Remote Reset and Power-Down Functions
LDCM Support
System Management Bus (SMBus) Communications
Standby Mode to Minimize Power Consumption
Limit Comparison of all Monitored Values
DAC Output for Linear Fan Speed Control
Ramp Rate Register for Control of Rate of Change of

Fan Speed, Reduction of Fan Acoustics

APPLICATIONS
Network Servers and Personal Computers
Microprocessor-Based Office Equipment
Test Equipment and Measuring Instruments

Monitor with Linear Fan Control

ADM1028

GENERAL DESCRIPTION

The ADM1028 is a low-cost temperature monitor and fan
controller for microprocessor-based systems. The temperature
of a remote sensor diode may be measured, allowing monitoring
of processor temperature in single processor systems. An on-chip
temperature sensor monitors ambient system temperature.

Measured values can be read out via the System Management
Bus, and values for limit comparisons can be programmed in
over the same serial bus.

The ADM1028 also contains a DAC for fan speed control. An
automatic hardware temperature trip point is provided and the fan
will be driven to full speed if it is exceeded. A Ramp Rate Register
is provided to control the rate with which fan speed is increased or
decreased. This is to eliminate sudden changes in fan speed,
thereby reducing fan acoustics and prolonging the fan’s life.

Finally, the chip has remote reset and power-down functionality,
allowing it to be remotely shut down via the SMBus.

The ADM1028’s 3.0 V to 5.5 V supply voltage range, low
supply current, and SMBus make it ideal for a wide range of
applications. These include hardware monitoring applications
in PCs, electronic test equipment, and office electronics.

R_OFF

R_RST

AUXRST

RST

THERMA/NTEST_OUT

THERMB

FUNCTIONAL BLOCK DIAGRAM

V

CC3AUX

V

CC3AUX

10k⍀

RESET

FAN_SPD SHUTOFF
AND R_OFF RESET

D+

D–

V

CC3AUX

10k⍀

ADM1028

ANALOG

SIGNAL

CONDITIONING

POWER-ON
RESET

REMOTE
FUNCTION
REGISTER

ADDRESS

POINTER

REGISTER

ALERT

STATUS

REGISTER

ADC

2.5V

BANDGAP

REFERENCE

SERIAL BUS

INTERFACE

ANALOG O/P

REGISTER,

COUNTER

AND 8-BIT DAC

VALUE AND

LIMIT

REGISTERS

LIMIT

COMPARATORS

INTERRUPT

STATUS

REGISTERS

INT MASK

REGISTER

MASK

GATING

CONFIGURATION

REGISTER

SDA

SCL

FAN_SPD/NTEST_IN

INT

FAN_OFF

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

GPI

GND

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

1, 2

ADM1028–SPECIFICATIONS

(TA = T

Parameter Min Typ Max Unit Test Conditions

POWER SUPPLY

Supply Voltage, V
Supply Current, I

CC

CC

3.0 3.30 5.5 V

TEMPERATURE-TO-DIGITAL CONVERTER

Internal Sensor Accuracy ± 3 °C

Resolution 1 °C
External Diode Sensor Accuracy ± 5 °C

Resolution 1 °C
Remote Sensor Source Current 120 µA High Level (D+ = D– + 0.65 V)

ANALOG OUTPUT

Output Voltage Range 0 2.5 V
Total Unadjusted Error, TUE ± 3%I
Full-Scale Error ± 1 ±3%
Zero Error ± 2 LSB No Load
Differential Nonlinearity, DNL ± 1 LSB Monotonic by Design
Integral Nonlinearity ± 1 LSB
Output Source Current 2 mA
Output Sink Current 1 mA

THERMA OUTPUT

THERMA Pull-Up Resistance 9 12 14 kΩ

DIGITAL OUTPUT THERMA/NTEST_OUT,

R_OFF

Output High Voltage, V
Output Low Voltage, V

OL

OH

2.4 V I

OPEN-DRAIN DIGITAL OUTPUTS

(INT, THERMB, FAN_OFF, R_RST)

Output Low Voltage, V
High Level Output Leakage Current, I

OL

OH

FAN SPEED RAMP RATES

Counter Frequency 1 ± 50% 16 ± 50% Hz

OPEN-DRAIN SERIAL DATA

BUS OUTPUT (SDA)

Output Low Voltage, V
High Level Output Leakage Current, I

OL

OH

SERIAL BUS DIGITAL INPUTS

(SCL, SDA)

Input High Voltage, V
Input Low Voltage, V

IL

IH

2.1 V

Input Leakage Current ±5 µA
Hysteresis 500 mV Note 4

DIGITAL INPUT LOGIC LEVELS

(FAN_SPD/TEST_IN, GPI)

Input High Voltage, V
Input Low Voltage, V

IL

IH

2.2 V

DIGITAL INPUT LEAKAGE CURRENT

(ALL DIGITAL INPUTS)

Input High Current, I
Input Low Current, I
Input Capacitance, C

IL

IN

IH

–1 –0.005 µAV

3 6 9 pF Note 4

to T

MIN

, VCC = V

MAX

MIN

to V

, unless otherwise noted.)

MAX

2 3.2 mA Interface Inactive, ADC Active

± 2 °C60°C ≤ T

± 3 °C60°C ≤ T

≤ 100°C

A

≤ 100°C

A

7 µA Low Level (D+ = D– + 0.65 V)

= 2 mA

L

= 3.0 mA

OUT

0.4 V

0.4 V I

0.1 1 µAV

0.4 V I

0.1 1 µAV

= –3.0 mA

OUT

= V

OUT

= –3.0 mA

OUT

= V

OUT

CC

CC

3

0.8 V

0.8 V

= V

IN

+0.005 +1 µAV

IN

CC

= 0

–2–

REV. A

Parameter Min Typ Max Unit Test Conditions

SCLK

BUF

SU;STA

HD;STA

LOW

HIGH

SU;DAT

HD;DAT

4

100 kHz See Figure 1

4.7 µs See Figure 1

4.7 µs See Figure 1

4.0 µs See Figure 1

SU;STO

4.0 µs See Figure 1

4.7 µs See Figure 1

4.0 µs See Figure 1

r

f

1000 ns See Figure 1

300 ns See Figure 1
250 ns See Figure 1
300 ns See Figure 1

= 0.8 V for a falling edge and V

IL

= 2.2 V for a rising edge.

IH

SERIAL BUS TIMING

Clock Frequency, f
Bus Free Time, t
Start Setup Time, t
Start Hold Time, t
Stop Condition Setup Time, t
SCL Low Time, t
SCL High Time, t
SCL, SDA Rise Time, t
SCL, SDA Fall Time, t
Data Setup Time, t
Data Hold Time, t

NOTES

1

Typicals are at TA = 25°C and represent most likely parametric norm. Standby current typ is measured with VCC = 3.3 V.

2

Timing specifications are tested at logic levels of V

3

IOH for FAN_OFF guaranteed by design, not production tested.

4

Guaranteed by design, not production tested.

Specifications subject to change without notice.

ADM1028

ABSOLUTE MAXIMUM RATINGS

*

Positive Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . 6.5 V

Voltage on Digital Inputs Except Therm

and D– . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6.5 V

Voltage on Therm Pin . . . . . . . . . . . . . . –0.3 V to V

+ 0.3 V

CC

Voltage on D– Pin . . . . . . . . . . . . . . . . . . . . –0.3 V to + 0.6 V

Voltage on Any Other Input . . . . . . . . . . –0.3 V to V

+ 0.3 V

CC

or Output Pin

Input Current at Any Pin . . . . . . . . . . . . . . . . . . . . . . . ± 5 mA

Package Input Current . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA

Maximum Junction Temperature (T

max) . . . . . . . . . . 150°C

J

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperatures

Soldering (10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

IR Reflow Peak Temperature . . . . . . . . . . . . . . . . . . . 220°C

ESD Rating (Human Body Model) . . . . . . . . . . . . . . . 4000 V

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional. Operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

t

t

F

HIGH

SCL

t

LOW

t

HD; STA

t

R

t

HD; DAT

THERMAL CHARACTERISTICS

16-Lead QSOP Package:

θ

= 105°C/W, θJC = 39°C/W

JA

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

ADM1028ARQ 0°C to 100°C Shrink Small Outline RQ-16

Package (QSOP)

t

HD; STA

t

SU; DAT

t

SU; STA

t

SU; STO

REV. A

SDA

t

BUF

PS

S

Figure 1. Serial Bus Timing Diagram

–3–

P

ADM1028

PIN CONFIGURATION

FAN_OFF

GPI

AUXRST

GND

V

CC3AUX

RST

R_RST

FAN_SPD/NTEST_IN

1

2

3

ADM1028

4

TOP VIEW

5

(Not to Scale)

6

7

8

16

SDA

15

SCL

14

INT

13

R_OFF

12

THERMB

11

THERMA/NTEST_OUT

10

D+

9

D–

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Description

1 FAN_OFF Digital Output (Open Drain) Fan Off Request. When asserted low, this indicates a

request to shut off the fan independent of the FAN_SPD output. When negated (output
FET off) it indicates that the fan may be turned on.

2 GPI Digital Input (12 V tolerant). This pin is a general-purpose logic input with 12 V toler-

ance. It can be programmed as an active high or active low input that sets Bit 4 of the
Interrupt Status Register. A voltage >2.2 V on this pin, represents a Logic “1,” while a
floating condition is interpreted as Logic “0.”

3 AUXRST Digital Input. This pin can be driven low as an input to reset the ADM1028.
4 GND Ground. Power and signal ground.
5V

CC3AUX

Power 3.3 V Aux. Power source and voltage monitor input for power-on reset.

6 RST Digital Input. This pin can be pulled low externally to indicate to the ADM1028 that the

main system power has been removed. The ADM1028 will shut off the FAN_SPD out­put and reset its R_OFF output.

7 R_RST Digital Output (Open Drain). This pin is a remote reset output that pulses low on

receipt of a specific SMBus message.

8 FAN_SPD/NTEST_IN Analog Output/Test Input. An active-high input that enables NAND board-level

connectivity testing. Refer to section on NAND testing.
Used as an analog output for fan speed control when NAND test is not selected.

9 D– Remote Thermal Diode Negative Input. This is the negative input (current sink) from

the remote thermal diode. This also serves as the negative input into the A/D.

10 D+ Remote Thermal Diode Positive Input. This is the positive input (current source) from

the remote thermal diode. This serves as the positive input into the A/D.

11 THERMA/NTEST_OUT Digital Output (Open Drain with Integrated V

Pull-Up). An active low thermal

CC3AUX

overload output that indicates a violation of a temperature setpoint (over temperature).
The fan is on full-speed whenever this pin is asserted low. Acts as the output of the NAND
Tree when the ADM1028 is in NAND Tree Test Mode.

12 THERMB Digital Output (Open Drain). This pin is a second THERM signal. It can be used to

drive external circuitry with a different external pull-up supply rail.

13 R_OFF Digital Output or Open Drain with Integrated V

Pull-Up. Remote off (power-

CC3AUX

down) output. This pin is driven high on receipt of a specific SMBus message. The pin
(and its associated register bit) remain high until the RST input is asserted low.

14 INT Digital Output (Open Drain), System Interrupt Output. This signal indicates a violation

of a set trip point. The output is enabled when Bit 1 of the Configuration Register is set

to 1. The default state is disabled.
15 SCL Digital Input. SMBus Clock.
16 SDA Digital I/O (Open Drain). SMBus Bidirectional Data.

–4–

REV. A

Typical Performance Characteristics–ADM1028

SCLK FREQUENCY – kHz

SUPPLY CURRENT – mA

1.77

1 5 10 25 50 75 100

1.67

1.72

1.82

1.87

1.92

1.97

2.02

250 500 750 1000

VDD = 5V

VDD = 3.3V

30

20

10

0

–10

TEMPERATURE ERROR – ⴗC

–20

–30

1

D+ TO GND

D+ TO V

DD

LEAKAGE RESISTANCE – M⍀

10 100

TPC 1. Temperature Error vs. PC Board Track Resistance
(D+ to V

)

DD

14

12

10

8

6

4

TEMPERATURE ERROR – ⴗC

2

0

1

10 100k 1000M

VIN = 250mV p-p

= 100mV p-p

V

IN

10k 100M1k 10M100 1M

FREQUENCY – Hz

TPC 2. Temperature Error vs. Power Supply
Noise Frequency

4

3

2

1

0

–1

ERROR – ⴗC

–2

–3

–4

–5

0 102030405060708090

LOWER SPEC LEVEL

UPPER SPEC LEVEL

100

TEMPERATURE – ⴗC

TPC 4. Temperature Error of ADM1028 vs. Pentium® III
Temperature

40

35

30

25

20

15

10

TEMPERATURE ERROR – ⴗC

5

0

–5

010203040506070

CAPACITANCE – nF

TPC 5. Temperature Error vs. Capacitance Between
D+ and D–

14

13

12

11

10

9

8

7

6

5

4

3

TEMPERATURE ERROR – ⴗC

2

1

0

1 10 100 1k 10k 100k 1M 10M 100M 1G

TPC 3. Temperature Error vs. Common-Mode
Noise Frequency

REV. A

VIN = 100mV p-p

VIN = 50mV p-p

VIN = 25mV p-p

FREQUENCY – Hz

TPC 6. Standby Current vs. Clock Frequency

–5–

ADM1028

2

VIN = 10mV p-p

1

TEMPERATURE ERROR – ⴗC

0

1

1k 1M10 100 10k 100k 10M 100M 1B

FREQUENCY – Hz

TPC 7. Temperature Error vs. Differential-Mode
Noise Frequency

FUNCTIONAL DESCRIPTION

The ADM1028 is a low-cost temperature monitor and fan con­troller for microprocessor-based systems. The temperature of
a remote sensor diode may be measured, allowing monitoring
of processor temperature in a single-processor system. An on­chip temperature sensor allows monitoring of system ambient
temperature.

Measured values can be read out via the serial System Manage­ment Bus, and values for limit comparisons can be programmed
in over the same serial bus.

The ADM1028 also contains a DAC for fan speed control. An
automatic hardware temperature trip point is provided for fault
tolerant fan control and the fan will be driven to full speed if this
is exceeded. Two interrupt outputs are provided, which will be
asserted if the software or hardware limits are exceeded.

Finally, the chip has remote reset and shutdown capabilities.

INTERNAL REGISTERS OF THE ADM1028

A brief description of the ADM1028’s principal internal registers
is given below. More detailed information on the function of
each register is given in Tables III to IX.

Configuration Register: Provides control and configuration.

Address Pointer Register: This register contains the address

that selects one of the other internal registers. When writing to
the ADM1028, the first byte of data is always a register address,
which is written to the Address Pointer Register.

Interrupt (INT) Status Register: This register provides sta­tus of each Interrupt event.

Interrupt (INT) Mask Register: Allows masking of individual
interrupt sources.

Value and Limit Registers: The results of temperature mea­surements are stored in these registers, along with their limit values.

Analog Output Register: The code controlling the analog
output DAC is stored in this register.

Alert Status Register: Indicates the status of the THERM
signal and GPI pin.

Remote Function Register: This register allows control of the
R_RST and R_OFF outputs.

2.3

2.2

2.1

2.0

1.9

1.8

1.7

STANDBY SUPPLY CURRENT – mA

1.6

1.5

–40

–20 0 20 40 60 80 100 130–10–30 10 30 50 70 90 120

VDD = 5.5V

VDD = 3.0V

VDD = 3.3V

TEMPERATURE – ⴗC

TPC 8. Standby Supply Current vs. Temperature

Fan Speed Ramp Register: This register allows enabling/
disabling of DAC ramp, as well as providing control of fan
speed ramp rate.

SERIAL BUS INTERFACE

Control of the ADM1028 is carried out via the serial bus. The
ADM1028 is connected to this bus as a slave device, under the
control of a master device, e.g. the 810 chipset.

The ADM1028 has a 7-bit serial bus address. When the device
powers up, it will do so with a default serial bus address. The
SMBus address for the ADM1028 is 0101110 binary.

The serial bus protocol operates as follows:

1. The master initiates data transfer by establishing a START
condition, defined as a high-to-low transition on the serial
data line SDA, while the serial clock line SCL remains high.
This indicates that an address/data stream will follow. All
slave peripherals connected to the serial bus respond to the
START condition, and shift in the next eight bits, consisting
of a 7-bit address (MSB first) plus an R/W bit, which deter­mines the direction of the data transfer, i.e., whether data
will be written to or read from the slave device.

The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the low
period before the ninth clock pulse, known as the Acknowl­edge Bit. All other devices on the bus now remain idle while
the selected device waits for data to be read from or written
to it. If the R/W bit is a 0, the master will write to the slave
device. If the R/W bit is a 1, the master will read from the
slave device.

2. Data is sent over the serial bus in sequences of nine clock
pulses, eight bits of data followed by an Acknowledge Bit
from the slave device. Transitions on the data line must occur
during the low period of the clock signal and remain stable
during the high period, as a low-to-high transition when the
clock is high may be interpreted as a STOP signal. The num­ber of data bytes that can be transmitted over the serial bus
in a single READ or WRITE operation is limited only by
what the master and slave devices can handle.

3. When all data bytes have been read or written, stop condi­tions are established. In WRITE mode, the master will pull
the data line high during the tenth clock pulse to assert a

–6–

REV. A

ADM1028

STOP condition. In READ mode, the master device will
override the acknowledge bit by pulling the data line high
during the low period before the ninth clock pulse. This is
known as No Acknowledge. The master will then take the
data line low during the low period before the tenth clock
pulse, then high during the tenth clock pulse to assert a
STOP condition.

Any number of bytes of data may be transferred over the serial
bus in one operation, but it is not possible to mix read and write
in one operation, because the type of operation is determined at
the beginning and cannot subsequently be changed without
starting a new operation.

In the case of the ADM1028, write operations contain either
one or two bytes, and read operations contain one byte, and
perform the following functions:

To write data to one of the device data registers or read data
from it, the Address Pointer Register must be set so that the
correct data register is addressed, then data can be written into
that register or read from it. The first byte of a write operation
always contains an address that is stored in the Address Pointer
Register. If data is to be written to the device, the write opera­tion contains a second data byte that is written to the register
selected by the address pointer register.

19

SCL

This is illustrated in Figure 2a. The device address is sent over
the bus followed by R/W set to 0. This is followed by two data
bytes. The first data byte is the address of the internal data
register to be written to, which is stored in the Address Pointer
Register. The second data byte is the data to be written to the
internal data register.

When reading data from a register there is only one possibility:

1. The serial bus address is written to the device along with the
address pointer register value. The ADM1028 should then
acknowledge the write by pulling SDA low during the ninth
clock pulse. The master does not generate a STOP condition
but issues a new START condition. The serial bus address
is again sent but with the R/W bit high, indicating a READ
operation. The ADM1028 will then return the data from the
selected register, and a No Acknowledge is generated to signify
the end of the read operation. The master will then initiate a
STOP condition to end the transaction and release the SMBus.

In Figures 2a and 2b, the serial bus address is shown as the
default value 0101110.

1

9

SDA

START BY

MASTER

0

10

1

FRAME 1

SERIAL BUS ADDRESS BYTE

1

10 D7D6D5 D4 D3

SCL (CONTINUED)

SDA (CONTINUED)

R/W

ACK. BY

ADM1028

1

D7 D6

ADDRESS POINTER REGISTER BYTE

D5 D4 D3

FRAME 2

FRAME 3

DATA BYTE

D2

D2

D1

D1 D0

D0

9

ACK. BY

ADM1028

ACK. BY

ADM1028

STOP BY
MASTER

Figure 2a. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register

SCL

SDA

START BY

MASTER

SCL

19

0

101110 D7D6D5 D4 D3

FRAME 1

SERIAL BUS ADDRESS BYTE

191

R/W

ADM1028

ACK. BY

1

ADDRESS POINTER REGISTER BYTE

FRAME 2

D2

D1

D0

9

ACK. BY

ADM1028

9

REV. A

SDA

START BY

MASTER

0

101110 D7D6D5 D4 D3 D2 D1

FRAME 1

SERIAL BUS ADDRESS BYTE

R/W

ACK. BY

ADM1028

FRAME 2

DATA BYTE FROM ADM1028

Figure 2b. Reading Data from the ADM1028

–7–

D0

NO ACK.

BY MASTER

STOP BY
MASTER

ADM1028

TEMPERATURE MEASUREMENT SYSTEM
Internal Temperature Measurement

The ADM1028 contains an on-chip bandgap temperature sen­sor. The on-chip ADC performs conversions on the output of
this sensor and outputs the temperature data in 8-bit two’s
complement format. The format of the temperature data is
shown in Table I.

Table I. Temperature Data Format

Temperature Digital Output

–128°C 1000 0000
–125°C 1000 0011
–100°C 1001 1100
–75°C 1011 0101
–50°C 1100 1110
–25°C 1110 0111
–1°C 1111 1111
0°C 0000 0000
+1°C 0000 0001
+10°C 0000 1010
+25°C 0001 1001
+50°C 0011 0010
+75°C 0100 1011
+100°C 0110 0100
+125°C 0111 1101
+127°C 0111 1111

External Temperature Measurement

The ADM1028 can measure the temperature of an external
diode sensor or diode-connected transistor, connected to Pins 9
and 10.

Pins 9 and 10 are a dedicated temperature input channel. The
default functions of Pins 11 and 12 are as THERM outputs to
indicate over-temperature conditions.

The forward voltage of a diode or diode-connected transistor,
operated at a constant current, exhibits a negative temperature
coefficient of about –2 mV/°C. Unfortunately, the absolute value
of V

varies from device to device, and individual calibration

BE

is required to null this out, making the technique unsuitable
for mass production.

The technique used in the ADM1028 is to measure the change
in V

when the device is operated at two different currents.

BE

This is given by:

∆V

= KT/q × ln(N)

BE

where:

K is Boltzmann’s constant.
q is charge on the carrier.
T is absolute temperature in Kelvins.
N is ratio of the two currents.

Figure 3 shows the input signal conditioning used to measure
the output of an external temperature sensor. This figure shows
the external sensor as a substrate transistor, provided for tempera­ture monitoring on some microprocessors, but it could equally
well be a discrete transistor.

If a discrete transistor is used, the collector will not be grounded,
and should be linked to the base. If a PNP transistor is used, the
base is connected to the D– input and the emitter to the D+
input. If an NPN transistor is used, the emitter is connected to
the D– input and the base to the D+ input.

–8–

To prevent ground noise interfering with the measurement, the
more negative terminal of the sensor is not referenced to ground,
but is biased above ground by an internal diode at the D– input.

If the sensor is used in a very noisy environment, a capacitor of
value up to 1000 pF may be placed between the D+ and D–
inputs to filter the noise.

To measure ∆V

, the sensor is switched between operating

BE

currents of I and N × I. The resulting waveform is passed
through a 65 kHz low-pass filter to remove noise, thence to a
chopper-stabilized amplifier that performs the functions of
amplification and rectification of the waveform to produce a dc
voltage proportional to ∆V

. This voltage is measured by the

BE

ADC to give a temperature output in 8-bit two’s complement
format. To further reduce the effects of noise, digital filtering is
performed by averaging the results of 16 measurement cycles.
An external temperature measurement nominally takes 9.6 ms.

V

LOW-PASS

FILTER

fC = 65kHz

DD

V

OUT+

TO
ADC

V

OUT–

REMOTE

SENSING

TRANSISTOR

IN ⴛ II

D+

D–

BIAS

DIODE

BIAS

Figure 3. Signal Conditioning

LAYOUT CONSIDERATIONS

Digital boards can be electrically noisy environments, and care
must be taken to protect the analog inputs from noise, particu­larly when measuring the very small voltages from a remote
diode sensor. The following precautions should be taken:

1. Place the ADM1028 as close as possible to the remote sens­ing diode. Provided that the worst noise sources such as clock
generators, data/address buses and CRTs are avoided, this
distance can be 4 to 8 inches.

2. Route the D+ and D– tracks close together, in parallel with
grounded guard tracks on each side. Provide a ground plane
under the tracks if possible.

3. Use wide tracks to minimize inductance and reduce noise
pickup. Ten mil track minimum width and spacing is rec­ommended.

4. Try to minimize the number of copper/solder joints, which
can cause thermocouple effects. Where copper/solder joints
are used, make sure that they are in both the D+ and D–
path and at the same temperature.

Thermocouple effects should not be a major problem as 1°C
corresponds to about 200 µV, and thermocouple voltages are
about 3 µV/

o

C of temperature difference. Unless there are
two thermocouples with a big temperature differential between
them, thermocouple voltages should be much less than 200 µV.

5. Place 0.1 µF bypass and 2200 pF input filter capacitors close
to the ADM1028.

6. If the distance to the remote sensor is more than 8 inches, the
use of twisted-pair cable is recommended. This will work up
to about 6 to 12 feet.

REV. A

ADM1028

12V

Q4
BD132
TIP32A

R4
100k⍀

R5

100k⍀

FAN_SPD

R6

5k⍀

Q1/Q2

MBT3904

DUAL

R2

3.9k⍀

R1

1k⍀

R3

100⍀

Q3
BC556
2N3906

7. For really long distances (up to 100 feet) use shielded twisted­pair such as Belden #8451 microphone cable. Connect the
twisted pair to D+ and D– and the shield to GND close to
the ADM1028. Leave the remote end of the shield uncon­nected to avoid ground loops.

GND

D+

D–

GND

10MIL

10MIL

10MIL

10MIL

10MIL

10MIL

10MIL

Figure 4. Arrangement of Signal Tracks

Because the measurement technique uses switched current
sources, excessive cable and/or filter capacitance can affect the
measurement. When using long cables, the filter capacitor C1
may be reduced or removed. In any case, the total shunt capaci­tance should not exceed 1000 pF.

Cable resistance can also introduce errors. 1 Ω series resistance
introduces about 0.5°C error.

ANALOG OUTPUT

The ADM1028 has a single analog output (FAN_SPD) from an
unsigned 8-bit DAC which produces 0 V–2.5 V. The analog
output register defaults to 00 during power-on reset, which pro­duces minimum fan speed. The analog output may be amplified
and buffered with external circuitry such as an op amp and tran­sistor to provide fan speed control.

Suitable fan drive circuits are given in Figures 5a to 5e. When
using any of these circuits, the following points should be noted:

1. All of these circuits will provide an output range from zero

to almost +V

FAN

.

2. To amplify the 2.5 V range of the analog output up to

, the gain of these circuits needs to be set as shown.

+V

FAN

3. Care must be taken when choosing the op amp to ensure

that its input common-mode range and output voltage swing
are suitable.

4. The op amp may be powered from the +V rail alone. If it is

powered from +V then the input common-mode range
should include ground to accommodate the minimum out­put voltage of the DAC, and the output voltage should
swing below 0.6 V to ensure that the transistor can be
turned fully off.

5. In all these circuits, the output transistor must have an I

greater than the maximum fan current, and be capable of
dissipating power due to the voltage dropped across it when
the fan is not operating at full-speed.

6. If the fan motor produces a large back e.m.f. when switched

off, it may be necessary to add clamp diodes to protect the
output transistors in the event that the output very quickly
goes from full-scale to zero.

Figure 5c shows how the FAN_OFF signal may be used (with
any of the control circuits) to gate the fan on and off indepen­dent of the value on the FAN_SPD/NTEST_IN pin.

REV. A

CMAX

5V

FAN_SPD

R1
10k⍀

AD8541

+

R2

15k⍀

Figure 5a. 5 V Fan Circuit with Op Amp

R4

1k⍀

FAN_SPD

R1
10k⍀

AD8519

+

R3

1k⍀

R2

39k⍀

Figure 5b. 12 V Fan Circuit with Op Amp and PNP
Transistor

R3

R2

39k⍀

1k⍀

100k⍀

3.3V

R4

FAN_SPD

R1
10k⍀

AD8519

+

FAN_OFF

Figure 5c. 12 V Fan Circuit with Op Amp and
P-Channel MOSFET

FAN_SPD

5k⍀

R3

100k⍀

MBT3904

R5

Q1/Q2

DUAL

R4
100k⍀

3.9k⍀

1k⍀

R2

R1

Figure 5d. Discrete 12 V Fan Drive Circuit with
P-Channel MOSFET, Single Supply

Figure 5e. Discrete 12 V Fan Drive Circuit with
Bipolar Output Single Supply

–9–

Q1
NDT452 P

5V
FAN

12V

Q1
BD136
2SA968

12V

Q1
NDT452 P

Q2
MMFT305 5V

12V

Q3
NDT452 P

ADM1028

FAULT TOLERANT FAN CONTROL

The ADM1028 incorporates a fault tolerant fan control capability
that is tied to operation of the THERMA, THERMB outputs. It
can override the setting of the analog output and force it to
maximum to give full fan speed in the event of a critical over­temperature problem, even if, for some reason, this has not been
handled by the system software.

There are two temperature set point registers that will activate
the fault tolerant fan control. One of these limits is program­mable by the user and one is a hardware (read-only) register
that will operate if the user does not program any limit. The
fault tolerant fan control is activated if a limit is exceeded for
three or more consecutive readings. These limits are separate
from the normal high and low temperature limits for the INT
output, which do not affect the fault tolerant fan control or
THERM outputs.

A hardware limit of 100°C is programmed into the register at
address 18h, for the remote diode Default THERM limit. This
is the default limit and the analog output will be forced to full­scale if the remote sensor reads more than 100°C. This makes
the fault tolerant fan control fail-safe in that it will operate at
this temperature even if the user has programmed no other
limit, or in the event of a software malfunction. Similarly, the
Default Internal Temp THERM limit held in register 17h,
forces the analog output full-scale if the ambient temperature
measured is more than 70°C.

The user may override the default limits by programming a new
limit into register 14h for the remote sensor and a new limit into
register 13h for the internal sensor. The default value in register
14h is the same as for the read-only register (100°C), but it may
be programmed with higher or lower values.

Once registers 13h and 14h have been programmed, or if the
defaults are acceptable, Bit 3 of the configuration register must
be set to “1.” This bit is a write-once bit that can only be writ­ten to “1,” and it has two effects:

1. It makes the values in registers 13h and 14h the active limits,
and disables read-only registers 17h and 18h.

2. It locks the data into registers 13h and 14h, so that it cannot
be changed until the lock bit is reset, either when AUXRST
or RST is asserted, or a Power-On Reset occurs.

Once the hardware override of the analog output is triggered, it
will only return to normal operation after three consecutive
measurements that are 5 degrees lower than the set limit.

Whenever FAN_SPD output is forced to full-scale, the FAN_OFF
output is negated.

to the Fan Speed Register, the counter begins counting up or
down (depending on whether the current value is greater or
less than the target value). The counter will then count at the
rate specified by the ramp rate bits of the Fan Speed Ramp
Register. Once the counter reaches the target value the counter
will stop counting. The FAN_SPD value is derived from the
output of the counter. If a new value is written to the Fan Speed
Register while a ramp function is occurring, the counter may
change count direction to reach the new target value. The operation of
THERM is independent of the fan speed ramping mechanism.
Thus, THERM will assert immediately for over-temperature
conditions.

FAN SPEED

REGISTER

UP/DOWN

FAN SPEED RAMP

RATE REGISTER

RAMP ENABLE

RAMP RATE

START/STOP

COUNTER

(CURRENT SPEED)

COMPARE

FAN SPD

DAC

Figure 6.

THE ADM1028 INTERRUPT SYSTEM

The ADM1028 has three interrupt outputs, INT, THERMA
and THERMB. These have different functions. INT responds
to violations of software programmed temperature limits and its
interrupt sources are maskable, as described in more detail later.
Interrupts and status bits are only set if a limit is exceeded for at
least three consecutive conversions.

Operation of the INT output is illustrated in Figure 7. Assum­ing that the temperature starts off within the programmed limits
and that temperature interrupt sources are not masked, INT will
go low if the temperature measured by the external sensor goes
outside the programmed high or low temperature limit for the
sensor. INT also goes low whenever THERM is low.

100ⴗC

90ⴗC

80ⴗC

70ⴗC

60ⴗC

50ⴗC

40ⴗC

TEMP

LOW LIMIT

HIGH LIMIT

FAN SPEED RAMPING

The ADM1028 device contains a Fan Speed Ramping mechanism
that is accomplished using an 8-bit counter and a control
register. On power-up, or an assertion of RST or AUXRST, the
Fan Speed Register, counter, and Fan Speed Ramp Register are
initialized to 0x00. The fan speed ramping mechanism is disabled
by default and any value written to the Fan Speed Register is
immediately reflected on the FAN_SPD output. Setting Bit 0 of
the Fan Speed Ramp Rate Register enables the ramping mecha­nism. The counter is then preloaded with the current value
contained in the Fan Speed Register, which prevents the fan
speed from changing until a new value is written to the Fan
Speed Register. When a new target Fan Speed Value is written

–10–

INT

*INT CLEARED BY
SOFTWARE

Figure 7. Operation of

**

T

INTERRUPT

HIGH

LOGIC REARMED

HERE

INT

Output

Once the interrupt has been cleared, it will not be reasserted even if
the temperature remains outside the limit previously exceeded.
However, INT will be rearmed if the temperature falls back within
the set limits for three consecutive conversions. Once the INT
function has been rearmed, it will then be reasserted once a
limit is exceeded for three consecutive conversions.

REV. A

ADM1028

STATUS

BIT

MASK

BIT

MASK GATING ⴛ 8

HIGH
LIMIT

VALUE

LOW

LIMIT

FROM

VALUE

AND LIMIT

REGISTERS

1 = OUT

OF

LIMIT

INT. TEMP

FLAG1

FLAG2

INT. THERM

GPI

EXT. TEMP

EXT. THERM

DIODE FAULT

0

1

2

3
4
5

6

7

MASKING

DATA

FROM BUS

EIGHT MASK BITS

(SAME BIT

ORDER AS

STATUS

REGISTER)

HIGH
AND
LOW

LIMIT

COMPARA-

TORS

INTERRUPT

MASK

REGISTER

INTERRUPT

STATUS

REGISTER

DATA

DEMULTI-

PLEXER

CONFIGURATION

REGISTER

INT_ENABLE

INT

INTERRUPT MASKING

Any of the bits in the Interrupt Status Register can be masked out
by setting the corresponding mask bit in the Interrupt Mask Regis­ter. That interrupt source will then no longer generate an interrupt.
However, the bits in the status register will be set as normal.

INTERRUPT CLEARING

The Interrupt Status Register reflects out-of-limit conditions.
The Status bits may be individually cleared by writing a “1” to
the appropriate status bits. Writing a “1” to Bits 1 and 2 causes
software interrupts to be generated. Bit 4 (GPI) of the Interrupt
Status Register reflects the current status of the GPI pin, and so
cannot be cleared by writing to this bit.

The INT output is cleared with the INT_Enable bit, which is
Bit 1 of the Configuration Register, without affecting the con­tents of the Interrupt (INT) Status Registers.

THERM OUTPUTS

The THERMA, THERMB signals are functionally identical.
These system over-temperature outputs will assert together
when an over-temperature is detected. THERMA (Pin 11) is
an open drain digital output which has an integrated pull-up resis­tor to V

. THERMB is an open drain digital output,

CC3AUX

intended to drive external circuitry operating at a different
supply voltage level.

THERM OPERATING MODE

THERM only responds to the “hardware” temperature limits at
addresses 14h and 18h, not to the software programmed limits.
The function of these registers was described earlier with regard
to fault tolerant fan speed control.

THERM will go low if the hardware temperature limit is exceeded
for three consecutive measurements. It will remain low until the
temperature falls five degrees below the limit for three consecu­tive measurements. While THERM is low, the analog output will
go to FFh to boost a controlled fan to full speed and FAN_OFF
will be negated.

HARDWARE

TRIP POINT

5ⴗ

TEMP

THERM

PROGRAMMED

ANALOG

OUTPUT

VALUE

Figure 8. Operation of

FFh

THERM

PREVIOUS FAN

SPEED VALUE

Outputs

When the Fault Tolerant Fan Control state is exited, the analog
FAN_SPD output returns to its previously programmed value,
which may have been changed during the time that the FAN_SPD
output was forced to FFh.

INTERRUPT STRUCTURE

The Interrupt Structure of the ADM1028 is shown in more
detail in Figure 9. As each measurement value is obtained and
stored in the appropriate value register, the value and the limits
from the corresponding limit registers are fed to the high and
low limit comparators. The result of each comparison (1 = out
of limit, 0 = in limit) is routed to the corresponding bit input of
the Interrupt Status Register via a data demultiplexer, and used
to set that bit high or low as appropriate.

The Interrupt Mask Register has bits corresponding to each of
the Interrupt Status Register Bits. Setting an Interrupt Mask Bit
high forces the corresponding Status Bit output low, while set­ting an Interrupt Mask Bit low allows the corresponding Status
Bit to be asserted. After masking, the status bits are all OR’d
together to produce the INT output, which will pull low if any
unmasked status bit goes high, i.e. when any measured value
goes out of limit.

The INT output is enabled when Bit 1 of the Configuration
Register (INT_Enable) is high.

REV. A

Figure 9. Interrupt Register Structure

–11–

ADM1028

GENERAL-PURPOSE LOGIC INPUT (GPI)

Pin 2 is used as a general-purpose logic input with 12 V toler­ance. The GPI input may be programmed to be active high or
active low by clearing or setting Bit 6 of the Configuration Reg­ister. The default value is active high. Bit 4 of the Interrupt Status
register follows the state (or inverted state) of GPI and will gen­erate an interrupt when it is set to 1, like any other input to the
Interrupt Status Register. However, the GPI bit is not latched
in the Status Register and always reflects the current state (or
inverted state) of the GPI input. If it is 1, it will not be cleared
by reading the Status Register.

POWER-ON RESET

When the ADM1028 is powered up, it will initiate a power-on
reset sequence when the supply voltage V

CC3AUX

rises above
the power-on reset threshold, with registers being reset to their
power-on values. Normal operation will begin when the supply
voltage rises above the reset threshold. Registers whose power­on values are not shown have power-on conditions that are
indeterminate (this includes the Value and Limit Registers). In
most applications, usually the first action after power-on would
be to write limits into the Limit Registers.

Power-on reset clears or initializes the following registers (the
initialized values are shown in Table III):

• Configuration Register

• Interrupt Status Register

• Interrupt Mask Register

• Analog Output Register

• Programmable Trip Point Registers

The ADM1028 can also be reset by taking AUXRST low as an
input. All registers will be reset to their default values and the
ADC will remain inactive as long as AUXRST is below the
reset threshold. Taking the RST pin low will cause the following
registers to be reset.

• Bit 3 of the Configuration Register (Programmable THERM

Limit Lock Bit)

• DAC Output, Fan Speed

NAND TREE TEST

A NAND tree is provided in the ADM1028 for Automated Test
Equipment (ATE) board level connectivity testing. The device
is placed into NAND tree test mode by powering up with pin
FAN_SPD/NTEST_IN (Pin 8) held high. This pin is sampled
and its state at power-up is latched. If it is connected high, then
the NAND tree test mode is invoked. NAND tree test mode will
only be exited once the ADM1028 is powered down.

In NAND tree test mode, all digital inputs may be tested as
illustrated in Table II. THERMA/NTEST_OUT will become
the NAND tree output pin.

The structure of the NAND Tree is shown in Figure 10. To per­form a NAND Tree test, all pins are initially driven low. The
test vectors set all inputs low then, one-by-one, toggles them
high (keeping them high). Exercising the test circuit with this
“walking one” pattern, starting with the input closest to the
output of the tree, cycling toward the farthest, causes the out­put of the tree to toggle with each input change. Allow for a
typical propagation delay of 500 ns.

POWER-ON

RESET

CLK

FAN_SPD/
NTEST_IN

RST

AUXRST

GPI

SDA

SCL

DQ

LATCH

ENABLE

THERMA/
NTEST_OUT

Figure 10. NAND Tree

CONFIGURING THE INTERRUPT

On power-up, the Interrupt functionality of the device is disabled.
The Configuration Register (0x40) must be written to, in order
to enable the interrupt output. The INT_Enable bit (Bit 1) of
the Register should be set to 1.

INITIALIZATION (SOFT RESET)

Soft reset performs a similar, but not identical, function to
power-on reset. It restores the power-on default values to the
Configuration Register, the Interrupt Status Register and the
Interrupt Mask Register. The Limit Registers remain unchanged.
It rearms the INT structure but not the THERM structure.

Soft reset is accomplished by setting Bit 4 of the Configuration
Register high. This bit automatically clears after being set.

Unlike clearing INT, where the temperature must fall back within
the set limits for three conversions before the INT function is
rearmed, the soft reset allows INT to be pulled low immediately
after the soft reset.

–12–

Table II. Test Vectors

RST AUXRST GPI SDA SCL THERMA

00 000 1
00 001 0
00 011 1
00 111 0
01 111 1
11 111 0

REV. A

ADM1028

Table III. ADM1028 Registers

Register Name Address A7–A0 in Hex Comments

Value Registers 0x14–0x38 See Table IV
Company ID 0x3E This location will contain the company identification number. This

register is read only.

Revision 0x3F This location will contain the revision number of the part in the

lower four bits of the register [3:0]. The upper four bits reflect the
ADM1028 Version Number [7:4]. The first version is 1101. The
next version of ADM1028 would be 1110, etc. For instance, if the
stepping were A0 and this part is an ADM1028, this register would

read 1101 0000. This register is read only.
Configuration Register 0x40 See Table V. Power-on value = 0010 0001.
Interrupt Status Register 0x41 See Table VI. Power-on value = 0000 0000.
Interrupt Mask Register 0x43 See Table VII. Power-on value = 0000 0000.
Manufacturer Test 0x44–0x4A Test Registers for manufacturer’s use only. Do not write to these

registers.
Remote Function 0x4B See Table VIII. Power-on value = 0000 0000.
Alert Status 0x4C See Table IX. Power-on value = 0000 0000.

Fan Speed Ramp Register 0xCO See Table X. Power-on value = 0000 0000.

Table IV. Registers 0x13–0x3A Value Registers

Address Read/Write Description

0x13 Read/Write Programmable Internal Therm Automatic Trip Point—Default 127°C. This register can only be

written to if the write once bit in the Configuration Register (0x40, Bit 3) has not been set.

0x14 Read/Write Programmable Remote Thermal Diode Automatic Trip Point—Default 100°C. This register

can only be written to if the write once bit in the Configuration Register (0x40, Bit 3) has

not been set.
0x15 Read/Write Test register for manufacturer’s use only. Do not write to this register.
0x17 Read Only Default Internal Therm Automatic Trip Point—Default 70°C. Cannot be changed. Disabled

when Bit 3 of Configuration Register is set.
0x18 Read Only Default Remote Thermal Diode Automatic Trip Point—Default 100°C. Cannot be changed.

Disabled when Bit 3 of Configuration Register is set.
0x19 Read/Write Analog Output, FAN_SPD (Defaults to 0x00h).
0x26 Read Only External/Remote Temperature Value.
0x27 Read Only Internal Temperature Value.
0x37 Read/Write External/Remote Temperature High Limit—Default +127°C.
0x38 Read/Write External/Remote Temperature Low Limit—Default –128°C.
0x39 Read/Write Internal Temperature High Limit—Default +127°C.
0x3A Read/Write Internal Temperature Low Limit—Default –128°C.

REV. A

–13–

ADM1028

Table V. Register 0x40 Configuration Register Power-On Default <7:0> = 21h

Bit Name R/W Description

0 START Read/Write Setting this bit to a “1” enables startup of ADM1028; clearing this bit to “0”

places ADM1028 in standby mode. At startup, temperature monitoring and
limit checking functions begin. Note, all limit values should be programmed
into ADM1028 prior to using the standard thermal interrupt mechanism
based upon high and low limits. (Power-Up Default = 1.)

1 INT Enable Read/Write Setting this bit to a “1” enables the INT output. 1 = Enabled 0 = Disabled

(Power-Up Default = 0.)
2 Reserved Read Only Reserved (Default = 0).
3 Programmable Read/Write Once Setting this bit to a “1” will lock in the value set into the Programmable Remote

Therm Limit Therm Limit Register (Value Register 0x14). Furthermore, if this bit is set,
Lock Bit the values in the Default Remote Therm Limit Register Bit (Value Register

0x18) will no longer have an effect on the THERM, FAN_SPD, or FAN_OFF

outputs. This bit cannot be written again until after RST has been asserted.

(Power-Up Default = 0.)
4 Soft Reset Read/Write Setting this bit to a “1” will restore power-up default values to the Configu-

ration Register, Interrupt Status Register and Interrupt Mask Register. This

also rearms INT structure but not the THERM structure. This bit automati-

cally clears itself since the power-on default is zero.
5 FAN_OFF Read/Write Setting this bit to a “1” will cause the FAN_OFF pin to be floated. Clearing

this bit to “0” will cause the FAN_OFF pin to be driven low which requests

that the fan be turned off. This bit will be unconditionally set if the THERM

pin is ever asserted; once THERM is negated this bit must be returned to its

prior state (prior to THERM assertion). Reading this bit reflects the state of

the FAN_OFF output buffer. Due to the open-drain nature of this pin the

value read does not represent the actual state of the external circuit con-

nected to it. (Power-Up Default = 1.)
6 GPI Invert Read/Write Setting this bit to a “1” will invert the GPI input for the purpose of level

detection and interrupt generation. Clearing this bit to “0” leaves the GPI

input unmodified. (Power-Up Default = 0.)
7 Reserved Read Only Reserved. (Power-Up Default = 0).

Table VI. Register 0x41. Interrupt Status Register. Power-On Default <7:0> = 00h

Bit Name Read/Write Description

0 Int. Temp Error Read/Write A one indicates that one of the limits for the internal temperature sensor

“1” to clear has been exceeded.

1 Flag 1 Read/Write This bit can be used as a general purpose flag with the capability of generat-

ing an interrupt. Writing a “1” to this bit causes it to be set to “1.” Writing a

“0” clears this bit.
2 Flag 2 Read/Write This bit can be used as a general purpose flag with the capability of generat-

ing an interrupt. Writing a “1” to this bit causes it to be set to “1.” Writing a

“0” clears this bit.
3 Int. THERM Read/Write A one indicates that the internal thermal overload (THERM) limit has

“1” to clear been exceeded.

4 GPI Input Read Only A “1” indicates that the GPI pin is asserted. The polarity of the GPI pin is

determined by GPI Invert (Bit 6) in the Configuration Register. For ex-

ample, if GPI Invert is cleared then this bit will be “1” when the GPI pin is

high (“1”); this bit will be “0” when the GPI pin is low (“0”.) If GPI Invert

is set then this bit will be “1” when the GPI pin is low (“0”); this bit will be

“0” when the GPI pin is high (“1”). Note that the state of GPI is not latched;

this bit simply reflects the state or inverted state of the GPI pin. Note: if this

bit is “1” reading this register will NOT clear it to “0.”
5 Ext. Temp Error Read/Write A one indicates that one of the limits for the external temperature sensor

“1” to clear has been exceeded.

6 Ext. THERM Read/Write A one indicates that the external thermal overload (THERM) limit has

“1” to clear been exceeded.

7 Ext Diode Fault Read/Write A one indicates either a short- or open-circuit fault on the remote sensor diode.

“1” to clear

–14–

REV. A

ADM1028

Table VII. Register 0x43 Interrupt Mask Register. Power-On Default <7:0> = 00h

Bit Name Read/Write Description

0 Int Temp Error Read/Write A one disables the corresponding interrupt status bit for the INT output.
1 Flag 1 Mask Read/Write A one disables the corresponding interrupt status bit for the INT output.
2 Flag 2 Mask Read/Write A one disables the corresponding interrupt status bit for the INT output.
3 Int THERM Read/Write A one disables the corresponding interrupt status bit for the INT output.
4 GPI Mask Read/Write A one disables the corresponding interrupt status bit for the INT output.
5 Ext Temp Error Read/Write A one disables the corresponding interrupt status bit for the INT output.
6 Ext THERM Read/Write A one disables the corresponding interrupt status bit for the INT output.
7 Ext Diode Fault Read/Write A one disables the corresponding interrupt status bit for the INT output.

Table VIII. Register 0x4B Remote Function Register. Power-On Default <7:0> = 00h

Bit Name Read/Write Description

0 R_RST Read/Write Writing a “1” to this bit causes the R_RST output to be pulsed low for a

minimum of 125 µs. This bit will self-clear to 0 when the R_RST pulse is
complete. Writing a “0” to this bit has no effect. Reading this bit reflects the
state of this register bit and not the state of the pin. The power-on default
value is “0.”

1 R_OFF Read/Write Writing a “1” to this bit causes the R_OFF output to be driven high. This bit

will be cleared, and the output driven low, when RST is asserted. Writing a

“0” to this bit has no effect. The power-on default value is “0.”
2 Reserved Read/Write Reserved (Default = 0).
3 Reserved Read/Write Reserved (Default = 0).
4 Reserved Read/Write Reserved (Default = 0).
5 Reserved Read/Write Reserved (Default = 0).
6 Reserved Read/Write Reserved (Default = 0).
7 Reserved Read/Write Reserved (Default = 0).

Table IX. Register 0x4C Alert Status Register. Power-On Default <7:0> = 00h

Bit Name Read/Write Description

0 Ext THERM Alert Read Only A one indicates that the external thermal overload limit is currently exceeded.
1 GPI Alert Read Only This bit represents the logic level of the GPI pin if Bit 6 of the Configuration

Register is “0,” or the inverse logic level of the GPI pin if Bit 6 of the Con-

figuration Register is “1.”
2 Int THERM Alert Read Only A one indicates that the internal thermal overload limit is currently exceeded.
3 Reserved Read Only Undefined.
4 Reserved Read Only Undefined.
5 Reserved Read Only Undefined.
6 Reserved Read Only Undefined.
7 Reserved Read Only Undefined.

REV. A

–15–

ADM1028

Table X. Register 0xCO Fan Speed Ramp Register. Power-On Default <7:0> = 00h

Bit Name Read/Write Description

0 Fan Speed Ramp Read/Write Setting this bit to a “1” will enable the fan speed ramping mechanism.

Enable When this bit is a 1, writing to the Fan Speed Register will set the new

target fan speed; the input to the DAC will then count, up or down as
appropriate, to the new fan speed value at the rate specified in bits [1:2]
of this register. Clearing this bit to “0” will disable the fan speed ramp­ing mechanism and will cause data written to the Fan Speed Register to
be immediately reflected to the DAC. The DAC input may or may not
continue ramping if this bit is changed from a “1” to a “0” while the fan
speed is currently ramping.

<2:1> Ramp Rate Read/Write Fan Speed Ramp Rate. The speed at which the fan speed ramp counter

increments/decrements is selected as follows:

Bits <2:1> Count Rate Counter Frequency
00 1.0s 1 Hz
01 0.25s 4 Hz
10 0.125s 8 Hz
11 0.0625s 16 Hz

<7:3> Reserved Read/Write Reserved (Default = 0)

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

C02365–0–2/02(A)

16-Lead Shrink Small Outline Package (QSOP)

(RQ-16)

0.197 (5.00)

0.189 (4.80)

16

0.157 (3.99)

0.150 (3.81)

0.010 (0.25)

0.004 (0.10)

REF: JEDEC 0.150" SSOP – DRAWING NUMBER MO-137

0.059 (1.50)
MAX

1

PIN 1

(0.64)

0.025

BSC

9

8

0.069 (1.75)

0.053 (1.35)

0.012 (0.30)

0.008 (0.20)

0.244 (6.20)

0.228 (5.79)

SEATING
PLANE

0.010 (0.20)

0.007 (0.18)

8ⴗ
0ⴗ

0.050 (1.27)

0.016 (0.41)

Revision History

Location Page

Data Sheet changed from REV. 0 to REV. A.

Edits to FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Added Fan Speed Ramp Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Edits to Table III . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Added Table X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

PRINTED IN U.S.A.

–16–

REV. A