Datasheet ADM1026 Datasheet (Analog Devices)

Complete Thermal System

FEATURES

Up to 19 analog measurement channels (including internal

measurements) Up to 8 fan speed measurement channels Up to 17 general-purpose logic I/O pins Remote temperature measurement with remote diode (two

channels) On-chip temperature sensor Analog and PWM fan speed control outputs 2-wire serial system management bus (SMBus) 8 kB on-chip EEPROM

GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10

GPIO9 GPIO8

FAN7/GPIO7 FAN6/GPIO6 FAN5/GPIO5 FAN4/GPIO4 FAN3/GPIO3 FAN2/GPIO2 FAN1/GPIO1 FAN0/GPIO0

BAT

+5 V

–12 V

+12 V

+V A A A A A A

IN6

IN7

D2+/

IN8

D2–/A

IN9

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Anal og Devices. Trademarks and registered trademarks are the property of their respective owners.

CCP

(0V – +3V)

IN0

(0V – +3V)

IN1

(0V – +3V)

IN2

(0V – +3V)

IN3

(0V – +3V)

IN4

(0V – +3V)

IN5

(0V – +2.5V) (0V – +2.5V) (0V – +2.5V) (0V – +2.5V)

D1+

D1–/NTESTIN

BAND GAP

TEMPERATURE

SENSOR

GPIO

REGISTERS

FAN

SPEED

COUNTER

INPUT

ATTENUATORS

AND

ANALOG

MULTIPLEXER

Figure 1. Functional Block Diagram

AGND V

ADDRESS

POINTER

8k BYTES

EEPROM

AUTOMATIC

FAN SPEED

CONTROL

ADM1026

8-BIT

ADC

BAND GAP

REFERENCE

DGND

Management Controller

ADM1026

Full SMBus 1.1 support includes packet error checking (PEC) Chassis intrusion detection Interrupt output (SMBAlert) Reset input, reset outputs Thermal interrupt (

Limit comparison of all monitored values

APPLICATIONS

Network servers and personal computers Telecommunications equipment Test equipment and measuring instruments

ADD/

NTESTOUT

SERIAL BUS

INTERFACE

(1.82V OR 2.5V)

REF

3.3V STBY

SCLSDA

PWM REGISTER

AND CONTROLLER

VALUE AND

LIMIT

REGISTERS

LIMIT

COMPARATORS

INTERRUPT

STATUS

REGISTERS

INT MASK

REGISTERS

INTERRUPT

MASKING

CONFIGURATION

REGISTERS

ANALOG

OUTPUT REGISTER

AND 8-BIT DAC

THERM

GENERATOR

) output

3.3V MAIN

3.3V MAIN RESET

3.3V STBY RESET

REGISTERS

RESET IN

100kΩ

TO GPIO

100kΩ

RESETMAIN

RESETSTBY

PWM

INT

GPIO16/THERM

DAC

02657-A-001

ADM1026

TABLE OF CONTENTS

Specifications..................................................................................... 3

Measurement Inputs .................................................................. 16

Absolute Maximum Ratings............................................................ 5

Thermal Characteristics .............................................................. 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 8

Product Description....................................................................... 10

Functional Description.............................................................. 10

Internal Registers........................................................................ 11

EEPROM .....................................................................................11

SMBus Protocols for RAM and EEPROM.............................. 13

REVISION HISTORY

3/04—Data Sheet Changed from Rev. 0 to Rev. A

Updated Format..................................................................Universal

Change to Footnote 4, Table 1..........................................................4

Added Figure 15.................................................................................9

Changes to Table 6.......................................................................... 17

Changes to Figure 27...................................................................... 18

Change to Figure 31 ....................................................................... 19

Change to Battery Measurement Input Section ......................... 19

Changes to Table 7.......................................................................... 21

Changes to Equations in Fan Speed Measurement Section...... 26

Change to Chassis Intrusion Input Section ................................ 27

Changes to Reset Input and Outputs Section ............................. 31

Changes to Software Reset Function Section ............................. 34

Changes to Ordering Guide.......................................................... 55

Temperature Measurement System.......................................... 20

Analog Output............................................................................ 22

Fan Speed Measurement ........................................................... 25

Enabling and Clearing Interrupts ............................................ 29

NAND Tree Tests........................................................................ 31

Using the ADM1026 .................................................................. 33

Registers........................................................................................... 36

Detailed Register Descriptions................................................. 38

Outline Dimensions....................................................................... 54

Ordering Guide .......................................................................... 55

5/02—Revision 0: Initial Version

Rev. A | Page 2 of 56

ADM1026

SPECIFICATIONS1, 2, 3

Table 1. TA = T

MIN

to T

, VCC = V

MAX

MIN

to V

, unless otherwise noted.

MAX

Parameter Min Typ Max Test Conditions/Comments Unit

POWER SUPPLY

Supply Voltage, 3.3 V STBY, 3.3 V MAIN 3.0 3.3 5.5 V Supply Current, I

2.5 4.0 Interface inactive, ADC active mA

TEMPERATURE-TO-DIGITAL CONVERTER

Internal Sensor Accuracy ±3 °C Resolution ±1 °C External Diode Sensor Accuracy ±3 0°C < TD < 100°C °C Resolution ±1 °C Remote Sensor Source Current 90 High level µA

5.5 Low level µA ANALOG-TO-DIGITAL CONVERTER (including MUX and attenuators)

Total Unadjusted Error (TUE)4 ±2 % Differential Nonlinearity (DNL) ±1 LSB Power Supply Sensitivity ±0.1 %/V Conversion Time (Analog Input or Internal Temperature)5 11.38 12.06 ms Conversion Time (External Temperature)5 34.13 36.18 ms Input Resistance (+5 VIN, V

CCP

, A

− A

IN0

) 80 100 120 kΩ

IN5

Input Resistance of +12 VIN pin 70 100 115 kΩ Input Resistance of −12 VIN pin 8 10 12 kΩ Input Resistance (A Input Resistance of V V

Current Drain (when measured) 80 100 CR2032 battery life >10 years nA

BAT

Current Drain (when not measured) 6 nA

BAT

− A

) 5 MΩ

IN6

IN9

pin4 80 100 120 kΩ

BAT

ANALOG OUTPUT (DAC)

Output Voltage Range 0–2.5 V Total Unadjusted Error (TUE) ±5 IL = 2 mA % Zero Error 1 No load LSB Differential Nonlinearity (DNL) ±1 Monotonic by design LSB Integral Nonlinearity ±0.5 LSB Output Source Current 2 mA Output Sink Current 1 mA

REFERENCE OUTPUT

Output Voltage 1.8 1.82 1.84 Bit 2 of Register 07h = 0 V Output Voltage 2.47 2.50 2.53 Bit 2 of Register 07h = 1 V Load Regulation (I Load Regulation (I

= 2 mA) 0.15 %

SINK

= 2 mA) 0.15 %

SOURCE

Short Circuit Current 25 VCC = 3.3 V mA Output Current Source 2 mA Output Current Sink 2 mA

FAN RPM-TO-DIGITAL CONVERTER6

Accuracy ±12 % Full-Scale Count 255 FAN0 to FAN7 Nominal Input RPM5 8800 Divisor = 1, fan count = 153 RPM 4400 Divisor = 2, fan count = 153 RPM 2200 Divisor = 4, fan count = 153 RPM 1100 Divisor = 8, fan count = 153 RPM Internal Clock Frequency 20 22.5 25 kHz

OPEN DRAIN O/Ps, PWM, GPIO0 to 16

Output High Voltage, VOH 2.4 I

= 3.0 mA, VCC = 3.3 V V

OUT

Rev. A | Page 3 of 56

ADM1026

Parameter Min Typ Max Test Conditions/Comments Unit

High Level Output Leakage Current, IOH 0.1 1 V

Output Low Voltage, VOL 0.4 I

PWM Output Frequency 75 Hz DIGITAL OUTPUTS (INT, RESETMAIN, RESETBY)

Output Low Voltage, VOL 0.4 I

RESET Pulse Width

140 180 240 ms

OPEN DRAIN SERIAL DATABUS OUTPUT (SDA)

Output Low Voltage, VOL 0.4 I

High Level Output Leakage Current, IOH 0.1 1 V SERIAL BUS DIGITAL INPUTS (SCL, SDA)

Input High Voltage, VIH 2.2 V

Input Low Voltage, VIL 0.8 V

Hysteresis 500 mV DIGITAL INPUT LOGIC LEVELS (ADD, CI, FAN 0 to 7, GPIO 0 to 16)7, 8

Input High Voltage, VIH 2.4 VCC = 3.3 V V

Input Low Voltage, VIL 0.8 VCC = 3.3 V V

Hysteresis (Fan 0 to 7) 250 VCC = 3.3 V mV RESETMAIN, RESETSTBY

RESETMAIN Threshold

RESETSBY Threshold

RESETMAIN Hysteresis

RESETSTBY Hysteresis

2.89 2.94 2.97 Falling voltage V

3.01 3.05 3.10 Falling voltage V 60 mV 70 mV

DIGITAL INPUT CURRENT

Input High Current, IIH –1 VIN = VCC µA

Input Low Current, IIL 1 V

Input Capacitance, CIN 20 pF EEPROM RELIABILITY

Endurance9 100 700 kcycles

Data Retention10 10 Years SERIAL BUS TIMING See Figure 2 for all parameters.

Clock Frequency, f

400 kHz

SCLK

Glitch Immunity, tSW 50 ns

Bus Free Time, t

Start Setup Time, t

Start Hold Time, t

SCL Low Time, t

SCL High Time, t

4.7 µs

BUF

4.7 µs

SU; STA

4 µs

HD; STA

4.7 µs

LOW

4 µs

HIGH

SCL, SDA Rise Time, tr 1000 ns

SCL, SDA Fall Time, tf 300 ns

Data Setup Time, t

Data Hold Time, t

250 ns

SU; DAT

300 ns

HD; DAT

All voltages are measured with respect to GND, unless otherwise specified.

Typicals are at TA = 25°C and represent the most likely parametric norm. Shutdown current typ is measured with VCC = 3.3 V.

Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.1 V for a rising edge.

Total unadjusted error (TUE) includes offset, gain, and linearity errors of the ADC, multiplexer, and on-chip input attenuators. V

greater than 1.5 V (see Figure 15).

Total analog monitoring cycle time is nominally 273 ms, made up of 18 ms × 11.38 ms measurements on analog input and internal temperature channels, and

2 ms × 34.13 ms measurements on external temperature channels.

The total fan count is based on two pulses per revolution of the fan tachometer output. The total fan monitoring time depends on the number of fans connected and

the fan speed. See the Fan Speed Measurement section for more details.

ADD is a three-state input that may be pulled high, low, or left open-circuit.

Logic inputs accept input high voltages up to 5 V even when device is operating at supply voltages below 5 V.

Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117, and measured at −40°C, +25°C, and +85°C. Typical endurance at +25°C is 700,000 cycles.

Retention lifetime equivalent at junction temperature (TJ ) = 55°C as per JEDEC Std. 22 method A117. Retention lifetime based on an activation energy of 0.6 V derates with junction temperature as shown in Figure 16.

= VCC µA

OUT

= −3.0 mA, VCC = 3.3 V V

OUT

= −3.0 mA, VCC = 3.3 V V

OUT

= –3.0 mA, VCC = 3.3 V V

OUT

= VCC µA

OUT

= 0 µA

is accurate only for V

BAT

voltages

BAT

Rev. A | Page 4 of 56

ADM1026

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Positive Supply Voltage (VCC) 6.5 V Voltage on +12 V VIN Pin +20 V Voltage on −12 V VIN Pin −20 V Voltage on Analog Pins −0.3 V to (VCC + 0.3 V) Voltage on Open Drain Digital Pins −0.3 V to +6.5 V Input Current at any Pin ±5 mA Package Input Current ±20 mA Maximum Junction Temperature (T

) 150°C

J MAX

Storage Temperature Range −65°C to +150°C Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 200°C ESD Rating, −12 VIN Pin 1000 V ESD Rating, All Other Pins 2000 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL CHARACTERISTICS

• 48-Lead LQFP package

• θ

= 50°C/W, θJC = 10°C/W

HIGH

Figure 2. Serial Bus Timing Diagram

SU; DAT

SU; STA

HD; STA

SCL

SDA

BUF

LOW

HD; STA

HD; DAT

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

SU; STO

02657-A-002

Rev. A | Page 5 of 56

ADM1026

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

(0V – 3V)

GPIO10

GPIO11

GPIO12

GPIO13

4847464544434241403938

GPIO14

GPIO15

GPIO16/THERM

IN0

(0V – 3V)

IN1

IN2

IN3

IN4

GPIO9

GPIO8 FAN0/GPIO0 FAN1/GPIO1 FAN2/GPIO2 FAN3/GPIO3

3.3V MAIN DGND

FAN4/GPIO4 FAN5/GPIO5 FAN6/GPIO6 FAN7/GPIO7

PIN 1 IDENTIFIER

2 3 4 5 6 7 8

9 10 11 12

1314151617181920212223

SCL

SDA

ADM1026

TOP VIEW

(Not to Scale)

ADD/NTESTOUT

INT

PWM

RESETSTBY

DAC

AGND

3.3V STBY

RESETMAIN

REF

IN5

IN6

IN7

CCP

+12 V

–12 V

+5 V

BAT

D2+/A

D2–/A

D1+

D1–/NTESTIN

(0V – 3V) (0V – 2.5V) (0V – 2.5V)

IN IN

(0V – 2.5V)

IN8

(0V – 2.5V)

IN9

02657-A-003

Figure 3. Pin Configuration

Table 3.

Pin No. Mnemonic Type Description

1 GPIO9 Digital I/O1 General-purpose I/O pin that can be configured as digital inputs or outputs. 2 GPIO8 Digital I/O1 General-purpose I/O pin that can be configured as digital inputs or outputs. 3 FAN0/GPIO0 Digital I/O

Fan tachometer input with internal 10 kΩ pull-up resistor to 3.3 V STBY. Can be reconfigured as a general-purpose, open drain, digital I/O pin.

4 FAN1/GPIO1 Digital I/O

Fan tachometer input with internal 10 kΩ pull-up resistor to 3.3 V STBY. Can be reconfigured as a general-purpose, open drain, digital I/O pin.

5 FAN2/GPIO2 Digital I/O

Fan tachometer input with internal 10 kΩ pull-up resistor to 3.3 V STBY. Can be reconfigured as a general-purpose, open drain, digital I/O pin.

6 FAN3/GPIO3 Digital I/O

Fan tachometer input with internal 10 kΩ pull-up resistor to 3.3 V STBY. Can be

reconfigured as a general-purpose, open drain, digital I/O pin. 7 3.3 V MAIN Analog Input Monitors the main 3.3 V system supply. Does not power the device. 8 DGND Ground Ground pin for digital circuits. 9 FAN4/GPIO4 Digital I/O

Fan tachometer input with internal 10 kΩ pull-up resistor to 3.3 V STBY. Can be

reconfigured as a general-purpose, open drain, digital I/O pin. 10 FAN5/GPIO5 Digital I/O

Fan tachometer input with internal 10 kΩ pull-up resistor to 3.3 V STBY. Can be

reconfigured as a general-purpose, open drain, digital I/O pin. 11 FAN6/GPIO6 Digital I/O

Fan tachometer input with internal 10 kΩ pull-up resistor to 3.3 V STBY. Can be

reconfigured as a general-purpose, open drain, digital I/O pin. 12 FAN7/GPIO7 Digital I/O

Fan tachometer input with internal 10 kΩ pull-up resistor to 3.3 V STBY. Can be

reconfigured as a general-purpose, open drain, digital I/O pin. 13 SCL Digital Input Open Drain Serial Bus Clock. Requires a 2.2 kΩ pull-up resistor. 14 SDA Digital I/O Serial Bus Data. Open drain I/O. Requires a 2.2 kΩ pull-up resistor. 15 ADD/NTESTOUT Digital Input

This is a three-state input that controls the two LSBs of the serial bus address. It also

functions as the output for NAND tree testing. 16 CI Digital Input

An active high input that captures a chassis intrusion event in Bit 6 of Status Register 4.

This bit remains set until cleared, as long as battery voltage is applied to the V

even when the ADM1026 is powered off. 17

INT

Digital Output

Interrupt Request (Open Drain). The output is enabled when Bit 1 of the configuration

BAT

input,

Rev. A | Page 6 of 56

ADM1026

Pin No. Mnemonic Type Description

18 PWM Digital Output

RESETSTBY

RESETMAIN

Digital Output

Digital I/O

21 AGND Ground Ground pin for analog circuits. 22 3.3 V STBY Power Supply Supplies 3.3 V power. Also monitors the 3.3 V standby power rail. 23 DAC Analog Output 0 V to 2.5 V output for analog control of the fan speed. 24 V

Analog Output Reference Voltage Output. Can be selected as 1.8 V (default) or 2.5 V.

REF

25 D1–/NTESTIN Analog Input

26 D1+ Analog Input Connected to the anode of the first remote temperature sensing diode. 27 D2–/A

28 D2+/A

29 V

Programmable

IN9

Programmable

IN8

Analog Input Monitors battery voltage, nominally +3 V.

BAT

30 +5 VIN Analog Input Monitors the +5 V supply. 31

−12 V

Analog Input 32 +12 VIN Analog Input Monitors the +12 V supply. 33 +V 34 A 35 A 36 A 37 A 38 A 39 A 40 A 41 A 42

Analog Input Monitors the processor core voltage (0 V to 3.0 V).

CCP

Analog Input General-purpose 0 V to 2.5 V analog inputs.

IN7

Analog Input General-purpose 0 V to 2.5 V analog inputs.

IN6

Analog Input General-purpose 0 V to 3 V analog inputs.

IN5

Analog Input General-purpose 0 V to 3 V analog inputs.

IN4

Analog Input General-purpose 0 V to 3 V analog inputs.

IN3

Analog Input General-purpose 0 V to 3 V analog inputs.

IN2

Analog Input General-purpose 0 V to 3 V analog inputs.

IN1

Analog Input General-purpose 0 V to 3 V analog inputs.

IN0

GPIO16/THERM

Digital I/O

43 GPIO15 Digital I/O1 General-purpose I/O pin that can be configured as a digital input or output. 44 GPIO14 Digital I/O1 General-purpose I/O pin that can be configured as a digital input or output. 45 GPIO13 Digital I/O1 General-purpose I/O pin that can be configured as a digital input or output. 46 GPIO12 Digital I/O1 General-purpose I/O pin that can be configured as a digital input or output. 47 GPIO11 Digital I/O1 General-purpose I/O pin that can be configured as a digital input or output. 48 GPIO10 Digital I/O1 General-purpose I/O pin that can be configured as a digital input or output.

Open drain pulse width modulated output for control of the fan speed. This pin defaults to high for the 100% duty cycle for use with NMOS drive circuitry. If a PMOS device is used to drive the fan, the PWM output may be inverted by setting Bit 1 of Test Register 1 = 1.

Power-On Reset. 5 mA driver (weak 100 kΩ pull-up), active low output (100 kΩ pull-up) with a 180 ms typical pulse width. RESETSTBY

is asserted whenever 3.3 V STBY is below

the reset threshold. It remains asserted for approximately 180 ms after 3.3 V STBY rises above the reset threshold.

Power-On Reset. 5 mA driver (weak 100 kΩ pull-up), active low output (100 kΩ pull-up) with a 180 ms typical pulse width. RESETMAIN

is asserted whenever 3.3 V MAIN is below the reset threshold. It remains asserted for approximately 180 ms after 3.3 V MAIN rises above the reset threshold. If, however, 3.3 V STBY rises with or before 3.3 V MAIN, then RESETMAIN

remains asserted for 180 ms after RESETSTBY is deasserted. Pin 20 also

functions as an active low RESET input.

Connected to a cathode of the first remote temperature sensing diode. If it is held high at power-on, it activates the NAND tree test mode.

Connected to the cathode of the second remote temperature sensing diode, or the analog input may be reconfigured as a 0 V− 2.5 V analog input.

Connected to the anode of the second remote temperature sensing diode, or the analog input may be reconfigured as a 0 V − 2.5 V analog input.

Monitors the −12 V supply.

General-purpose I/O pin that can be configured as a digital input or output. Can also be configured as a bidirectional THERM

pin (100 kΩ pull-up).

GPIO pins are open drain and require external pull-up resistors. Fan inputs have integrated 10 kΩ pull-ups, but these pins become open drain when reconfigured as

GPIOs.

Rev. A | Page 7 of 56

ADM1026

TYPICAL PERFORMANCE CHARACTERISTICS

25 20

D+ TO GND

–5

D+ TO V

–10

TEMPERATURE ERROR (°C)

–15 –20

–25

30 60 1200

LEAKAGE RESISTANCE (MΩ)

02657-A-004

110 100

90 80 70 60 50

READING (°C)

40 30 20 10

0 10 20 30 40 50 60 70 80 90 100 110

PIII TEMPERATURE (°C)

02657-A-007

Figure 4. Temperature Error vs. PCB Track Resistance

250mV

TEMPERATURE ERROR (°C)

100mV

100 200 300 400 500

FREQUENCY (MHz)

Figure 5. Temperature Error vs. Power Supply Noise Frequency

100mV 60mV 40mV

600

Figure 7. Pentium® III Temperature vs. ADM1026 Reading

–5

–10

–15

TEMPERATURE ERROR (°C)

–20

–25

02657-A-005

01020304050

CAPACITANCE (nF)

02657-A-008

Figure 8. Temperature Error vs. Capacitance Between D+ and D–

TEMPERATURE ERROR (°C)

100

0 200 300 400 500 600

FREQUENCY (MHz)

Figure 6. Temperature Error vs. Common-Mode Noise Frequency

02657-A-006

Rev. A | Page 8 of 56

TEMPERATURE ERROR (°C)

100

100mV

60mV

40mV

200 300 400 500

FREQUENCY (MHz)

600

Figure 9. Temperature Error vs. Differential-Mode Noise Frequency

02657-A-009

ADM1026

450

400

350

300

250

200

150

RESET TIMEOUT (ms)

100

0204060–40 100 120

–20

TEMPERATURE (°C)

Figure 10. Power-up Reset Timeout vs. Temperature

3.0

140

02657-A-010

1.0

0.5

–0.5

–1.0

TEMPERATURE ERROR (°C)

–1.5

–2.0

10 20 30 40 50 60 70 80 90 100 110 120

TEMPERATURE (°C)

Figure 13. Remote Sensor Temperature Error

120

02657-A-013

2.5

2.0

1.5

(mA)

1.0

0.5

3.00 4.003.25 3.50 3.75 4.25 4.50 4.75 5.255.00 VCC(V)

Figure 11. Supply Current vs. Supply Voltage

1.8

1.6

1.4

1.2

1.0

0.8

0.6

TEMPERATURE ERROR (°C)

0.4

0.2

10 20 30 40 50 60 70 80 90 100 110 120

TEMPERATURE (°C)

Figure 12. Local Sensor Temperature Error

5.50

100

TEMPERATURE (°C)

02657-A-011

068101214161820222426

TIME (s)

02657-A-014

Figure 14. Response to Thermal Shock

3.5

3.0

2.5

2.0

1.5

MEASUREMENT

BAT

1.0

0.5

01234

02657-A-012

Figure 15. V

VOLTAGE

BAT

Measurement vs. Voltage

BAT

02657-A-015

Rev. A | Page 9 of 56

ADM1026

PRODUCT DESCRIPTION

The ADM1026 is a complete system hardware monitor for microprocessor-based systems, providing measurement and limit comparison of various system parameters. The ADM1026 has up to 19 analog measurement channels. Fifteen analog voltage inputs are provided, five of which are dedicated to monitoring +3.3 V, +5 V, and ±12 V power supplies, and the processor core voltage. The ADM1026 can monitor two other power supply voltages by measuring its own V system supply. One input (two pins) is dedicated to a remote temperature-sensing diode. Two additional pins can be configured as general-purpose analog inputs to measure 0 V to 2.5 V, or as a second temperature sensing input. The eight remaining inputs are general-purpose analog inputs with a range of 0 V to 2.5 V or 0 V to 3 V. The ADM1026 also has an on-chip temperature sensor.

The ADM1026 has eight pins that can be configured for fan speed measurement or as general-purpose logic I/O pins. Another eight pins are dedicated to general-purpose logic I/O. An additional pin can be configured as a general-purpose I/O or as the bidirectional

Measured values can be read out via a 2-wire serial system management bus, and values for limit comparisons can be programmed over the same serial bus. The high speed, successive approximation ADC allows frequent sampling of all analog channels to ensure a fast interrupt response to any outof-limit measurement.

THERM

pin.

FUNCTIONAL DESCRIPTION

The ADM1026 is a complete system hardware monitor for microprocessor-based systems. The device communicates with the system via a serial system management bus. The serial bus controller has a hardwired address line for device selection (ADD, Pin 15), a s erial data line for reading and writing addresses and data (SDA, Pin 14), and an input line for the serial clock (SCL, Pin 13). All control and programming functions of the ADM1026 are performed over the serial bus.

Measurement Inputs

Programmability of the analog and digital measurement inputs makes the ADM1026 extremely flexible and versatile. The device has an 8-bit A/D converter, and 17 analog measurement input pins that can be configured in different ways.

Pins 25 and 26 are dedicated temperature inputs and may be connected to the cathode and anode of a remote temperaturesensing diode.

and the main

Pins 29 to 33 are dedicated analog inputs with on-chip attenuators configured to monitor V and the processor core voltage V

Pins 34 to 41 are general-purpose analog inputs with a range of 0 V to 2.5 V or 0 V to 3 V. These are mainly intended for monitoring SCSI termination voltages, but may be used for other purposes.

The ADC also accepts input from an on-chip band gap temperature sensor that monitors system ambient temperature.

In addition, the ADM1026 monitors the supply from which it is powered, 3.3 V STBY, so there is no need for a separate pin to monitor the power supply voltage.

The ADM1026 has eight pins that are general-purpose logic I/O pins (Pins 1, 2, and 43 to 48), a pin that can be configured as GPIO or as a bidirectional thermal interrupt (

(Pin 42), and eight pins that can be configured for fan speed measurement or as general-purpose logic pins (Pins 3 to 6 and Pins 9 to 12).

, +5 V, −12 V, +12 V,

BAT

, respectively.

CCP

THERM

) pin

Sequential Measurement

When the ADM1026 monitoring sequence is started, it cycles sequentially through the measurement of analog inputs and the temperature sensor, while at the same time the fan speed inputs are independently monitored. Measured values from these inputs are stored in value registers. These can be read over the serial bus, or can be compared with programmed limits stored in the limit registers. The results of out-of-limit comparisons are stored in the interrupt status registers. An out-of-limit event generates an interrupt on the

Any or all of the interrupt status bits can be masked by appropriate programming of the interrupt mask registers.

line (Pin 17).

INT

Chassis Intrusion

A chassis intrusion input (Pin 16) is provided to detect unauthorized tampering with the equipment. This event is latched in a battery-backed register bit.

Resets

The ADM1026 has two power-on reset outputs, and

RESETSTBY STBY fall below the reset threshold. These give a 180 ms reset pulse at power-up. RESET input.

, that are asserted when 3.3 V MAIN or 3.3 V

RESETMAIN

also functions as an active-low

RESETMAIN

Pins 27 and 28 may be configured as temperature inputs and connected to a second temperature-sensing diode, or may be reconfigured as analog inputs with a range of 0 V to 2.5 V.

Rev. A | Page 10 of 56

ADM1026

Fan Speed Control Outputs

The ADM1026 has two outputs intended to control fan speed, though they can also be used for other purposes. Pin 18 is an open drain, pulse width modulated (PWM) output with a programmable duty cycle and an output frequency of 75 Hz. Pin 23 is connected to the output of an on-chip, 8-bit, digital-toanalog converter with an output range of 0 V to 2.5 V.

Either or both of these outputs may be used to implement a temperature-controlled fan by controlling the speed of a fan using the temperature measured by the on-chip temperature sensor or remote temperature sensors.

INTERNAL REGISTERS

Table 4 describes the principal registers of the ADM1026. For more detailed information, see Table 11 to Table 124.

Tabl e 4 . Prin c ip a l Re g ist e r s

Type Description

Address Pointer

Configuration Registers

Fan Divisor Registers

DAC/PWM Control Registers

GPIO Configuration Registers

Value and Limit Registers

Status Registers

Mask Registers

Contains the address that selects one of the other internal registers. When writing to the ADM1026, the first byte of data is always a register address, and is written to the address pointer register.

Provide control and configuration for various operating parameters.

Contain counter prescaler values for fan speed measurement.

Contain speed values for PWM and DAC fan drive outputs.

Configure the GPIO pins as input or output and for signal polarity.

Store the results of analog voltage inputs, temperature, and fan speed measurements, along with their limit values.

Store events from the various interrupt sources.

Allow masking of individual interrupt sources.

• Writing to the EEPROM should be restricted because its

typical cycle life is 100,000 write operations, due to the usual EEPROM wear-out mechanisms.

The EEPROM in the ADM1026 has been qualified for two key EEPROM memory characteristics: memory cycling endurance and memory data retention.

Endurance qualifies the ability of the EEPROM to be cycled through many program, read, and erase cycles. In real terms, a single endurance cycle is composed of four independent, sequential events, as follows:

1. Initial page erase sequence

2. Read/verify sequence

3. Program sequence

4. Second read/verify sequence

In reliability qualification, every byte is cycled from 00h to FFh until a first fail is recorded, signifying the endurance limit of the EEPROM memory.

Retention quantifies the ability of the memory to retain its programmed data over time. The EEPROM in the ADM1026 has been qualified in accordance with the formal JEDEC Retention Lifetime Specification (A117) at a specific junction temperature (T

= 55°C) to guarantee a minimum of 10 years

retention time. As part of this qualification procedure, the EEPROM memory is cycled to its specified endurance limit described above before data retention is characterized. This means that the EEPROM memory is guaranteed to retain its data for its full specified retention lifetime every time the EEPROM is reprogrammed. Note that retention lifetime based on an activation energy of 0.6 V derates with T

, as shown in

Figure 16.

300

250

200

EEPROM

The ADM1026 has 8 kB of nonvolatile, electrically erasable, programmable read-only memory (EEPROM) from register Addresses 8000h to 9FFFh. This may be used for permanent storage of data that is not lost when the ADM1026 is powered down, unlike the data in the volatile registers. Although referred to as read-only memory, the EEPROM can be written to (as well as read from) via the serial bus in exactly the same way as the other registers. The main differences between the EEPROM and other registers are

• An EEPROM location must be blank before it can be

written to. If it contains data, it must first be erased.

• Writing to EEPROM is slower than writing to RAM.

Rev. A | Page 11 of 56

150

100

RETENTION (Years)

60 70 80 90 10040

JUNCTION TEMPERATURE (°C)

Figure 16. Typical EEPROM Memory Retention

110

120

02657-A-016

ADM1026

Serial Bus Interface

Control of the ADM1026 is carried out via the serial system management bus (SMBus). The ADM1026 is connected to this bus as a slave device, under the control of a master device.

The ADM1026 has a 7-bit serial bus slave address. When the device is powered on, it does so with a default serial bus address. The 5 MSBs of the address are set to 01011, and the 2 LSBs are determined by the logical states of Pin 15 ADD/NTESTOUT. This pin is a three-state input that can be grounded, connected

, or left open-circuit to give three different addresses.

to V

Table 5. Address Pin Truth Table

ADD Pin A1 A0

GND 0 0 No Connect 1 0 V

0 1

If ADD is left open-circuit, the default address is 0101110 (5Ch). ADD is sampled only at power-up on the first valid SMBus transaction, so any changes made while the power is on (and the address is locked) have no effect.

The facility to make hardwired changes to device addresses allows the user to avoid conflicts with other devices sharing the same serial bus, for example if more than one ADM1026 is used in a system.

General SMBus Timing

Figure 17 and Figure 18 show timing diagrams for general read and write operations using the SMBus. The SMBus specification defines specific conditions for different types of read and write operations, which are discussed later in this section.

The general SMBus protocol

1. The master initiates data transfer by establishing a start

condition, defined as a high-to-low transition on the serial data line (SDA) while the serial clock line SCL remains high. This indicates that a data stream follows. All slave peripherals connected to the serial bus respond to the start condition and shift in the next 8 bits, consisting of a 7-bit slave address (MSB first) and an R/

the direction of the data transfer, that is, whether data is written to or read from the slave device (0 = write, 1 = read).

operates as follows:

bit, which determine

The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit, and holding it low during the high period of this clock pulse. All other devices on the bus remain idle while the selected device waits for data to be read from or written to it. If the R/

slave device. If the R/

bit is 0, the master writes to the

bit is 1, the master reads from the

slave device.

2. Data is sent over the serial bus in sequences of nine clock

pulses, 8 bits of data followed by an acknowledge bit from the slave device. Data transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-to-high transition when the clock is high may be interpreted as a stop signal.

If the operation is a write operation, the first data byte after the slave address is a command byte. This tells the slave device what to expect next. It may be an instruction telling the slave device to expect a block write, or it may simply be a register address that tells the slave where subsequent data is to be written.

Because data can flow in only one direction as defined by the R/

bit, it is not possible to send a command to a slave

W device during a read operation. Before doing a read operation, it may first be necessary to do a write operation to tell the slave what type of read operation to expect and/or

the address from which data is to be read.

3. When all data bytes have been read or written, stop

conditions are established. In write mode, the master pulls the data line high during the 10th clock pulse to assert a stop condition. In read mode, the master device releases the SDA line during the low period before the ninth clock pulse, but the slave device does not pull it low (called No Acknowledge). The master takes the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a stop condition.

If it is required to perform several read or write operations in succession, the

master can send a repeat start condition instead of a stop condition to begin a new operation.

Rev. A | Page 12 of 56

ADM1026

191

SCL

SDA

START BY

MASTER

SCL

(CONTINUED)

SDA

(CONTINUED)

SCL

SDA

START BY

MASTER

SCL

(CONTINUED)

1011

FRAME 1

SLAVE ADDRESS

D7 D6 D5 D4 D3 D2 D1 D0

FRAME 3

DATA BYTE

R/W

ACK. BY

SLAVE

ACK. BY

SLAVE

FRAME 2

COMMAND CODE

199

D7 D6 D5 D4 D3 D2 D1 D0

FRAME N

DATA BYTE

ACK. BY

Figure 17. General SMBus Write Timing Diagram

191

FRAME 1

SLAVE ADDRESS

R/W

ACK. BY

SLAVE

FRAME 2

DATA BYTE

199

ACK. BY MASTER

SLAVE

ACK. BY

SLAVE

STOP BY MASTER

02657-A-017

SDA

(CONTINUED)

D7 D6 D5 D4 D3 D2 D1 D0

FRAME 3

DATA BYTE

ACK. BY

MASTER

Figure 18. General SMBus Read Timing Diagram

SMBus PROTOCOLS FOR RAM AND EEPROM

The ADM1026 contains volatile registers (RAM) and nonvolatile EEPROM. RAM occupies Addresses 00h to 6Fh, while EEPROM occupies Addresses 8000h to 9FFFh.

Data can be written to and read from both RAM and EEPROM as single data bytes and as block (sequential) read or write operations of 32 data bytes, the maximum block size allowed by the SMBus specification.

Data can only be written to unprogrammed EEPROM locations. To write new data to a programmed location, it is first necessary to erase it. EEPROM erasure cannot be done at the byte level; the EEPROM is arranged as 128 pages of 64 bytes, and an entire page must be erased. Note that of these 128 pages, only 124 pages are available to the user. The last four pages are reserved for manufacturing purposes and cannot be erased/rewritten.

The EEPROM has three RAM registers associated with it, EEPROM Registers 1, 2, and 3 at Addresses 06h, 0Ch, and 13h.

D7 D6 D5 D4 D3 D2 D1 D0

STOP BY

MASTER

02657-A-018

FRAME N

DATA BYTE

NO ACK.

EEPROM Registers 1 and 2 are for factory use only. EEPROM Register 3 sets up the EEPROM operating mode. Setting Bit 0 of EEPROM Register 3 puts the EEPROM into read mode. Setting Bit 1 puts it into programming mode. Setting Bit 2 puts it into erase mode.

Only one of these bits must be set before the EEPROM may be accessed. Setting no bits or more than one of them causes the device to respond with No Acknowledge if an EEPROM read, program, or erase operation is attempted.

It is important to distinguish between SMBus write operations, such as sending an address or command, and EEPROM programming operations. It is possible to write an EEPROM address over the SMBus, whatever the state of EEPROM Register 3. However, EEPROM Register 3 must be correctly set before a subsequent EEPROM operation can be performed. For example, when reading from the EEPROM, Bit 0 of EEPROM Register 3 can be set, even though SMBus write operations are required to set up the EEPROM address for reading.

Rev. A | Page 13 of 56

ADM1026

Bit 3 of EEPROM Register 3 is used for EEPROM write protection. Setting this bit prevents accidental programming or erasure of the EEPROM. If an EEPROM write or erase operation is attempted when this bit is set, the ADM1026 responds with No Acknowledge. This bit is write-once and can only be cleared by a power-on reset.

EEPROM Register 3 Bit 7 is used for clock extend. Programming an EEPROM byte takes approximately 250 µs, which would limit the SMBus clock for repeated or block write operations. Because EEPROM block read/write access is slow, it is recommended that this clock extend bit typically be set to 1. This allows the ADM1026 to pull SCL low and extend the clock pulse when it cannot accept any more data.

ADM1026 SMBus Operations

The SMBus specification defines several protocols for different types of read and write operations. The ones used in the ADM1026 are discussed below. The following abbreviations are used in the diagrams:

S Start W Write P Stop A Acknowledge R Read A

No Acknowledge

ADM1026 Write Operations

Send Byte

In this operation, the master device sends a single command byte to a slave device, as follows:

1. The master device asserts a start condition on the SDA.

2. The master sends the 7-bit slave address followed by the

write bit (low).

3. The addressed slave device asserts an ACK on the SDA.

4. The master sends a command code.

5. The slave asserts ACK on the SDA.

6. The master asserts a stop condition on the SDA and the

transaction ends.

In the ADM1026, the send byte protocol is used to write a register address to RAM for a subsequent single-byte read from the same address or block read or write starting at that address. This is illustrated in Figure 19.

12 3 4 56

SLAVE

ADDRESS

Figure 19. Setting a RAM Address for Subsequent Read

If it is required to read data from the RAM immediately after setting up the address, the master can assert a repeat start condition immediately after the final ACK and carry out a single byte read, block read, or block write operation without asserting an intermediate stop condition.

RAM

ADDRESS

(00h TO 6Fh)

AAP

02657-A-019

Writ e B yte / Word

In this operation, the master device sends a command byte and one or two data bytes to the slave device as follows:

1. The master device asserts a start condition on the SDA.

2. The master sends the 7-bit slave address followed by the

write bit (low).

3. The addressed slave device asserts an ACK on the SDA.

4. The master sends a command code.

5. The slave asserts an ACK on the SDA.

6. The master sends a data byte.

7. The slave asserts an ACK on the SDA.

8. The master sends a data byte (or may assert stop here.)

9. The slave asserts an ACK on the SDA.

10. The master asserts a stop condition on the SDA to end the

transaction.

In the ADM1026, the write byte/word protocol is used for four purposes. The ADM1026 knows how to respond by the value of the command byte and EEPROM Register 3.

The first purpose is to write a single byte of data to RAM. In this case, the command byte is the RAM address from 00h to 6Fh and the (only) data byte is the actual data. This is illustrated in Figure 20.

12 3 4 56

SLAVE

ADDRESS

Figure 20. Single Byte Write to RAM

RAM

ADDRESS

(00h TO 6Fh)

DATA

02657-A-020

The protocol is also used to set up a 2-byte EEPROM address for a subsequent read or block read. In this case, the command byte is the high byte of the EEPROM address from 80h to 9Fh. The (only) data byte is the low byte of the EEPROM address. This is illustrated in Figure 21.

13456

EEPROM

ADDRESS

HIGH BYTE

(80h TO 9Fh)

SLAVE

ADDRESS

Figure 21. Setting an EEPROM Address

EEPROM

ADDRESS

LOW BYTE

(00h TO FFh)

02657-A-021

If it is required to read data from the EEPROM immediately after setting up the address, the master can assert a repeat start condition immediately after the final ACK and carry out a single-byte read or block read operation without asserting an intermediate stop condition. In this case, Bit 0 of EEPROM Register 3 should be set.

The third use is to erase a page of EEPROM memory. EEPROM memory can be written to only if it is previously erased. Before writing to one or more EEPROM memory locations that are already programmed, the page or pages containing those locations must first be erased. EEPROM memory is erased by writing an EEPROM page address plus an arbitrary byte of data with Bit 2 of EEPROM Register 3 set to 1.

Rev. A | Page 14 of 56

ADM1026

Because the EEPROM consists of 128 pages of 64 bytes, the EEPROM page address consists of the EEPROM address high byte (from 80h to 9Fh) and the two MSBs of the low byte. The lower six bits of the EEPROM address (low byte only) specify addresses within a page and are ignored during an erase operation.

12 3 4 5 6

SLAVE

ADDRESS

EEPROM

ADDRESS

HIGH BYTE

(80h TO 9Fh)

EEPROM

ADDRESS

LOW BYTE

(00h TO FFh)

Figure 22. EEPROM Page Erasure

ARBITRARY

DATA

02657-A-022

Page erasure takes approximately 20 ms. If the EEPROM is accessed before erasure is complete, the ADM1026 responds with No Acknowledge.

Last, this protocol is used to write a single byte of data to EEPROM. In this case, the command byte is the high byte of the EEPROM address from 80h to 9Fh. The first data byte is the low byte of the EEPROM address, and the second data byte is the actual data. Bit 1 of EEPROM Register 3 must be set. This is illustrated in Figure 23.

9. The slave asserts an ACK on the SDA after each data byte.

10. The master sends a packet error checking (PEC ) byte.

11. The ADM1026 checks the PEC byte and issues an ACK if

correct. If incorrect (NACK), the master resends the data bytes.

12. The master asserts a stop condition on the SDA to end the

transaction.

COMMAND A0h BLOCK

WRITE

BYTE

A A DATA 1

COUNT

Figure 24. Block Write to EEPROM or RAM

DATA

PEC

APDATA 2 A

SLAVE

ADDRESS

When performing a block write to EEPROM, Bit 1 of EEPROM Register 3 must be set.

Unlike some EEPROM devices that limit block writes to within a page boundary, there is no limitation on the start address when performing a block write to EEPROM, except:

• There must be at least 32 locations from the start address

to the highest EEPROM address (9FFF) to avoid writing to invalid addresses.

02857-A-024

12 3 4 5 6

SLAVE

ADDRESS

EEPROM

ADDRESS

HIGH BYTE

(80h TO 9Fh)

EEPROM

ADDRESS

LOW BYTE

(00h TO FFh)

DATA

910

02657-A-023

Figure 23. Single-Byte Write to EEPROM

Block Write

In this operation, the master device writes a block of data to a slave device. The start address for a block write must have been set previously. In the case of the ADM1026, this is done by a Send Byte operation to set a RAM address or by a write byte/word operation to set an EEPROM address.

1. The master device asserts a start condition on the SDA.

2. The master sends the 7-bit slave address followed by the

write bit (low).

3. The addressed slave device asserts an ACK on the SDA.

4. The master sends a command code that tells the slave

device to expect a block write. The ADM1026 command code for a block write is A0h (10100000).

5. The slave asserts an ACK on the SDA.

6. The master sends a data byte (20h) that tells the slave

device that 32 data bytes are being sent to it. The master should always send 32 data bytes to the ADM1026.

7. The slave asserts an ACK on the SDA.

8. The master sends 32 data bytes.

• If the addresses cross a page boundary, both pages must be

erased before programming.

ADM1026 Read Operations

The ADM1026 uses the SMBus read protocols described here.

Receive Byte

In this operation, the master device receives a single byte from a slave device as follows:

1. The master device asserts a start condition on the SDA.

2. The master sends the 7-bit slave address followed by the

read bit (high).

3. The addressed slave device asserts an ACK on the SDA.

4. The master receives a data byte.

5. The master asserts a NO ACK on the SDA.

6. The master asserts a stop condition on the SDA to end the

transaction.

In the ADM1026, the receive byte protocol is used to read a single byte of data from a RAM or EEPROM location whose address has previously been set by a send byte or write byte/word operation. Figure 25 shows this. When reading from EEPROM, Bit 0 of EEPROM Register 3 must be set.

12 3456

SLAVE

ADDRESS

Figure 25. Single-Byte Read from EEPROM or RAM

DATA

02657-A-025

Rev. A | Page 15 of 56

ADM1026

Block Read

In this operation, the master device reads a block of data from a slave device. The start address for a block read must have been set previously. In the case of the ADM1026 this is done by a send byte operation to set a RAM address, or by a write byte/word operation to set an EEPROM address. The block read operation consists of a send byte operation that sends a block read command to the slave, immediately followed by a repeated start and a read operation that reads out multiple data bytes as follows:

1. The master device asserts a start condition on the SDA.

2. The master sends the 7-bit slave address followed by the

write bit (low).

3. The addressed slave device asserts an ACK on the SDA.

4. The master sends a command code that tells the slave

device to expect a block read. The ADM1026 command code for a block read is A1h (10100001).

5. The slave asserts an ACK on the SDA.

6. The master asserts a repeat start condition on the SDA.

7. The master sends the 7-bit slave address followed by the

read bit (high).

8. The slave asserts an ACK on the SDA.

9. The ADM1026 sends a byte count data byte that tells the

master how many data bytes to expect. The ADM1026 always returns 32 data bytes (20h), the maximum allowed by the SMBus 1.1 specification.

10. The master asserts an ACK on the SDA.

11. The master receives 32 data bytes.

12. The master asserts an ACK on the SDA after each data byte.

13. The ADM1026 issues a PEC byte to the master. The master

should check the PEC byte and issue another block read if the PEC byte is incorrect.

14. A NACK is generated after the PEC byte to signal the end

of the read.

15. The master asserts a stop condition on the SDA to end the

transaction.

A DATA 1

COMMAND

A1h BLOCK

READ

SLAVE

A S R

ADDRESS

DATA

PEC

02657-A-026

SLAVE

ADDRESS

BYTE

COUNT

Figure 26. Block Read from EEPROM or RAM

When block reading from EEPROM, Bit 0 of EEPROM Register 3 must be set.

Note that although the ADM1026 supports packet error checking (PEC), its use is optional. The PEC byte is calculated using CRC-8. The frame check sequence (FCS) conforms to CRC-8 by the polynomial:

C(x) = x

+ x2 + x1 + 1

Consult the SMBus 1.1 Specification for more information.

MEASUREMENT INPUTS

The ADM1026 has 17 external analog measurement pins that can be configured to perform various functions. It also measures two supply voltages, 3.3 V MAIN and 3.3 V STBY, and the internal chip temperature.

Pins 25 and 26 are dedicated to remote temperature measurement, while Pins 27 and 28 can be configured as analog inputs with a range of 0 V to 2.5 V, or as inputs for a second remote temperature sensor.

Pins 29 to 33 are dedicated to measuring V +12 V supplies, and the processor core voltage V remaining analog inputs, Pins 34 to 41, are general-purpose analog inputs with a range of 0 V to 2.5 V (Pins 34 and 35) or 0 V to 3 V (Pins 36 to 41).

A-to-D Converter (ADC)

These inputs are multiplexed into the on-chip, successive approximation, analog-to-digital converter. The ADC has a resolution of 8 bits. The basic input range is 0 V to 2.5 V, which

to A

is the input range of A

IN6

, but five of the inputs have

IN9

built-in attenuators to allow measurement of V +12 V, and the processor core voltage V components. To allow the tolerance of these supply voltages, the ADC produces an output of 3/4 full scale (decimal 192) for the nominal input voltage, and so has adequate headroom to cope with over voltages. Table 6 shows the input ranges of the analog inputs and output codes of the ADC.

When the ADC is running, it samples and converts an analog or local temperature input every 711 µs (typical value). Each input is measured 16 times and the measurements are averaged to reduce noise, so the total conversion time for each input is

11.38 ms.

Measurements on the remote temperature (D1 and D2) inputs take 2.13 ms. These are also measured 16 times and are averaged, so the total conversion time for a remote temperature input is 34.13 ms.

, + 5 V, − 1 2 V,

BAT

The

CCP.

, +5 V, −12 V,

BAT

, without any exter nal

CCP

Rev. A | Page 16 of 56

ADM1026

Table 6. A-to-D Output Code vs. V

+12 VIN –12 VIN +5 VIN

< 0.0625 < -15.928 < 0.026 < 0.0172 NA < 0.012 < 0.012 < 0.010 0 00000000

0.062-0.125

0.125-0.187

0.188-0.250

0.250-0.313

0.313-0.375

0.375-0.438

0.438-0.500

0.500-0.563

4.000-4.063

8.000-8.063

12.000-12.063

15.313-15.375 1.705-1.777 6.38-6.406 4.249-4.267 3.828-3.844 2.871-2.883 2.871-2.883 2.392-2.402 245 11110101

15.375-15.437 1.777-1.850 6.406-6.432 4.267-4.284 3.844-3.860 2.883-2.895 2.883-2.895 2.402-2.412 246 11110110

15.437-15.500 1.850-1.922 6.432-6.458 4.284-4.301 3.860-3.875 2.895-2.906 2.895-2.906 2.412-2.422 247 11110111

15.500-15.563 1.922-1.994 6.458-6.484 4.301-4.319 3.875-3.890 2.906-2.918 2.906-2.918 2.422-2.431 248 11111000

15.562-15.625 1.994-2.066 6.484-6.51 4.319-4.336 3.890-3.906 2.918-2.930 2.918-2.930 2.431-2.441 249 11111001

15.625-15.688 2.066-2.139 6.51-6.536 4.336-4.353 3.906-3.921 2.930-2.941 2.930-2.941 2.441-2.451 250 11111010

15.688-15.750 2.139-2.211 6.536-6.563 4.353-4.371 3.921-3.937 2.941-2.953 2.941-2.953 2.451-2.460 251 11111011

15.750-15.812 2.211-2.283 6.563-6.589 4.371-4.388 3.937-3.953 2.953-2.965 2.953-2.965 2.460-2.470 252 11111100

15.812-15.875 2.283-2.355 6.589-6.615 4.388-4.405 3.953-3.969 2.965-2.977 2.965-2.977 2.470-2.480 253 11111101

15.875-15.938 2.355-2.428 6.615-6.641 4.405-4.423 3.969-3.984 2.977-2.988 2.977-2.988 2.480-2.490 254 11111110 >15.938 >2.428 >6.634 >4.423 >3.984 >2.988 >2.988 >2.490 255 11111111

−15.928-15.855

−15.855-15.783

−15.783-15.711

−15.711-15.639

−15.639-15.566

−15.566-15.494

−15.494-15.422

−15.422-15.349

•

−11.375-11.303

•

−6.750−6.678

•

−2.125-2.053

•

Input Voltage A-to-D Output

3.3 V MAIN

3.3 V STBY

0.026-0.052 0.017-0.034 NA 0.012-0.023 0.012-0.023 0.010-0.019 1 00000001

0.052-0.078 0.034-0.052 NA 0.023-0.035 0.023-0.035 0.019-0.029 2 00000010

0.078-0.104 0.052-0.069 NA 0.035-0.047 0.035-0.047 0.029-0.039 3 00000011

0.104-0.130 0.069-0.086 NA 0.047-0.058 0.047-0.058 0.039-0.049 4 00000100

0.130-0.156 0.086-0.103 NA 0.058-0.070 0.058-0.070 0.049-0.058 5 00000101

0.156-0.182 0.103-0.120 NA 0.070-0.082 0.070-0.082 0.058-0.068 6 00000110

0.182-0.208 0.120-0.138 NA 0.082-0.094 0.082-0.094 0.068-0.078 7 00000111

0.208-0.234 0.138-0.155 NA 0.094-0.105 0.094-0.105 0.078-0.087 8 00001000

1.667-1.693 1.110-1.127 NA 0.750-0.780 0.750-0.780 0.625-0.635 64

3.333-3.359 2.000-2.016 2.000-2.016 1.500-1.512 1.500-1.512 1.250-1.260 128

5-5.026 3.330-3.347 3.000-3.016 2.250-2.262 2.250-2.262 1.875-1.885 192

BAT

CCP

IN (0–5)

Decimal Binary

IN (6–9)

(1⁄4 scale)

(1⁄2 scale)

(3⁄4 scale)

01000000

10000000

11000000

is not accurate for voltages under 1.5 V (see Figure 15).

BAT

Rev. A | Page 17 of 56

ADM1026

(

)

−

(

)

−

Voltage Measurement Inputs

The internal structure for all the analog inputs is shown in Figure 27. Each input circuit consists of an input protection diode, an attenuator, plus a capacitor to form a first-order lowpass filter that gives each voltage measurement input immunity to high frequency noise. The −12 V input also has a resistor connected to the on-chip reference to offset the negative voltage range so that it is always positive and can be handled by the ADC. This allows most popular power supply voltages to be monitored directly by the ADM1026 without requiring any additional resistor scaling.

– A

IN0

(0V – 3V)

– A

IN6

(0V – 2.5V)

+12V

IN5

IN9

21.9kΩ

109.4kΩ

52.5kΩ

113.5kΩ

21kΩ

4.6pF

9.3pF

However, when scaling A

IN0

to A

, it should be noted that

IN5

these inputs already have an on-chip attenuator, because their primary function is to monitor SCSI termination voltages. This attenuator loads any external attenuator. The input resistance of the on-chip attenuator can be between 100 kΩ and 200 kΩ. For this tolerance not to affect the accuracy, the output resistance of the external attenuator should be very much lower than this, that is, 1 kΩ in order to add not more than 1% to the total unadjusted error (TUE). Alternatively, the input can be buffered using an op amp.

0.3

()

0.3

5.2

()

5.2

tofor

IN5IN0

tofor

IN9IN6

Negative and bipolar input ranges can be accommodated by using a positive reference voltage to offset the input voltage range so that it is always positive. To monitor a negative input voltage, an attenuator can be used as shown in Figure 29.

REF

17.5kΩ

–12V

+5V

BAT

CCP

114.3kΩ

83.5kΩ

50kΩ

49.5kΩ

82.7kΩ

*SEE TEXT

21.9k

109.4kΩ

Figure 27. Voltage Measurement Inputs

9.3pF

4.6pF

4.5pF

18.5pF

MUX

02657-A-027

Setting Other Input Ranges

to A

IN0

can easily be scaled to voltages other than 2.5 V or

IN9

3 V. If the input voltage range is zero to some positive voltage, all that is required is an input attenuator, as shown in Figure 28.

Figure 28. Scaling A

IN(0–9)

− A

IN0

02657-A-028

IN9

Figure 29. Scaling and Offsetting A

IN(0–9)

− A

for Negative Inputs

IN0

IN9

02657-A-029

This offsets the negative voltage so that the ADC always sees a positive voltage. R1 and R2 are chosen so that the ADC input voltage is zero when the negative input voltage is at its maximum (most negative) value, that is:

−

This is a simple and low cost solution, but note the following:

• Because the input signal is offset but not inverted, the input

range is transposed. An increase in the magnitude of the negative voltage (going more negative) causes the input voltage to fall and give a lower output code from the ADC. Conversely, a decrease in the magnitude of the negative voltage causes the ADC code to increase. The maximum negative voltage corresponds to zero output from the ADC. This means that the upper and lower limits are transposed.

• For the ADC output to be full scale when the negative

voltage is zero, V voltage of the ADC, because V R2. If V

is equal to or less than the full-scale voltage of

must be greater than the full-scale

is attenuated by R1 and

the ADC, the input range is bipolar but not necessarily symmetrical.

This is a problem only if the ADC output must be full scale when the negative voltage is zero.

Rev. A | Page 18 of 56

ADM1026

(

)

(

)

Symmetrical bipolar input ranges can be accommodated easily by making V

equal to the full-scale voltage of the analog input,

and by adding a third resistor to set the positive full scale.

IN(0–9)

02657-A-030

Figure 30. Scaling and Offsetting A

R1 R2

IN0

−

− A

for Bipolar Inputs

IN9

Note that R3 has no effect as the input voltage at the device pin is zero when V

= negative full scale.

−

0.3

−

5.2

()

tofor

IN5IN0

IN9IN6

Also, note that R2 has no effect as the input voltage at the device pin is equal to V

Battery Measurement Input (V

The V

input allows the condition of a CMOS backup battery

BAT

when VIN = positive full scale.

)

BAT

to be monitored. This is typically a lithium coin cell such as a CR2032. The V

input is accurate only for voltages greater

BAT

than 1.5 V (see Figure 15). Typically, the battery in a system is required to keep some device powered on when the system is in a powered-off state. The V

measurement input is specially

BAT

designed to minimize battery drain. To reduce current drain from the battery, the lower resistor of the V connected, except whenever a V The total current drain on the V maximum V

voltage = 4 V), so a CR2032 CMOS battery

BAT

measurement is being made.

BAT

pin is 80 nA typical (for a

BAT

attenuator is not

BAT

functions in a system in excess of the expected 10 years. Note that when a V

measurement is not being made, the current

BAT

drain is reduced to 6 nA typical. Under normal voltage measurement operating conditions, all measurements are made in a round-robin format, and each reading is actually the result of 16 digitally averaged measurements. However, averaging is not carried out on the V

measurement to reduce measurement

BAT

time and therefore reduce the current drain from the battery.

The V

current drain when a measurement is being made is

BAT

calculated by

I ×=

BAT

PULSE

Ωk100

PERIOD

For example, when V

where T

PERIOD

and V

Input Battery Protection

BAT

= V

PULSE

= time to measure all analog inputs (273 ms typical),

input battery protection.

BAT

In addition to minimizing battery current drain, the V

= 3 V,

BAT

711

×=sI

Ωk100

measurement time (711 µs typical),

BAT

ms273

An78

BAT

measurement circuitry was specifically designed with battery protection in mind. Internal circuitry prevents the battery from being back-biased by the ADM1026 supply or through any other path under normal operating conditions. In the unlikely event of a catastrophic ADM1026 failure, the ADM1026 includes a second level of battery protection including a series 3 kΩ resistor to limit current to the battery, as recommended by UL. Thus, it is not necessary to add a series resistor between the battery and the V to the V

input to improve voltage measurement accuracy.

BAT

.5pF

Figure 31. Equivalent V

Reference Output (V

input; the battery can be connected directly

BAT

49.5kΩ

82.7kΩ

REF

3kΩ

Input Protection Circuit

BAT

)

3kΩ

DIGITAL CONTROL

ADC

02657-A-031

The ADM1026 offers an on-chip reference voltage (Pin 24) that can be used to provide a 1.82 V or 2.5 V reference voltage output. This output is buffered and specified to sink or source a load current of 2 mA. The reference voltage outputs 1.82 V if Bit 2 of Configuration Register 3 (Address 07h) is 0; it outputs

2.5 V when this bit is set to 1. This voltage reference output can be used to provide a stable reference voltage to external circuitry such as LDOs. The load regulation of the V

output is

REF

typically 0.15% for a sink current of 2 mA and 0.15% for 2 mA source current. There may be some ripple present on the V output that requires filtering (±4 m V recommended circuitry for the V

). Figure 32 shows the

MAX

output for loads less than

REF

2 mA. For loads in excess of 2 mA, external circuitry, such as that shown in Figure 33, can be used to buffer the V

ADM1026

10kΩ

0.1µF

Loads < 2 mA

REF

Figure 32. V

REF

Interface Circuit for V

REF

output.

REF

02657-A-033

Rev. A | Page 19 of 56

ADM1026

If the V nected. Do not connect V internal output buffer on the voltage reference is capacitively loaded, which can cause the voltage reference to oscillate. This affects temperature readings reported back by the ADM1026. The recommended interface circuit for the V in Figure 33.

output is not being used, it should be left uncon-

REF

to GND using a capacitor. The

REF

output is shown

REF

+12V

The forward voltage of a diode or diode-connected transistor, operated at a constant current, exhibits a negative temperature coefficient of about −2 mV/°C. Unfortunately, the absolute value of V

varies from device to device, and individual

calibration is required to null this out, so the technique is unsuitable for mass production.

The technique used in the ADM1026 is to measure the change

when the device is operated at two different currents,

in V

given by

ADM1026

REF

10kΩ

0.1µF

Figure 33. V

Interface Circuit for V

REF

50Ω

NDT3055

0.1µF

Loads > 2 mA

REF

10µF

REF

02657-A-034

TEMPERATURE MEASUREMENT SYSTEM

Local Temperature Measurement

The ADM1026 contains an on-chip band gap temperature sensor whose output is digitized by the on-chip ADC. The temperature data is stored in the local temperature value register (Address 1Fh). As both positive and negative temperatures can be measured, the temperature data is stored in twos complement format, as shown in Table 7. Theoretically, the temperature sensor and ADC can measure temperatures from

−128°C to +127°C with a resolution of 1°C. Temperatures below and above T

MIN

range of the device, however, so local temperature measurements outside this range are not possible. Temperature measurement from −128°C to +127°C is possible using a remote sensor.

Remote Temperature Measurement

The ADM1026 can measure the temperature of two remote diode sensors, or diode-connected transistors, connected to Pins 25 and 26, or 27 and 28.

Pins 25 and 26 are a dedicated temperature input channel. Pins 27 and 28 can be configured to measure a diode sensor by clearing Bit 3 of Configuration Register 1 (Address 00h) to 0. If this bit is 1, then Pins 27 and 28 are A

are outside the operating temperature

MAX

and A

IN8

IN9

()

logΔ ×

where K is Boltzmann’s constant, q is the charge on the carrier, T is the absolute temperature in Kelvins, and N is the ratio of the two currents.

Figure 34 shows the input signal conditioning used to measure the output of a remote temperature sensor. This figure shows the external sensor as a substrate transistor provided for temperature monitoring on some microprocessors, but it could equally well be a discrete transistor such as a 2N3904.

If a discrete transistor is used, the collector is not grounded and should be linked to the base. If a PNP transistor is used, the base is connected to the D− input and the emitter to the D+ input. If an NPN transistor is used, the emitter is connected to the D− input and the base to the D+ input.

To prevent ground noise from interfering with the measurement, the more negative terminal of the sensor is not referenced to ground but is biased above ground by an internal diode at the D− input.

To m e as u re Δ V

, the sensor is switched between operating

currents of I and N × I. The resulting waveform is passed through a 65 kHz low-pass filter to remove noise, and to a chopper-stabilized amplifier that performs the functions of amplification and rectification of the waveform to produce a DC voltage proportional to ΔV

. This voltage is measured

by the ADC to give a temperature output in 8-bit, twos complement format. To further reduce the effects of noise, digital filtering is performed by averaging the results of 16 measurement cycles. A remote temperature measurement takes nominally 2.14 ms.

Rev. A | Page 20 of 56

ADM1026

IN× I I

BIAS

D+

REMOTE

SENSING

RANSISTO

C1*

D–

CAPACITOR C1 IS OPTIONAL. IT IS ONLY NECESSARY IN NOISY ENVIRONMENTS. C1 = 2.2nF TYPICAL, 3nF MAX.

Figure 34. Signal Conditioning for Remote Diode Temperature Sensors

BIAS

DIODE

The results of external temperature measurements are stored in 8-bit, twos complement format, as illustrated in Table 7.

Table 7. Temperature Data Format

Temperature Digital Output Hex

−128°C 1000 0000 80

−125°C 1000 0011 83

−100°C 1001 1100 9C

−75°C 1011 0101 B5

−50°C 1100 1110 CE

−25°C 1110 0111 E7

−10°C 11110110 F6 0°C 0000 0000 00 10°C 0000 1010 0A 25°C 0001 1001 19 50°C 0011 0010 32 75°C 0100 1011 4B 100°C 0110 0100 64 125°C 0111 1101 7D 127°C 0111 1111 7F

Layout Considerations

Digital boards can be electrically noisy environments. Take these precautions to protect the analog inputs from noise, particularly when measuring the very small voltages from a remote diode sensor.

Place the ADM1026 as close as possible to the remote

•

sensing diode. Provided that the worst noise sources such as clock generators, data/address buses, and CRTs are avoided, this distance can be 4 to 8 inches.

Route the D+ and D− tracks close together, in parallel, with

•

grounded guard tracks on each side. Provide a ground plane under the tracks if possible.

Use wide tracks to minimize inductance and reduce noise

•

pickup. A 10 mil track minimum width and spacing is recommended.

OUT+

TO ADC V

LOW-PASS FILTER

= 65kHz

GND

D+

D–

Figure 35. Arrangement of Signal Tracks

OUT–

02657-A-032

10MIL 10MIL 10MIL 10MIL 10MIL 10MIL 10MIL

• Try to minimize the number of copper/solder joints, which

can cause thermocouple effects. Where copper/solder joints are used, make sure that they are in both the D+ and D− paths and are at the same temperature.

Thermocouple effects should not be a major problem

•

because 1°C corresponds to about 240 µV, and thermocouple voltages are about 3 µV/°C of temperature difference. Unless there are two thermocouples with a big temperature differential between them, thermocouple voltages should be much less than 200 mV.

Place a 0.1 µF bypass capacitor close to the ADM1026.

•

If the distance to the remote sensor is more than eight

•

inches, the use of twisted-pair cable is recommended. This works from about 6 to 12 feet.

For very long distances (up to 100 feet), use shielded

•

twisted pair such as Belden #8451 microphone cable. Connect the twisted pair to D+ and D− and the shield to GND close to the ADM1026. Leave the remote end of the shield unconnected to avoid ground loops.

Because the measurement technique uses switched current sources, excessive cable and/or filter capacitance can affect the measurement. When using long cables, the filter capacitor may be reduced or removed. Cable resistance can also introduce errors. A 1 Ω series resistance introduces about 0.5°C error.

02657-A-035

Rev. A | Page 21 of 56

ADM1026

Limit Values

Limit values for analog measurements are stored in the appropri ate limit registers. In the case of voltage measurements, high and low limits can be stored so that an interrupt request is generated if the measured value goes above or below acceptable values. In the case of temperature, a hot temperature or high limit can be programmed, and a hot temperature hysteresis or low limit can be programmed, which is usually some degrees lower. This can be useful because it allows the system to be shut down when the hot limit is exceeded, and restarted automatically when it has cooled down to a safe temperature.

Analog Monitoring Cycle Time

The analog monitoring cycle begins when a 1 is written to the start bit (Bit 0), and a 0 to the INT_Clear bit (Bit 2) of the configuration register. INT_Enable (Bit 1) should be set to 1 to enable the

turn, starting with Remote Temperature Channel 1 and ending with local temperature. As each measurement is completed, the result is automatically stored in the appropriate value register. This round-robin monitoring cycle continues until it is disabled by writing a 0 to Bit 0 of the configuration register. Because the ADC is typically left to free-run in this way, the most recently measured value of any input can be read out at any time.

For applications where the monitoring cycle time is important, it can easily be calculated.

The total number of channels measured is

Five dedicated supply voltage inputs

•

Ten general-purpose analog inputs

•

3.3 V MAIN

•

3.3 V STBY

•

Local temperature

•

Two remote temperature

•

Pins 28 and 27 are measured both as analog inputs A as remote temperature input D2+/D2−, irrespective of which configuration is selected for these pins.

If Pins 28 and 27 are configured as A for these channels are stored in Registers 27h and 29h, and the invalid temperature measurement is discarded. On the other hand, if Pins 28 and 27 are configured as D2+/D2−, the temperature measurement is stored in Register 29h, and there is no valid result in Register 27h.

As mentioned previously, the ADC performs a conversion every 711 µs on the analog and local temperature inputs and every

2.13 ms on the remote temperature inputs. Each input is

measured 16 times and averaged to reduce noise.

The total monitoring cycle time for voltage and temperature inputs is therefore nominally

(18 × 16 × 0.711) + (2 × 16 × 2.13) = 273 ms

output. The ADC measures each analog input in

INT

IN8/AIN9

, the measurements

IN8/AIN9

and

The ADC uses the internal 22.5 kHz clock, which has a tolerance of ±6%, so the worst-case monitoring cycle time is 290 ms. The fan speed measurement uses a completely separate monitoring loop, as described later.

Input Safety

Scaling of the analog inputs is performed on-chip, so external attenuators are typically not required. However, because the power supply voltages appear directly at the pins, it is advisable to add small external resistors (that is, 500 Ω) in series with the supply traces to the chip to prevent damaging the traces or power supplies should an accidental short such as a probe connect two power supplies together.

Because the resistors form part of the input attenuators, they affect the accuracy of the analog measurement if their value is too high. The worst such accident would be connecting

−12 V to +12 V where there is a total of 24 V difference. With the series resistors, this would draw a maximum current of approximately 24 mA.

ANALOG OUTPUT

The ADM1026 has a single analog output from an unsigned 8-bit DAC that produces 0 V to 2.5 V (independent of the reference voltage setting). The input data for this DAC is contained in the DAC control register (Address 04h). The DAC control register defaults to FFh during a power-on reset, which produces maximum fan speed. The analog output may be amplified and buffered with external circuitry such as an op amp and a transistor to provide fan speed control. During automatic fan speed control, described later, the four MSBs of this register set the minimum fan speed.

Suitable fan drive circuits are shown in Figure 36 through Figure 40. When using any of these circuits, note the following:

All of these circuits provide an output range from 0 V to

•

almost +12 V, apart from Figure 36, which loses the baseemitter voltage drop of Q1 due to the emitter-follower configuration.

To amplify the 2.5 V range of the analog output up to 12 V,

•

the gain of these circuits needs to be about 4.8.

Take care when choosing the op amp to ensure that its

•

input common-mode range and output voltage swing are suitable.

The op amp may be powered from the +12 V rail alone

•

or from ±12 V. If it is powered from +12 V, the input common-mode range should include ground to accommodate the minimum output voltage of the DAC, and the output voltage should swing below 0.6 V to ensure that the transistor can be turned fully off.

If the op amp is powered from −12 V, precautions such as

•

a clamp diode to ground may be needed to prevent the base-emitter junction of the output transistor being reverse-biased in the unlikely event that the output of the op amp should swing negative for any reason.

Rev. A | Page 22 of 56

ADM1026

• In all these circuits, the output transistor must have an

greater than the maximum fan current, and be

CMAX

capable of dissipating power due to the voltage dropped across it when the fan is not operating at full speed.

If the fan motor produces a large back EMF when switched

•

off, it may be necessary to add clamp diodes to protect the output transistors in the event that the output goes from full scale to zero very quickly.

12V

1/4 LM324

DAC

36kΩ

R1 10kΩ

Figure 36. Fan Drive Circuit with Op Amp and Emitter-Follower

DAC

1/4 LM324

R1 10kΩ

39kΩ

1kΩ

Figure 37. Fan Drive Circuit with Op Amp and PNP Transistor

DAC

1/4 LM324

39kΩ

100kΩ

12V

2N2219A

BD136

2SA968

12V

IRF9620

02657-A-036

02657-A-037

R2 100kΩ

R3 39kΩ

R4 10kΩ

DAC

100kΩ

Q1/Q2

MBT3904

DUAL

Figure 39. Discrete Fan Drive Circuit with P-Channel MOSFET, Single Supply

R2 100kΩ

R3 39kΩ

R4 10kΩ

DAC

Q1/Q2

MBT3904

DUAL

4.7kΩ

–12V

Figure 40. Discrete Fan Drive Circuit with P-Channel MOSFET, Dual Supply

PWM Output

Fan speed may also be controlled using pulse width modulation (PWM). The PWM output (Pin 18) produces a pulsed output with a frequency of approximately 75 Hz and a duty cycle defined by the contents of the PWM control register (Address 05h). During automatic fan speed control, described below, the four MSBs of this register set the minimum fan speed.

The open drain PWM output must be amplified and buffered to drive the fans. The PWM output is intended to be used with an NMOS driver, but may be inverted by setting Bit 1 of Test Register 1 (Address 14h) if using PMOS drivers. Figure 41 shows how a fan may be driven under PWM control using an N-channel MOSFET.

3.3V

10kΩ

TYP

12V

IRF9620

5V OR 12V FAN

+12V

IRF9620

02657-A-039

02657-A-040

R1 10kΩ

02657-A-038

Figure 38. Fan Drive Circuit with Op Amp and P-Channel MOSFET

Rev. A | Page 23 of 56

PWM

NDT3055L

02657-A-041

Figure 41. PWM Fan Drive Circuit Using an N-Channel MOSFET

ADM1026

Automatic Fan Speed Control

The ADM1026 offers a simple method of controlling fan speed according to temperature without intervention from the host processor. Monitoring must be enabled by setting Bit 0 of Configuration Register 1 (Address 00h), to enable automatic fan speed control. Automatic fan speed control can be applied to the DAC output, the PWM output, or both, by setting Bit 5 and/or Bit 6 of Configuration Register 1.

The T temperature values for the three temperature channels (on-chip sensor and two remote diodes). This is the temperature at which a fan starts to operate when the temperature sensed by the controlling sensor exceeds T different for all three channels. T complement temperature value to the T sensor channel is not required for automatic fan speed control, T

In automatic fan speed control mode, (as shown Figure 42 and Figure 43) the four MSBs of the DAC control register (Address 04h) and PWM control register (Address 05h) set the minimum values for the DAC and PWM outputs. Note that, if both DAC control and PWM control are enabled (Bits 5 and 6 of Configuration Register 1 = 1), the four MSBs of the DAC control register (Address 04h) define the minimum fan speed values for both the DAC and PWM outputs. The value in the PWM control register (Address 05h) has no effect.

registers (Addresses 10h to 12h) contain minimum

MIN

. T

MIN

for that channel should be set to 127°C (01111111).

MIN

Minimum DAC Code DAC

VoltageOutputDAC ×=

can be the same or

MIN

is set by writing a twos

MIN

registers. If any

MIN

= 16 × D

MIN

Code

5.2 256

Minimum PWM Duty Cycle PWMMIN = 6.67 × D

output jumps to full scale. To ensure that the maximum cooling capacity is always available, the fan drive is always set by the sensor channel demanding the highest fan speed.

If the temperature falls, the fan does not turn off until the temperature measured by all three temperature sensors has fallen to their corresponding T

− 4°C. This prevents the fan

MIN

from cycling on and off continuously when the temperature is close to T

MIN

Whenever a fan starts or stops during automatic fan speed control, a one-off interrupt is generated at the

output. This

INT

is described in more detail in the section on the ADM1026 Interrupt Structure.

100%

PWM UTPUT

MIN

Figure 42. Automatic PWM Fan Control Transfer Function

255

SPIN UP FOR 2 SECONDS

– 4°C T

MIN

TEMPERATURE

SPIN UP FOR 2 SECONDS

MIN

+ 20°C

240

02657-A-042

where D is the decimal equivalent of Bits 7 to 4 of the register.

DAC

UTPUT

When the temperature measured by any of the sensors exceeds the corresponding T the fan drive set to maximum (full scale from the DAC or 100% PWM duty cycle). The fan speed is then set to the minimum as

, the fan is spun up for 2 seconds with

MIN

previously defined. As the temperature increases, the fan drive increases until the temperature reaches T

The fan drive at any temperature up to 20°C above T given by

()

100

PWMPWMPWM

()

240

DACDACDAC

For simplicity of the automatic fan speed algorithm, the DAC code increases linearly up to 240, not its full scale of 255. However, when the temperature exceeds T

+ 20°C.

MIN

×−+=

MINMIN

ACTUAL

×−+=

MINMIN

+20°C, the DAC

MIN

ACTUAL

MIN

−

MIN

Figure 43. Automatic DAC Fan Control Transfer Function

Fan Inputs

MIN

– 4°C T

MIN

TEMPERATURE

MIN

+ 20°C

02657-A-043

Pins 3 to 6 and 9 to 12 may be configured as fan speed

−

MIN

measuring inputs by clearing the corresponding bit(s) of Configuration Register 2 (Address 01h), or as general-purpose logic inputs/outputs by setting bits in this register. The poweron default value for this register is 00h, which means all the inputs are set for fan speed measurement.

Rev. A | Page 24 of 56

ADM1026

Signal conditioning in the ADM1026 accommodates the slow rise and fall times typical of fan tachometer outputs. The fan tach inputs have internal 10 kΩ pull-up resistors to 3.3 V STBY. In the event that these inputs are supplied from fan outputs that exceed the supply, either resistive attenuation of the fan signal or diode clamping must be included to keep inputs within an acceptable range. Figure 44 through Figure 47 show circuits for common fan tach outputs.

If the fan tach output is open-drain or has a resistive pull-up to

, then it can be connected directly to the fan input, as shown

in Figure 44.

12V

PULL-UP

4.7kΩ TYP

OUTPUT

FAN(0–7)

TACH

Figure 44. Fan with Tach Pull-Up to +V

FAN SPEED

COUNTER

02657-A-044

If the fan output has a resistive pull-up to +12 V (or other voltage greater than 3.3 V STBY), the fan output can be clamped with a Zener diode, as shown in Figure 45. The Zener voltage should be chosen so that it is greater than V

but less than 3.3 V

STBY, allowing for the voltage tolerance of the Zener.

12V

PULL-UP

Ω

4.7k TYP

*CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8 × V

TACH

OUTPUT

FAN(0–7)

ZD1*

ZENER

Figure 45. Fan with Tach Pull-Up to Voltage > V

Clamped with Zener Diode

FAN SPEED

COUNTER

(e.g. 12 V),

02657-A-045

If the fan has a strong pull-up (less than 1 kΩ) to +12 V, or a totem pole output, a series resistor can be added to limit the Zener current, as shown in Figure 46. Alternatively, a resistive attenuator may be used, as shown in Figure 47.

R1 and R2 should be chosen such that

V2V <

PULLUP

()

PULLUP

++×<R2R1

STBYV3.3

Figure 46. Fan with Strong Tach Pull-Up to > VCC or Totem Pole Output,

FAN SPEED MEASUREMENT

The fan counter does not count the fan tach output pulses directly because the fan speed may be less than 1000 RPM and it would take several seconds to accumulate a reasonably large and accurate count. Instead, the period of the fan revolution is measured by gating an on-chip 22.5 kHz oscillator into the input of an 8-bit counter for two periods of the fan tach output, as shown in Figure 48, so the accumulated count is actually proportional to the fan tach period and inversely proportional to the fan speed.

CONFIGURATION

The monitoring cycle begins when a 1 is written to the monitor bit (Bit 0 of Configuration Register 1). The INT_Enable (Bit 1) should be set to 1 to enable the

12V

TACH

OUTPUT

PULL-UP TYP <1 kΩ OR TOTEM POLE

*CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8 × V

10kΩ

FAN(0–7)

ZD1*

ZENER

Clamped with Zener and Resistor

12V

<1 kΩ

R1*

TACH

OUTPUT

*SEE TEXT

FAN(0–7)

Figure 47. Fan with Strong Tach Pull-Up to >V

Attenuated with R1/R2

22.5kHz

CLOCK

REG. 1 BIT 0

FAN0 MEASUREMENT PERIOD

FAN0

INPUT

FAN1

INPUT

START OF MONITORING CYCLE

Figure 48. Fan Speed Measurement

output.

INT

FAN SPEED

COUNTER

FAN SPEED

COUNTER

or Totem Pole Output,

FAN1 MEASUREMENT PERIOD

02657-A-046

02657-A-047

02657-A-048

Rev. A | Page 25 of 56

ADM1026

The fan speed counter starts counting as soon as the fan channel has been switched to. If the fan tach count reaches 0xFF, the fan has failed or is not connected. If a fan is connected and running, the counter is reset on the second tach rising edge, and oscillator pulses are actually counted from the second rising tach edge to the fourth rising edge. The measurement then switches to the next fan channel. Here again, the counter begins counting and is reset on the second tach rising edge, and oscillator pulses are counted from the second rising edge to the fourth rising edge. This is repeated for the other six fan channels.

Note that fan speed measurement does not occur until 1.8 seconds after the monitor bit has been set. This is to allow the fans adequate time to spin up. Otherwise, the ADM1026 could generate false fan failure interrupts. During the 1.8 second fan spin-up time, all fan tach registers read 0x00.

To accommodate fans of different speed and/or different numbers of output pulses per revolution, a prescaler (divisor) of 1, 2, 4, or 8 may be added before the counter. Divisor values for Fans 0 to 3 are contained in the Fan 0–3 divisor register (Address 02h) and those for Fans 4 to 7 in the Fan 4–7 divisor register (Address 03h). The default value is 2, which gives a count of 153 for a fan running at 4400 RPM producing two output pulses per revolution. The count is calculated by the equation:

××

60105.22

Count

DivisorRPM

For constant-speed fans, fan failure is typically considered to have occurred when the speed drops below 70% of nominal, corresponding to a count of 219. Full scale (255) is reached if the fan speed fell to 60% of its nominal value. For temperaturecontrolled, variable-speed fans, the situation is different.

Limit Values

Fans generally do not over-speed if run from the correct voltage, so the failure condition of interest is under speed due to electrical or mechanical failure. For this reason, only low speed limits are programmed into the limit registers for the fans. It should be noted that because fan period rather than speed is being measured, a fan failure interrupt occurs when the measurement exceeds the limit value.

Fan Monitoring Cycle Time

The fan speeds are measured in sequence from 0 to 7. The monitoring cycle time depends on the fan speed, the number of tach output pulses per revolution, and the number of fans being monitored.

If a fan is stopped or running so slowly that the fan speed counter reaches 255 before the second tach pulse after initialization, or before the fourth tach pulse during measurement, the measurement is terminated. This also occurs if an input is configured as GPIO instead of fan. Any channels connected in this manner time out after 255 clock pulses.

The worst-case measurement time for a fan-configured channel occurs when the counter reaches 254 from start to the second tach pulse and reaches 255 after the second tach pulse. Taking into account the tolerance of the oscillator frequency, the worstcase measurement time is

509 × D × 0.05 ms

where: 509 is the total number of clock pulses. D is the divisor: 1, 2, 4, or 8.

0.05 ms is the worst-case oscillator period in ms.

The worst-case fan monitoring cycle time is the sum of the worst-case measurement time for each fan.

Table 8 shows the relationship between fan speed and time per revolution at 60%, 70%, and 100% of nominal RPM for fan speeds of 1100, 2200, 4400, and 8800 RPM, and the divisor that

Although the fan monitoring cycle and the analog input monitoring cycle are started together, they are not synchronized in any other way.

would be used for each of these fans, based on two tach pulses per revolution.

Table 8. Fan Speeds and Divisors

Time Per Divisor RPM Nominal Rev RPM (ms) 70% RPM Rev 70% (ms) 60% RPM Rev 60% (ms)

÷ 1 8800 6.82 6160 9.74 5280 11.36 ÷ 2 4400 13.64 3080 19.48 2640 22.73 ÷ 4 2200 27.27 1540 38.96 1320 45.45 ÷ 8 1100 54.54 770 77.92 660 90.9

Rev. A | Page 26 of 56

ADM1026

Chassis Intrusion Input

The chassis intrusion input is an active high input intended for detection and signaling of unauthorized tampering with the system. When this input goes high, the event is latched in Bit 6 of Status Register 4, and an interrupt is generated. The bit remains set until cleared by writing a 1 to CI clear, Bit 1 of Configuration Register 3 (05h), as long as battery voltage is connected to the V

input. The CI clear bit itself is cleared by

BAT

writing a 0 to it.

The CI input detects chassis intrusion events even when the ADM1026 is powered off (provided battery voltage is applied to

) but does not immediately generate an interrupt. Once a

BAT

chassis intrusion event is detected and latched, an interrupt is generated when the system is powered on.

The actual detection of chassis intrusion is performed by an external circuit that detects, for example, when the cover has been removed. A wide variety of techniques may be used for the detection, for example:

A microswitch that opens or closes when the cover is

•

removed.

A reed switch operated by magnet fixed to the cover.

•

A hall-effect switch operated by magnet fixed to the cover.

•

A phototransistor that detects light when the cover is

•

removed.

The chassis intrusion input can also be used for other types of alarm input. Figure 49 shows a temperature alarm circuit using an AD22105 temperature switch sensor. This produces a lowgoing output when the preset temperature is exceeded, so the output is inverted by Q1 to make it compatible with the CI input. Q1 can be almost any small-signal NPN transistor, or a TTL or CMOS inverter gate may be used if one is available. See the AD22105 data sheet on the Analog Devices, Inc. website (www.analog.com) for information on selecting R

SET

Figure 49. Using the CI Input with a Temperature Sensor

AD22105

TEMPERATURE

SENSOR

10kΩ

SET

02657-A-049

General-Purpose I/O Pins (Open Drain)

The ADM1026 has eight pins that are dedicated to generalpurpose logic input/output (Pins 1, 2, and 43 to 48), eight pins that can be configured as general-purpose logic pins or fan speed inputs (Pins 3 to 6, and 9 to 12), and one pin that can be configured as GPIO16 or the bidirectional

THERM

(Pin 42). The GPIO/FAN pins are configured as generalpurpose logic pins by setting Bits 0 to 7 of Configuration Register 2 (Address 01h). Pin 42 is configured as GPIO16 by setting Bit 0 of Configuration Register 3, or as the

THERM

function by clearing this bit.

Each GPIO pin has four data bits associated with it, two bits in one of the GPIO configuration registers (Addresses 08h to 0Bh), one in the GPIO status registers (Addresses 24h and 25h), and one in the GPIO mask registers (Addresses 1Ch and 1Dh)

Setting a direction bit = 1 in one of the GPIO configuration registers makes the corresponding GPIO pin an output. Clearing the direction bit to 0 makes it an input.

Setting a polarity bit = 1 in one of the GPIO configuration registers makes the corresponding GPIO pin active high. Clearing the polarity bit to 0 makes it active low.

When a GPIO pin is configured as an input, the corresponding bit in one of the GPIO status registers is read-only, and is set when the input is asserted (“asserted” may be high or low depending on the setting of the polarity bit).

When a GPIO pin is configured as an output, the corresponding bit in one of the GPIO status registers becomes read/write. Setting this bit then asserts the GPIO output. (Here again, “asserted” may be high or low depending on the setting of the polarity bit.)

The effect of a GPIO status register bit on the

output can

INT

be masked out by setting the corresponding bit in one of the GPIO mask registers. When the pin is configured as an output, this bit is automatically masked to prevent the data written to the status bit from causing an interrupt, with the exception of GPIO16, which must be masked manually by setting Bit 7 of Mask Register 4 (Reg 1Bh).

When configured as inputs, the GPIO pins may be connected to external interrupt sources such as temperature sensors with digital output. Another application of the GPIO pins would be to monitor a processor’s voltage ID code (VID code).

Rev. A | Page 27 of 56

ADM1026

ADM1026 Interrupt Structure

The Interrupt Structure of the ADM1026 is shown in Figure 53. Interrupts can come from a number of sources, which are combined to form a common

this output pulls low. The

output. When

INT

pin has an internal, 100 kΩ

INT

pull-up resistor.

Analog/Temperature Inputs

As each analog measurement value is obtained and stored in the appropriate value register, the value and the limits from the corresponding limit registers are fed to the high and low limit comparators. The device performs greater than comparisons to the high limits. An out-of-limit is also generated if a result is less than or equal to a low limit. The result of each comparison (1 = out of limit, 0 = in limit) is routed to the corresponding bit input of Interrupt Status Register 1, 2, or 4 via a data demultiplexer, and used to set that bit high or low as appropriate. Status bits are self-clearing. If a bit in a status register is set due to an out-of-limit measurement, it continues to cause

to be asserted as long as it remains set, as described later.

INT However, if a subsequent measurement is in limit, it is reset and

does not cause

to be reasserted. Status bits are unaffected

INT

by clearing the interrupt.

is asserted,

INT

Interrupt Mask Registers 1, 2, and 4 have bits corresponding to each of the interrupt status register bits. Setting an interrupt mask bit high conceals an asserted status bit from display on Interrupt Pin 17. Setting an interrupt mask bit low allows the corresponding status bit to be asserted and displayed on Pin 17. After mask gating, the status bits are all OR’ed together to produce the analog and fan interrupt that is used to set a latch. The output of this latch is OR’ed with other interrupt sources to produce the

output. This pulls low if any unmasked status

INT

bit goes high, that is, when any measured value goes out of limit.

When an

output caused by an out-of-limit analog/

INT

temperature measurement is cleared by one of the methods described later, the latch is reset. It is not set again, and

INT

not reasserted until after two local temperature measure-ments have been taken, even if the status bit remains set or a new analog/temperature event occurs, as shown in Figure 50. This delay corresponds to almost two monitoring cycles, and is about 530 ms. However, interrupts from other sources such as a fan or GPIO can still occur. This is illustrated in Figure 51.

START OF ANALOG

START OF ANALO MONITORING CYCLE

INT

OUT-OF-LIMIT

MEASUREMENT

INT CLEARED

LOCAL TEMPERATURE MEASUREMENT

START OF ANALOG MONITORING CYCLE

FULL MONITORING CYCLE = 273ms

Figure 50. Delay After Clearing

OUT-OF-LIMIT MEASUREMENT

Before Reassertion

INT

LOCAL

TEMPERATURE

MEASUREMENT

MONITORING CYCLE

INT RE-ASSERTED

02657-A-051

START OF ANALO MONITORING CYCLE

INT

OUT-OF-LIMIT MEASUREMENT

INT CLEARED

NEW INT FROM FAN

LOCAL TEMPEREATURE MEASUREMENT

INT CLEARED

START OF ANALOG MONITORING CYCLE

GPIO DE-ASSERTED

NEW

INT

FROM GPIO

Figure 51. Other Interrupt Sources Can Reasser t

LOCAL TEMPERATURE

MEASUREMENT

Immediately

INT

START OF ANALOG MONITORING CYCLE

INT RE-ASSERTED

02657-A-052

Rev. A | Page 28 of 56

ADM1026

Status Register 4 also stores inputs from two other interrupt sources that operate in a different way from the other status bits. If automatic fan speed control (AFC) is enabled, Bit 4 of Status Register 4 is set whenever a fan starts or stops. This bit causes a one-off

the next monitoring cycle and if not cause

FAN ON

FAN OFF

In a similar way, a change of state at the

output as shown in Figure 52. It is cleared during

INT

has been cleared, it does

INT

to be reasserted.

INT

INT CLEARED BY STATUS REGULAR 1 READ, BIT 2 OF CONFIGURATION REGULAR 1 SET, OR ARA

Figure 52. Assertion of

INT

Due to AFC Event

THERM

output

02657-A-053

(described in more detail later), sets Bit 3 of Status Register 4 and causes a one-off

the

THERM

output also causes Bit 0 of Status Register 1, Bit 1

output. A change of state at

INT

of Status Register 1, or Bit 0 of Status Register 4 to be set, depending on which temperature channel caused the

THERM

event. This bit is reset during the next monitoring cycle, provided the temperature channel is within the normal high and low limits.

Fan Inputs

Fan inputs generate interrupts in a similar way to analog/ temperature inputs, but as the analog/ temperature inputs and fan inputs have different monitoring cycles, they have separate interrupt circuits. As the speed of each fan is measured, the output of the fan speed counter is stored in a value register. The result is compared to the fan speed limit and is used to set or clear a bit in Status Register 3. In this case, the fan is monitored only for under-speed (fan counter > fan speed limit). Mask Register 3 is used to mask fan interrupts. After mask gating, the fan status bits are OR’ed together and used to set a latch, whose output is OR’ed with other interrupt sources to produce the

INT

output.

Like the analog/temp interrupt, an

output caused by an

INT

out-of-limit fan speed measurement, once cleared, is not reasserted until the end of the next monitoring cycle, although other interrupt sources may cause

to be asserted.

INT

GPIO and CI Pins. When GPIO pins are configured as inputs, asserting a GPIO input (high or low, depending on polarity) sets the corresponding GPIO status bit in Status Registers 5 and 6, or Bit 7 of Status Register 4 (GPIO16). A chassis intrusion event sets Bit 6 of Status Register 4.

The GPIO and CI status bits, after mask gating, are OR’ed together and OR’ed with other interrupt sources to produce the

output. GPIO and CI interrupts are not latched and cannot

INT be cleared by normal interrupt clearing. They can only be

cleared by masking the status bits or by removing the source of the interrupt.

ENABLING AND CLEARING INTERRUPTS

The Register 1 (INT_Enable) is high, and Bit 2 (INT_Clear) is low.

INT

•

Bidirectional

The ADM1026 has a second interrupt pin (GPIO16/ Pin 42) that responds only to critical thermal events. The

THERM This function is useful for CPU throttling or system shutdown.

In addition, whenever outputs go full scale to provide fail-safe system cooling. This

output is enabled by setting Bit 4 of Configuration Register 1 (Register 00h). Whenever a

Status Register 4 (Reg 23h) is set, even if the is disabled (Bit 4 of Configuration Register 1 = 0). In this case,

the not forced to full scale.

Three thermal limit registers are provided for the three temperature sensors at Addresses 0Dh to 0Fh. These registers are dedicated to the

limit registers have any effect on the

If any of the temperature measurements exceed the corresponding limit,

outputs go to maximum to drive any cooling fans to full speed.

To avoid cooling fans cycling on and off continually when the temperature is close to the limit, a fixed hysteresis of 5°C is provided.

temperature of all three sensors is 5°C below the limit.

Whenever the shown in Figure 54. However, this is edge-triggered, so if is subsequently cleared by one of the methods previously

described, it is not reasserted, even if

THERM

output is enabled when Bit 1 of Configuration

INT

may be cleared if

Status Register 1 is read. Ideally, if polling the status

registers trying to identify interrupt sources, Status Register 1 should be polled last, because a read of Status Register 1 clears all the other interrupt status registers.

The ADM1026 receives the alert response address (ARA)

(0001 100) over the SMBus.

Bit 2 of Configuration Register 1 is set.

THERM

pin goes low whenever a

THERM

status bit is set, but the PWM and DAC outputs are

THERM

is asserted (low) and the DAC and PWM

is only deasserted when the measured

THERM

is activated, the PWM and DAC

THERM

function and none of the other

output changes,

limit is exceeded.

limit is exceeded, Bit 3 of

function

THERM

INT

THERM

output.

is asserted, as

INT

remains asserted.

causes

THERM

to be reasserted only when it changes state.

INT

Rev. A | Page 29 of 56

ADM1026

FROM ANALOG/TEMP

HIGH LIMIT

VALUE

LOW LIMIT

VALUE

FROM FAN SPEED

VALUE AND

LIMIT REGISTERS

HIGH LIMIT

VALUE AND LIMIT

REGISTERS

HIGH AND

LOW LIMIT

COMPARATORS

HIGH LIMIT

COMPARATOR

1 = OUT

OF LIMIT

1 = OUT

OF LIMIT

MASK DATA FROM

SMBus (SAME BIT

NAMES AND ORDER

AS STATUS BITS)

DATA

DEMULTIPLEXER

MASK DATA FROM

SMBus (SAME BIT

NAMES AND ORDER

AS STATUS BITS)

MASK DATA FROM

SMBus (SAME BIT

NAMES AND ORDER

AS STATUS BITS)

DATA

DEMULTIPLEXER

MASK DATA FROM

SMBus (SAME BIT

NAMES AND ORDER

AS STATUS BITS)

EXT1 TEMP

EXT 2 TEMP

3.3V STBY

3.3V MAIN +5V

CCP

+12V –12V

A A A A A A A A

INT TEMP

BAT

IN8

THERM

AFC

RESERVED

GPIO16

FAN0 FAN1 FAN2 FAN3 FAN4 FAN5 FAN6 FAN7

IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7

0 1 2 3 4

STATUS

6 7

MASK

0 1 2 3 4

STATUS

6 7

MASK

0 1 2 3 4

STATUS

6 7

MASK

0 1 2 3 4

STATUS

6 7

MASK

MASK GATING × 8

STATUS BIT

MASK BIT

MASK GATING × 8

STATUS BIT

MASK BIT

MASK GATING × 8

STATUS BIT

MASK BIT

MASK GATING × 8

STATUS BIT

MASK BIT

CI GPIO16

IN OUT

LATCH

RESET

IN OUT

LATCH

RESET

INT

INT ENABLE

GPIO0 TO GPIO7

MASKING DATA

FROM SMBus

GPIO8 TO GPIO15

MASKING DATA

FROM SMBus

STATUS REGISTER 5

MASK REGISTER 5

STATUS REGISTER 6

MASK REGISTER 6

Figure 53. Interrupt Structure

Rev. A | Page 30 of 56

MASK GATING × 8

STATUS BIT

MASK BIT

MASK GATING × 8

STATUS BIT

MASK BIT

INT CLEAR

02657-A-050

ADM1026

Note that the

THERM

pin is bidirectional, so

THERM

may be

pulled low externally as an input. This causes the PWM and DAC outputs to go to full scale until

again. To disable

THERM

as an input, set Bit 0 of Configuration

THERM

is returned high

Register 3 (Reg. 07h). This configures Pin 42 as GPIO16 and prevents a low on Pin 42 from driving the fans at full speed.

3.3VSTBY

3.3VMAIN

RESETSTBY

~1V

TEMPERATURE

THERM LIMIT

THERM LIMIT – 5°C

THERM

INT

INT CLEARED BY STATUS REG 1 READ, BIT 2 OF CONFIG. REG. 1 SET, OR ARA

Figure 54. Assertion of

INT

Due to

THERM

Event

Reset Input and Outputs

The ADM1026 has two active low, power-on reset outputs, RESETMAIN

RESETSTBY

and

RESETSTBY

monitors 3.3 V STBY. At power-up,

. These operate as follows.

RESETSTBY

asserted (pulled low) until 180 ms after 3.3 V STBY rises above the reset threshold.

RESETMAIN up,

RESETMAIN

monitors 3.3 V MAIN. This means that at power-

is asserted (pulled low) until 180 ms after

3.3 V MAIN rises above the reset threshold.

If 3.3 V MAIN rises with or before DV remains asserted until 180 ms after

RESETMAIN

can also function as a RESET input. Pulling this

RESETMAIN

RESETSTBY

is negated.

pin low resets the registers, which are initialized to their default values by a software reset. (See the Software Reset Function section for register details).

Note that the 3.3 V STBY pin supplies power to the ADM1026. In applications that do not require monitoring of a 3.3 V STBY and 3.3 V MAIN supply, these two pins should be connected together (3.3 V MAIN should not be left floating).

To ensure that the 3.3 V STBY pin does not become backdriven, the 3.3 V STBY supply should power on before all other voltages in the system.

See Table 3 for more information about pin configuration.

02657-A-054

RESETMAIN

180ms

POWER-ON RESET

Figure 55. Operation of Offset Outputs

180ms

02657-A-055

NAND TREE TESTS

A NAND tree is provided in the ADM1026 for automated test equipment (ATE) board-level connectivity testing. This allows the functionality of all digital inputs to be tested in a simple manner and any pins that are nonfunctional or shorted together to be identified. The structure of the NAND tree is shown in Figure 56. The device is placed into NAND tree test mode by powering up with Pin 25 held high. This pin is sampled automatically after power-up, and if it is connected high, then the NAND test mode is invoked.

GPIO8

FAN0

FAN1

FAN2

INT

SDA

SCL

FAN7

FAN3

FAN4

FAN5

FAN6

Figure 56. NAND Tree

The NAND tree test may be carried out in one of two ways.

Start with all inputs low and take them high in turn,

1. starting with the input nearest to NTEST_OUT (GPIO16/

THERM

) and working back up the tree to the input furthest from NTESTOUT ( the characteristic output pattern shown in Figure 57, with

NTESTOUT toggling each time an input is taken high.

Start with all inputs high and take them low in turn,

2. starting with the input furthest from NTEST_OUT (

and working down the tree to the input nearest to NTEST_OUT (GPIO16/

similar output pattern to Figure 58.

GPIO9

GPIO10

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

GPIO16

THERM

NTESTOUT

). This should give

INT

). This should give a

INT

02657-A-056

)

Rev. A | Page 31 of 56

ADM1026

Notes

• For a NAND tree test to work, all outputs (

, RSTMAIN,

INT

RSTSTBY, and PWM) must remain high during the test.

When generating test waveforms, allow for a typical

•

propagation delay of 500 ns through the NAND tree.

•

If any of the inputs shown in Figure 56 are unused, they

should not be connected direct to ground, but via a resistor such as 10 kΩ. This allows the automatic test equipment (ATE) to drive every input high so that the NAND tree test can be properly carried out.

GPIO16

GPIO15

GPIO14

GPIO13

GPIO12

GPIO11

GPIO10

GPIO9

GPIO8

FAN0

FAN1

FAN2

FAN3

FAN4

FAN5

FAN6

FAN7

SCL

SDA

INT

NTESTOUT

Figure 57. NAND Tree Test Taking Inputs High in Turn

In the event of an input being nonfunctional (stuck high or low) or two inputs shorted together, the output pattern is different. Some examples are given in Figure 59 through Figure 61.

INT

SDA

SCL

FAN7

FAN6

FAN5 FAN4

FAN3

FAN2

FAN1

FAN0 GPIO8

GPIO9

GPIO10

GPIO11

GPIO12 GPIO13

GPIO14

GPIO15

GPIO16

NTESTOUT

02657-A-058

Figure 58. NAND Tree Test Taking Inputs Low in Turn

GPIO16

GPIO15

GPIO14

GPIO13

GPIO12

GPIO11

GPIO10

GPIO9

GPIO8

FAN0

02657-A-057

FAN1

NTESTOUT

Figure 59. NAND Tree Test with GPIO11 Stuck Low

02657-A-059

Figure 59 shows the effect of one input being stuck low. The output pattern is normal until the stuck input is reached. Because that input is permanently low, neither it nor any inputs further up the tree can have any effect on the output.

Rev. A | Page 32 of 56

ADM1026

Figure 60 shows the effect of one input being stuck high. Taking GPIO12 high should take the output high. However, the next input up the tree, GPIO11, is already high, so the output immediately goes low again, causing a missing pulse in the output pattern.

GPIO16

GPIO15

GPIO14

GPIO13

GPIO12

GPIO11

GPIO10

GPIO9

GPIO8

FAN0

FAN1

NTESTOUT

Figure 60. NAND Tree Test with One Input Stuck High

A similar effect occurs if two adjacent inputs are shorted together. The example in Figure 61 assumes that the current sink capability of the circuit driving the inputs is considerably higher than the source capability, so the inputs are low if either is low, but high only if both are high.

When GPIO12 goes high the output should go high. But because GPIO12 and GPIO11 are shorted, they both go high together, causing a missing pulse in the output pattern.

GPIO16

GPIO15

GPIO14

GPIO13

GPIO12

GPIO11

GPIO10

GPIO9

GPIO8

FAN0

FAN1

NTESTOUT

Figure 61. NAND Tree Test with Two Inputs Shorted

USING THE ADM1026

When power is first applied, the ADM1026 performs a poweron reset on all its registers (not EEPROM), which sets them to default conditions as shown in Table 12. In particular, note that all GPIO pins are configured as inputs to avoid possible conflicts with circuits trying to drive these pins.

02657-A-060

02657-A-061

The ADM1026 can also be initialized at any time by writing a 1 to Bit 7 of Configuration Register 1, which sets some registers to their default power-on conditions. This bit should be cleared by writing a 0 to it.

After power-on, the ADM1026 must be configured to the user’s specific requirements. This consists of

•

Writing values to the limit registers. Configuring Pins 3 to 6, and 9 to 12 as fan inputs or GPIO,

•

using Configuration Register 2 (Address 01h).

Setting the fan divisors using the fan divisor registers

•

(Addresses 02h and 03h).

Configuring the GPIO pins for input/output polarity, using

•

GPIO Configuration Registers 1 to 4 (Addresses 08h to 0Bh) and Bits 6 and 7 of Configuration Register 3.

Setting mask bits in Mask Registers 1 to 6 (Addresses 18h

•

to 1Dh) for any inputs that are to be masked out.

Setting up Configuration Registers 1 and 3, as described in

•

Table 9 and Table 10.

Table 9. Configuration Register 1

Bit Description

Controls the monitoring loop of the ADM1026. Setting Bit 0 low stops the monitoring loop and puts the ADM1026 into low power mode and reduces power consumption. Serial bus communication is still possible with any register in the ADM1026 while in low power mode. Setting bit 0 high starts the monitoring loop.

Enables or disables the INT Bit 1 high enables the INT

interrupt output. Setting

output, setting Bit 1 low

disables the output.

Used to clear the INT

interrupt output when set high. GPIO pins and interrupt status register contents are not affected.

Configures Pins 27 and 28 as the second external temperature channel when 0, and as A

and A

IN8

IN9

when set to 1.

4 5

Enables the THERM Enables automatic fan speed control on the DAC

output when set to 1.

Enables automatic fan speed control on the PWM output when set to 1.

7 Performs a soft reset when set to 1.

Table 10. Configuration Register 3

Bit Description

Configures Pin 42 as GPIO when set to 1 or as THERM when cleared to 0.

Clears the CI latch when set to 1. Thereafter, a 0 must be written to allow subsequent CI detection.

Selects V

as 2.5 V when set to 1 or as 1.82 V when

REF

cleared to 0.

3–5 Unused. 6, 7 Set up GPIO16 for direction and polarity.

Rev. A | Page 33 of 56

ADM1026

Starting Conversion

The monitoring function (analog inputs, temperature, and fan speeds) in the ADM1026 is started by writing to Configuration Register 1 and setting Start (Bit 0) high. The

(Bit 1) should be set to 1, and enable interrupts. The to 1 to enable temperature interrupts at the from initially starting together, the analog measurements and

fan speed measurements proceed independently, and are not synchronized in any way.

THERM

Clear (Bit 2) set to 0 to

INT

enable bit (Bit 4) should be set

Reduced Power Mode

The ADM1026 can be placed in a low power mode by setting Bit 0 of the configuration register to 0. This disables the internal ADC.

Software Reset Function

As previously mentioned, the ADM1026 can be reset in software by setting Bit 7 of Configuration Register 1 (Reg. 00h) to 1. Configuration Register 1, 00h, should then be manually cleared. Note that the software reset differs from a power-on reset in that only some of the ADM1026 registers are reinitialized to their power-on default values. The registers that are initialized to their default values by the software reset are

_Enable

INT

THERM

pin. Apart

Note that the limit registers (0Dh to 12h, 40h to 6Dh) are not reset by the software reset function. This can be useful if one needs to reset the part but does not want to reprogram all parameters again. Note that a power-on reset initializes all registers on the ADM1026, including the limit registers.

Application Schematic

Figure 62 shows how the ADM1026 could be used in an application that requires system management of a PC or server. Several GPIOs are used to read the VID codes of the CPU. Up to two CPU temperature measurements can be read back. All power supply voltages are monitored in the system. Up to eight fan speeds can be measured, irrespective of whether they are controlled by the ADM1026 or hardwired to a system supply. The V

output includes the recommended filtering circuitry.

REF

Configuration Registers (Registers 01h to 0Bh)

•

Mask Registers 1 to 6, internal temperature offset, and

•

Status Registers 4, 5, and 6 (Registers 18h to 25h)

All value registers (Registers 1Fh, 20h to 3Fh)

•

External 1 and External 2 Offset Registers (6Eh, 6Fh)

•

Rev. A | Page 34 of 56

ADM1026

_OUT

SYS_THERM

37 38 39 40 41 42 43 44

45 46 47 48

CCP

CPU1_V

CPU2_V

+12 VIN–12 VIN+5 V

3635343332313029282726

IN4

IN3

IN2

IN1

IN0

THERM

GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10

IN5AIN6AIN7

CCP

+12 V

–12V

+5 V

IN8

BAT

D2+/A

ADM1026_SKT

CPU1_THERMDC

CPU1_THERMDA

CPU2_THERMDC

CPU2_THERMDA

IN9

D1–

D1+

D2–/A

DAC

3.3V STBY AGND

RESETMAIN

RESETSTBY

PWM

ADD SDA

SCL

REF

INT

24 23 22 21 20 19 18 17

16 15 14 13

REF

10kΩ

0–2.5V_OUT

0.1µF

3.3V_STBY

470kΩ

10kΩ

CPURESET

SMB_ALERT

POWER_GOOD

CPU1_VID4

CPU1_VID3

CPU1_VID2

CPU1_VID1

+12V

CPU1_VID0

GPIO9

GPIO8

FAN0/GPIO0

FAN1/GPIO1

123456789

FAN

FAN4/GPIO4

FAN5/GPIO5

FAN6/GPIO6

3.3VMAIN

FAN2/GPIO2

FAN3/GPIO3

DGND

FAN7/GPIO7

101112

+12V12

+12V

Figure 62. ADM1026 Schematic

3.3V STDY

FAN

+12V

2kΩ

SDATA

SCLOCK

FAN

02657-A-062

Rev. A | Page 35 of 56

ADM1026

REGISTERS

Table 11. Address Pointer Register

Bit Name

7–0 Address Pointer Write Address of ADM1026 registers. See the following tables for details.

Table 12. List of Registers

Hex Address Name Power-On Value Description

00 Configuration 1 00h Configures various operating parameters 01 Configuration 2 00h Configures Pins 3–6 and 9–12 as fan inputs or GPIO 02 Fan 0–3 Divisor 55h Sets oscillator frequency for Fan 0–3 speed measurement 03 Fan 4–7 Divisor 55h Sets oscillator frequency for Fan 4–7 speed measurement 04 DAC Control FFh

05 PWM Control FFh

06 EEPROM Register 100h For factory use only 07 Configuration Register 300h

08 GPIO Config 1 00h Configures GPIO0 to GPIO3 as input or output and as active high or active low 09 GPIO Config 2 00h Configures GPIO4 to GPIO7 as input or output and as active high or active low 0A GPIO Config 3 00h

0B GPIO Config 4 00h

0C EEPROM Register 2 00h For factory use only 0D

Int Temp THERM

TDM1 THERM

TDM2 THERM

10 Int Temp T

11 TDM1 T

12 TDM2 T

MIN

Limit

28h (40°C)

MIN

40h (64°C)

13 EEPROM Register 3 00h Configures EEPROM for read/write/erase, etc. 14 Test Register 1 00h Manufacturer’s test register 15 Test Register 2 00h For manufacturer’s use only 16 Manufacturer’s ID 41h Contains manufacturer’s ID code 17 Revision 4xh Contains code for major and minor revisions 18 Mask Register 1 00h Interrupt mask register for temperature and supply voltage faults 19 Mask Register 2 00h Interrupt mask register for analog input faults 1A Mask Register 3 00h Interrupt mask register for fan faults 1B Mask Register 4 00h 1C Mask Register 5 00h Interrupt mask register for GPIO0 to GPIO7 1D Mask Register 6 00h Interrupt mask register for GPIO8 to GPIO15 1E Int Temp Offset 00h Offset register for internal temperature measurement 1F Int Temp Value 00h Measured temperature from on–chip sensor 20 Status Register 1 00h Interrupt status register for external temp and supply voltage faults 21 Status Register 2 00h Interrupt status register for analog input faults 22 Status Register 3 00h Interrupt status register for fan faults 23 Status Register 4 00h

37h (55°C)

50h (80°C)

Description

Contains value for fan speed DAC (analog fan speed control) or minimum value for automatic fan speed control

Contains value for PWM fan speed control or minimum value for automatic fan speed control

, V

Configuration register for THERM

and GPIO16

REF

Configures GPIO8 to GPIO11 as input or output and as active high or active low

Configures GPIO12 to GPIO15 as input or output and as active high or active low

High limit for THERM interrupt output based on internal temperature measurement

High limit for THERM interrupt output based on Remote Channel 1 (D1) temperature measurement

High limit for THERM interrupt output based on Remote Channel 2 (D2) temperature measurement

value for automatic fan speed control based on internal temperature

MIN

measurement

value for automatic fan speed control based on Remote Channel 1 (D1)

MIN

temperature measurement

value for automatic fan speed control based on Remote Channel 2 (D2)

MIN

temperature measurement

, A

Interrupt mask register for local temp, V

Interrupt status register for local temp, V

, THERM, AFC, CI and GPIO16

BAT

IN8

, A

, THERM, AFC, CI, and GPIO16

BAT

IN8

Rev. A | Page 36 of 56

ADM1026

Hex Address Name Power-On Value Description

24 Status Register 5 00h Interrupt status register for GPIO0 to GPIO7 25 Status Register 6 00h Interrupt status register for GPIO8 to GPIO15 26 V 27 A 28 TDM1 Value 00h Measured value of remote temperature channel 1 (D1) 29 TDM2/A 2A 3.3 V STBY Value 00h Measured value of 3.3 V STBY 2B 3.3 V MAIN Value 00h Measured value of 3.3 V MAIN 2C +5 V Value 00h Measured value of +5 V supply 2D V 2E +12 V Value 00h Measured value of +12 V supply 2F 30 A 31 A 32 A 33 A 34 A 35 A 36 A 37 A 38 FAN0 Value 00h Measured speed of Fan 0 39 FAN1 Value 00h Measured speed of Fan 1 3A FAN2 Value 00h Measured speed of Fan 2 3B FAN3 Value 00h Measured speed of Fan 3 3C FAN4 Value 00h Measured speed of Fan 4 3D FAN5 Value 00h Measured speed of Fan 5 3E FAN6 Value 00h Measured speed of Fan 6 3F FAN7 Value 00h Measured speed of Fan 7 40 TDM1 High Limit 64h (100°C) High limit for Remote Temperature Channel 1 (D1) measurement 41 TDM2/A 42 3.3 V STBY High Limit FFh High limit for 3.3 V STBY measurement 43 3.3 V MAIN High Limit FFh High limit for 3.3 V MAIN measurement 44 +5 V High Limit FFh High limit for +5 V supply measurement 45 V 46 +12 V High Limit FFh High limit for +12 V supply measurement 47 48 TDM1 Low Limit 80h Low limit for Remote Temperature Channel 1 (D1) measurement 49 TDM2/A 4A 3.3 V STBY Low Limit 00h Low limit for 3.3 V STBY measurement 4B 3.3 V MAIN Low Limit 00h Low limit for 3.3 V MAIN measurement 4C +5 V Low Limit 00h Low limit for +5 V supply 4D V 4E +12 V Low Limit 00h Low limit for +12 V supply measurement 4F 50 A 51 A 52 A 53 A 54 A 55 A 56 A 57 A

Value 00h Measured value of V

BAT

Value 00h Measured value of A

IN8

Value 00h Measured value of remote temperature channel 2 (D2) or A

IN9

Value 00h Measured value of processor core voltage

CCP

−12 V Value Value 00h Measured value of A

IN0

Value 00h Measured value of A

IN1

Value 00h Measured value of A

IN2

Value 00h Measured value of A

IN3

Value 00h Measured value of A

IN4

Value 00h Measured value of A

IN5

Value 00h Measured value of A

IN6

Value 00h Measured value of A

IN7

High Limit 64h (100°C) High limit for Remote Temperature Channel 2 (D2) or A

IN9

High Limit FFh High limit for processor core voltage measurement

CCP

−12 V High Limit

Low Limit 80h Low limit for Remote Temperature Channel 2 (D2) or A

IN9

Low Limit 00h Low limit for processor core voltage measurement

CCP

−12 V Low Limit High Limit FFh High limit for A

IN0

High Limit FFh High limit for A

IN1

High Limit FFh High limit for A

IN2

High Limit FFh High limit for A

IN3

High Limit FFh High limit for A

IN4

High Limit FFh High limit for A

IN5

High Limit FFh High limit for A

IN6

High Limit FFh High limit for A

IN7

00h

FFh

00h

Measured value of −12 V supply

High limit for −12 V supply measurement

Low limit for −12 V supply measurement

BAT

IN8

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

measurement

IN0

measurement

IN1

measurement

IN2

measurement

IN3

measurement

IN4

measurement

IN5

measurement

IN6

measurement

IN7

IN9

measurement

IN9

measurement

IN9

Rev. A | Page 37 of 56

ADM1026

Hex Address Name Power-On Value Description

58 A 59 A 5A A 5B A 5C A 5D A 5E A 5F A 60 FAN0 High Limit FFh High limit for Fan 0 speed measurement (no low limit) 61 FAN1 High Limit FFh High limit for Fan 1 speed measurement (no low limit) 62 FAN2 High Limit FFh High limit for Fan 2 speed measurement (no low limit) 63 FAN3 High Limit FFh High limit for Fan 3 speed measurement (no low limit) 64 FAN4 High Limit FFh High limit for Fan 4 speed measurement (no low limit) 65 FAN5 High Limit FFh High limit for Fan 5 speed measurement (no low limit) 66 FAN6 High Limit FFh High limit for Fan 6 speed measurement (no low limit) 67 FAN7 High Limit FFh High limit for Fan 7 speed measurement (no low limit) 68 Int. Temp. High Limit 50h (80°C) High limit for local temperature measurement 69 Int. Temp. Low Limit 80h Low limit for local temperature measurement 6A V 6B V 6C A 6D A 6E Ext1 Temp Offset 00h Offset register for Remote Temperature Channel 1 6F Ext2 Temp Offset 00h Offset register for Remote Temperature Channel 2

DETAILED REGISTER DESCRIPTIONS

Low Limit 00h Low limit for A

IN0

Low Limit 00h Low limit for A

IN1

Low Limit 00h Low limit for A

IN2

Low Limit 00h Low limit for A

IN3

Low Limit 00h Low limit for A

IN4

Low Limit 00h Low limit for A

IN5

Low Limit 00h Low limit for A

IN6

Low Limit 00h Low limit for A

IN7

High Limit FFh High limit for V

BAT

Low Limit 00h Low limit for V

BAT

High Limit FFh High limit for A

IN8

Low Limit 00h Low limit for A

IN8

measurement

IN0

measurement

IN1

measurement

IN2

measurement

IN3

measurement

IN4

measurement

IN5

measurement

IN6

measurement

IN7

measurement

BAT

measurement

BAT

measurement

IN8

measurement

IN8

Table 13. Register 00h, Configuration Register 1 (Power-On Default 00h)

Bit Name R/W Description

0 Monitor = 0

When this bit is set the ADM1026 monitors all voltage, temperature and fan channels in a round

R/W

robin manner.

1 Int Enable = 0 2 Int Clear = 0

When this bit is set, the INT output pin is enabled.

R/W

Setting this bit clears an interrupt from the voltage, temperature or fan speed channels. Because

R/W

GPIO interrupts are level triggered, this bit has no effect on interrupts originating from GPIO channels. This bit is cleared by writing a 0 to it. If in monitoring mode voltages, temperatures and fan speeds continue to be monitored after writing to this bit to clear an interrupt, so an interrupt may be set again on the next monitoring cycle.

3 Enable Voltage/Ext2 = 0

When this bit is 1, the ADM1026 monitors voltage (A

R/W

When this bit is 0, the ADM1026 monitors a second thermal diode temperature channel, D2, on these pins. If the second thermal diode channel is not being used, it is recommended that the bit be set to 1.

Enable THERM

5 Enable DAC AFC = 0

= 0 R/W When this bit is 1, the THERM pin (Pin 42) is asserted (go low) if any of the THERM limits are

exceeded. If THERM until THERM

When this bit is 1, the DAC output is enabled for automatic fan speed control (AFC) based on

R/W

is pulled low as an input, the DAC and PWM outputs are forced to full scale

is taken high.

temperature. When this bit is 0, the DAC Output reflects the value in Reg 04h, the DAC Control Register.

6 Enable PWM AFC = 0

When this bit is 1, the PWM output is enabled for automatic fan speed control (AFC) based on

R/W

temperature. When this bit is 0, the PWM Output reflects the value in Reg 05h, the PWM Control Register.

7 Software Reset = 0

Writing a 1 to this bit restores all registers to the power-on defaults. This bit is cleared by writing a

R/W

0 to it. For more info, see the Software Reset Function section.

and A

IN8

) on Pins 28 and 27, respectively.

IN9

Rev. A | Page 38 of 56

ADM1026

Table 14. Register 01h, Configuration Register 2 (Power-On Default 00h)

Bit Name R/W Description

0 Enable GPIO0/Fan0 = 0

1 Enable GPIO1/Fan1 = 0

2 Enable GPIO2/Fan2 = 0

3 Enable GPIO3/Fan3 = 0

4 Enable GPIO4/Fan4 = 0

5 Enable GPIO5/Fan5 = 0

6 Enable GPIO6/Fan6 = 0

7 Enable GPIO7/Fan7 = 0

Table 15. Register 02h, Fans 0 to 3 Fan Divisor Register (Power-On Default 55h)

Bit Name R/W Description

1–0 Fan 0 Divisor

00 1 22.5 8800, nominal, for count of 153 01 2 11.25 4400, nominal, for count of 153 10 4 5.62 2200, nominal, for count of 153 11 8 2.81 1100, nominal, for count of 153 3–2 Fan 1 Divisor

5–4 Fan 2 Divisor 7–6 Fan 3 Divisor

R/W

R/W R/W R/W

When this bit is 1, Pin 3 is enabled as a general-purpose I/O pin (GPIO0), otherwise it is a fan tach

R/W

measurement input (Fan 0).

When this bit is 1, Pin 4 is enabled as a general-purpose I/O pin (GPIO1), otherwise it is a fan tach

R/W

measurement input (Fan 1).

When this bit is 1, Pin 5 is enabled as a general-purpose I/O pin (GPIO2), otherwise it is a fan tach

R/W

measurement input (Fan 2).

When this bit is 1, Pin 6 is enabled as a general-purpose I/O pin (GPIO3), otherwise it is a fan tach

R/W

measurement input (Fan 3).

When this bit is 1, Pin 9 is enabled as a general-purpose I/O pin (GPIO4), otherwise it is a fan tach

R/W

measurement input (Fan 4).

When this bit is 1, Pin 10 is enabled as a general-purpose I/O pin (GPIO5), otherwise it is a fan tach

R/W

measurement input (Fan 5).

When this bit is 1, Pin 11 is enabled as a general-purpose I/O pin (GPIO6), otherwise it is a fan tach

R/W

measurement input (Fan 6).

When this bit is 1, Pin 12 is enabled as a general-purpose I/O pin (GPIO7), otherwise it is a fan tach

R/W

measurement input (Fan 7).

Sets the oscillator prescaler division ratio for Fan 0 speed measurement. The division ratios, oscillator

frequencies, and typical fan speeds (based on 2 tach pulses per revolution) are as follows:

Code

Same as Fan 0 Same as Fan 0 Same as Fan 0

Divide By

Oscillator Frequency (kHz)

Fan Speed (RPM)

Table 16. Register 03h, Fans 4 to 7 Fan Divisor Register (Power-On Default 55h)

Bit Name R/W Description

1–0 Fan 4 Divisor

00 1 22.5 8800, nominal, for count of 153 01 2 11.25 4400, nominal, for count of 153 10 4 5.62 2200, nominal, for count of 153 11 8 2.81 1100, nominal, for count of 153 3-2 Fan 5 Divisor

5-4 Fan 6 Divisor 7-6 Fan 7 Divisor

Sets the oscillator prescaler division ratio for Fan 4 speed measurement. The division ratios, oscillator

R/W

frequencies, and typical fan speeds (based on 2 tach pulses per revolution) are as follows:

R/W R/W R/W

Code

Same as Fan 4 Same as Fan 4 Same as Fan 4

Divide By

Oscillator Frequency (kHz)

Fan Speed (RPM)

Table 17. Register 04h, DAC Control Register (Power-On Default FFh)

Bit Name R/W Description

7–0 DAC Control

This register contains the value to which the fan speed DAC is programmed in normal mode, or the

R/W

4 MSBs contain the minimum fan speed in auto fan speed control mode.

Rev. A | Page 39 of 56

ADM1026

Table 18. Register 05h, PWM Control Register (Power-On Default FFh)

Bit Name R/W Description

7–4 PWM Control

0000 = 0% Duty Cycle 0001 = 7% Duty Cycle 0101 = 33% Duty Cycle 0110 = 40% Duty Cycle 0111 = 47% Duty Cycle 1110 = 93% Duty Cycle 1111 = 100% Duty Cycle 3–0 Unused R Undefined

Table 19. Register 06h, EEPROM Register 1 (Power-On Default 00h)

Bit Name R/W Description

7–0 Factory Use

Table 20. Register 07h, Configuration Register 3 (Power-On Default 00h)

Bit Name R/W Description

1 CI Clear = 0 2 V 5–3 Unused R Undefined, reads back 0. 6 GPIO16 Direction 7 GPIO16 Polarity

Enable GPIO16/ THERM

Select = 0

REF

= 0 R/W

This register contains the value to which the PWM fan speed is programmed in normal

R/W

mode, or the 4 MSBs contain the minimum fan speed in auto fan speed control mode.

For factory use only. Do not write to this register.

R/W

When this bit is 1, Pin 42 is enabled as a general-purpose I/O pin (GPIO16); otherwise it

output.

REF

(Pin 24) outputs 1.82 V, otherwise, it outputs 2.5 V.

R/W R/W

is the THERM

Writing a 1 to this bit clears the CI latch. This bit is cleared by writing a 0 to it. When this bit is 0, V

When this bit is 0, GPIO16 is configured as an input; otherwise, it is an output. When this bit is 0, GPIO16 is active low; otherwise, it is active high.

Table 21. Register 08h, GPIO Configuration Register 1 (Power-On Default 00h)

Bit Name R/W Description

0 GPIO0 Direction 1 GPIO0 Polarity 2 GPIO1 Direction 3 GPIO1 Polarity 4 GPIO2 Direction 5 GPIO2 Polarity 6 GPIO3 Direction 7 GPIO3 Polarity

R/W R/W R/W R/W R/W R/W R/W R/W

When this bit is 0, GPIO0 is configured as an input; otherwise, it is an output. When this bit is 0, GPIO0 is active low; otherwise it is active high. When this bit is 0, GPIO1 is configured as an input; otherwise, it is an output. When this bit is 0, GPIO1 is active low; otherwise it is active high. When this bit is 0, GPIO2 is configured as an input; otherwise, it is an output. When this bit is 0, GPIO2 is active low; otherwise, it is active high. When this bit is 0, GPIO3 is configured as an input; otherwise, it is an output. When this bit is 0, GPIO3 is active low; otherwise, it is active high.

Table 22. Register 09h, GPIO Configuration Register 2 (Power-On Default 00h)

Bit Name R/W Description

0 GPIO4 Direction 1 GPIO4 Polarity 2 GPIO5 Direction 3 GPIO5 Polarity 4 GPIO6 Direction 5 GPIO6 Polarity 6 GPIO7 Direction 7 GPIO7 Polarity

R/W R/W R/W R/W R/W R/W R/W R/W

When this bit is 0, GPIO4 is configured as an input; otherwise, it is an output. When this bit is 0, GPIO4 is active low; otherwise, it is active high. When this bit is 0, GPIO5 is configured as an input; otherwise, it is an output. When this bit is 0, GPIO5 is active low; otherwise, it is active high. When this bit is 0, GPIO6 is configured as an input; otherwise, it is an output. When this bit is 0, GPIO6 is active low; otherwise, it is active high. When this bit is 0, GPIO7 is configured as an input; otherwise, it is an output. When this bit is 0, GPIO7 is active low; otherwise, it is active high.

Rev. A | Page 40 of 56

ADM1026

Table 23. Register 0Ah, GPIO Configuration Register 3 (Power-On Default 00h)

Bit Name R/W Description

0 GPIO8 Direction 1 GPIO8 Polarity 2 GPIO9 Direction 3 GPIO9 Polarity 4 GPIO10 Direction 5 GPIO10 Polarity 6 GPIO11 Direction 7 GPIO11 Polarity

R/W R/W R/W R/W R/W R/W R/W R/W

Table 24. Register 0Bh, GPIO Configuration Register 4 (Power-On Default 00h)

Bit Name R/W Description

0 GPIO12 Direction 1 GPIO12 Polarity 2 GPIO13 Direction 3 GPIO13 Polarity 4 GPIO14 Direction 5 GPIO14 Polarity 6 GPIO15 Direction 7 GPIO15 Polarity

R/W R/W R/W R/W R/W R/W R/W R/W

When this bit is 0, GPIO8 is configured as an input; otherwise, it is an output. When this bit is 0, GPIO8 is active low; otherwise, it is active high. When this bit is 0, GPIO9 is configured as an input; otherwise, it is an output. When this bit is 0, GPIO9 is active low; otherwise, it is active high. When this bit is 0, GPIO10 is configured as an input; otherwise, it is an output. When this bit is 0, GPIO10 is active low; otherwise, it is active high. When this bit is 0, GPIO11 is configured as an input; otherwise, it is an output. When this bit is 0, GPIO11 is active low; otherwise, it is active high.

When this bit is 0, GPIO12 is configured as an input; otherwise, it is an output. When this bit is 0, GPIO12 is active low; otherwise, it is active high. When this bit is 0, GPIO13 is configured as an input; otherwise, it is an output. When this bit is 0, GPIO13 is active low; otherwise, it is active high. When this bit is 0, GPIO14 is configured as an input; otherwise, it is an output. When this bit is 0, GPIO14 is active low; otherwise, it is active high. When this bit is 0, GPIO15 is configured as an input; otherwise, it is an output. When this bit is 0, GPIO15 is active low; otherwise, it is active high.

Table 25. Register 0ch, EEPROM Register 2 (Power-On Default 00h)

Bit Name R/W Description

7–0 Factory Use R For factory use only. Do not write to this register.

Table 26. Register 0Dh, Internal Temperature

THERM

Limit (Power-On Default, 37h 55°C)

Bit Name R/W Description

7–0

Int Temp THERM

Table 27. Register 0Eh, TDM1

Limit R/W This register contains the THERM limit for the internal temperature channel. Exceeding this limit

output pin to be asserted.

THERM

causes the THERM

Limit (Power-On Default 50h, 80°C)

Bit Name R/W Description

7–0

TDM1 THERM

Table 28. Register 0Fh, TDM2

Limit R/W This register contains the THERM limit for the TDM1 temperature channel. Exceeding this limit

output pin to be asserted.

THERM

causes the THERM

Limit (Power-On Default 50h, 80°C)

Bit Name R/W Description

7–0

TDM2 THERM

Limit

Table 29. Register 10h, Internal Temperature T

R/W

This register contains the THERM limit for the TDM2 temperature channel. Exceeding this limit causes the THERM

(Power-On Default 28h, 40°C)

MIN

output pin to be asserted.

Bit Name R/W Description

7–0 Internal Temp T

MIN

This register contains the T

R/W

value for automatic fan speed control based on the internal

MIN

temperature channel.

Table 30. Register 11h, TDM1 Temperature T

(Power-On Default 40h, 64°C)

MIN

Bit Name R/W Description

7–0 TDM1 Temp T

MIN

This register contains the T

R/W

value for automatic fan speed control based on the TDM1

MIN

temperature channel.

Rev. A | Page 41 of 56

ADM1026

Table 31. Register 12h, TDM2 Temperature T

Bit Name R/W Description

7–0 TDM2 Temp T

MIN

This register contains the T

R/W

channel.

Table 32. Register 13h, EEPROM Register 3 (Power-On Default 00h)

Bit Name

0 Read 1 Write 2 Erase 3 Write Protect

4 Test Mode Bit 0 5 Test Mode Bit 1 6 Test Mode Bit 2

Clock Extend

R/W R/W R/W R/W Once R/W R/W R/W R/W

Description

Setting this bit puts the EEPROM into read mode. Setting this bit puts the EEPROM in write (program) mode. Setting this bit puts the EEPROM into erase mode.

Setting this bit protects the EEPROM against accidental writing or erasure. This bit is write-once and can only be cleared by a power-on reset.

Test mode bits. For factory use only Test mode bits. For factory use only. Test mode bits. For factory use only

Setting this bit enables SMBus clock extension. The ADM1026 can pull SCL low to extend the clock

pulse if it cannot accept any more data. It is recommended to set this bit to 1 to extend the clock pulse during repeated EEPROM write or block write operations.

Table 33. Register 14h, Manufacturer’s Test Register 1 (Power-On Default 00h)

Bit Name R/W Description

7–0 Manufacturer’s Test 1

This register is used by the manufacturer for test purposes. It should not be read from or written

R/W

(Power-On Default 40h, 64°C)

MIN

to in normal operation.

value for automatic fan speed control based on the TDM2 temperature

Table 34. Register 15h, Manufacturer’s Test Register 2 (Power-On Default 00h)

Bit Name R/W Description

7–0 Manufacturer’s Test 2

This register is used by the manufacturer for test purposes. It should not be read from or written

R/W

to in normal operation.

Table 35. Register 16h, Manufacturer’s ID (Power-On Default 41h)

Bit Name R/W Description

7–0 Manufacturer’s ID Code R This register contains the manufacturer’s ID code.

Table 36. Register 17h, Revision Register (Power-On Default 4xh)

Bit Name R/W Description

3–0 Minor Revision Code R

This nibble contains the manufacturer’s code for minor revisions to the device. Rev 1 = 0h, Rev 2 = 1h, and so on.

7–4 Major Revision Code R This nibble denotes the generation of the device. For the ADM1026, this nibble reads 4h.

Table 37. Register 18h, Mask Register 1 (Power-On Default 00h)

Bit Name R/W Description

0 Ext1 Temp Mask = 0 1 Ext2 Temp 2 3.3 V STBY Mask = 0 3 3.3 V MAIN Mask = 0 4 +5 V Mask = 0 5 V

Mask = 0

CCP

6 +12 V Mask = 0 7 −12 V Mask = 0

When this bit is set, interrupts generated on the Ext1 temperature channel are masked out.

R/W

When this bit is set, interrupts generated on the Ext2/A

R/W

When this bit is set, interrupts generated on the 3.3 V STBY voltage channel are masked out.

R/W

When this bit is set, interrupts generated on the 3.3 V MAIN voltage channel are masked out.

R/W

When this bit is set, interrupts generated on the +5 V voltage channel are masked out.

R/W

When this bit is set, interrupts generated on the V

R/W

When this bit is set, interrupts generated on the +12 V voltage channel are masked out.

R/W

When this bit is set, interrupts generated on the −12 V voltage channel are masked out.

R/W

channel are masked out.

IN9

voltage channel are masked out.

CCP

Rev. A | Page 42 of 56

ADM1026

Table 38. Register 19h, Mask Register 2 (Power-On Default 00h)

Bit Name R/W Description

0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 A

Mask = 0

IN0

Mask = 0

IN1

Mask = 0

IN2

Mask = 0

IN3

Mask = 0

IN4

Mask = 0

IN5

Mask = 0

IN6

Mask = 0

IN7

R/W R/W R/W R/W R/W R/W R/W R/W

Table 39. Register 1Ah, Mask Register 3 (Power-On Default 00h)

Bit Name R/W Description

0 FAN0 Mask = 0 1 FAN1 Mask = 0 2 FAN2 Mask = 0 3 FAN3 Mask = 0 4 FAN4 Mask = 0 5 FAN5 Mask = 0 6 FAN6 Mask = 0 7 FAN7 Mask = 0

When this bit is set, interrupts generated on the A When this bit is set, interrupts generated on the A When this bit is set, interrupts generated on the A When this bit is set, interrupts generated on the A When this bit is set, interrupts generated on the A When this bit is set, interrupts generated on the A When this bit is set, interrupts generated on the A When this bit is set, interrupts generated on the A

When this bit is set, interrupts generated on the FAN0 tach channel are masked out.

R/W

When this bit is set, interrupts generated on the FAN1 tach channel are masked out.

R/W

When this bit is set, interrupts generated on the FAN2 tach channel are masked out.

R/W

When this bit is set, interrupts generated on the FAN3 tach channel are masked out.

R/W

When this bit is set, interrupts generated on the FAN4 tach channel are masked out.

R/W

When this bit is set, interrupts generated on the FAN5 tach channel are masked out.

R/W

When this bit is set, interrupts generated on the FAN6 tach channel are masked out.

R/W

When this bit is set, interrupts generated on the FAN7 tach channel are masked out.

R/W

voltage channel are masked out.

IN0

voltage channel are masked out.

IN1

voltage channel are masked out.

IN2

voltage channel are masked out.

IN3

voltage channel are masked out.

IN4

voltage channel are masked out.

IN5

voltage channel are masked out.

IN6

voltage channel are masked out.

IN7

Table 40. Register 1Bh, Mask Register 4 (Power-On Default 00h)

Bit Name R/W Description

0 Int Temp Mask = 0 1 V 2 A 3

Mask = 0

BAT

Mask = 0

IN8

Mask = 0 R/W When this bit is set, interrupts generated from THERM events are masked out.

THERM 4 AFC Mask = 0 5 Unused 6 CI Mask = 0 7 GPIO16 Mask = 0

When this bit is set, interrupts generated on the internal temperature channel are masked out.

R/W

When this bit is set, interrupts generated on the V

R/W

When this bit is set, interrupts generated on the A

R/W

When this bit is set, interrupts generated from automatic fan control events are masked out.

R/W

Unused. Reads back 0.

R/W

When this bit is set, interrupts generated by the chassis intrusion input are masked out.

R/W

When this bit is set, interrupts generated on the GPIO16 channel are masked out.

R/W

Table 41. Register 1Ch, Mask Register 5 (Power-On Default 00h)

Bit Name R/W Description

0 GPIO0 Mask = 0 1 GPIO1 Mask = 0 2 GPIO2 Mask = 0 3 GPIO3 Mask = 0 4 GPIO4 Mask = 0 5 GPIO5 Mask = 0 6 GPIO6 Mask = 0 7 GPIO7 Mask = 0

R/W R/W R/W R/W R/W R/W R/W R/W

When this bit is set, interrupts generated on the GPIO0 channel are masked out. When this bit is set, interrupts generated on the GPIO1 channel are masked out. When this bit is set, interrupts generated on the GPIO2 channel are masked out. When this bit is set, interrupts generated on the GPIO3 channel are masked out. When this bit is set, interrupts generated on the GPIO4 channel are masked out. When this bit is set, interrupts generated on the GPIO5 channel are masked out. When this bit is set, interrupts generated on the GPIO6 channel are masked out. When this bit is set, interrupts generated on the GPIO7 channel are masked out.

voltage channel are masked out.

BAT

voltage channel are masked out.

IN8

Rev. A | Page 43 of 56

ADM1026

Table 42. Register 1Dh, Mask Register 6 (Power-On Default 00h)

Bit Name R/W Description

0 GPIO8 Mask = 0 1 GPIO9 Mask = 0 2 GPIO10 Mask = 0 3 GPIO11Mask = 0 4 GPIO12 Mask = 0 5 GPIO13 Mask = 0 6 GPIO14 Mask = 0 7 GPIO15 Mask = 0

R/W R/W R/W R/W R/W R/W R/W R/W

Table 43. Register 1Eh, INT Temp Offset (Power-On Default 00h)

Bit Name R/W Description

7–0 Int Temp Offset

R/W

Table 44. Register 1Fh, INT Temp Measured Value (Power-On Default 00h)

Bit Name R/W Description

7–0 Int Temp Value R This register contains the measured value of the internal temperature channel.

When this bit is set, interrupts generated on the GPIO8 channel are masked out. When this bit is set, interrupts generated on the GPIO9 channel are masked out. When this bit is set, interrupts generated on the GPIO10 channel are masked out. When this bit is set, interrupts generated on the GPIO11 channel are masked out. When this bit is set, interrupts generated on the GPIO12 channel are masked out. When this bit is set, interrupts generated on the GPIO13 channel are masked out. When this bit is set, interrupts generated on the GPIO14 channel are masked out. When this bit is set, interrupts generated on the GPIO15 channel are masked out.

This register contains the offset value for the internal temperature channel, a twos complement

result before it is stored or compared to limits. In this way, a sort of one-point calibration can be done whereby the whole transfer function of the channel can be moved up or down. From a software point of view, this may be a very simple method to vary the characteristics of the measurement channel if the thermal characteristics change for any reason (for instance from one chassis to another), if the measurement point is moved, if a plug-in card is inserted or removed, and so on.

Table 45. Register 20h, Status Register 1 (Power-On Default 00h)

Bit Name R/W Description

0 Ext1 Temp Status = 0 R

1, if Ext1 value is above the high limit or below the low limit on the previous conversion cycle; 0 otherwise. This bit is set (once only) if a THERM exceeding the Ext1 THERM result of Ext1 temperature readings going 5°C below Ext1 THERM

1 Ext2 Temp Status = 0 R

1, if Ext 2 value (or A

if in voltage measurement mode) is above the /A

IN9

below the low limit on the previous conversion cycle; 0 otherwise. This bit is set (once only) if a

mode is engaged as a result of Ext2 temperature readings exceeding the Ext2 THERM limit.

THERM This bit is also set (once only) if THERM going 5°C below Ext2 THERM

2 3.3 V STBY Status = 0 R

1, if 3.3 V STBY value is above the high limit or below the low limit on the previous conversion cycle; 0 otherwise.

3 3.3 V MAIN Status = 0 R

1, if 3.3 V MAIN value is above the high limit or below the low limit on the previous conversion cycle; 0 otherwise.

4 +5 V Status = 0 R

1, if +5 V value is above the high limit or below the low limit on the previous conversion cycle; 0 otherwise.

5 V

Status = 0 R

CCP

value is above the high limit or below the low limit on the previous conversion cycle;

1, if V

CCP

0 otherwise.

6 +12 V Status = 0 R

1, if +12 V value is above the high limit or below the low limit on the previous conversion cycle; 0 otherwise.

7 −12 V Status = 0 R

1, if −12 V value is above the high limit or below the low limit on the previous conversion cycle; 0 otherwise.

mode is engaged as a result of Ext1 temp readings

limit. This bit is also set (once only) if THERM mode is disengaged as a

limit.

status = 0 high limit or

IN9

mode is disengaged as a result of Ext2 temperature readings

limit.

Rev. A | Page 44 of 56

ADM1026

Table 46. Register 21h, Status Register 2 (Power-On Default 00h)

Bit Name

0 A

1 A

2 A

3 A

4 A

5 A

6 A

7 A

Status = 0 R

IN0

Status = 0 R

IN1

Status = 0 R

IN2

Status = 0 R

IN3

Status = 0 R

IN4

Status = 0 R

IN5

Status = 0 R

IN6

Status = 0 R

IN7

Table 47. Register 22h, Status Register 3 (Power-On Default 00h)

Bit Name

0 FAN0 Status 1 = 0 R 1, if FAN0 to FAN7 value is above the high limit on the previous conversion cycle; 0 otherwise. 1 FAN1 Status 1 = 0 R 1, if FAN0 to FAN7 value is above the high limit on the previous conversion cycle; 0 otherwise. 2 FAN2 Status 1 = 0 R 1, if FAN0 to FAN7 value is above the high limit on the previous conversion cycle; 0 otherwise. 3 FAN3 Status 1 = 0 R 1, if FAN0 to FAN7 value is above the high limit on the previous conversion cycle; 0 otherwise. 4 FAN4 Status 1 = 0 R 1, if FAN0 to FAN7 value is above the high limit on the previous conversion cycle; 0 otherwise. 5 FAN5 Status 1 = 0 R 1, if FAN0 to FAN7 value is above the high limit on the previous conversion cycle; 0 otherwise. 6 FAN6 Status 1 = 0 R 1, if FAN0 to FAN7 value is above the high limit on the previous conversion cycle; 0 otherwise. 7 FAN7 Status 1 = 0 R 1, if FAN0 to FAN7 value is above the high limit on the previous conversion cycle; 0 otherwise.

Description

1, if A cycle;0 otherwise.

Description

IN0

to A

value is above the high limit or below the low limit on the previous conversion

IN7

to A

value is above the high limit or below the low limit on the previous conversion

IN7

to A

value is above the high limit or below the low limit on the previous conversion

IN7

to A

value is above the high limit or below the low limit on the previous conversion

IN7

to A

value is above the high limit or below the low limit on the previous conversion

IN7

to A

value is above the high limit or below the low limit on the previous conversion

IN7

to A

value is above the high limit or below the low limit on the previous conversion

IN7

to A

value is above the high limit or below the low limit on the previous conversion

IN7

Table 48. Register 23h, Status Register 4 (Power-On Default 00h)

Bit Name R/W Description

0 Int Temp Status = 0 R

1, if Int value is above the high limit or below the low limit on the previous conversion cycle, 0 otherwise. This bit is set (once only) if a THERM readings exceeding the Int THERM

limit. This bit is also set (once only) if THERM mode is disengaged

as a result of internal temperature readings going 5°C below Int THERM

1 V

Status = 0 R

BAT

value is above the high limit or below the low limit on the previous conversion cycle,

1, if V

BAT

0 otherwise.

2 A

Status = 0 R

IN8

value is above the high limit or below the low limit on the previous conversion cycle,

1, if A

IN8

0 otherwise.

THERM

Status = 0

This bit is set (once only) if a THERM mode is engaged as a result of temperature readings exceeding the THERM

limits on any channel. This bit is also set (once only) if THERM mode is

disengaged as a result of temperature readings going 5°C below THERM

4 AFC Status = 0 R

This bit is set (once only) if the fan turns on when in automatic fan speed control (AFC) mode as a result of a temperature reading exceeding T

fan turns off when in automatic fan speed control mode. 5 Unused R Unused. Reads back 0. 6 CI Status = 0 R This bit latches a chassis intrusion event. 7 GPIO16 Status = 0 R

When GPIO16 is configured as an input, this bit is set when GPIO16 is asserted. (Asserted may be

active high or active low depending on the setting in GPIO configuration register.)

When GPIO16 is configured as an output, setting this bit asserts GPIO16. (Asserted may be active

R/W

high or active low depending on setting in GPIO configuration register.)

mode is engaged as a result of int temperature

limit.

limits on any channel.

on any channel. This bit is also set (once only) if the

MIN

Rev. A | Page 45 of 56

ADM1026

Table 49. Register 24h, Status Register 5 (Power-On Default 00h)

Bit Name R/

0 GPIO0 Status = 0 R

1 GPIO1 Status = 0 R

2 GPIO2 Status = 0 R

3 GPIO3 Status = 0 R

4 GPIO4 Status = 0 R

5 GPIO5 Status = 0 R

6 GPIO6 Status = 0 R

7 GPIO7 Status = 0 R

GPIO status bits can be written only when a GPIO pin is configured as output. Read-only otherwise.

Description

When GPIO0 is configured as an input, this bit is set when GPIO0 is asserted. (Asserted may be active high or active low depending on setting of Bit 1 in GPIO Configuration Register 1.)

When GPIO0 is configured as an output, setting this bit asserts GPIO0. (Asserted may be active high

R/W

or active low depending on setting of Bit 1 in GPIO Configuration Register 1.) When GPIO1 is configured as an input, this bit is set when GPIO1 is asserted. (Asserted may be

active high or active low depending on setting of Bit 3 in GPIO Configuration Register 1.)

When GPIO1 is configured as an output, setting this bit asserts GPIO1. (Asserted may be active high

R/W

or active low depending on setting of Bit 3 in GPIO Configuration Register 1.) When GPIO2 is configured as an input, this bit is set when GPIO2 is asserted. (Asserted may be

active high or active low depending on setting of Bit 5 in GPIO Configuration Register 1.)

When GPIO2 is configured as an output, setting this bit asserts GPIO2. (Asserted may be active high

R/W

or active low depending on setting of Bit 5 in GPIO Configuration Register 1.) When GPIO3 is configured as an input, this bit is set when GPIO3 is asserted. (Asserted may be

active high or active low depending on setting of Bit 7 in GPIO Configuration Register 1.)

When GPIO3 is configured as an output, setting this bit asserts GPIO3. (Asserted may be active high

R/W

or active low depending on setting of Bit 7 in GPIO Configuration Register 1.) When GPIO4 is configured as an input, this bit is set when GPIO4 is asserted. (Asserted may be

active high or active low depending on setting of Bit 1 in GPIO Configuration Register 2.)

When GPIO4 is configured as an output, setting this bit asserts GPIO4. (Asserted may be active high

R/W

or active low depending on setting of Bit 1 in GPIO Configuration Register 2.) When GPIO5 is configured as an input, this bit is set when GPIO5 is asserted. (Asserted may be

active high or active low depending on setting of Bit 3 in GPIO Configuration Register 2.)

When GPIO5 is configured as an output, setting this bit asserts GPIO5. (Asserted may be active high

R/W

or active low depending on setting of Bit 3 in GPIO Configuration Register 2.) When GPIO6 is configured as an input, this bit is set when GPIO6 is asserted. (Asserted may be

active high or active low depending on setting of Bit 5 in GPIO Configuration Register 2.)

When GPIO6 is configured as an output, setting this bit asserts GPIO6. (Asserted may be active high

R/W

or active low depending on setting of Bit 5 in GPIO Configuration Register 2.) When GPIO7 is configured as an input, this bit is set when GPIO7 is asserted. (Asserted may be

active high or active low depending on setting of Bit 7 in GPIO Configuration Register 2.)

When GPIO7 is configured as an output, setting this bit asserts GPIO7. (Asserted may be active high

R/W

or active low depending on setting of Bit 7 in GPIO Configuration Register 2.)

Rev. A | Page 46 of 56

ADM1026

Table 50. Register 25h, Status Register 6 (Power-On Default 00h)

Bit Name

0 GPIO8 Status = 0 R

1 GPIO9 Status = 0 R

2 GPIO10 Status = 0 R

3 GPIO11 Status = 0 R

4 GPIO12 Status = 0 R

5 GPIO13 Status = 0 R

6 GPIO14 Status = 0 R

7 GPIO15 Status = 0 R

GPIO status bits can be written only when a GPIO pin is configured as output. Read-only otherwise.

R/W

Description

When GPIO8 is configured as an input, this bit is set when GPIO8 is asserted. (Asserted may be active high or active low depending on setting of Bit 1 in GPIO Configuration Register 3.)

When GPIO8 is configured as an output, setting this bit asserts GPIO8. (Asserted may be active high or active low depending on setting of Bit 1 in GPIO Configuration Register 3.)

When GPIO9 is configured as an input, this bit is set when GPIO9 is asserted. (Asserted may be active high or active low depending on setting of Bit 3 in GPIO Configuration Register 3.)

When GPIO9 is configured as an output, setting this bit asserts GPIO9. (Asserted may be active high or active low depending on setting of Bit 3 in GPIO Configuration Register 3.)

When GPIO10 is configured as an input, this bit is set when GPIO10 is asserted. (Asserted may be active high or active low depending on setting of Bit 5 in GPIO Configuration Register 3.)

When GPIO10 is configured as an output, setting this bit asserts GPIO10. (Asserted may be active high or active low depending on setting of Bit 5 in GPIO Configuration Register 3.)

When GPIO11 is configured as an input, this bit is set when GPIO11 is asserted. (Asserted may be active high or active low depending on setting of Bit 7 in GPIO Configuration Register 3.)

When GPIO11 is configured as an output, setting this bit asserts GPIO11. (Asserted may be active high or active low depending on setting of Bit 7 in GPIO Configuration Register 3.)

When GPIO12 is configured as an input, this bit is set when GPIO12 is asserted. (Asserted may be active high or active low depending on setting of Bit 1 in GPIO Configuration Register 4.)

When GPIO12 is configured as an output, setting this bit asserts GPIO12. (Asserted may be active high or active low depending on setting of Bit 1 in GPIO Configuration Register 4.)

When GPIO13 is configured as an input , this bit is set when GPIO13 is asserted. (Asserted may be active high or active low depending on setting of Bit 3 in GPIO Configuration Register 4.)

When GPIO13 is configured as an output, setting this bit asserts GPIO13. (Asserted may be active high or active low depending on setting of Bit 3 in GPIO Configuration Register 4.)

When GPIO14 is configured as an input , this bit is set when GPIO14 is asserted. (Asserted may be active high or active low depending on setting of Bit 5 in GPIO Configuration Register 4.)

When GPIO14 is configured as an output, setting this bit asserts GPIO14. (Asserted may be active high or active low depending on setting of Bit 5 in GPIO Configuration Register 4.)

When GPIO15 is configured as an input, this bit is set when GPIO15 is asserted. (Asserted may be active high or active low depending on setting of Bit 7 in GPIO Configuration Register 4.)

When GPIO15 is configured as an output, setting this bit asserts GPIO15. (Asserted may be active high or active low depending on setting of Bit 7 in GPIO Configuration Register 4.)

Table 51. Register 26h, V

Measured Value (Power-On Default 00h)

BAT

Bit Name R/W Description

7–0 V

Table 52. Register 27h, A

Value R This register contains the measured value of the V

BAT

Measured Value (Power-On Default 00h)

IN8

analog input channel.

BAT

Bit Name R/W Description

7–0 A

Value R This register contains the measured value of the A

IN8

analog input channel.

IN8

Table 53. Register 28h, EXT1 Measured Value (Power-On Default 00h)

Bit Name R/W Description

7–0 Ext1 Value R This register contains the measured value of the Ext1 Temp channel.

Table 54. Register 29h, EXT2/A

Measured Value (Power-On Default 00h)

IN9

Bit Name R/W Description

7–0 Ext2 Temp/ A

Low Limit R

IN9

This register contains the measured value of the Ext2 Temp/A

channel depending on

IN9

which bit is configured.

Rev. A | Page 47 of 56

ADM1026

Table 55. Register 2Ah, 3.3 V STBY Measured Value (Power-On Default 00h)

Bit Name R/W Description

7–0 3.3 V STBY Value R This register contains the measured value of the 3.3 V STBY voltage.

Table 56. Register 2Bh, 3.3 V MAIN Measured Value (Power-On Default 00h)

Bit Name R/W Description

7–0 3.3 V MAIN Value R This register contains the measured value of the 3.3 V MAIN voltage.

Table 57. Register 2Ch, +5 V Measured Value (Power-On Default 00h)

Bit Name R/W Description

7–0 +5 V Value R This register contains the measured value of the +5 V analog input channel.

Table 58. Register 2Dh, VCCP Measured Value (Power-On Default 00h)

Bit Name R/W Description

7–0 V

Table 59. Register 2Eh, +12V Measured Value (Power-On Default 00h)

Bit Name R/W Description

7–0 +12 V Value R This register contains the measured value of the +12 V analog input channel.

Table 60. Register 2Fh, –12V Measured Value (Power-On Default 00h)

Bit Name R/W Description

7–0 –12 V Value R

Value R This register contains the measured value of the V

CCP

This register contains the measured value of the −12 V analog input channel.

analog input channel.

CCP

Table 61. Register 30h, A

Measured Value (Power-On Default 00h)

IN0

Bit Name R/W Description

7–0 A

Table 62. Register 31h, A

Value R This register contains the measured value of the A

IN0

Measured Value (Power-On Default 00h)

IN1

Bit Name R/W Description

7–0 A

Table 63. Register 32h, A

Value R This register contains the measured value of the A

IN1

Measured Value (Power-On Default 00h)

IN2

Bit Name R/W Description

7–0 A

Table 64. Register 33h, A

Value R This register contains the measured value of the A

IN2

Measured Value (Power-On Default 00h)

IN3

Bit Name R/W Description

7–0 A

Table 65. Register 34h, A

Value R This register contains the measured value of the A

IN3

Measured Value (Power-On Default 00h)

IN4

Bit Name R/W Description

7–0 A

Table 66. Register 35h, A

Value R This register contains the measured value of the A

IN4

Measured Value (Power-On Default 00h)

IN5

Bit Name R/W Description

7–0 A

Table 67. Register 36h, A

Value R This register contains the measured value of the A

IN5

Measured Value (Power-On Default 00h)

IN6

Bit Name R/W Description

7–0 A

Value R This register contains the measured value of the A

IN6

analog input channel.

IN0

analog input channel.

IN1

analog input channel.

IN2

analog input channel.

IN3

analog input channel.

IN4

analog input channel.

IN5

analog input channel.

IN6

Table 68. Register 37h, A

Measured Value (Power-On Default 00h)

IN7

Bit Name R/W Description

7–0 A

Value R This register contains the measured value of the A

IN7

Rev. A | Page 48 of 56

analog input channel.

IN7

ADM1026

Table 69. Register 38h, FAN0 Measured Value (Power-On Default 00h)

Bit Name R/W Description

7–0 FAN0 Value R This register contains the measured value of the FAN0 tach input channel.

Table 70. Register 39h, FAN1 Measured Value (Power-On Default 00h)

Bit Name R/W Description

7–0 FAN1 Value R This register contains the measured value of the FAN1 tach input channel.

Table 71. Register 3Ah, FAN2 Measured Value (Power-On Default 00h)

Bit Name R/W Description

7–0 FAN2 Value R This register contains the measured value of the FAN2 tach input channel.

Table 72. Register 3Bh, FAN3 Measured Value (Power-On Default 00h)

Bit Name R/W Description

7–0 FAN3 Value R This register contains the measured value of the FAN3 tach input channel.

Table 73. Register 3Ch, FAN4 Measured Value (Power-On Default 00h)

Bit Name R/W Description

7–0 FAN4 Value R This register contains the measured value of the FAN4 tach input channel.

Table 74. Register 3Dh, FAN5 Measured Value (Power-On Default 00h)

Bit Name R/W Description

7–0 FAN5 Value R This register contains the measured value of the FAN5 tach input channel.

Table 75. Register 3Eh, FAN6 Measured Value (Power-On Default 00h)

Bit Name R/W Description

7–0 FAN6 Value R This register contains the measured value of the FAN6 tach input channel.

Table 76. Register 3Fh, FAN7 Measured Value (Power-On Default 00h)

Bit Name R/W Description

7–0 FAN7 Value R This register contains the measured value of the FAN7 tach input channel.

Table 77. Register 40h, Ext1 High Limit (Power-On Default 64h/100°C)

Bit Name R/W Description

7–0 Ext1 High Limit

Table 78. Register 41h, Ext2/A

R/W

High Limit (Power-On Default 64h/100°C)

IN9

This register contains the high limit of the Ext1 Temp channel.

Bit Name R/W Description

7–0

Ext2 Temp/ A Limit

IN9

High

R/W This register contains the high limit of the Ext2 Temp/A

is configured.

channel depending on which one

IN9

Table 79. Register 42h, 3.3 V STBY High Limit (Power-On Default FFh)

Bit Name R/W Description

7–0 3.3 V STBY High Limit

R/W

This register contains the high limit of the 3.3 V STBY analog input channel.

Table 80. Register 43h, 3.3 V MAIN High Limit (Power-On Default FFh)

Bit Name R/W Description

7–0 3.3 V MAIN High Limit

R/W

This register contains the high limit of the 3.3 V MAIN analog input channel.

Table 81. Register 44h, +5 V High Limit (Power-On Default FFh)

Bit Name R/W Description

7–0 +5 V High Limit

R/W

This register contains the high limit of the +5 V analog input channel.

Table 82. Register 45h, V

High Limit (Power-On Default FFh)

CCP

Bit Name R/W Description

7–0 V

High Limit

CCP

R/W

This register contains the high limit of the V

Rev. A | Page 49 of 56

analog input channel.

CCP

ADM1026

Table 83. Register 46h, +12 V High Limit (Power-On Default FFh)

Bit Name R/W Description

7–0 +12 V High Limit

R/W

Table 84. Register 47h, −12 V High Limit (Power-On Default FFh)

Bit Name R/W Description

7–0 −12V High Limit

R/W

Table 85. Register 48h, Ext1 Low Limit (Power-On Default 80h)

Bit Name R/W Description

7–0 Ext1 Low Limit

R/W

This register contains the high limit of the +12 V analog input channel.

This register contains the high limit of the −12 V analog input channel.

This register contains the low limit of the Ext1 Temp channel.

Table 86. Register 49h, Ext2 / A

Low Limit (Power-On-Default 80h)

IN9

Bit Name R/W Description

7–0

Ext2 Temp /A Limit

IN9

Low

R/W This register contains the low limit of the Ext2 Temp/A

configured.

Table 87. Register 4Ah, 3.3 V STBY Low Limit (Power-On Default 00h)

Bit Name R/W Description

7–0 3.3 V STBY Low Limit

R/W

This register contains the low limit of the 3.3 V STBY analog input channel.

Table 88. Register 4Bh, 3.3 V MAIN Low Limit (Power-On Default 00h)

Bit Name R/W Description

7–0 3.3 V MAIN Low Limit

R/W

This register contains the low limit of the 3.3 V MAIN analog input channel.

Table 89. Register 4Ch, +5V Low Limit (Power-On Default 00h)

Bit Name R/W Description

7–0 0+5 V Low Limit

Table 90. Register 4Dh, V

R/W

Low Limit (Power-On Default 00h)

CCP

This register contains the low limit of the +5 V analog input channel.

Bit Name R/W Description

7–0 V

Low Limit

CCP

R/W

This register contains the low limit of the V

Table 91. Register 4Eh, +12V Low Limit (Power-On Default 00h)

Bit Name R/W Description

7–0 +12 V Low Limit

R/W

This register contains the low limit of the +12 V analog input channel.

Table 92. Register 4Fh, –12V Low Limit (Power-On Default 00h)

Bit Name R/W Description

7–0 −12 V Low Limit

R/W

This register contains the low limit of the −12 V analog input channel.

channel depending on which bit is

IN9

analog input channel.

CCP

Table 93. Register 50h, A

High Limit (Power-On Default FFh)

IN0

Bit Name R/W Description

7–0 A

High Limit

IN0

Table 94. Register 51h, A

R/W

High Limit (Power-On Default FFh)

IN1

This register contains the high limit of the A

Bit Name R/W Description

7–0 A

High Limit

IN1

Table 95. Register 52h, A

High Limit (Power-On Default FFh)

IN2

This register contains the high limit of the A

R/W

Bit Name R/W Description

7–0 A

High Limit

IN2

Table 96. Register 53h, A

R/W

High Limit (Power-On Default FFh)

IN3

This register contains the high limit of the A

Bit Name R/W Description

7–0 A

High Limit

IN3

R/W

This register contains the high limit of the A

Rev. A | Page 50 of 56

analog input channel.

IN0

analog input channel.

IN1

analog input channel.

IN2

analog input channel.

IN3

ADM1026

Table 97. Register 54h, A

Bit Name R/W Description

7–0 A

High Limit

IN4

High Limit (Power-On Default FFh)

IN4

This register contains the high limit of the A

R/W

analog input channel.

IN4

Table 98. Register 55h, A

High Limit (Power-On Default FFh)

IN5

Bit Name R/W Description

7–0 A

Table 99. Register 56h, A

High Limit R/W This register contains the high limit of the A

IN5

High Limit (Power-On Default FFh)

IN6

Bit Name R/W Description

7–0 A

Table 100. Register 57h, A

High Limit R/W This register contains the high limit of the A

IN6

High Limit (Power-On Default FFh)

IN7

Bit Name R/W Description

7–0 A

High Limit

IN7

Table 101. Register 58h, A

R/W

Low Limit (Power-On Default 00h)

IN0

This register contains the high limit of the A

Bit Name R/W Description

7–0 A

Low Limit

IN0

Table 102. Register 59h, A

R/W

Low Limit (Power-On Default 00h)

IN1

This register contains the low limit of the A

Bit Name R/W Description

7–0 A

Low Limit

IN1

Table 103. Register 5Ah, A

R/W

Low Limit (Power-On Default 00h)

IN2

This register contains the low limit of the A

Bit Name R/W Description

7–0 A

Low Limit

IN2

Table 104. Register 5Bh, A

R/W

Low Limit (Power-On Default 00h)

IN3

This register contains the low limit of the A

Bit Name R/W Description

7–0 A

Low Limit

IN3

R/W

This register contains the low limit of the A

analog input channel.

IN5

analog input channel.

IN6

analog input channel.

IN7

analog input channel.

IN0

analog input channel.

IN1

analog input channel.

IN2

analog input channel.

IN3

Table 105. Register 5Ch, A

Low Limit (Power-On Default 00h)

IN4

Bit Name R/W Description

7–0 A

Low Limit

IN4

Table 106. Register 5Dh, A

R/W

Low Limit (Power-On Default 00h)

IN5

This register contains the low limit of the A

analog input channel.

IN4

Bit Name R/W Description

7–0 A

Low Limit

IN5

Table 107. Register 5Eh, A

R/W

Low Limit (Power-On Default 00h)

IN6

This register contains the low limit of the A

analog input channel.

IN5

Bit Name R/W Description

7–0 A

Low Limit

IN6

Table 108. Register 5Fh, A

R/W

Low Limit (Power-On Default 00h)

IN7

This register contains the low limit of the A

analog input channel.

IN6

Bit Name R/W Description

7–0 A

Low Limit

IN7

R/W

This register contains the low limit of the A

analog input channel.

IN7

Table 109. Register 60h, FAN0 High Limit (Power-On Default FFh)

Bit Name R/W Description

7–0 FAN0 High Limit R/W This register contains the high limit of the FAN0 tach channel.

Table 110. Register 61h, FAN1 High Limit (Power-On Default FFh)

Bit Name R/W Description

7–0 FAN1 High Limit R/W This register contains the high limit of the FAN1 tach channel.

Rev. A | Page 51 of 56

ADM1026

Table 111. Register 62h, FAN2 High Limit (Power-On Default FFh)

Bit Name R/W Description

7–0 FAN2 High Limit

R/W

Table 112. Register 63h, FAN3 High Limit (Power-On Default FFh)

Bit Name R/W Description

7–0 FAN3 High Limit

R/W

Table 113. Register 64h, FAN4 High Limit (Power-On Default FFh)

Bit Name R/W Description

7–0 FAN4 High Limit

R/W

Table 114. Register 65h, FAN5 High Limit (Power-On Default FFh)

Bit Name R/W Description

7–0 FAN5 High Limit

R/W

Table 115. Register 66h, FAN6 High Limit (Power-On Default FFh)

Bit Name R/W Description

7–0 FAN6 High Limit

R/W

Table 116. Register 67h, FAN7 High Limit (Power-On Default FFh)

Bit Name R/W Description

7–0 FAN7 High Limit

R/W

This register contains the high limit of the FAN2 tach channel.

This register contains the high limit of the FAN3 tach channel.

This register contains the high limit of the FAN4 tach channel.

This register contains the high limit of the FAN5 tach channel.

This register contains the high limit of the FAN6 tach channel.

This register contains the high limit of the FAN7 tach channel.

Table 117. Register 68h, Int Temp High Limit (Power-On Default 50h (80°C))

Bit Name R/W Description

7–0 Int Temp High Limit

R/W

This register contains the high limit of the internal temperature channel.

Table 118. Register 69h, Int Temp Low Limit (Power-On Default 80h)

Bit Name R/W Description

7–0 Int Temp Low Limit

Table 119. Register 6Ah, V

R/W

High Limit (Power-On Default FFh)

BAT

This register contains the low limit of the internal temperature channel.

Bit Name R/W Description

7–0 V

Table 120. Register 6Bh, V

High Limit R/W This register contains the high limit of the V

BAT

Low Limit (Power-On Default 00h)

BAT

Bit Name R/W Description

7–0 V

Low Limit

BAT

Table 121. Register 6Ch, A

R/W

High Limit (Power-On Default FFh)

IN8

This register contains the low limit of the V

Bit Name R/W Description

7–0 A

High Limit

IN8

Table 122. Register 6Dh,

R/W

Low Limit (Power-On Default 00h)

AIN8

This register contains the high limit of the A

Bit Name R/W Description

7–0 A

Low Limit

IN8

R/W

This register contains the low limit of the A

analog input channel.

BAT

analog input channel.

BAT

analog input channel.

IN8

analog input channel.

IN8

Rev. A | Page 52 of 56

ADM1026

Table 123. Register 6Eh, Ext1 Temp Offset (Power-On Default 00h)

Bit Name R/W Description

7–0 Ext1 Temp Offset

Table 124. Register 6Fh, Ext2 Temp Offset (Power-On Default 00h)

Bit Name R/W Description

7–0 Ext2 Temp Offset

This register contains the offset value for the external 1 temperature channel. A twos complement

R/W

number can be written to this register, which is then added to the measured result before it is stored or compared to limits. In this way, a sort of one-point calibration can be done whereby the whole transfer function of the channel can be moved up or down. From a software point of view, this may be a very simple method to vary the characteristics of the measurement channel if the thermal characteristics change for any reason (for instance from one chassis to another), if the measurement point is moved, if a plug-in card is inserted or removed, and so on.

This register contains the offset value for the external 2 temperature channel. A twos complement

R/W

Rev. A | Page 53 of 56

ADM1026

OUTLINE DIMENSIONS

1.45

1.40

1.35

0.15

0.05

ROTATED 90°CCW

10°

6° 2°

SEATING PLANE

VIEW A

0.75

0.60

0.45

SEATING

PLANE

0.20

0.09 7°

3.5 0°

0.08 MAX COPLANARITY

COMPLIANT TO JEDEC STANDARDS MS-026BBC

1.60 MAX

VIEW A

Figure 63. 48-Lead Thin Plastic Quad Flat Package [LQFP]

7 mm x 7 mm x 1.4 mm Thick (ST-48)

Dimensions shown in millimeters

0.50

BSC

9.00 BSC SQ

PIN 1

TOP VIEW

(PINS DOWN)

0.27

0.22

0.17

7.00

BSC SQ

Rev. A | Page 54 of 56

ADM1026

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADM1026JST 0°C to 100°C 48-Lead LQFP ST-48 ADM1026JST-REEL 0°C to 100°C 48-Lead LQFP ST-48 ADM1026JST-REEL7 0°C to 100°C 48-Lead LQFP ST-48 ADM1026JSTZ-REEL1 0°C to 100°C 48-Lead LQFP ST-48 EVAL-ADM1026EB Evaluation Board

Z = Pb-free part.

Rev. A | Page 55 of 56

ADM1026

NOTES

C02657-0-3/04(A)

Rev. A | Page 56 of 56

Datasheet ADM1026 Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

PRODUCT DESCRIPTION

FUNCTIONAL DESCRIPTION

Measurement Inputs

Sequential Measurement

Chassis Intrusion

Resets

INTERNAL REGISTERS

EEPROM

General SMBus Timing

SMBus PROTOCOLS FOR RAM AND EEPROM

ADM1026 SMBus Operations

ADM1026 Write Operations

ADM1026 Read Operations

MEASUREMENT INPUTS

A-to-D Converter (ADC)

Voltage Measurement Inputs

Setting Other Input Ranges

TEMPERATURE MEASUREMENT SYSTEM

Local Temperature Measurement

Remote Temperature Measurement

Layout Considerations

Limit Values

Analog Monitoring Cycle Time

Input Safety

ANALOG OUTPUT

PWM Output

Automatic Fan Speed Control

Fan Inputs

FAN SPEED MEASUREMENT

Limit Values

Fan Monitoring Cycle Time

Chassis Intrusion Input

General-Purpose I/O Pins (Open Drain)

Analog/Temperature Inputs

Fan Inputs

ENABLING AND CLEARING INTERRUPTS

Reset Input and Outputs

NAND TREE TESTS

USING THE ADM1026

Reduced Power Mode

Software Reset Function

Application Schematic

REGISTERS

DETAILED REGISTER DESCRIPTIONS

OUTLINE DIMENSIONS

ORDERING GUIDE