50 MHz to 9 GHz
V
FEATURES
Accurate rms-to-dc conversion from 50 MHz to 9 GHz
Single-ended input dynamic range of 65 dB
No balun or external input matching required
Waveform and modulation independent, such as
GSM/CDMA/W-CDMA/TD-SCDMA/WiMAX/LTE
Linear-in-decibels output, scaled 53 mV/dB
Transfer function ripple: <±0.1 dB
Temperature stability: <±0.3 dB
All functions temperature and supply stable
Operates from 4.5 V to 5.5 V from −40°C to +125°C
Power-down capability to 1.5 mW
Pin-compatible with the 50 dB dynamic range AD8363
APPLICATIONS
Power amplifier linearization/control loops
Transmitter power controls
Transmitter signal strength indication (TSSI)
RF instrumentation
INHI
INLO
NC
NC
NC
65 dB TruPwr Detector
FUNCTIONAL BLOCK DIAGRAM
POS POS
ADL5902
14
15
LINEAR-IN-d B VGA
(NEGATIVE SLOPE)
2
16
BIAS AND POWER-
DOWN CONTRO L
13
3
1
VREF
2.3V
11
Figure 1.
10
I
DET
2
X
2
X
I
TGT
12
ADL5902
TEMPERATURE
SENSOR
G = 5
26pF
9
COMMCOMMVTGTVREFTADJ/PWDN
TEMP
8
7
VSET
6
VOUT
5
CLPF
4
08218-001
GENERAL DESCRIPTION
The ADL5902 is a true rms responding power detector that has
a 65 dB measurement range when driven with a single-ended
50 source. This feature makes the ADL5902 frequency
versatile by eliminating the need for a balun or any other form
of external input tuning for operation up to 9 GHz.
The ADL5902 provides a solution in a variety of high frequency
systems requiring an accurate measurement of signal power.
Requiring only a single supply of 5 V and a few capacitors, it is
easy to use and capable of being driven single-ended or with a
balun for differential input drive. The ADL5902 can operate
from 50 MHz to 9 GHz and can accept inputs from −62 dBm to
at least +3 dBm with large crest factors, such as GSM, CDMA,
W-CDMA, TD-SCDMA, WiMAX, and LTE modulated signals.
The ADL5902 can determine the true power of a high
frequency signal having a complex low frequency modulation
envelope or can be used as a simple low frequency rms
voltmeter. Used as a power measurement device, VOUT is
connected to VSET. The output is then proportional to the
logarithm of the rms value of the input. In other words, the
reading is presented directly in decibels and is scaled 1.06 V per
decade, or 53 mV/dB; other slopes are easily arranged. In
controller mode, the voltage applied to VSET determines the
power level required at the input to null the deviation from the
set point. The output buffer can provide high load currents.
The ADL5902 has 1.5 mW power consumption when powered
down by a logic high applied to the PWDN pin. It powers up
within approximately 5 µs to its nominal operating current of
73 mA at 25°C. The ADL5902 is supplied in a 4 mm × 4 mm,
16-lead LFCSP for operation over the wide temperature range
of −40°C to +125°C.
The ADL5902 is also pin-compatible with the AD8363, 50 dB
dynamic range TruPwr™ detector. This feature allows the
designer to create one circuit layout for projects requiring
different dynamic ranges. A fully populated RoHS-compliant
evaluation board is available.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2010–2011 Analog Devices, Inc. All rights reserved.
ADL5902
TABLE OF CONTENTS
Features.............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram ..............................................................1
General Description......................................................................... 1
Revision History ...............................................................................2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics............................................. 9
Theory of Operation ......................................................................15
Square Law Detector and Amplitude Target.............................. 15
RF Input Interface ...................................................................... 16
Small Signal Loop Response .....................................................17
Temperature Sensor Interface................................................... 17
VREF Interface ...........................................................................17
Temperature Compensation Interface..................................... 17
Power-Down Interface............................................................... 18
VSET Interface............................................................................ 18
Output Interface .........................................................................18
VTGT Interface .......................................................................... 19
Basis for Error Calculations...................................................... 19
Measurement Mode Basic Connections.................................. 19
Setting V
Setting V
Choosing a Value for C
.................................................................................. 20
TAD J
................................................................................. 20
TGT
............................................................ 20
LPF
Output Voltage Scaling.............................................................. 23
System Calibration and Error Calculation.............................. 24
High Frequency Performance................................................... 25
Low Frequency Performance.................................................... 25
Description of Characterization............................................... 25
Evaluation Board Schematics and Artwork................................ 26
Assembly Drawings.................................................................... 27
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 28
REVISION HISTORY
7/11—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Changes to Measurement Mode Basic Connections Section and
Figure 45 ..........................................................................................19
Changes to Setting V
C
Section...................................................................................... 20
LPF
Changes to Output Voltage Scaling Section, Figure 49, and
Table 7 .............................................................................................. 23
Changes to Figure 54 and Table 8................................................. 26
Changes to Figure 55 and Figure 56............................................. 27
4/10—Revision 0: Initial Version
Section and Choosing a Value for
TGT
Rev. A | Page 2 of 28
ADL5902
SPECIFICATIONS
VS = 5 V, TA = 25°C, ZO = 50 Ω, single-ended input drive, RT = 60.4 Ω, VOUT connected to VSET, V
current values imply that the ADL5902 is sourcing current out of the indicated pin.
Table 1.
Parameter Test Conditions Min Typ Max Unit
OVERALL FUNCTION
Frequency Range 50 to 9000 MHz
RF INPUT INTERFACE Pins INHI, INLO, ac-coupled
Input Impedance Single-ended drive, 50 MHz 2000 Ω
Common Mode Voltage 2.5 V
100 MHz
±1.0 dB Dynamic Range CW input, TA = +25°C, V
= 0.5 V 63 dB
TAD J
Maximum Input Level, ±1.0 dB Calibration at −60 dBm, −45 dBm, and 0 dBm 3 dBm
Minimum Input Level, ±1.0 dB Calibration at −60 dBm, −45 dBm, and 0 dBm −60 dBm
Deviation vs. Temperature Deviation from output at 25°C
−40°C < TA < +85°C; PIN = 0 dBm
−40°C < TA < +85°C; PIN = −45 dBm
−40°C < TA < +125°C; PIN = 0 dBm
−40°C < TA < +125°C; PIN = −45 dBm
Logarithmic Slope
−45 dBm < P
< 0 dBm; calibration at −45 dBm
IN
and 0 dBm
Logarithmic Intercept
−45 dBm < P
< 0 dBm; calibration at −45 dBm
IN
and 0 dBm
700 MHz
±1.0 dB Dynamic Range CW input, TA = +25°C,V
= 0.4 V 61 dB
TAD J
Maximum Input Level, ±1.0 dB Calibration at −60 dBm, −45 dBm, and 0 dBm 1 dBm
Minimum Input Level, ±1.0 dB Calibration at −60 dBm, −45 dBm, and 0 dBm −60 dBm
Deviation vs. Temperature Deviation from output at 25°C
−40°C < TA < +85°C; PIN = 0 dBm +0.3/−0.2 dB
−40°C < TA < +85°C; PIN = −45 dBm −0.1/0 dB
−40°C < TA < +125°C; PIN = 0 dBm +0.3/−0.4 dB
−40°C < TA < +125°C; PIN = −45 dBm −0.1/0 dB
Logarithmic Slope
−45 dBm < P
< 0 dBm; calibration at −45 dBm
IN
53.7 mV/dB
and 0 dBm
Logarithmic Intercept
−45 dBm < P
< 0 dBm; calibration at −45 dBm
IN
−62.8 dBm
and 0 dBm
900 MHz
±1.0 dB Dynamic Range CW input, TA = +25°C, V
= 0.4 V 61 dB
TAD J
Maximum Input Level, ±1.0 dB Calibration at −60 dBm, −45 dBm, and 0 dBm 1 dBm
Minimum Input Level, ±1.0 dB Calibration at −60 dBm, −45 dBm, and 0 dBm −60 dBm
Deviation vs. Temperature Deviation from output at 25°C
−40°C < TA < +85°C; PIN = 0 dBm +0.3/−0.2 dB
−40°C < TA < +85°C; PIN = −45 dBm 0/−0.1 dB
−40°C < TA < +125°C; PIN = 0 dBm +0.3/−0.4 dB
−40°C < TA < +125°C; PIN = −45 dBm 0/−0.1 dB
Logarithmic Slope
−45 dBm < P
< 0 dBm; calibration at −45 dBm
IN
53.7 mV/dB
and 0 dBm
Logarithmic Intercept
−45 dBm < P
< 0 dBm; calibration at −45 dBm
IN
−62.7 dBm
and 0 dBm
= 0.8 V, C
TGT
−0.11/+0.25
−0.22/+0.15
−0.35/+0.25
−0.22/+0.15
53.8
−62.1
= 0.1 µF. Negative
LPF
dB
dB
dB
dB
mV/dB
dBm
Rev. A | Page 3 of 28
ADL5902
Parameter Test Conditions Min Typ Max Unit
Deviation from CW Response 11.02 dB peak-to-rms ratio (CDMA2000) −0.1 dB
5.13 dB peak-to-rms ratio (16 QAM) −0.05 dB
2.76 dB peak-to-rms ratio (QPSK) −0.05 dB
1.9 GHz
±1.0 dB Dynamic Range CW input, TA = +25°C, V
Maximum Input Level, ±1.0 dB Calibration at −60 dBm, −45 dBm, and 0 dBm 3 dBm
Minimum Input Level, ±1.0 dB Calibration at −60 dBm, −45 dBm, and 0 dBm −61 dBm
Deviation vs. Temperature Deviation from output at 25°C
−40°C < TA < +85°C; PIN = 0 dBm −0.1/0 dB
−40°C < TA < +85°C; PIN = −45 dBm −0.3/+0.3 dB
−40°C < TA < +125°C; PIN = 0 dBm −0.1/0 dB
−40°C < TA < +125°C; PIN = −45 dBm −0.3/+0.4 dB
Logarithmic Slope
−45 dBm < P
< 0 dBm; calibration at −45 dBm,
IN
and 0 dBm
Logarithmic Intercept
−45 dBm < P
< 0 dBm; calibration at −45 dBm
IN
and 0 dBm
2.14 GHz
±1.0 dB Dynamic Range CW input, TA = +25°C, V
Maximum Input Level, ±1.0 dB Calibration at −60 dBm, −45 dBm, and 0 dBm 3 dBm
Minimum Input Level, ±1.0 dB Calibration at −60 dBm, −45 dBm, and 0 dBm −62 dBm
Deviation vs. Temperature Deviation from output at 25°C
−40°C < TA < +85°C; PIN = 0 dBm −0.1/0 dB
−40°C < TA < +85°C; PIN = −45 dBm −0.3/+0.3 dB
−40°C < TA < +125°C; PIN = 0 dBm −0.1/0 dB
−40°C < TA < +125°C; PIN = −45 dBm −0.3/+0.4 dB
Logarithmic Slope
−45 dBm < P
< 0 dBm; calibration at −45 dBm
IN
and 0 dBm
Logarithmic Intercept
−45 dBm < P
< 0 dBm; calibration at −45 dBm
IN
and 0 dBm
Deviation from CW Response 12.16 dB peak-to-rms ratio (four-carrier W-CDMA) −0.1 dB
11.58 dB peak-to-rms ratio (LTE TM1 1CR 20 MHz
BW)
10.56 dB peak-to-rms ratio (one-carrier W-CDMA) −0.1 dB
6.2 dB peak-to-rms ratio (64 QAM) −0.07
2.6 GHz
±1.0 dB Dynamic Range CW input, TA = +25°C, V
Maximum Input Level, ±1.0 dB Calibration at −60, −45 and 0 dBm 5 dBm
Minimum Input Level, ±1.0 dB Calibration at −60, −45 and 0 dBm −60 dBm
Deviation vs. Temperature Deviation from output at 25°C
−40°C < TA < +85°C; PIN = 0 dBm 0.4/0 dB
−40°C < TA < +85°C; PIN = −45 dBm +0.5/−0.6 dB
−40°C < TA < +125°C; PIN = 0 dBm 0.6/0 dB
−40°C < TA < +125°C; PIN = −45 dBm +0.7/−0.6 dB
Logarithmic Slope
−45 dBm < P
< 0 dBm; calibration at −45 dBm
IN
and 0 dBm
Logarithmic Intercept
−45 dBm < P
< 0 dBm; calibration at −45 dBm
IN
and 0 dBm
3.5 GHz
±1.0 dB Dynamic Range CW input, TA = +25°C, V
Maximum Input Level, ±1.0 dB Calibration at −60 dBm, −40 dBm, and 0 dBm 8 dBm
Minimum Input Level, ±1.0 dB Calibration at −60 dBm, −40 dBm, and 0 dBm −49 dBm
= 0.4 V 64 dB
TAD J
52.6 mV/dB
−62.6 dBm
= 0.4 V 65 dB
TAD J
52.4 mV/dB
−62.9 dBm
−0.1 dB
= 0.45 V 65 dB
TAD J
dB
51.0 mV/dB
−62.1 dBm
= 0.5 V 57 dB
TAD J
Rev. A | Page 4 of 28
ADL5902
Parameter Test Conditions Min Typ Max Unit
Deviation vs. Temperature Deviation from output at 25°C
−40°C < TA < +85°C; PIN = 0 dBm 0.2/0 dB
−40°C < TA < +85°C; PIN = −40 dBm −0.2/+0.4 dB
−40°C < TA < +125°C; PIN = 0 dBm +0.2/−0.3 dB
−40°C < TA < +125°C; PIN = −40 dBm −0.2/+0.4 dB
Logarithmic Slope
−40 dBm < P
< 0 dBm; calibration at −30 dBm
IN
and 0 dBm
Logarithmic Intercept
−40 dBm < P
< 0 dBm; calibration at −30 dBm
IN
and 0 dBm
5.8 GHz
±1.0 dB Dynamic Range CW input, TA = +25°C, V
= 0.95 V 61 dB
TAD J
Maximum Input Level, ±1.0 dB Calibration at −50 dBm, −30 dBm, and 0 dBm 9 dBm
Minimum Input Level, ±1.0 dB Calibration at −50 dBm, −30 dBm, and 0 dBm −52 dBm
Deviation vs. Temperature Deviation from output at 25°C
−40°C < TA < +85°C; PIN = 0 dBm −0.8/0 dB
−40°C < TA < +85°C; PIN = −30 dBm −1.3/+0.1 dB
−40°C < TA < +125°C; PIN = 0 dBm −1.6/0 dB
−40°C < TA < +125°C; PIN = −30 dBm −1.3/+0.1 dB
Logarithmic Slope
−30 dBm < P
< 0 dBm; calibration at −30 dBm
IN
and 0 dBm
Logarithmic Intercept
−30 dBm < P
< 0 dBm; calibration at −30 dBm
IN
and 0 dBm
OUTPUT INTERFACE VOUT (Pin 6)
Output Swing, Controller Mode Swing range minimum, RL ≥ 500 Ω to ground 0.03 V
Swing range maximum, RL ≥ 500 Ω to ground 4.8 V
Current Source/Sink Capability 10/10 mA
Voltage Regulation I
Output Noise
Rise Time
Fall Time
= 8 mA, source/sink +0.2/−0.2 %
LOAD
= 2.14 GHz, −20 dBm, f
RF
IN
= 220 pF
C
LPF
= 100 kHz,
NOISE
Transition from no input to 1 dB settling at
= −10 dBm, C
P
IN
= 220 pF
LPF
Transition from −10 dBm to off (1 dB of final value),
C
= 220 pF
LPF
SETPOINT INPUT VSET (Pin 7)
Voltage Range Log conformance error ≤ 1 dB, minimum 2.14 GHz 3.5 V
Log conformance error ≤ 1 dB, maximum 2.14 GHz 0.23 V
Input Resistance 72 kΩ
Logarithmic Scale Factor f = 2.14 GHz 52.4 mV/dB
Logarithmic Intercept f = 2.14 GHz −62.9 dBm
TEMPERATURE COMPENSATION Pin TADJ/PWDN (Pin 1)
Input Voltage Range 0 VS V
Input Bias Current V
Input Resistance V
= 0.4 V 2 μA
TAD J
= 0.4 V 200 kΩ
TAD J
VOLTAGE REFERENCE VREF (Pin 11)
Output Voltage PIN = −55 dBm 2.3 V
Temperature Sensitivity 25°C ≤ TA ≤ 125°C −0.16 mV/°C
−15°C ≤ TA ≤ +25°C 0.045 mV/°C
−40°C ≤ TA ≤ −15°C −0.04 mV/°C
Short-Circuit Current Source/
25°C ≤ T
≤ 125°C 4/0.05 mA
A
Sink Capability
−40°C ≤ TA < +25°C 3/0.05 mA
Voltage Regulation TA = 25°C, I
= 2 mA −0.4 %
LOAD
49.6 mV/dB
−63.1 dBm
42.7 mV/dB
−54.1 dBm
25 nV/√Hz
3 μs
25 μs
Rev. A | Page 5 of 28
ADL5902
Parameter Test Conditions Min Typ Max Unit
TEMPERATURE REFERENCE TEMP (Pin 8)
Output Voltage TA = 25°C, RL ≥ 10 kΩ 1.4 V
Temperature Coefficient −40°C ≤ TA ≤ +125°C, RL ≥ 10 kΩ 4.9 mV/°C
Short-Circuit Current Source/
25°C ≤ T
Sink Capability
−40°C ≤ TA < +25°C 3/0.05 mA
Voltage Regulation TA = 25°C, I
RMS TARGET INTERFACE VTGT (Pin 12)
Input Voltage Range 0.2 2.5 V
Input Bias Current V
Input Resistance 100 kΩ
POWER-DOWN INTERFACE Pin TADJ/PWDN (Pin 1)
Voltage Level to Enable V
Voltage Level to Disable V
Input Current V
V
V
Enable Time
V
C
Disable Time
V
C
POWER SUPPLY INTERFACE VPOS (Pin 3, Pin 10)
Supply Voltage 4.5 5 5.5 V
Quiescent Current TA = 25°C, PIN < −60 dBm 73 mA
T
Power-Down Current V
≤ 125°C 4/0.05 mA
A
= 1 mA −2.8 %
LOAD
= 0.8 V 8 μA
TGT
decreasing 4 V
PWDN
increasing 4.9 V
PWDN
= 5 V 1 μA
PWDN
= 4.5 V 500 μA
PWDN
= 0 V 3 μA
PWDN
low to V
TAD J
= 220 pF, PIN = 0 dBm
LPA/B
high to V
TAD J
= 220 pF, PIN = 0 dBm
LPA/B
= 125°C, PIN < −60 dBm 90 mA
A
> VS − 0.1 V 300 μA
TAD J
at 1 dB of final value,
OUT
at 1 dB of final value,
OUT
5 μs
3 μs
Rev. A | Page 6 of 28
ADL5902
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage, VPOS 5.5 V
Input Average RF Power1 21 dBm
Equivalent Voltage, Sine Wave Input 2.51 V p-p
Internal Power Dissipation 550 mW
2
θ
10.6°C/W
JC
2
θ
35.3°C/W
JB
2
θ
57.2°C/W
JA
2
Ψ
1.0°C/W
JT
2
Ψ
34°C/W
JB
Maximum Junction Temperature 150°C
Operating Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C
1
This is for long durations. Excursions above this level, with durations much
less than 1 second, are possible without damage.
2
No airflow with the exposed pad soldered to a 4-layer JEDEC board.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. A | Page 7 of 28
ADL5902
O
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC
INL
INHI
NC
14
13
16
15
PIN 1
INDICATOR
1TADJ/PWDN
2NC
ADL5902
3VPOS
TOP VIEW
(Not to Scale)
4COMM
5
6
OUT
CLPF
V
NOTES
1. NC = NO CONNECT.
2. THE EXPO SED PADDLE IS COMM AND SHOULD
HAVE BOTH A GOOD THE RMAL AND GOOD
ELECTRICAL CONNECTION TO GROUND.
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 TADJ/PWDN
This is a dual function pin used for controlling the amount of nonlinear intercept temperature compensation at
voltages <2.5 V and/or for shutting down the device at voltages >4 V. If the shutdown function is not used, this pin
can be connected to the VREF pin through a voltage divider. See Figure 41 for an equivalent circuit.
2 NC No Connect. Do not connect this pin.
3, 10 VPOS
Supply for the Device. Connect this pin to a 5 V power supply. Pin 3 and Pin 10 are not internally connected;
therefore, both must connect to the source.
4, 9, EPAD COMM
System Common Connection. Connect these pins via low impedance to system common. The exposed paddle
is also COMM and should have both a good thermal and good electrical connection to ground.
5 CLPF
Connection for RMS Averaging Capacitor. Connect a ground-referenced capacitor to this pin. A resistor can be
connected in series with this capacitor to modify loop stability and response time. See Figure 43 for an
equivalent circuit.
6 VOUT
Output. In measurement mode, this pin is connected to VSET. In controller mode, this pin can be used to drive
a gain control element. See Figure 43 for an equivalent circuit.
7 VSET
The voltage applied to this pin sets the decibel value of the required RF input voltage that results in zero
current flow in the loop integrating capacitor pin, CLPF. This pin controls the variable gain amplifier (VGA) gain
such that a 50 mV change in V
changes the gain by approximately 1 dB. See Figure 42 for an equivalent
SET
circuit.
8 TEMP Temperature Sensor Output of 1.4 V at 25°C with a Coefficient of 5 mV/°C. See Figure 38 for an equivalent circuit.
11 VREF General-Purpose Reference Voltage Output of 2.3 V at 25°C. See Figure 39 for an equivalent circuit.
12 VTGT
The voltage applied to this pin determines the target power at the input of the RF squaring circuit. The intercept
voltage is proportional to the voltage applied to this pin. The use of a lower target voltage increases the crest
factor capacity; however, this may affect the system loop response. See Figure 44 for an equivalent circuit.
13 NC No Connect. Do not connect this pin.
14 INHI
RF Input. The RF input signal is normally ac-coupled to this pin through a coupling capacitor. See Figure 37 for
an equivalent circuit.
15 INLO
RF Input Common. This pin is normally ac-coupled to ground through a coupling capacitor. See Figure 37 for
an equivalent circuit.
16 NC No Connect. Do not connect this pin.
12 VTGT
11 VRE F
10 VPOS
9COMM
8
7
VSET
TEMP
08218-002
Rev. A | Page 8 of 28
ADL5902
T
T
T
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, ZO = 50 Ω, single-ended input drive, VOUT connected to VSET, V
+85°C (red), +125°C (orange) where appropriate. Error referred to the best fit line (linear regression) from − 10 dBm to − 40 dBm, unless
otherwise indicated. Input RF signal is a sine wave (CW), unless otherwise indicated.
6.0
T
= 0.5V
ADJ
5.5
CALIBRATIO N AT 0dBm, –45dBm, AND –60dBm
5.0
4.5
4.0
3.5
3.0
2.5
2.0
OU T PU T V OLTA G E ( V)
1.5
1.0
0.5
0
–60 –50 –40 –30 –20 –10 0 10
PIN (dBm)
Figure 3. Typical V
and Log Conformance Error with Respect to 25°C Ideal
OUT
Line over Temperature vs. Input Amplitude at 100 MHz, CW
6.0
T
= 0.4V
ADJ
5.5
CALIBRATIO N AT 0dBm, –45d Bm, AND –60dBm
5.0
4.5
4.0
3.5
AGE (V)
3.0
2.5
2.0
OUTPUT VOL
1.5
1.0
0.5
0
–60 –50 –40 –30 –20 –10 0 10
PIN (dBm)
Figure 4. Typical V
and Log Conformance Error with Respect to 25°C Ideal
OUT
Line over Temperature vs. Input Amplitude at 700 MHz, CW
6.0
T
= 0.4V
ADJ
5.5
CALIBRATIO N AT 0dBm, –45d Bm, AND –60dBm
5.0
4.5
4.0
3.5
3.0
2.5
2.0
OUTPUT VOLTAGE (V)
1.5
1.0
0.5
0
–60 –50 –40 –30 –20 –10 0 10
PIN (dBm)
Figure 5. Typical V
and Log Conformance Error with Respect to 25°C Ideal
OUT
Line over Temperature vs. Input Amplitude at 900 MHz, CW
6
5
4
3
2
1
0
–1
ERROR (dB)
–2
–3
–4
–5
–6
08218-003
6
5
4
3
2
1
0
–1
ERROR (dB)
–2
–3
–4
–5
–6
08218-004
6
5
4
3
2
1
0
–1
ERROR (d B)
–2
–3
–4
–5
–6
08218-005
Rev. A | Page 9 of 28
= 0.8 V, C
TGT
6.0
V
5.5
REPRESENTS 55 DEVICES FRO M 2 LOTS
5.0
4.5
4.0
3.5
AGE (V)
3.0
2.5
2.0
OUTPUT VOL
1.5
1.0
0.5
0
–60 –50 –40 –30 –20 –10 0 10
= 0.1 µF, TA = +25°C (black), −40°C (blue),
LPF
= 0.5V
TADJ
PIN (dBm)
6
5
4
3
2
1
0
–1
–2
–3
–4
–5
–6
Figure 6. Distribution of Error with Respect to 25°C over Temperature vs.
Input Amplitude, CW, Frequency = 100 MHz
6.0
V
= 0.4V
TADJ
5.5
REPRESENTS 55 DEVICES FROM 2 LOTS
5.0
4.5
4.0
3.5
AGE (V)
3.0
2.5
2.0
OUTPUT VOL
1.5
1.0
0.5
0
–60 –50 –40 –30 –20 –10 0 10
PIN (dBm)
6
5
4
3
2
1
0
–1
–2
–3
–4
–5
–6
Figure 7. Distribution of Error with Respect to 25°C over Temperature vs.
Input Amplitude, CW, Frequency = 700 MHz
6.0
V
= 0.4V
TADJ
5.5
REPRESENTS 55 DEVICES FROM 2 LOTS
5.0
4.5
4.0
3.5
3.0
2.5
2.0
OUTPUT VOLTAGE (V)
1.5
1.0
0.5
0
–60 –50 –40 –30 –20 –10 0 10
PIN (dBm)
6
5
4
3
2
1
0
–1
–2
–3
–4
–5
–6
Figure 8. Distribution of Error with Respect to 25°C over Temperature vs.
Inpu t Amplitude, CW, Frequency = 900 MHz
ERROR (dB)
ERROR (dB)
ERROR (dB)
08218-006
08218-007
08218-008
ADL5902
6.0
T
= 0.4V
ADJ
5.5
CALIBRATIO N AT 0dBm, –45d Bm, AND –60dBm
5.0
4.5
4.0
3.5
3.0
2.5
2.0
OUTPUT VOLTAGE (V)
1.5
1.0
0.5
0
–60 –50 –40 –30 –20 –10 0 10
PIN (dBm)
Figure 9. Typical V
and Log Conformance Error with Respect to 25°C Ideal
OUT
Line over Temperature vs. Input Amplitude at 1.9 GHz, CW
6.0
T
= 0.4V
ADJ
5.5
CALIBRATIO N AT 0dBm, –45d Bm, AND –60dBm
5.0
4.5
4.0
3.5
3.0
2.5
2.0
OUTPUT VOLTAGE (V)
1.5
1.0
0.5
0
–60 –50 –40 –30 –20 –10 0 10
PIN (dBm)
Figure 10. Typical V
and Log Conformance Error with Respect to 25°C Ideal
OUT
Line over Temperature vs. Input Amplitude at 2.14 GHz, CW
6.0
T
= 0.45V
ADJ
5.5
CALIBRATIO N AT 0dBm, –45d Bm, AND –60dBm
5.0
4.5
4.0
3.5
3.0
2.5
2.0
OUTPUT VOLTAGE (V)
1.5
1.0
0.5
0
–60 –50 –40 –30 –20 –10 0 10
PIN (dBm)
Figure 11. Typical V
and Log Conformance Error with Respect to 25°C Ideal
OUT
Line over Temperature vs. Input Amplitude at 2.6 GHz, CW
6
5
4
3
2
1
0
–1
ERROR (dB)
–2
–3
–4
–5
–6
08218-009
6.0
V
= 0.4V
TADJ
5.5
REPRESENTS 55 DEVICES FROM 2 LOTS
5.0
4.5
4.0
3.5
3.0
2.5
2.0
OUTPUT VOLTAGE (V)
1.5
1.0
0.5
0
–60 –50 –40 –30 –20 –10 0 10
PIN (dBm)
6
5
4
3
2
1
0
–1
ERROR (dB)
–2
–3
–4
–5
–6
08218-012
Figure 12. Distribution of Error with Respect to 25°C over Temperature vs.
Input Amplitude, CW, Frequency = 1.9 GHz
6
5
4
3
2
1
0
–1
ERROR (dB)
–2
–3
–4
–5
–6
08218-010
6.0
V
= 0.4V
TADJ
5.5
REPRESENTS 55 DEVICES FROM 2 LOTS
5.0
4.5
4.0
3.5
3.0
2.5
2.0
OUTPUT VOLTAGE (V)
1.5
1.0
0.5
0
–60 –50 –40 –30 –20 –10 0 10
PIN (dBm)
6
5
4
3
2
1
0
–1
ERROR (dB)
–2
–3
–4
–5
–6
08218-013
Figure 13. Distribution of Error with Respect to 25°C over Temperature vs.
Input Amplitude, CW, Frequency = 2.14 GHz
6
5
4
3
2
1
0
–1
ERROR (dB)
–2
–3
–4
–5
–6
08218-011
6.0
V
= 0.45V
TADJ
5.5
REPRESENTS 55 DEVICES FROM 2 LOTS
5.0
4.5
4.0
3.5
3.0
2.5
2.0
OU T PU T V OLTA G E ( V)
1.5
1.0
0.5
0
–60 –50 –40 –30 –20 –10 0 10
PIN (dBm)
6
5
4
3
2
1
0
–1
ERROR (dB)
–2
–3
–4
–5
–6
8218-014
Figure 14. Distribution of Error with Respect to 25°C over Temperature vs.
Input Amplitude, CW, Frequency = 2.6 GHz
Rev. A | Page 10 of 28
ADL5902
6.0
T
= 0.5V
ADJ
CALIBRATIO N AT 0dBm, –40d Bm, AND –60dBm
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
OUTPUT VOLTAGE (V)
1.5
1.0
0.5
0
–60 –50 –40 –30 –20 –10 0 10
PIN (dBm)
Figure 15. Typical V
and Log Conformance Error with Respect to 25°C Ideal
OUT
Line over Temperature vs. Input Amplitude at 3.5 GHz, CW
3.0
T
= 0.95V
ADJ
CALIBRATIO N AT 0dBm, –30d Bm, AND –50dBm
2.5
2.0
1.5
1.0
OUTPUT VOLTAGE (V)
0.5
0
–60 –50 –40 –30 –20 –10 0 10
PIN (dBm)
Figure 16. Typical V
and Log Conformance Error with Respect to 25°C Ideal
OUT
Line over Temperature vs. Input Amplitude at 5.8 GHz, CW
350
300
250
200
COUNT
150
REPRESENTS 1900
PARTS FROM 3 LOTS
6
5
4
3
2
1
0
–1
ERROR (dB)
–2
–3
–4
–5
–6
08218-115
6.0
V
= 0.5V
TADJ
5.5
REPRESENTS 55 DEVICES FROM 2 LOTS
5.0
4.5
4.0
3.5
3.0
2.5
2.0
OUTPUT VOLTAGE (V)
1.5
1.0
0.5
0
–60 –50 –40 –30 –20 –10 0 10
PIN (dBm)
6
5
4
3
2
1
0
–1
ERROR (dB)
–2
–3
–4
–5
–6
Figure 18. Distribution of Error with Respect to 25°C over Temperature vs.
Input Amplitude, CW, Frequency = 3.5 GHz
6
5
4
3
2
1
0
–1
ERROR (dB)
–2
–3
–4
–5
–6
08218-016
3.0
2.5
2.0
1.5
1.0
OUTPUT VOLTAGE (V)
0.5
V
= 0.95V
TADJ
REPRESENTS 55 DEVICES FROM 2 LOTS
0
–60 –50 –40 –30 –20 –10 0 10
PIN (dBm)
6
5
4
3
2
1
0
–1
ERROR (d B)
–2
–3
–4
–5
–6
Figure 19. Distribution of Error with Respect to 25°C over Temperature vs.
Input Amplitude, CW, Frequency = 5.8 GHz
COUNT
350
300
250
200
150
REPRESENTS 1900
PARTS FROM 3 LOTS
08218-018
8218-019
100
50
0
2.65 2.70 2.75 2.80 2.85 2.90 2.95 3.00 3.05
(V)
V
OUT
Figure 17. Distribution of V
, PIN = −10 dBm, 900 MHz
OUT
08218-017
Rev. A | Page 11 of 28
100
50
0
0.20 0.25 0.30 0.35 0.40 0.45 0.50
V
(V)
OUT
Figure 20. Distribution of V
, PIN = −60 dBm, 900 MHz
OUT
08218-020
ADL5902
6.0
V
CW PEP = 0dB
OUT
V
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
OU T PU T V OLTA G E ( V)
1.5
1.0
0.5
0
QPSK PEP = 2.76
OUT
V
16 QAM PEP = 5.13
OUT
V
CDMA2000 PEP = 11. 02
OUT
ERROR CW
ERROR QPSK
ERROR 16 QAM
ERROR CDMA2000
–60 –50 –40 –30 –20 –10 0 10
PIN (dBm)
Figure 21. Error from CW Linear Reference vs. Signal Modulation,
Frequency = 900 MHz, C
= 0.1µF, Three-Point Calibration at 0 dBm,
LPF
−45 dBm, and −60 dBm
6
5
RF ENVELOPE
0dBm
–10dBm
–20dBm
–30dBm
–40dBm
6
5
4
3
2
1
0
–1
ERROR (dB)
–2
–3
–4
–5
–6
08218-121
6.0
V
CW PEP = 0dB
OUT
5.5
V
64 QAM PEP = 6.2dB
OUT
V
1CR W-CDMA PEP = 10. 56dB
OUT
5.0
V
4CR W-CDMA
OUT
V
LTE TM 1 1CR 20MHz PEP = 11.58dB
OUT
4.5
ERROR CW
ERROR 64 QAM
4.0
ERROR 1CR W-CDMA
ERROR 4CR W-CDMA
3.5
ERROR LTE T M1 1CR 20MHz
3.0
2.5
2.0
OUTPUT VOLTAGE (V)
1.5
1.0
0.5
0
–60 –50 –40 –30 –20 –10 0 10
PIN (dBm)
Figure 24. Error from CW Linear Reference vs. Signal Modulation,
Frequency = 2.14 GHz, C
= 0.1 µF, Three-Point Calibration at −10 dBm,
LPF
−45 dBm, and −60 dBm
6
5
RF ENVELOPE
0dBm
–10dBm
–20dBm
–30dBm
–40dBm
6
5
4
3
2
1
0
–1
ERROR (dB)
–2
–3
–4
–5
–6
08218-124
4
3
2
OUTPUT VOLTAGE (V)
1
0
–10123456789
TIME (µs)
08218-027
Figure 22. Output Response to RF Burst Input, Carrier Frequency 2.14 GHz,
= 220 pF, Rising Edge
C
LPF
6
RF ENVELOPE
0dBm
–10dBm
5
4
3
2
OUTPUT VOLTAGE (V)
1
–20dBm
–30dBm
–40dBm
4
3
2
OUTPUT VOLTAGE (V)
1
0
–4 0 4 8 12162024283236
TIME (µs)
08218-030
Figure 25. Output Response to RF Burst Input, Carrier Frequency 2.14 GHz,
= 220 pF, Falling Edge
C
LPF
6
RF ENVELOPE
0dBm
–10dBm
5
4
3
2
OUTPUT VOLTAGE (V)
1
–20dBm
–30dBm
–40dBm
0
–200 0 200 400 600 800 1000 1200 1400 1600 1800
TIME (µs)
8218-028
Figure 23. Output Response to RF Burst Input, Carrier Frequency 2.14 GHz,
= 0.1 F, Rising Edge
C
LPF
Rev. A | Page 12 of 28
0
–2000 0 2000 4000 6000 8000 10,000 12,000 14,000 16,000 18,000
TIME (µs)
08218-031
Figure 26. Output Response to RF Burst Input, Carrier Frequency 2.14 GHz,
= 0.1 µF, Falling Edge
C
LPF
ADL5902
REPRESENTS 1900
PARTS FROM 3 LOTS
400
300
COUNT
200
100
0
1.29 1.32 1.35 1.38 1.41 1.44 1.47 1.50
V
Figure 27. Distribution of V
400
VOLTAGE
TEMP
TEMP
(V)
Voltage at 25°C, No RF Input
REPRESENTS 1900
PARTS FROM 3 LOTS
2.5
2.3
2.1
1.9
1.7
(V)
1.5
TEMP
V
1.3
1.1
0.9
0.7
0.5
–55 –35 –15 5 25 45 65 85 105 125
08218-033
Figure 30. V
TEMP
TEMPERATURE (°C)
and Linearity Error with Respect to Straight Line vs.
Temperature for Typical Device
0.2
0
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
ERROR (°C)
08218-036
300
COUNT
200
100
0
2.19 2.22 2.25 2 .28 2.31 2.34 2.37 2.40 2.43
BIAS VOLT AGE (V)
V
REF
Figure 28. Distribution of V
40
30
20
(mV)
10
REF
0
–10
CHANGE IN V
–20
–30
–40
–55 –35 –15 5 25 45 65 85 105 125
Figure 29. Change in V
Voltage at 25°C, No RF Input
REF
TEMPERATURE (°C)
vs. Temperature with Respect to 25°C,
REF
RF Input = −40 dBm, Typical Device
–0.2
(mV)
REF
–0.4
–0.6
CHANGE IN V
–0.8
–1.0
–50 –40 –30 –20 –10 0 10 20
08218-034
Figure 31. Change in V
REF
PIN (dBm)
vs. Input Amplitude with Respect to −40 dBm,
08218-035
25°C, Typical Device
100
10
V
PWDN
(V)
DECREASING
V
PWDN
INCREASING
PWDN
08218-038
1
SUPPLY CURRENT (mA)
0.1
08218-037
4.04.14.24.34.44.54.64.74.84.95.0
V
PWDN
Figure 32. Supply Current vs. V
Rev. A | Page 13 of 28
ADL5902
√
7
6
TADJ/PWDN PUL SE
5
4
3
OUTPUT VOLTAGE (V)
2
1
0
–4 0 4 8 121620242832
TIME (µs)
0dBm
–10dBm
–20dBm
–30dBm
–40dBm
Figure 33. Output Response Using Power-Down Mode for Various RF Input
Levels Carrier Frequency 2.14 GHz, C
3.5
3.0
2.5
2.0
(V)
OUT
1.5
V
–10dBm
–30dBm
= 220 pF
LPF
200
180
Hz)
160
140
120
100
80
60
40
NOISE SPECT RAL DENSITY (n V/
20
0
100 1k 10k 100k 1M 10M
08218-032
Figure 35. Noise Spectral Density of V
FREQUENCY (Hz)
, RF Input = −20 dBm, All C
OUT
Values
LPF
08218-039
1.0
0.5
0
Figure 34. Typical V
0123456789
FREQUENCY (G Hz)
vs. Frequency for Two RF Input Amplitudes,
OUT
50 MHz to 9 GHz
8218-026
Rev. A | Page 14 of 28
ADL5902
V
V
THEORY OF OPERATION
The ADL5902 is a 50 MHz to 9 GHz true rms responding
detector with a 65 dB measurement range at 2.14 GHz and a
greater than 56 dB measurement range at frequencies up to
6 GHz. It incorporates a modified AD8362 architecture that
increases the frequency range and improves measurement
accuracy at high frequencies. Transfer function peak-to-peak
ripple has been reduced to <±0.1 dB over the entire dynamic
range. Temperature stability of the rms output measurements
provides <±0.3 dB error, typically, over the specified temperature
range of −40°C to 125°C through proprietary techniques. The
device accurately measures waveforms that have a high peak-torms ratio (crest factor).
The ADL5902 consists of a high performance AGC loop. As
shown in Figure 36, the AGC loop comprises a wide bandwidth
variable gain amplifier (VGA), square law detectors, an amplitude
target circuit, and an output driver. For a more detailed description
of the functional blocks, see the AD8362 data sheet.
The nomenclature used in this data sheet to distinguish
between a pin name and the signal on that pin is as follows:
• The pin name is all uppercase, for example, VPOS,
COMM, and VOUT.
• The signal name or a value associated with that pin is the
pin mnemonic with a partial subscript, for example, C
and V
OUT
.
LPF
SQUARE LAW DETECTOR AND AMPLITUDE TARGET
The VGA gain has the form
)/(
VV−
= GO e (1)
G
SET
where:
G
is the basic fixed gain.
O
V
is a scaling voltage that defines the gain slope (the decibel
GNS
change per voltage). The gain decreases with increasing V
GNSSET
.
SET
POS
C
H
INHI
INLO
(INTERNAL)
VGA
V
SIG
I
2
X
SUMMING
NODE
SQRITGT
The VGA output is
)/(
VV−
V
SIG
where RF
= G
× RFIN = GO × RFIN e (2)
SET
is the ac voltage applied to the input terminals of the
IN
GNSSET
ADL5902.
The output of the VGA, V
, is applied to a wideband square
SIG
law detector. The detector provides the true rms response of the
RF input signal, independent of waveform. The detector output,
I
, is a fluctuating current with positive mean value. The
SQR
difference between I
I
, is integrated by the parallel combination of CF and the
TGT
and an internally generated current,
SQR
external capacitor attached to the CLPF pin at the summing
node. C
is an on-chip 26 pF filter capacitor, and C
F
LPF
, the
external capacitance connected to the CLPF pin, can be used to
arbitrarily increase the averaging time while trading off with the
response time. When the AGC loop is at equilibrium
Mean(I
SQR
) = I
TGT
This equilibrium occurs only when
Mean(V
where V
2
) = V
SIG
is the voltage presented at the VTGT pin. This pin
TGT
2
(4)
TGT
can conveniently be connected to the VREF pin through a voltage
divider to establish a target rms voltage, V
V
= 0.8 V.
TGT
, of ~40 mV rms when
ATG
Because the square law detectors are electrically identical and
well matched, process and temperature dependent variations
are effectively cancelled.
V
TGT
V
=
ATG
20
2
X
VTGT
(3)
G
SET
SET
C
LPF
(EXTERNAL)
TEMPERATURE CO MPENSATION
TEMPERATURE
REFERENCE
SENSOR
BAND GAP
C
F
(INTERNAL)
AND BIAS
CLPF
VOUT
COMM
TADJ/PWDN
TEMP (1.4V)
VREF (2.3V)
08218-040
Figure 36. Simplified Architecture Details
Rev. A | Page 15 of 28
ADL5902
V
When forcing the previous identity by varying the VGA setpoint, it
is apparent that
RMS(V
) = √(Mean(V
SIG
Substituting the value of V
RMS(G
× RFIN e ) = V
0
2
)) = √(V
SIG
from Equation 2 results in
SIG
)/(
VV−
GNSSET
When connected as a measurement device, V
for V
as a function of RFIN,
OUT
= V
V
OUT
× log10(RMS(RFIN)/VZ) (7)
SLOPE
ATG
ATG
2
) = V
SET
ATG
= V
. Solving
OUT
(5)
(6)
where:
V
is 1.06 V/decade (or 53 mV/dB) at 2.14 GHz.
SLOPE
is the intercept voltage.
V
Z
When RMS(RF
log
(1) = 0. This makes the intercept the input that forces V
10
0 V if the ADL5902 had no sensitivity limit. The P
) = VZ, this implies that V
IN
= 0 V because
OUT
INTERCEPT
(in
OUT
=
decibels relative to 1 milliwatt, that is, dBm) corresponding to
Vz (in volts) in ADL5902 is given by the following equation:
P
where V
P
MINDET
= −(V
INTERCEPT
PEDISTAL
PEDISTAL/VSLOPE
is the VSET interface’s pedestal voltage, and
is the minimum detectable signal in decibels relative to 1
) + P
MINDET
(8)
milliwatt, given by the following expression:
P
= dBm (V
MINDET
where dBm(V
ATG
1 milliwatt corresponding to a given V
) – GO (9)
ATG
) is the equivalent power in decibels relative to
.
TGT
Combining Equation 8 and Equation 9 results in
P
For the ADL5902, V
given by V
then decreases at higher frequencies. V
V
= −(V
INTERCEPT
TGT
= 40 mV
ATG
PEDISTAL/VSLOPE
PEDISTAL
/20. GO is 45 dB below approximately 4 GHz and
) + dBm (V
ATG
is approximately 0.275 V and V
= 0.8 V; therefore,
TGT
) – G
(10)
O
is
ATG
and
dBm (V
At 2.14 GHz, V
This results in a P
) = 10 log
ATG
SLOPE
INTERCEPT
((40 mV)2/50 Ω)/1 mW) ≈ −14.9 dBm
10
≈ 53 mV/dB and GO at 2.14 GHz = 45 dB.
≈ −65 dBm. This differs slightly from
the value in Table 1 due to the choice of calibration points and
the slight nonideality of the response.
In most applications, the AGC loop is closed through the
setpoint interface and the VSET pin. In measurement mode,
VOUT is directly connected to VSET (see the Measurement
Mode Basic Connections section for more information). In
controller mode, a control voltage is applied to VSET, and the
VOUT pin typically drives the control input of an amplification
or attenuation system. In this case, the voltage at the VSET pin
forces a signal amplitude at the RF inputs of the ADL5902 that
balances the system through feedback.
Rev. A | Page 16 of 28
RF INPUT INTERFACE
Figure 37 shows the RF input connections within the ADL5902.
The input impedance is set primarily by an internal 2 kΩ resistor
connected between INHI and INLO. A dc level of approximately
half the supply voltage on each pin is established internally.
Either the INHI or INLO pin can be used as the single-ended
RF input pin. Signal coupling capacitors must be connected
from the input signal to the INHI and INLO pins. A single
external 60.4 Ω resistor to ground from the desired input
creates an equivalent 50 Ω impedance over a broad section of
the operating frequency range. The other input pin should be
RF ac-coupled to common (ground). The input signal high-pass
corner formed by the input coupling capacitor’s internal and
external resistances is
f
= 1/(2 × π × 50 × C) (11)
HIGHPASS
where C is the capacitance in farads and f
input coupling capacitors must be large enough in value to pass
the input signal frequency of interest and determine the low end
of the frequency response. INHI and INLO can also be driven
differentially using a balun.
BIAS
VPOS
COMM
ESD
ESD
ESD
2kΩ 2kΩ
LOAD
ESD ESD ESD ESD
ESD
ESD ESD ESD
Figure 37. RF Inputs
Extensive ESD protection is employed on the RF inputs, and
this protection limits the maximum possible input to the
ADL5902.
is in hertz. The
HIGHPASS
ESD
INLOINHI
ESD
08218-041
ADL5902
V
V
SMALL SIGNAL LOOP RESPONSE
The ADL5902 uses a VGA in a loop to force a squared RF signal
to be equal to a squared dc voltage. This nonlinear loop can be
simplified and solved for a small signal loop response. The lowpass corner pole is given by
Freq
≈ 1.83 × I
LP
TGT
/(C
) (12)
LPF
where:
I
is in amperes.
TGT
C
is in farads.
LPF
is in hertz.
Freq
LP
I
is derived from V
TGT
V
multiplied by a transresistance, namely
TGT
= gm × V
I
TGT
g
is approximately 18.9 µs; therefore, with V
m
typically recommended 0.8 V, I
TGT
; however, I
TGT
2
is a squared value of
TGT
equal to the
TGT
is approximately 12 µA. The
TGT
(13)
value of this current varies with temperature; therefore, the small
signal pole varies with temperature. However, because the RF
squaring circuit and dc squaring circuit track with temperature,
there is no temperature variation contribution to the absolute value
of V
.
OUT
For CW signals,
Freq
≈ 67.7 × 10−6/(C
LP
) (14)
LPF
However, signals with large crest factors include low pseudorandom frequency content that must be either filtered out or
sampled and averaged out (see the Choosing a Value for C
LPF
section for more information).
TEMPERATURE SENSOR INTERFACE
The ADL5902 provides a temperature sensor output with a
scaling factor of the output voltage of approximately 4.9 mV/°C.
The output is capable of sourcing 4 mA and sinking 50 A
maximum at 25°C. An external resistor can be connected from
TEMP to COMM to provide additional current sink capability.
The typical output voltage at 25°C is approximately 1.4 V.
POS
INTERNAL
VPAT
TEMP
12kΩ
4kΩ
COMM
Figure 38. TEMP Interface Simplified Schematic
08218-042
VREF INTERFACE
The VREF pin provides an internally generated voltage reference
for the user. The VREF voltage is a temperature stable 2.3 V
reference that is capable of sourcing 4 mA and sinking 50 A
maximum. An external resistor can be connected from VREF to
COMM to provide additional current sink capability. The
voltage on this pin can be used to drive the TADJ/PWDN and
VTGT pins.
POS
INTERNAL
VOLTAGE
VREF
16kΩ
COMM
Figure 39. VREF Interface Simplified Schematic
08218-143
TEMPERATURE COMPENSATION INTERFACE
While the ADL5902 has a highly stable measurement output
with respect to temperature using proprietary techniques, for
optimal performance, the output temperature drift must be
compensated for using the TADJ pin. The absolute value of
compensation varies with frequency and V
recommended voltages for V
to maintain a temperature drift
TAD J
error of typically ±0.5 dB or better over the intended temperature
range (−40°C < T
V
= 0.8 V.
TGT
Table 4. Recommended V
< +85°C) when driven single-ended and
A
for Selected Frequencies
TADJ
R9 in Figure 54
Frequency V
TAD J
(V)
(Ω)
100 MHz 0.5 1430 402
700 MHz 0.4 1430 301
900 MHz 0.4 1430 301
1.9 GHz 0.4 1430 301
2.14 GHz 0.4 1430 301
2.6 GHz 0.45 1430 348
3.5 GHz 0.5 1430 402
5.8 GHz 0.95 1430 1007
The values in Table 4 were chosen to give the best drift
performance at the high end of the usable dynamic range
over the −40°C to +85°C temperature range. There is often a
trade off in setting values, and optimizing for one area of the
dynamic range may mean less than optimal drift performance
at other input amplitudes.
. Table 4 shows the
TGT
R12 in Figure 54
(Ω)
Rev. A | Page 17 of 28
ADL5902
V
V
Compensating the device for temperature drift using TADJ allows
for great flexibility. If the user requires minimum temperature
drift at a given input power, a subset of the dynamic range, or
even over a different temperature range than shown in this data
sheet, the V
can be swept while monitoring V
TAD J
over the
OUT
temperature at the frequency and amplitude of interest. The
optimal V
power and frequency is the value of V
to achieve minimum temperature drift at a given
TAD J
where the output has
TAD J
minimum movement.
2.83
+125°C
2.81
2.79
(V)
OUT
V
2.77
2.75
2.73
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
V
(V)
TADJ
Figure 40. Effect of V
at Various Temperatures, 2.14 GHz, −10 dBm
TADJ
+105°C
+85°C
+55°C
+25°C
0°C
–20°C
–40°C
08218-044
Var yin g VTADJ has only a very slight effect on VOUT at device
temperatures near 25°C; however, the compensation circuit
has more and more effect as the temperature departs farther
from 25°C.
The TADJ pin has a high input impedance and can be conveniently driven from an external source or from an attenuated
value of V
using a resistor divider. Table 4 gives suggested
REF
voltage divider values to generate the required voltage from
V
. The resistors are shown in the evaluation board schematic
REF
(see Figure 54). V
does change slightly with temperature and
REF
also input RF amplitude; however, the amount of change is
unlikely to result in a significant effect on the final temperature
stability of the RF measurement system. Typically, the
temperature compensation circuit responds only to voltages
between 0 and V
/2, or about 2.5 V when VS = 5 V.
S
Figure 41 in the Power-Down Interface section shows a simplified schematic representation of the TADJ/PWDN interface.
POWER-DOWN INTERFACE
The quiescent and disabled currents for the ADL5902 at 25°C
are approximately 73 mA and 300 µA, respectively. The dual
function TADJ/PWDN pin is connected to the temperature
compensation circuit as well as the power-down circuit.
Typically, the temperature compensation circuit responds only
to voltages between 0 and V
When the voltage on this pin is greater than V
device is fully powered down. Figure 32 shows this characteristic as a function of V
of this section of the ADL5902, as V
/2, or about 2.5 V when VS = 5 V.
S
− 0.1 V, the
S
. Note that, because of the design
PWDN
passes through a
PWDN
narrow range at ~4.5 V (or ~V
sinks approximately 500 µA. The source used to disable the
ADL5902 must have a sufficiently high current capability for this
reason. Figure 33 shows the typical response times for various
RF input levels. The output reaches within 0.1 dB of its steadystate value in approximately 5 µs; however, the reference voltage is
available to full accuracy in a much shorter time. This wake-up
response varies depending on the input coupling and C
POS
ESD
SHUTDOWN
CIRCUIT
TADJ /
PWDN
COMM
200Ω
ESD
Figure 41. TADJ/PWDN Interface Simplified Schematic
VSET INTERFACE
The VSET interface has a high input impedance of 72 kΩ. The
voltage at VSET is converted to an internal current used to set
the internal VGA gain. The VGA attenuation control is approximately 19 dB/V.
VSET
Figure 42. VSET Interface Simplified Schematic
OUTPUT INTERFACE
The ADL5902 incorporates rail-to-rail output drivers with pullup and pull-down capabilities. The closed-loop, − 3dB bandwidth
from the input of the output amplifier to the output with no
load is approximately 58 MHz with a single-pole roll off of
approximately −20 dB/decade. The output noise is approximately 25 nV/√Hz at 100 kHz. The VOUT pin can source and
sink up to 10 mA. There is also an internal load from VOUT
to COMM of 2500 Ω.
POS
ESD
CLPF
ESD
ESD
COMM
Figure 43. VOUT Interface Simplified Schematic
− 0.5 V), the TADJ/PWDN pin
S
POWER-UP
CIRCUIT
54kΩ
18kΩ
2pF
7kΩ 7kΩ
200Ω
200Ω
GAIN ADJUST
2.5kΩ
ACOM
LPF
ESD
VREF
INTERCEPT
TEMPERATURE
COMPENSATION
08218-149
VOUT
2kΩ
500Ω
.
08218-076
08218-045
Rev. A | Page 18 of 28
ADL5902
V
VTGT INTERFACE
The target voltage can be set with an external source or by
connecting the VREF pin (nominally 2.3 V) to the VTGT pin
through a resistive voltage divider. With 0.8 V on the VTGT pin,
the rms voltage that must be provided by the VGA to balance the
AGC feedback loop is 0.8 V × 0.05 = 40 mV rms. Most of the
characterization information in this data sheet was collected at
V
= 0.8 V. Voltages higher and lower than this can be used;
TGT
however, doing so increases or decreases the gain at the internal
squaring cell, which results in a corresponding increase or
decrease in intercept. This, in turn, affects the sensitivity and the
usable measurement range, in addition to the sensitivity to
different carrier modulation schemes. As V
decreases, the
TGT
squaring circuits produce more noise; this becomes noticeable
in the output response at low input signal amplitudes. As V
TGT
increases, measurement error due to modulation increases and
temperature drift tends to decrease. The chosen V
value of
TGT
0.8 V represents a compromise between these characteristics.
POS
VTGT
ESD
ESD
50kΩ
50kΩ
ESD
COMM
Figure 44. VTGT Interface
10kΩ
g × X
2
ITGT
08218-048
BASIS FOR ERROR CALCULATIONS
The slope and intercept used in the error plots are calculated using
the coefficients of a linear regression performed on data collected
in its central operating range. The error plots in the Typ ic al
Performance Characteristics section are shown in two formats:
error from the ideal line and error with respect to the 25°C output
voltage. The error from the ideal line is the decibel difference in
V
from the ideal straight-line fit of V
OUT
linear-regression fit over the linear range of the detector,
typically at 25°C. The error in decibels is calculated by
Error (dB) = (V
where P
Z
is the x-axis intercept expressed in decibels relative to
− Slope × (PIN − PZ))/Slope (15)
OUT
1 milliwatt (the input amplitude that would produce a 0 V output
if such an output were possible).
The error from the ideal line is not a measure of absolute accuracy
because it is calculated using the slope and intercept of each device.
However, it verifies the linearity and the effect of temperature
and modulation on the response of the device. An example of
this type of plot is Figure 3. The slope and intercept that form the
calculated by the
OUT
ideal line are those at 25°C with CW modulation. Figure 21 and
Figure 24 show the error with various popular forms of modulation
with respect to the ideal CW line. This method for calculating
error is accurate, assuming that each device is calibrated at
room temperature.
In the second plot format, the V
voltage at a given input
OUT
amplitude and temperature is subtracted from the corresponding
V
at 25°C and then divided by the 25°C slope to obtain an error
OUT
in decibels. This type of plot does not provide any information
on the linear-in-dB performance of the device; it merely shows
the decibel equivalent of the deviation of V
over temperature,
OUT
given a calibration at 25°C. When calculating error from any
one particular calibration point, this error format is accurate. It
is accurate over the full range shown on the plot assuming that
enough calibration points are used. Figure 6 shows this plot type.
The error calculations for Figure 30 are similar to those for the
V
plots. The slope and intercept of the V
OUT
function vs.
TEMP
temperature are determined and applied as follows:
Error (°C) = (V
− Slope × (Temp − TZ))/Slope (16)
TEMP
where:
T
is the x-axis intercept expressed in degrees Celsius (the
Z
temperature that would result in a V
of 0 V if this were
TEMP
possible).
Te mp is the ambient temperature of the ADL5902 in degrees
Celsius.
Slope is, typically, 4.9 mV/°C.
V
is the voltage at the TEMP pin at that temperature.
TEMP
MEASUREMENT MODE BASIC CONNECTIONS
Figure 45 shows the basic connections for operating the ADL5902
as they are implemented on the device’s evaluation board. The
ADL5902 requires a single supply of nominally 5 V. The supply
is connected to the two VPOS supply pins. These pins should
each be decoupled using the two capacitors with values equal or
similar to those shown in Figure 45. These capacitors should be
placed as close as possible to the VPOS pins.
An external 60.4 resistor (R3) combines with the relatively high
RF input impedance of the ADL5902 to provide a broadband 50
match. An ac coupling capacitor should be placed between this
resistor and INHI. The INLO input should be ac-coupled to
ground using the same value capacitor. Because the ADL5902 has
a minimum input operating frequency of 50 MHz, 100 pF ac
coupling capacitors can be used.
The ADL5902 is placed in measurement mode by connecting
VOUT to VSET. In measurement mode, the output voltage is
proportional to the log of the rms input signal level.
Rev. A | Page 19 of 28
ADL5902
V
0.1µF
100pF
ADL5902
C10
100pF
INHI
RFIN
R3
60.4Ω
TC2 PWDN
(BLACK)
INLO
C12
100pF
NC
NC
NC
14
15
LINEAR-I N-dB VGA
(NEGATIVE SLOPE)
2
16
BIAS AND POWE R-
DOWN CONT ROL
13
R12
301Ω
POS
+5V
(RED)
C3
C4
VPOS POS
1
R9
1430Ω
3
VREF
VREF
(BLACK)
2.3V
11
10
X
X
R10
3.74kΩ
I
DET
2
2
I
TGT
12
(BLACK)
C7
0.1µF
C5
100pF
TEMPERAT URE
SENSOR
G = 5
9
COMMVTGTVREFTADJ/PWDN
VTGT
(BLACK)
R11
2kΩ
GND
26pF
4
COMM
8
7
6
5
(BLACK)
TEMP
VSET
VOUT
CLPF
TEMP
C9
10µF
VSET
(BLACK)
R6
0Ω
R2
OPEN
R1
0Ω
R15
OPEN
VOUT
(BLACK)
08218-145
Figure 45. Basic Connections for Operation in Measurement Mode
SETTING V
TADJ
As discussed in the Theory of Operation section, the output
temperature drift must be compensated by applying a voltage to
the TADJ pin. The compensating voltage varies with frequency.
The voltage for the TADJ pin can be easily derived from a resistor
divider connected to the VREF pin. Table 5 shows the recommended V
for operation from −40°C to +85°C, along with
TAD J
resistor divider values. Resistor values are chosen so that they
neither pull too much current from VREF (VREF short-circuit
current is 4 mA) nor are so large that the TADJ pin’s bias current of
3 µA affects the resulting voltage at the TADJ pin.
Table 5. Recommended V
Frequency V
for Selected Frequencies
TADJ
(V) R9 (Ω) R12 (Ω)
TAD J
100 MHz 0.5 1430 402
700 MHz to 2.14 GHz 0.4 1430 301
2.6 GHz 0.45 1430 348
3.5 GHz 0.5 1430 402
5.8 GHz 0.95 1430 1007
SETTING V
TGT
As discussed in the Theory of Operation section, setting the
voltage on VTGT to 0.8 V represents a compromise between
achieving excellent rms compliance and maximizing dynamic
range. The voltage on VTGT can be derived from the VREF pin
using a resistor divider as shown Figure 45 (Resistor R10 and
Resistor R11). Like the resistors chosen to set the V
the resistors setting V
should have reasonable values that do
TGT
voltage,
TAD J
not pull too much current from VREF or cause bias current
errors. Also, attention should be paid to the combined current
that VREF must deliver to generate the V
TAD J
and V
voltages.
TGT
This current should be kept well below the VREF short-circuit
current of 4 mA.
CHOOSING A VALUE FOR C
C
(C9 in Figure 45) provides the averaging function for the
LPF
internal rms computation. Using the minimum value for C
LPF
LPF
allows the quickest response time to a pulsed waveform but
leaves significant output noise on the output voltage signal. By
the same token, a large filter cap reduces output noise but at the
expense of response time.
For non response-time critical applications, a relatively large
capacitor can be placed on the CLPF pin. In Figure 45, a value
of 0.1 µF is used. For most signal modulation schemes, this
value ensures excellent rms measurement compliance and low
residual output noise. There is no maximum capacitance limit
for C
.
LPF
Rev. A | Page 20 of 28
ADL5902
O
V
Figure 46 shows how output noise varies with C
when the
LPF
ADL5902 is driven by a single-carrier W-CDMA signal (Test
Model TM1-64, peak envelope power = 10.56 dB, bandwidth =
3.84 MHz). With a 10 µF capacitor on CLPF, there is residual
noise on V
of 4.4 mV p-p, which is less than 0.1 dB error
OUT
(assuming a slope of approximately 53 mV/dB).
300
250
200
150
100
OUTPUT NOISE (mV p-p)
50
0
1 10 100 1000
OUTPUT NOISE (mV p-p)
10% TO 90% RIS E TIME (µs)
90% TO 10% FALL TIME (µs)
(nF)
C
LPF
Figure 46. Output Noise, Rise and Fall Times vs. C
Carrier W-CDMA (TM1-64) at 2.14 GHz with P
Figure 46 also shows how C
affects the response time of V
LPF
Capacitance, Single-
LPF
= 0 dBm
IN
1M
100k
10k
1k
100
10
1
RISE/FALL TIME (µs)
OUT
To measure this, a RF burst at 2.14 GHz at −10 dBm was applied to
the ADL5902. The 10% to 90% rise time and 90% to 10% fall
time were then measured. It is notable that the fall time is much
longer than the rise time. This can also be seen in the response
time plots, Figure 22, Figure 23, Figure 25, and Figure 26.
POS POS
3
10
ADL5902
14
INL
INHI
NC
NC
NC
15
2
16
13
LINEAR-I N-dB VG A
(NEGATIVE SLOPE)
BIAS AND POWER-
DOWN CONT ROL
1
VREF
2.3V
11
2
X
2
X
Figure 47. Optimizing Setting Time and Residual Ripple
08218-146
.
I
DET
I
TGT
12
In applications where the response time is critical, a different
approach to signal filtering can be taken. This is shown in
Figure 47. The capacitor on the CLPF pin is set to the minimum
value that ensures that a valid rms computation has been
performed. The job of noise removal is then handed off to an
RC filter on the VOUT pin. This approach ensures that there is
enough averaging to ensure good rms compliance and does not
burden the rms computation loop with extra filtering that will
significantly slow down the response time. By finishing the
filtering process using an RC filter after VOUT, faster fall times
can be achieved with an equivalent amount of output noise. It
should be noted that the RC filter can also be implemented in
the digital domain after the analog-to-digital converter.
In Figure 47, C
is equal to 10 nF. This value was experimentally
LPF
determined to be the minimum capacitance that ensures good
rms compliance when the ADL5902 is driven by a 1 C W-CDMA
signal (TM1-64). This test was carried out by starting out with a
large capacitance value on the CLPF pin (for example, 10 µF).
The value of V
example, −10 dBm). The value of C
was noted for a fixed input power level (for
OUT
was then progressively
LPF
reduced (this can be done with press-down capacitors) until
the value of V
started to deviate from its original value (this
OUT
indicates that the accuracy of the rms computation is degrading
and that C
is getting too small).
LPF
TEMPERAT URE
SENSOR
G = 5
26pF
9
TEMP
8
VSET
7
R
FILTER
2kΩ
6
VOUT
CLPF
C9
5
10nF
(SEE TABL E 6 AND
4
COMMCOMMVTGTVREFTADJ/PW DN
FIGURE 46.)
VOUT
C
FILTER
(SEE FIGURE 48.)
8218-147
Rev. A | Page 21 of 28
ADL5902
A
Figure 48 shows the resulting rise and fall times (signal is pulsed
between off and −10 dBm) with CLPF equal to 10 nF. A 2 kΩ
resistor is placed in series with the VOUT pin, and the capacitance
from this resistor to ground (CFILTER in Figure 47) is varied
up to 1 µF.
300
250
200
150
L RIPPLE (mV p-p)
100
RESIDU
50
0
1 10 100 1k
RESIDUAL RIPP LE (V p-p )
10% TO 90% RIS E TIME (µs)
90% TO 10% FALL TIME (µs)
C
(nF)
FILTER
Figure 48. Residual Ripple, Rise and Fall Times Using an RC Low-Pass Filter
at VOUT, P
= 0 dBm at 2.14 GHz
IN
1M
100k
10k
1k
100
10
1
RISE/FALL TIME (µs)
For large values of C
, the fall time is dramatically reduced
FILTER
compared to Figure 46. This comes at the expense of a moderate
increase in rise time.
As C
the fall time is now dominated by the 10 nF C
is reduced, the fall time flattens out. This is because
FILTER
which is
LPF
present throughout the measurement.
Table 6 shows recommended minimum values of C
LPF
for
popular modulation schemes, using just a single filter capacitor
at the CLPF pin. Using lower capacitor values results in rms
measurement errors. Output response time (10% to 90%) is also
shown. If the output noise shown in Tab le 6 is unacceptably
high, it can be reduced by
• Increasing C
LPF
• Adding an RC filter at VOUT, as shown in Figure 47
• Implementing an averaging algorithm after the ADL5902’s
output voltage has been digitized by an ADC
08218-148
Table 6. Recommended Minimum C
Modulation/Standard
Values for Various Modulation Schemes
LPF
Peak-Envelope
Power
Signal
Bandwidth C
(min) Output Noise Rise/Fall Time (10% to 90%)
LPF
W-CDMA, One-Carrier, TM1-64 10.56 dB 3.84 MHz 10 nF 95 mV p-p
W-CDMA Four-Carrier, TM1-64, TM1-32,
12.08 dB 18.84 MHz 5.6 nF 164 mV p-p
TM1-16, TM1-8
LTE, TM1 1CR 20 MHz (2048 Subcarriers,
11.58 dB 20 MHz 1000 pF 452 mV p-p
QPSK Subcarrier Modulation)
12/330 μs
7/200 μs
1.3/38 μs
Rev. A | Page 22 of 28
ADL5902
OUTPUT VOLTAGE SCALING
The output voltage range of the ADL5902 (nominally 0.3 V to
3.5 V) can be easily increased or decreased. There are a number
of situations where adjustment of the output scaling makes
sense. For example, if the ADL5902 is driving an analog-todigital converter (ADC) with a 0 V to 5 V input range, it makes
sense to increase the detector’s nominal maximum output
voltage of 3.5 V so that it is closer to 5 V. This makes better use
of the input range of the ADC and maximizes the resolution of
the system in terms of bits/dB. For more information on
interfacing the ADL5902 to an ADC, please refer to Circuit
Note CN0178.
If only a part of the ADL5902’s RF input power range is being
used (for example, −10 dBm to −60 dBm), it may make sense to
increase the scaling so that this reduced input range fits into the
ADL5902’s available output swing of 0 V to 4.8 V.
The output swing can also be reduced by simply adding a
voltage divider on the output pin, as shown in the circuit on the
left-hand side of Figure 49. Reducing the output scaling may, for
example, be used when interfacing the ADL5902 to an ADC
with a 0 V to 2.5 V input range. Recommended scaling resistors
for a slope decrease are provided in Table 7.
The output voltage swing can be increased using a technique
that is analogous to setting the gain of an op amp in noninverting
mode with the VSET pin being the equivalent of the inverting
input of the op amp. This is shown in the circuit on the left-hand
side of Figure 49.
Connecting VOUT to VSET results in the nominal 0 V to 3.5 V
swing and a slope of approximately 53 mV/dB (this varies slightly
with frequency). Figure 49 and Table 7 show the configurations
for increasing the slope, along with recommended standard
resistor values for particular input ranges and output swings.
R2
VSET
7
R1
VOUT
6
R15
Figure 49. Decreasing and Increasing Slope
7
6
VSET
VOUT
R6
08218-049
Table 7. Output Voltage Range Scaling
Desired
Input
Range
(dBm)
0 to −60 665 2000 72.1 0.195 to 4.52
−10 to −50 1180 2000 86.3 1.096 to 4.55
0 to −60 806 2000 38.3 0.103 to 2.49
−10 to −50 324 2000 46.2 0.587 to 2.43
R6
(Ω)
R2
(Ω)
R1
(Ω)
R15
(Ω)
New
Slope
(mV/dB)
Nominal
Output
Voltage
Range (V)
Equation 17 is the general function that governs this.
'
⎞
⎛
V
O
(17)
⎟
⎜
RR2R
−= 1)||(6
IN
⎟
⎜
V
O
⎠
⎝
where:
V
is the nominal maximum output voltage (see Figure 6
O
through Figure 18).
V'
is the new maximum output voltage (for example, up to 4.8 V).
O
R
is the VSET input resistance (72 kΩ).
IN
When choosing R6 and R2, attention must be paid to the current
drive capability of the VOUT pin and the input resistance of the
VSET pin. The choice of resistors should not result in excessive
current draw out of VOUT. However, making R6 and R2 too
large is also problematic. If the value of R2 is compatible with the
input resistance of the VSET input (72 kΩ), this input resistance,
which will vary slightly from part to part, contributes to the
resulting slope and output voltage. In general, the value of R2
should be at least ten times smaller than the input resistance of
VSET. Values for R6 and R2 should, therefore, be in the 1 k to
5 k range.
It is also important to take into account part-to-part and frequency
variation in output swing along with the ADL5902 output stage’s
maximum output voltage of 4.8 V. The V
OUT distribution is well
characterized at major frequencies’ bands in the Typ ic al
Performance Characteristics section (see Figure 6 through
Figure 8, Figure 12 through Figure 14, Figure 18, and Figure 19).
The resistor values in Tabl e 7, which were calculated based on
900 MHz performance, are conservatively chosen so that there
is no chance that the output voltages exceed the ADL5902 output
swing or the input range of a 0 V to 2.5 V and 0 V to 5 V ADC.
Because the output swing does not vary much with frequency
(it does start to drop off above 3 GHz), these values work for
multiple frequencies.
Rev. A | Page 23 of 28
ADL5902
SYSTEM CALIBRATION AND ERROR CALCULATION
The measured transfer function of the ADL5902 at 2.14 GHz is
shown in Figure 50, which contains plots of both output voltage
vs. input amplitude (power) and calculated error vs. input level. As
the input level varies from −62 dBm to +3 dBm, the output
voltage varies from ~0.25 V to ~3.5 V.
6
5
4
(V)
3
OUT
V
2
1
0
–70 –60 –50 –40 –30 –20 –10 100
V
OUT
ERROR 2-P OINT CAL AT 0dBm, AND 40dBm
ERROR 3-P OINT CAL AT 0 dBm,
–45dBm, AND 60dBm
ERROR 4-POINT CAL AT 0dBm, –20dBm,
–45dBm, AND –60dBm
PIN (dBm)
Figure 50. 2.14 GHz Transfer Function, Using Various Calibration Techniques
Because slope and intercept vary from device to device, boardlevel calibration must be performed to achieve high accuracy.
The equation for the idealized output voltage can be written as
V
= Slope × (PIN − Intercept) (18)
OUT(IDEAL)
where:
Slope is the change in output voltage divided by the change in
input power (dB).
Intercept is the calculated input power level at which the output
voltage is 0 V (note that Intercept is an extrapolated theoretical
value not a measured value).
In general, calibration is performed during equipment manufacture by applying two or more known signal levels to the
input of the ADL5902 and measuring the corresponding output
voltages. The calibration points are generally within the linearin-dB operating range of the device.
With a two-point calibration, the slope and intercept are
calculated as follows:
Slope = (V
Intercept = P
OUT1
IN1
− V
− (V
)/(P
− P
OUT2
IN1
/Slope) (20)
OUT1
) (19)
IN2
After the slope and intercept are calculated and stored in nonvolatile memory during equipment calibration, an equation can
be used to calculate an unknown input power based on the
output voltage of the detector.
P
(Unknown) = (V
IN
OUT1(MEASURED)
/Slope) + Intercept (21)
The log conformance error is the difference between this
straight line and the actual performance of the detector.
Error (dB) = (V
OUT(MEASURED)
− V
OUT(IDEAL)
)/Slope (22)
6
5
4
3
2
1
0
–1
ERROR (dB)
–2
–3
–4
–5
–6
08218-050
Figure 50 includes a plot of this error when using a two-point
calibration (calibration points are 0 dBm and −40 dBm). The
error at the calibration points (in this case, −40 dBm and 0 dBm)
is equal to 0 by definition.
The residual nonlinearity of the transfer function that is
apparent in the two-point calibration error plot can be reduced
by increasing the number of calibration points. Figure 50 shows
the postcalibration error plots for three-point and four-point
calibrations. With a multipoint calibration, the transfer function
is segmented, with each segment having its own slope and
intercept. Multiple known power levels are applied, and multiple
voltages are measured. When the equipment is in operation, the
measured voltage from the detector is first used to determine
which of the stored slope and intercept calibration coefficients
are to be used. Then the unknown power level is calculated by
inserting the appropriate slope and intercept into Equation 21.
Figure 51 shows the output voltage and error at 25°C and over
temperature when a four-point calibration is used (calibration
points are 0 dBm, −20 dBm, −45 dBm, and −60 dBm). When
choosing calibration points, there is no requirement for, or
value, in equal spacing between the points. There is also no
limit to the number of calibration points used. However, using
more calibration points increases calibration time.
6
+85°C V
OUT
+25°C V
OUT
–40°C V
5
4
(V)
3
OUT
V
2
1
0
–70 –60 –50 –40 –30 –20 –10 100
OUT
+85°C ERRO R 4-POINT CAL
+25°C ERROR 4-PO INT CAL AT 0dBm,
–20dBm, –45dBm, AND –60dBm
–40°C ERROR 4-POI NT CAL
P
(dBm)
IN
Figure 51. 2.14 GHz Transfer Function and Error at +25°C, −40°C, and +85°C
Using a Four-Point Calibration (0 dBm, −20 dBm, −45 dBm, −60 dBm)
6
5
4
3
2
1
0
–1
ERROR (dB)
–2
–3
–4
–5
–6
08218-051
The −40°C and +85°C error plots in Figure 51 are generated
using the 25°C calibration coefficients. This is consistent with
equipment calibration in a mass production environment where
calibration at just a single temperature is practical.
Rev. A | Page 24 of 28
ADL5902
HIGH FREQUENCY PERFORMANCE DESCRIPTION OF CHARACTERIZATION
The ADL5902 is specified to 6 GHz; however, operation is
possible to as high as 9 GHz with sufficient dynamic range for
many purposes. Figure 52 shows the typical V
response and
OUT
conformance error at 7 GHz, 8 GHz, and 9 GHz.
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
OUTPUT VOLTAGE (V)
0.75
0.50
0.25
0
–50 –40 –30 –20 –10 0 10
PIN (dBm)
Figure 52. Typical V
and Log Conformance Error at 7 GHz, 8 GHz,
OUT
and 9 GHz, 25°C Only
7GHz
8GHz
9GHz
6
5
4
3
2
1
0
–1
–2
–3
–4
–5
–6
LOW FREQUENCY PERFORMANCE
The lowest frequency of operation of the ADL5902 is approximately 50 MHz. This is the result of the circuit design and
architecture of the ADL5902.
ERROR (dB)
08218-057
The general hardware configuration used for most of the ADL5902
characterization is shown in Figure 53. The ADL5902 was driven in
a single-ended configuration for most characterization, except
where noted.
Much of the data was taken using an Agilent E4438C signal source
as a RF input stimulus. Several ADL5902 devices mounted on
circuit boards constructed of Rodgers 3006 material were put
into a test chamber simultaneously, and a Keithley S46 RF
switching network connected the signal source to the appropriate
device under test. The test chamber temperature was set to cycle
over the appropriate temperature range. The signal source,
switching, and chamber temperature were all controlled by a
PC running Agilent VEE Pro.
The subsequent response to stimulus was measured with a
voltmeter and the results stored in a database for analysis later.
In this way, multiple ADL5902 devices were characterized over
amplitude, frequency, and temperature in a minimum amount
of time. The RF stimulus amplitude was calibrated up to the
circuit board that carries the ADL5902, and, thus, it does not
account for the slight losses due to the connector on the circuit
board that carries the ADL5902 nor for the loss of traces on the
circuit board. For this reason, there is a small absolute amplitude
error (generally <0.5 dB) not accounted for in the characterization
data, but this is generally not important because the ADL5902’s
relative accuracy is unaffected.
PERSONAL
COMPUTER
AGILENT 34980A
SWITCH MATRIX/
DC METER
KEITHLEY S46
MICROWAVE
SWITCH
AGILENT E3631A
DC POWER
SUPPLIES
AGILENT E8251A
MICROWAVE
SIGNAL
GENERATOR
RF DC DATA AND CONTRO L
Figure 53. General Characterization Configuration
ADL5902
CHARACTERIZ ATION
BOARD – TEST SITE 1
ADL5902
CHARACTERIZ ATION
BOARD – TEST SITE 2
ADL5902
CHARACTERIZ ATION
BOARD – TEST SITE 3
08218-075
Rev. A | Page 25 of 28
ADL5902
V
EVALUATION BOARD SCHEMATICS AND ARTWORK
POS
+5V
C3
0.1µF
(RED)
C7
0.1µF
GND
(BLACK)
RFIN
R3
60.4Ω
C10
100pF
TC2 PWDN
(BLACK)
INHI
INLO
C12
100pF
NC
NC
NC
100pF
ADL5902
14
15
LINEAR-I N-dB VGA
(NEGATIVE SLOPE)
2
16
BIAS AND POWER-
DOWN CONTRO L
13
R12
301Ω
C4
VPOS POS
3
1
R9
1430Ω
VREF
2.3V
11
VREF
(BLACK)
R10
3.74kΩ
10
2
X
2
X
C5
100pF
TEMPERAT URE
SENSOR
I
DET
I
TGT
12
COMMVTGTVREFTADJ/PWDN
VTGT
(BLACK)
R11
2kΩ
G = 5
26pF
9
4
COMM
8
7
6
5
(BLACK)
TEMP
VSET
VOUT
CLPF
TEMP
(BLACK)
C9
10µF
VSET
R2
OPEN
R6
0Ω
R1
0Ω
R15
OPEN
VOUT
(BLACK)
08218-150
Figure 54. Evaluation Board Schematic
Table 8. Evaluation Board Configuration Options
Component Function/Notes Default Value
C10, C12, R3
R10, R11 VTGT interface. R10 and R11 are set up to provide 0.8 V to VTGT derived from VREF.
RF input. The ADL5902 is generally driven single-ended. R3 is the input termination resistor and is
chosen to give a 50 Ω input impedance over a broad frequency range.
C10 = C12 = 100 pF
R3 = 60.4 Ω
R10 = 3.74 kΩ,
R11 = 2 kΩ
C4, C5, C7, C3
R1, R15, R2,
R6
Power supply decoupling. The nominal supply decoupling consists of two pairs of 100 pF and
0.1 μF capacitors placed close to the two power supply pins of the ADL5902.
Output interface. In measurement mode, a portion of the voltage at the VOUT pin is fed back to
the VSET pin via R6. Using the voltage divider created by R2 and R6, the magnitude of the slope
of V
is increased by reducing the portion of V
OUT
that is fed back to V
OUT
. In controller mode, R6
SET
C4 = C5 = 100 pF,
C7 = C3 = 0.1 μF
R1 = R6= 0 Ω,
R2 = R15 = open
must be open. In this mode, the ADL5902 can control the gain of an external component. A
setpoint voltage is applied to the VSET pin, the value of which corresponds to the desired RF input
signal level applied to the ADL5902.
C9
Low-pass filter capacitors, C
. The low-pass filter capacitor provides the averaging for the
LPF
C9 = 0.1 μF
ADL5902’s rms computation.
R9, R12
TADJ/PWDN. The TADJ/PWDN pin controls the amount of nonlinear intercept temperature
compensation and/or shuts down the device. The evaluation board is configured with TADJ
R9 = 1430 Ω
R12 = 301 Ω
connected to VREF through a resistor divider (R9, R12).
Rev. A | Page 26 of 28
ADL5902
SSEMBLY DRAWINGS A
08218-060
Figure 55. Evaluation Board Layout, Top Side
Figure 56. Evaluation Board Layout, Bottom Side
08218-061
Rev. A | Page 27 of 28
ADL5902
OUTLINE DIMENSIONS
4.00
PIN 1
INDICATOR
1.00
0.85
0.80
12° MAX
SEATING
PLANE
BSC SQ
TOP
VIEW
0.80 MAX
0.65 TYP
COMPLIANT TO JEDEC STANDARDS MO-220-VGG C
0.35
0.30
0.25
3.75
BSC SQ
0.20 REF
0.60 MAX
0.65 BSC
0.05 MAX
0.02 NOM
COPLANARIT Y
0.50
0.40
0.30
0.08
Figure 57. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-16-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Ordering Quantity
ADL5902ACPZ-R7 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-10 1,500
ADL5902ACPZ-R2 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-10 250
ADL5902ACPZ-WP −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-10 64
ADL5902-EVALZ Evaluation Board
1
Z = RoHS Compliant Part.
0.60 MAX
13
16
12
EXPOSED
(BOTTOM VIEW)
9
8
1.95 BSC
1
PA D
4
5
FOR PROPER CONNECTION O F
THE EXPOSED PAD, REFER TO
THE PIN CONF IGURATIO N AND
FUNCTION DES CRIPTIONS
SECTION O F THIS DAT A SHEET.
PIN 1
INDICATOR
2.50
2.35 SQ
2.20
0.25 MIN
082008-A
©2010–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08218-0-7/11(A)
Rev. A | Page 28 of 28
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