Datasheet ADL5811 Datasheet (ANALOG DEVICES)

High IP3, 700 MHz to 2800 MHz, Double Balanced,

Passive Mixer, IF Amplifier, and Wideband LO Amplifier

FEATURES

RF frequency: 700 MHz to 2800 MHz continuous LO frequency: 250 MHz to 2800 MHz, high-side or

low-side inject IF range: 30 MHz to 450 MHz Power conversion gain of 7.5 dB at 1900 MHz SSB noise figure of 10.7 dB at 1900 MHz Input IP3 of 27.5 dBm at 1900 MHz Input P1dB of 12.7 dBm at 1900 MHz Typical LO drive of 0 dBm Single-ended, 50 Ω RF port Single-ended or balanced LO input port Single-supply operation: 3.6 V to 5.0 V Serial port interface control on all functions Exposed paddle 5 mm × 5 mm, 32-lead LFCSP package

APPLICATIONS

Multiband/multistandard cellular base station receivers Wideband radio link diversity downconverters Multimode cellular extenders and broadband receivers

ADL5811

FUNCTIONAL BLOCK DIAGRAM

VPIF

IFGMNCIFOP

30 29 28 27 26 2532 31

1

NC

2

RFCT

3

NC

4

RFIN

5

NC

6

NC

BIAS

7

NC

GEN

8

11 12 13 14 15 169 10

VLO4

COMM

VLO3

COMM

Figure 1.

IFONNCIFGD

ADL5811

SERIAL

PORT

INTERFACE

VLO2

COMM

24

NC

23

NC

22

NC

21

LOIP

20

LOIN

19

LE

18

DATA

17

CLK

VLO1

COMM

09912-001

GENERAL DESCRIPTION

The ADL5811 uses revolutionary new broadband, square wave limiting, local oscillator (LO) amplifiers to achieve an unprecedented radio frequency (RF) bandwidth of 700 MHz to 2800 MHz. Unlike conventional narrow-band sine wave LO amplifier solutions, this permits the LO to be applied either above or below the RF input over an extremely wide bandwidth. Because energy storage elements are not used, the dc current consumption also decreases with decreasing LO frequency.

The ADL5811 uses highly linear, doubly balanced, passive mixer cores along with integrated RF and LO balancing circuits to allow single-ended operation. The ADL5811 incorporates programmable RF baluns, allowing optimal performance over a 700 MHz to 2800 MHz RF input frequency. The balanced passive mixer arrangement provides outstanding LO-to-RF and LO-toIF leakages, excellent RF-to-IF isolation, and excellent intermodulation performance over the full RF bandwidth.

The balanced mixer cores also provide extremely high input linearity, allowing the device to be used in demanding

wideband applications where in-band blocking signals may otherwise result in the degradation of dynamic range. Blocker noise figure performance is comparable to narrow-band passive mixer designs. High linearity IF buffer amplifiers follow the passive mixer cores, yielding typical power conversion gains of

7.5 dB, and can be used with a wide range of output impedances. For low voltage applications, the ADL5811 is capable of operation at voltages down to 3.6 V with substantially reduced current. Two logic bits are provided to power down (<1.5 mA) the circuit when desired.

All features of the ADL5811 are controlled via a 3-wire serial port interface, resulting in optimum performance and minimum external components.

The ADL5811 is fabricated using a BiCMOS high performance IC process. The device is available in a 32-lead, 5mm × 5mm, LFCSP package and operates over a −40°C to +85°C temperature range. An evaluation board is also available.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADL5811

REVISION HISTORY

7/11—Revision 0: Initial Version

Rev. 0 | Page 2 of 28

ADL5811

SPECIFICATIONS

VS = 5 V, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, RF power = −10 dBm, LO power = 0 dBm, R1 = 910 Ω, ZO = 50 Ω, optimum SPI settings, unless otherwise noted.

Table 1.

Parameter Test Conditions/Comments Min Typ Max Unit

RF INPUT INTERFACE

Return Loss Tunable to >20 dB broadband via serial port 15 dB

Input Impedance 50 Ω

RF Frequency Range 700 2800 MHz

OUTPUT INTERFACE

Output Impedance Differential impedance, f = 200 MHz 260||1.0 Ω||pF

IF Frequency Range 30 450 MHz

DC Bias Voltage1 Externally generated VS V

LO INTERFACE

LO Power −6 0 +10 dBm

Return Loss 13 dB

Input Impedance 50 Ω

LO Frequency Range Low-side or high-side LO 250 2800 MHz

DYNAMIC PERFORMANCE

Power Conversion Gain Including 4:1 IF port transformer and PCB loss 7.5 dB

Voltage Conversion Gain Z

SSB Noise Figure 10.7 dB

SSB Noise Figure Under Blocking

Input Third-Order Intercept

Input Second-Order Intercept

Input 1 dB Compression Point 12.7 dBm

LO-to-IF Output Leakage Unfiltered IF output −40 dBm

LO-to-RF Input Leakage −25 dBm

RF-to-IF Output Isolation 26 dB

IF/2 Spurious −10 dBm input power −73 dBc

IF/3 Spurious −10 dBm input power −75 dBc

POWER INTERFACE

Supply Voltage, VS 3.6 5 5.5 V

Quiescent Current Resistor programmable IF current 185 mA

Power-Down Current 1.4 mA

1

Supply voltage must be applied from external circuit through choke inductors.

= 50 Ω, differential Z

SOURCE

= 200 Ω differential 13.9 dB

LOAD

5 dBm blocker present ±10 MHz from wanted RF input, LO source filtered

= 1900 MHz, f

f

RF1

= 1901 MHz, fLO = 1697 MHz,

RF2

each RF tone at −10 dBm

= 1900 MHz, f

f

RF1

= 2000 MHz, fLO = 1697 MHz,

RF2

each RF tone at −10 dBm

20.7 dB

27.5 dBm

62 dBm

Rev. 0 | Page 3 of 28

ADL5811

A

TIMING CHARACTERISTICS

Low logic level ≤ 0.4 V, and high logic level ≥ 1.4 V.

Table 2. Serial Interface Timing

Parameter Limit Unit Test Conditions/Comments

t1 20 ns minimum LE setup time t2 10 ns minimum DATA-to-CLK setup time t3 10 ns minimum DATA-to-CLK hold time t4 25 ns minimum CLK high duration t5 25 ns minimum CLK low duration t6 10 ns minimum CLK-to-LE setup time t7 20 ns minimum LE pulse width

Timing Diagram

CLK

t

4

t

5

t

2

D

DB23 (MSB) DB22

TA

LE

t

3

DB2 DB1

(CONTROL BIT C2)(CONTROL BIT C3)

DB0 ( LSB)

(CONTROL BIT C1)

t

7

6

1

09912-002

Figure 2. Timing Diagram

Rev. 0 | Page 4 of 28

ADL5811

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltage, V CLK, DATA, LE 5.5 V IF Output Bias 6.0 V RF Input Power 20 dBm LO Input Power 13 dBm Internal Power Dissipation 1.1 W θJA (Exposed Paddle Soldered Down) 25°C/W Maximum Junction Temperature 150°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C

5.5 V

POS

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. 0 | Page 5 of 28

ADL5811

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VPIF

IFGMNCIFOP

IFONNCIFGD

32313029282726

1

NC

2

RFCT

NC

3 4 5 6 7 8

ADL5811

TOP VIEW

(Not to Scale)

9

10111213141516

VLO4

VLO3

COMM

RFIN

NC NC NC NC

NOTES

1. NC = NO CO NNECT. CAN BE GROUNDED.

2. EXPOSED PAD MUST BE CONNECTED TO GROUND.

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1, 3, 5 to 8, 22 to 24, 27, 30 NC No Connect. Can be grounded. 2 RFCT RF Balun Center Tap (AC Ground). 4 RFIN RF Input. Should be ac-coupled. 9, 11, 13, 15 VLO4, VLO3, VLO2, VLO1 Positive Supply Voltages for LO Amplifier. 10, 12, 14, 16, 25 COMM Ground. 17, 18, 19 CLK, DATA, LE Serial Port Interface Control. 20 LOIN Ground Return for LO Input. 21 LOIP LO Input. Should be ac-coupled. 26 IFGD Supply Return for IF Amplifier. Must be grounded. 28, 29 IFOP, IFON

IF Differential Open-Collector Outputs. Should be pulled up to V

external inductors. 31 IFGM IF Amplifier Bias Control. 32 VPIF Supply Voltage for IF Amplifier. EPAD Exposed pad must be connected to ground.

COMM

25

NC

24 23

NC NC

22

LOIP

21 20

LOIN

19

LE

18

DATA CLK

17

VLO2

VLO1

COMM

09912-003

using

CC

Rev. 0 | Page 6 of 28

ADL5811

TYPICAL PERFORMANCE CHARACTERISTICS

VS = 5 V, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, RF power = −10 dBm, LO power = 0 dBm, R1 = 910 Ω, ZO = 50 Ω, optimum SPI settings, unless otherwise noted.

220

TA = –40°C

= +25°C

T

A

210

200

190

180

170

160

150

SUPPLY CURRENT (mA)

140

130

120

= +85°C

T

A

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

RF FREQUE NCY (MHz)

Figure 4. Supply Current vs. RF Frequency

10

TA = –40°C T

= +25°C

A

T

= +85°C

9

A

8

7

6

5

CONVERSIO N GAIN (dB)

4

3

2

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

RF FREQUE NCY (MHz)

Figure 5. Power Conversion Gain vs. RF Frequency

45

TA = –40°C T

= +25°C

A

T

= +85°C

A

40

35

30

25

INPUT IP3 (dBm)

20

15

10

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

RF FREQUENCY (MHz)

Figure 6. Input IP3 vs. RF Frequency

09912-004

09912-005

09912-006

90

TA = –40°C T

= +25°C

A

T

= +85°C

80

A

70

60

50

40

INPUT IP2 (dBm)

30

20

10

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

RF FREQUE NCY (MHz)

Figure 7. Input IP2 vs. RF Frequency

20

TA = –40°C T

= +25°C

A

18

T

= +85°C

A

16

14

12

10

8

INPUT P1dB (dBm)

6

4

2

0

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

RF FREQUENCY (MHz)

Figure 8. Input P1dB vs. RF Frequency

16

TA = –40°C

= +25°C

T

A

15

= +85°C

T

A

14

13

12

11

10

NOISE FIGURE (dB)

9

8

7

6

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

RF FREQ UENCY (MHz)

Figure 9. SSB Noise Figure vs. RF Frequency

09912-007

09912-008

09912-009

Rev. 0 | Page 7 of 28

ADL5811

235

RF = 1900MHz

225

215

205

195

185

175

165

SUPPLY CURRENT (mA)

155

145

135

–40 –30 –20 –10 01020304050607080

TEMPERAT URE (°C)

V

POS

V

POS

V

POS

Figure 10. Supply Current vs. Temperature

10.0

RF = 1900MHz

9.5

9.0

8.5

8.0

7.5

7.0

6.5

CONVERSION GAIN (dB)

6.0

5.5

5.0

–40 –30 –20 –10 0 1020304050607080

TEMPERATURE (°C)

V

POS

V

POS

V

POS

Figure 11. Power Conversion Gain vs. Temperature

35

RF = 1900MHz

33

31

29

27

25

23

INPUT IP3 (dBm)

21

19

17

15

–40 –30 –20 –10 0 1020304050607080

TEMPERATURE (°C)

V

POS

V

POS

V

POS

Figure 12. Input IP3 vs. Temperature

= 4.75V = 5.00V = 5.25V

09912-010

09912-011

09912-012

80

RF = 1900MHz

75

70

65

60

55

50

INPUT IP2 (dBm)

45

40

35

30

–40 –30 –20 –10 0 1020304050607080

TEMPERATURE (°C)

V

POS

V

POS

V

POS

Figure 13. Input IP2 vs. Temperature

20

RF = 1900MHz

18

16

14

12

10

INPUT P1dB (dBm)

8

6

4

–40 –30 –20 –10 0 1020304050607080

TEMPERATURE (°C)

V

POS

V

POS

V

POS

Figure 14. Input P1dB vs. Temperature

15

RF = 1900MHz

14

13

12

11

10

SSB NOISE FIGURE ( dB)

9

8

–40 –30 –20 –10 0 1020304050607080

TEMPERATURE (°C)

V

POS

V

POS

V

POS

Figure 15. SSB Noise Figure vs. Temperature

= 4.75V = 5.00V = 5.25V

09912-013

09912-014

09912-015

Rev. 0 | Page 8 of 28

ADL5811

200

195

TA = 25°C

RF = 900MHz RF = 1900MHz RF = 2500MHz

80

70

TA = 25°C

190

185

180

175

SUPPLY CURRENT (mA)

170

165

160

30 80 130 180 230 280 330 380 430

IF FREQUENCY (MHz)

Figure 16. Supply Current vs. IF Frequency

11

TA = 25°C

10

9

8

7

6

CONVERSION GAIN (dB)

5

RF = 900MHz RF = 1900MHz RF = 2500MHz

60

50

40

30

INPUT IP2 (dBm)

20

RF = 900MHz

10

RF = 1900MHz RF = 2500MHz

0

30 80 130 180 230 280 330 380 430

09912-016

IF FREQUENCY (MHz)

09912-019

Figure 19. Input IP2 vs. IF Frequency

18

TA = 25°C

16

14

12

10

8

INPUT P1dB (dBm)

6

4

RF = 900MHz RF = 1900MHz RF = 2500MHz

4

30 80 130 180 230 280 330 380 430

IF FREQUENCY (MHz)

Figure 17. Power Conversion Gain vs. IF Frequency

30

TA = 25°C

39

28

27

26

25

INPUT IP3 (dBm)

24

23

22

30 80 130 180 230 280 330 380 430

IF FREQUENCY (MHz)

RF = 900MHz RF = 1900MHz RF = 2500MHz

Figure 18. Input IP3 vs. IF Frequency

2

30 80 130 180 230 280 330 380 430

09912-017

IF FREQ UENCY (MHz)

09912-020

Figure 20. Input P1dB vs. IF Frequency

20

TA = 25°C

18

16

14

12

10

SSB NOISE FIGURE (dB)

8

6

4

30 80 130 180 230 280 330 380 430

09912-018

IF FREQ UENCY (MHz)

RF = 900MHz RF = 1900MHz RF = 2500MHz

09912-021

Figure 21. SSB Noise Figure vs. IF Frequency

Rev. 0 | Page 9 of 28

ADL5811

–

11

10

TA = 25°C

RF = 900MHz RF = 1900MHz RF = 2500MHz

20

18

TA = 25°C

RF = 900MHz RF = 1900MHz RF = 2500MHz

9

8

7

6

CONVERSION GAIN (dB)

5

4

3

–

6 –4 –20246810

LO POWER (dBm)

Figure 22. Power Conversion Gain vs. LO Power

35

TA = 25°C

33

31

29

27

25

23

INPUT IP3 (dBm)

21

19

17

15

–6–4–20246810

LO POWER (dBm)

RF = 900MHz RF = 1900MHz RF = 2500MHz

Figure 23. Input IP3 vs. LO Power

80

TA = 25°C

70

16

14

12

10

INPUT P1dB (dBm)

8

6

4

–6 –4 –20246810

09912-022

LO POWER (d Bm)

09912-025

Figure 25. Input P1dB vs. LO Power

40

TA = –40°C T

= +25°C

A

–45

T

= +85°C

A

–50

–55

–60

–65

–70

IF/2 SPURIOUS (dBc)

–75

–80

–85

–90

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

09912-023

RF FREQUENC Y (MHz)

09912-026

Figure 26. IF/2 Spurious vs. RF Frequency, RF Power = −10 dBm

55

TA = –40°C T

= +25°C

A

T

= +85°C

A

–60

60

50

40

INPUT IP2 (dBm)

30

20

RF = 900MHz RF = 1900MHz RF = 2500MHz

10

–

6 –4 –20 2 4 6 810

LO POWER (dBm)

Figure 24. Input IP2 vs. LO Power

09912-024

–65

–70

–75

IF/3 SPURIOUS (dBc)

–80

–85

–90

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

RF FREQUE NCY (MHz)

Figure 27. IF/3 Spurious vs. RF Frequency, RF Power = −10 dBm

09912-027

Rev. 0 | Page 10 of 28

ADL5811

100

80

MEAN: 7.5 SD: 0.12%

500

400

TA = 25°C

RF = 900MHz RF = 1900MHz RF = 2500MHz

10

8

PERCENTAGE (%)

60

40

20

0

100

80

60

40

20

0

100

80

7.57.3 7.7 7.97.1

CONVERSION GAIN (dB)

Figure 28. Conversion Gain Distribution

MEAN: 27.5 SD: 0.36%

27.525.5 29.5 31.523.5

INPUT IP3 (dBm)

Figure 29. Input IP3 Distribution

MEAN: 11.68 SD: 0.36%

300

200

RESISTANCE ( )

100

0

80 130 180 230 280 330 380 43030

09912-028

IF FREQUENCY (MHz)

6

4

CAPACITANCE (pF )

2

0

09912-031

Figure 31. IF Output Impedance (R Parallel C Equivalent)

0

TA = +25°C

–5

–10

–15

–20

–25

–30

RF PORT RET URN LOSS (dB)

–35

–40

700 900 1100 1300 1500 1700 1900 2100 2300 2500

09912-029

RF FREQUENCY (MHz)

2700

09912-032

Figure 32. RF Port Return Loss, Fixed IF vs. RF Frequency

0

TA = 25°C

–3

–6

60

40

PERCENTAGE (%)

20

0

10.5 11.0 11.5 12.0 12.5

INPUT P1dB (dBm)

Figure 30. Input P1dB Distribution

09912-030

Rev. 0 | Page 11 of 28

–9

–12

–15

LO RETURN L OSS (dB)

–18

–21

–24

500 700 900 1100 1300 1500 1700 1900 2100 2300 2500

LO FREQUENCY (MHz)

Figure 33. LO Return Loss

09912-033

ADL5811

A

–

0

TA = –40°C

= +25°C

T

A

= +85°C

T

–10

A

–20

–30

TION (dB)

–40

–50

RF-TO-IF ISOL

–60

–70

2XLO LEAKAGE (dBm)

–10

–20

–30

–40

–50

–60

0

2LO-TO-IF 2LO-TO-RF

TA = 25°C

–80

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

RF FREQUENCY (MHz)

Figure 34. RF-to-IF Isolation vs. RF Frequency

0

TA = –40°C T

= +25°C

A

T

= +85°C

–10

A

–20

–30

–40

–50

LO-TO-IF LEAKAGE ( dBm)

–60

–70

–80

500 700 900 1100 1300 1500 1700 1900 2100 2300 2500

LO FRE QUENCY (MHz)

Figure 35. LO-to-IF Leakage vs. LO Frequency

0

TA = –40°C T

= +25°C

A

T

= +85°C

–10

A

–20

–30

–40

–50

–60

LO-TO-RF LEAKAGE (d Bm)

–70

–80

500 700 900 1100 1300 1500 1700 1900 2100 2300 2500

LO FRE QUENCY (MHz)

Figure 36. LO-to-RF Leakage vs. LO Frequency

–70

500 700 900 1100 1300 1500 1700 1900 2100 2300 2500

09912-034

LO FREQ UENCY (MHz)

09912-037

Figure 37. 2XLO Leakage vs. LO Frequency

10

3LO-TO-IF 3LO-TO-RF

–20

–30

–40

–50

3XLO LE AKAGE (dBm)

–60

–70

–80

500 700 900 1100 1300 1500 1700 1900 2100 2300 2500

09912-035

LO FREQ UENCY (MHz)

TA = 25°C

09912-038

Figure 38. 3XLO Leakage vs. LO Frequency

14

TA = +25°C

13

12

NOISE FI GURE

11

10

9

8

7

CONVERSIO N GAIN (dB)

6

5

VGS = 0 VGS = 1

4

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

09912-036

GAIN

VGS = 2

VGS = 4

VGS = 3

VGS = 5

RF FREQUE NCY (MHz)

VGS = 6 VGS = 7

16

15

14

13

12

11

10

9

SSB NOISE F IGURE (d B)

8

7

09912-0139

Figure 39. Power Conversion Gain and SSB Noise Figure vs. RF Frequency

for All VGS Settings

Rev. 0 | Page 12 of 28

ADL5811

35

VGS = 0

VGS = 2

VGS = 4

VGS = 1

VGS = 3

30

INPUT IP3

25

20

15

INPUT IP3 (dBm)

10

5

INPUT P1dB

0

700 900 1100 1300 1500 1700 1900 2100 2300 2500 27 00

RF FREQUE NCY (MHz)

VGS = 5

VGS = 6 VGS = 7

TA = +25°C

Figure 40. Input IP3 and Input P1dB vs. RF Frequency for All VGS Settings

35

RF = 900MHz RF = 1900MHz RF = 2500MHz

30

25

20

15

10

SSB NOISE FIGURE (dB)

5

0

–30 –25 –20 –15 –10 –50 510

BLOCKER POW ER (dBm)

TA = +25°C

Figure 41. SSB Noise Figure vs. 10 MHz Offset Blocker Level

27

24

21

18

15

INPUT P1dB (dBm)

12

9

6

09912-140

240

TA = 25°C

220

200

180

160

140

SUPPLY CURRENT (mA)

120

100

600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800

IF BIAS RESISTOR VALUE ()

RF = 900MHz RF = 1900MHz RF = 2500MHz

09912-042

Figure 42. Supply Current vs. IF Bias Resistor Value

20

TA = 25°C

18

16

14

12

10

8

6

CONVERSIO N GAIN AND SSB NOI SE FIG URE (dB)

4

600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1 800

09912-141

INPUT IP3

NOISE F IGURE

GAIN

IF BIAS RESISTOR VALUE ()

RF = 900MHz RF = 1900MHz RF = 2500MHz

32

28

24

20

16

12

INPUT IP3 (dBm)

8

4

0

09912-043

Figure 43. Power Conversion Gain, SSB Noise Figure, and Input IP3 vs.

IF Bias Resistor Value

Rev. 0 | Page 13 of 28

ADL5811

11

RFB = 0 RFB = 1 RFB = 2

10

RFB = 3 RFB = 4

9

RFB = 5 RFB = 6 RFB = 7

8

7

6

5

4

CONVERSION GAIN (dB)

3

2

1

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

RF FREQUENCY (MHz)

TA = +25°C

Figure 44. Conversion Gain vs. RF Frequency for All RFB Settings

32

RFB = 0 RFB = 1

31

RFB = 2 RFB = 3 RFB = 4

30

RFB = 5 RFB = 6 RFB = 7

29

28

27

26

INPUT IP3 (dBm)

25

24

23

22

700 900 1100 1300 1500 1700 1900 2100 2300 2500 270 0

RF FREQUE NCY (MHz)

TA = +25°C

Figure 45. Input IP3 vs. RF Frequency for All RFB Settings

09912-044

09912-045

18

RFB = 0 RFB = 1 RFB = 2

17

RFB = 3 RFB = 4

16

RFB = 5 RFB = 6 RFB = 7

15

14

13

12

INPUT P1dB (dBm)

11

10

9

8

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

RF FREQ UENCY (MHz)

TA = +25°C

Figure 46. Input P1dB vs. RF Frequency for All RFB Settings

16

RFB = 0 RFB = 1 RFB = 2

15

RFB = 3 RFB = 4

14

RFB = 5 RFB = 6 RFB = 7

13

12

11

10

9

SSB NOISE F IGURE (d B)

8

7

6

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

RF FREQUENCY (MHz)

TA = +25°C

Figure 47. SSB Noise Figure vs. RF Frequency for All RFB Settings

09912-046

09912-047

Rev. 0 | Page 14 of 28

ADL5811

12

LPF = 0 LPF = 1 LPF = 2

10

LPF = 3

8

6

4

2

CONVERSION GAIN (dB)

0

RFB0

RFB7

TA = +25°C

21

LPF = 0 LPF = 1 LPF = 2

19

LPF = 3

17

15

13

11

INPUT P1dB (dBm)

9

7

RFB0

TA = +25°C

RFB7

–2

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

RF FREQUENCY (MHz)

Figure 48. Conversion Gain vs. RF Frequency for All LPF Settings at

RFB7 and RFB0

35

TA = +25°C

33

31

29

27

25

23

INPUT IP3 (dBm)

21

19

LPF = 0 LPF = 1

17

LPF = 2 LPF = 3

15

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

RF FREQ UENCY (MHz)

RFB0

RFB7

Figu re 49. Input I P3 vs. RF Frequency for All LPF Settings at RFB7 and RFB0

5

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

09912-048

RF FREQUENCY (MHz)

09912-050

Figure 50. Input P1dB vs. RF Frequency for All LPF Settings at RFB7 and RFB0

20

LPF = 0 LPF = 1

18

LPF = 2 LPF = 3

16

14

12

10

8

SSB NOISE FIGURE (dB)

6

4

2

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

09912-049

RFB7

RF FREQUENCY (MHz)

RFB0

TA = +25°C

09912-051

Figure 51. SSB Noise Figure vs. RF Frequency for

All LPF Settings at RFB7 and RFB0

Rev. 0 | Page 15 of 28

ADL5811

3.6 V PERFORMANCE

VS = 3.6 V, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, RF power = −10 dBm, LO power = 0 dBm, R1 = 800 Ω, ZO = 50 Ω, optimum SPI settings, unless otherwise noted.

150

140

130

TA = –40°C T

= +25°C

A

T

= +85°C

A

80

70

60

TA = –40°C T

= +25°C

A

T

= +85°C

A

120

110

100

SUPPLY CURRENT (mA)

90

80

70

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

RF FREQUENCY (MHz)

Figure 52. Supply Current vs. RF Frequency at 3.6 V

14

TA = –40°C T

= +25°C

A

T

= +85°C

A

12

10

8

6

4

CONVERSIO N GAIN (dB)

2

0

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

RF FREQUENCY (MHz)

Figure 53. Power Conversion Gain vs. RF Frequency at 3.6 V

35

TA = –40°C T

= +25°C

A

T

= +85°C

A

30

25

20

15

INPUT IP3 (dBm)

10

5

50

40

30

INPUT IP2 (dBm)

20

10

0

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

09912-052

RF FREQUENCY (MHz)

09912-055

Figure 55. Input IP2 vs. RF Frequency at 3.6 V

24

TA = –40°C T

= +25°C

A

T

= +85°C

21

A

18

15

12

9

INPUT P1dB (dBm)

6

3

0

700 900 1100 1300 1500 1700 1900 2100 2300 2500 270 0

09912-053

RF FREQUENCY (MHz)

09912-056

Figure 56. Input P1dB vs. RF Frequency at 3.6 V

24

TA = –40°C T

= +25°C

A

T

= +85°C

21

A

18

15

12

9

SSB NOISE F IGURE (dB)

6

3

0

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

RF FREQUENCY (MHz)

Figure 54. Input IP3 vs. RF Frequency at 3.6 V

09912-054

0

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

RF FREQUENCY (MHz)

Figure 57. SSB Noise Figure vs. RF Frequency at 3.6 V

09912-057

Rev. 0 | Page 16 of 28

ADL5811

SPURIOUS PERFORMANCE

(N × fRF) − (M × fLO) spur measurements were made using the standard evaluation board. Mixer spurious products are measured in dBc from the IF output power level. Data was measured only for frequencies less than 6 GHz. Typical noise floor of the measurement system = −100 dBm.

5 V Performance

VS = 5 V, TA = 25°C, RF power = −10 dBm, LO power = 0 dBm, R1 = 910 Ω, ZO = 50 Ω, optimum SPI settings, unless otherwise noted.

Table 5. RF = 900 MHz, LO = 697 MHz

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 −54.2 −31.4 −41.5 −29.4 −58.5 −49.3 −70.5 −52.9 1 −37.8 0.0 −38.7 −19.6 −51.6 −38.0 −62.9 −52.4 −70.2 −57.9 2 −65.0 −54.4 −69.6 −53.4 −72.5 −82.3 −93.5 −97.4 −93.0 −98.8 <−100 <−100 3 −94.0 −86.7 <−100 −91.0 <−100 −95.3 <−100 <−100 <−100 <−100 <−100 <−100 <−100 4 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 5 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 6 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 7 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100

N

8 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 9 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 10 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 11 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 12 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 13 <−100 <−100 <−100 <−100 <−100 <−100 <−100 14 <−100 <−100 <−100 <−100 <−100 <−100 15 <−100 <−100 <−100 <−100 <−100

M

Table 6. RF = 1900 MHz, LO = 1697 MHz

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 −34.9 −30.7 −66.0 1 −33.2 0.0 −56.6 −51.3 −77.8 2 −75.0 −78.5 −71.5 −85.2 −80.3 <−100 3 <−100 <−100 <−100 −89.5 −94.8 <−100 <−100 4 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 5 <−100 <−100 <−100 <−100 <−100 <−100 <−100 6 <−100 <−100 <−100 <−100 <−100 <−100 <−100 7 <−100 <−100 <−100 <−100 <−100 <−100 <−100

N

8 <−100 <−100 <−100 <−100 <−100 <−100 <−100 9 <−100 <−100 <−100 <−100 <−100 <−100 <−100 10 <−100 <−100 <−100 <−100 <−100 <−100 <−100 11 <−100 <−100 <−100 <−100 <−100 <−100 <−100 12 <−100 <−100 <−100 <−100 <−100 <−100 13 <−100 <−100 <−100 <−100 14 <−100 <−100 <−100 15 <−100 <−100

M

Rev. 0 | Page 17 of 28

ADL5811

Table 7. RF = 2500 MHz, LO = 2297 MHz

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 −28.6 −45.7 1 −32.5 0.0 −53.0 −52.4 2 −91.2 −82.8 −60.5 −80.8 −97.3 3 <−100 <−100 −87.7 <−100 <−100 4 <−100 <−100 <−100 <−100 <−100 5 <−100 <−100 <−100 <−100 <−100 <−100 6 <−100 <−100 <−100 <−100 <−100 <−100 7 <−100 <−100 <−100 <−100 <−100

N

8 <−100 <−100 <−100 <−100 <−100 9 <−100 <−100 <−100 <−100 <−100 10 <−100 <−100 <−100 <−100 <−100 11 <−100 <−100 <−100 <−100 <−100 12 <−100 <−100 <−100 <−100 <−100 13 <−100 <−100 <−100 <−100 14 <−100 <−100 <−100 15 <−100 <−100

3.6 V Performance

VS = 3.6 V, TA = 25°C, RF power = −10 dBm, LO power = 0 dBm, R1 = 800 Ω, ZO = 50 Ω, optimum SPI settings, unless otherwise noted.

M

Table 8. RF = 900 MHz, LO = 697 MHz

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 −45.5 −35.1 −44.1 −30.2 −49.9 −48.7 −66.6 −66.5 1 −41.0 0.0 −37.3 −18.9 −54.8 −40.4 −62.4 −53.2 −73.0 −66.8 2 −59.2 −54.7 −78.2 −54.8 −62.8 −83.1 −78.3 −96.1 −79.5 −96.2 −96.2 <−100 3 −90.0 −81.9 <−100 −73.9 −89.6 −79.4 <−100 −95.3 <−100 <−100 <−100 <−100 <−100 4 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 5 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 6 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 7 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100

N

8 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 9 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 10 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 11 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 12 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 13 <−100 <−100 <−100 <−100 <−100 <−100 <−100 14 <−100 <−100 <−100 <−100 <−100 <−100 15 <−100 <−100 <−100 <−100 <−100

M

Rev. 0 | Page 18 of 28

ADL5811

Table 9. RF = 1900 MHz, LO = 1697 MHz

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 −46.6 −30.5 −78.5 1 −33.4 0.0 −57.0 −53.8 −79.5 2 −68.9 −77.2 −69.2 −72.8 −75.2 <−100 3 <−100 <−100 <−100 −74.4 −94.0 <−100 <−100 4 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 5 <−100 <−100 <−100 <−100 <−100 <−100 <−100 6 <−100 <−100 <−100 <−100 <−100 <−100 <−100 7 <−100 <−100 <−100 <−100 <−100 <−100 <−100

N

8 <−100 <−100 <−100 <−100 <−100 <−100 <−100 9 <−100 <−100 <−100 <−100 <−100 <−100 <−100 10 <−100 <−100 <−100 <−100 <−100 <−100 <−100 11 <−100 <−100 <−100 <−100 <−100 <−100 <−100 12 <−100 <−100 <−100 <−100 <−100 <−100 13 <−100 <−100 <−100 <−100 14 <−100 <−100 <−100 15 <−100 <−100

Table 10. RF = 2500 MHz, LO = 2297 MHz

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 −30.0 −51.1 1 −32.1 0.0 −53.6 −51.7 2 −89.0 −78.0 −65.5 −72.9 −88.2 3 <−100 <−100 −73.5 <−100 <−100 4 <−100 <−100 <−100 <−100 <−100 5 <−100 <−100 <−100 <−100 <−100 <−100 6 <−100 <−100 <−100 <−100 <−100 <−100 7 <−100 <−100 <−100 <−100 <−100

N

8 <−100 <−100 <−100 <−100 <−100 9 <−100 <−100 <−100 <−100 <−100 10 <−100 <−100 <−100 <−100 <−100 11 <−100 <−100 <−100 <−100 <−100 12 <−100 <−100 <−100 <−100 <−100 13 <−100 <−100 <−100 <−100 14 <−100 <−100 <−100 15 <−100 <−100

M

Rev. 0 | Page 19 of 28

ADL5811

CIRCUIT DESCRIPTION

The ADL5811 consists of two primary components: the RF subsystem and the LO subsystem. The combination of design, process, and packaging technology allows the functions of these subsystems to be integrated into a single die, using mature packaging and interconnection technologies to provide a high performance device with excellent electrical, mechanical, and thermal properties. The wideband frequency response and flexible frequency programming simplifies the receiver design, saves on-board space, and minimizes the need for external components.

The RF subsystem consists of an integrated, tunable, low loss RF balun; a double balanced, passive MOSFET mixer; a tunable sum termination network; and an IF amplifier.

The LO subsystem consists of a multistage limiting LO amplifier. The purpose of the LO subsystem is to provide a large, fixed amplitude, balanced signal to drive the mixer independent of the level of the LO input. A block diagram of the device is shown in Figure 58.

VPIF

IFGM

NC

IFOP

IFON

NC

IFGD

COMM

24

NC

23

NC

22

NC

21

LOIP

20

LOIN

19

LE

18

DATA

17

CLK

VLO1

COMM

09912-162

NC

RFCT

NC

RFIN

NC

30 29 28 27 26 2532 31

1

2

3

4

5

6

BIAS

7

GEN

8

11 12 13 14 15 169 10

VLO4

VLO3

COMM

Figure 58. Block Diagram

SERIAL

INTERFACE

VLO2

COMM

ADL5811

PORT

RF SUBSYSTEM

The single-ended, 50 Ω RF input is internally transformed to a balanced signal using a tunable, low loss, unbalanced-to-balanced (balun) transformer. This transformer is made possible by an extremely low loss metal stack, which provides both excellent balance and dc isolation for the RF port. Although the port can be dc connected, it is recommended that a blocking capacitor be used to avoid running excessive dc current through the part. The RF balun can easily support an RF input frequency range of 700 MHz to 2800 MHz. This balun is tuned over the frequency range by SPI controlled switched capacitor networks at the input and output of the RF balun.

The resulting balanced RF signal is applied to a passive mixer that commutates the RF input in accordance with the output of the LO subsystem. The passive mixer is essentially a balanced, low loss switch that adds minimum noise to the frequency translation. The only noise contribution from the mixer is due to the resistive loss of the switches, which is in the order of a few ohms.

Because the mixer is inherently broadband and bidirectional, it is necessary to properly terminate all idler (M × N product) frequencies generated by the mixing process. Terminating the mixer avoids the generation of unwanted intermodulation products and reduces the level of unwanted signals at the input of the IF amplifier, where high peak signal levels can compromise the compression and intermodulation performance of the system. This termination is accomplished by the addition of a programmable low-pass filter network between the IF amplifier and the mixer and in the feedback elements in the IF amplifier.

The IF amplifier is a balanced feedback design that simultaneously provides the desired gain, noise figure, and input impedance that is required to achieve the overall performance. The balanced open-collector output of the IF amplifier, with an impedance modified by the feedback within the amplifier, permits the output to be connected directly to a high impedance filter, a differential amplifier, or an analog-to-digital converter (ADC) input while providing optimum second-order intermodulation suppression. The differential output impedance of the IF amplifier is approximately 200 Ω. If operation in a 50 Ω system is desired, the output can be transformed to 50 Ω by using a 4:1 transformer or an LC impedance matching network.

The intermodulation performance of the design is generally limited by the IF amplifier. The IP3 performance can be optimized by adjusting the low-pass filter between the mixer and the IF amplifier. Further optimization can be made by adjusting the IF current with an external resistor.

Figure 42 and Figure 43 illustrate how various IF resistors affect the performance with a 5 V supply. Additionally, dc current can be saved by increasing the IF resistor. It is permissible to reduce the IF amplifier’s dc supply voltage to as low as 3.3 V, further reducing the dissipated power of the part. (Note that no performance enhancement is obtained by reducing the value of these resistors, and excessive dc power dissipation may result.)

Because the mixer is bidirectional, the tuning of the RF and IF ports is linked and it is possible for the user to optimize gain, noise figure, IP3, and impedance match via the SPI. This feature permits high performance operation and is achieved entirely using SPI control. Additionally, the performance of the mixer can be improved by setting the optimum gate voltage on the passive mixer, which is also controlled by the SPI to enable optimum performance of the part. See the Applications Information section for examples of this tuning.

Rev. 0 | Page 20 of 28

ADL5811

LO SUBSYSTEM

The LO amplifier is designed to provide a large signal level to the mixer to obtain optimum intermodulation and compression performance. The resulting LO amplifier provides very high performance over a wide range of LO input frequencies.

The ideal waveshape for switching the passive mixer is a square wave at the LO frequency to cause the mixer to switch through its resistive region (from on to off and off to on) as rapidly as possible. While it has always been possible to generate such a square wave, the amount of dc current required to generate a large amplitude square wave at high frequencies has made it impractical to create such a mixer. Novel circuitry within the

ADL5811 permits the generation of a near-square wave output

at frequencies of up to 2800 MHz with dc current that compares favorably with that employed by narrow-band passive mixers.

The input stages of the LO amplifier provide common-mode rejection, permitting the LO input to be driven either single ended or balanced. For a single-ended input, either LOIP or LOIN can be grounded. It is desirable to dc block the LO inputs to avoid damaging the part by the accidental application of a large dc voltage to the part. In addition, the LO inputs are internally dc blocked.

Because the LO amplifier is inherently wideband, the ADL5811 can be driven with either high-side or low-side LO by simply setting the optimum RF balun and LPF inputs to the SPI.

The LO amplifier converts a variable level, single or balanced input signal (−6 dBm to +10 dBm) to a hard voltage limited, balanced signal internally to drive the mixer. Excellent performance can be

obtained with a 0 dBm input level; however, the circuit continues to function at considerably lower levels of LO input power.

The performance of this amplifier is critical in achieving a high intercept passive mixer without degrading the noise floor of the system. This is a critical requirement in an interferer rich environment, such as cellular infrastructure, where blocking interferers can limit mixer performance. Blocking dynamic range can benefit from a higher level of LO drive, which pushes the LO amplifier stages harder into compression and causes them to switch harder and to limit the small signal gain of the chain. Both of these conditions are beneficial to low noise figure under blocking. NF under blocking can be improved several decibels for LO input power levels above 0 dBm.

The LO amplifier topology inherently minimizes the dc current based on the LO operating voltage and the LO operating frequency. It is permissible to reduce the LO supply voltage down as low as

3.6 V, which drops the dc current rapidly. The mixer dynamic range varies accordingly with the LO supply voltage. No external biasing resistor is required for optimizing the LO amplifier.

In addition, the ADL5811 has a power-down mode that can be used with any supply voltage applied to the part.

All of the SPI inputs are designed to work with any logic family that provides a Logic 0 input level of less than 0.4 V and a Logic 1 input level that exceeds 1.4 V.

All pins, including the RF pins, are ESD protected and have been tested up to a level of 2000 V HBM and 1250 V CDM.

Rev. 0 | Page 21 of 28

ADL5811

APPLICATIONS INFORMATION

BASIC CONNECTIONS

The ADL5811 mixer is designed to downconvert radio frequencies (RF) primarily between 700 MHz and 2800 MHz to lower intermediate frequencies (IF) between 30 MHz and 450 MHz. Figure 59 depicts the basic connections of the mixer. It is recommended to ac couple RF and LO input ports to prevent nonzero dc voltages from damaging the RF balun or LO input circuit. A RFIN capacitor value of 22 pF is recommended.

IF PORT

The mixer differential IF interface requires pull-up choke inductors to bias the open-collector outputs and to set the output match. The shunting impedance of the choke inductors used to couple dc current into the IF amplifier should be selected to provide the desired output return loss.

The real part of the output impedance is approximately 200 Ω, as seen in Figure 31, which matches many commonly used SAW filters without the need for a transformer. This results in a voltage conversion gain that is approximately 6 dB higher than the power conversion gain. When a 50 Ω output impedance is needed, use a 4:1 impedance transformer, as shown in Figure 59.

L1

C8

0.1µF

C2

0.1µF

C7

100pF

C6

22pF

470nH

L2

470nH

R1

910

PAD

32313029282726

PAD

1

NC

2

RFCT

3

NC

4

RFIN

5

NC

6

NC

7

NC

8

NC

VCC

C1

0.1µF

RFIN

VPIF

IFGM

ADL5811

BIAS RESISTOR SELECTION

An external resistor, R1, is used to adjust the bias current of the integrated amplifier at the IF terminal. It is necessary to have a sufficient amount of current to bias both the internal IF amplifier to optimize dc current vs. optimum input IP3 performance. Figure 42 and Figure 43 provide the reference for the bias resistor selection when lower power consumption is considered at the expense of conversion gain and input IP3 performance.

VGS PROGRAMMING

The ADL5811 allows programmability for internal gate-to-source voltages for optimizing mixer performance over the desired frequency bands. The ADL5811 defaults the VGS setting to 0. Power conversion gain, input IP3, NF, and input P1dB can be optimized, as shown in Figure 39 and Figure 40.

C3

NC

IFOP

120pF

C4

120pF

IFONNCIFGD

T1

TC4-1W+

C5 120pF

25

COMM

NC NC

NC LOIP LOIN

LE

DATA

CLK

24 23 22 21 20 19 18 17

R20 OPEN

R21 0

LE DATA CLK

IFOP

IFON

C17

22pF

LOIP

VLO4

COMM

VLO3

COMM

VLO2

COMM

VOL1

9

VCC

C23

10pF

VPOSAGND

RE

K

DBL

VCC

10111213141516

VCC

C20 10pF

COMM

VCC

C19 10pF

VCC

C18 10pF

09912-163

Figure 59. Basic Connections

Rev. 0 | Page 22 of 28

ADL5811

LOW-PASS FILTER PROGRAMMING

The ADL5811 allows programmability for the low-pass filter terminating the mixer output. This filter helps to block sum term mixing products at the expense of some noise figure and gain and can significantly increase input IP3. The ADL5811 defaults the LPF setting to 0. Power conversion gain, input IP3, NF, and input P1dB can be optimized, as shown in Figure 48 to Figure 51.

RF BALUN PROGRAMMING

The ADL5811 allows programmability for the RF balun by allowing capacitance to be switched into both the input and the output, which allows the balun to be tuned to cover the entire frequency band (700 MHz to 2800 MHz). Under most circumstances, the input and output can be tuned together though sometimes it may be advantageous for matching reasons to tune them separately. The ADL5811 defaults the RFB setting to 0. Power conversion gain, input IP3, NF, and input P1dB can be optimized, as shown in Figure 44 to Figure 47.

Rev. 0 | Page 23 of 28

ADL5811

REGISTER STRUCTURE

Figure 60 illustrates the register map of the ADL5811. The

ADL5811 only uses Register 5. Because of this, set all of the

control bits to 5. When set to 0, the ENBL bit, DB7, enables the part. By setting this bit to 1, the mixer is powered down. The RFB IN CAP DAC and RFB OUT CAP DAC bits are used to tune the RF balun. In most cases, they are tuned together with the higher settings, 7, tuning for the low frequencies, and with the lower settings, 0, tuning for the high frequencies. There are times where it becomes advantageous to tune the input and output of the RF balun separately and that ability is provided.

The LPF bits control the low-pass filter settings at the IF output. The ability to tune the low-pass filter allows some trade-off between gain, noise figure, and input IP3 with higher settings, 7, providing higher input IP3 at the cost of some gain and noise figure, and lower settings, 0, providing higher gain and lower NF at the cost of lower input IP3. The VGS bits control the VGS settings of the mixer core and allow further tuning of the device.

Tabl e 1 1 lists the optimum settings characterized for each frequency band. All register bits default to 0.

RESERVED CONTROL BITSVGS LPF RFB OUT CAP DAC RFB IN CAP DAC RESERVED

DB23 DB22 D B21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 VGS2 VGS1 VGS 0 LPF1 LPF 0 0 CDO2 DCDO1 CDO0 0 CDI2 CDI1 CDI0 0 EN 0 0 0 0 C3(1) C2(0) C1(1)

VGS2 VGS1 VGS0 VGS SETTING

000 0

''' '

111 7

LPF1 LPF0 LOW PASS FILTER SETTING

00 0

'' '

11 3

CDO2 CDO1 CDO0 RF BALUN O UTPUT T UNING

000 0

''' '

111 7

Figure 60. ADL5811 Register Maps

CDI2 CDI1 CDI0 RF BALUN I NTPUT T UNING

000 0

''' '

111 7

ENBL

MEN MAIN ENABLE

0 DEVICE ENABLED 1 DEVICE DI SABLED

09912-160

Table 11. Optimum Settings

RF Frequency (MHz) LO Frequency (MHz) VGS LPF RFB OUT CAP DAC RFB IN CAP DAC

700 497 3 1 7 7 800 597 1 1 6 6 900 697 2 1 6 6 1000 797 1 1 4 4 1100 897 3 1 7 7 1200 997 3 3 5 5 1300 1097 3 3 5 5 1400 1197 3 3 4 4 1500 1297 3 3 4 4 1600 1397 3 3 3 3 1700 1497 3 3 3 3 1800 1597 3 3 3 3 1900 1697 3 3 2 2 2000 1797 3 3 2 2 2100 1897 3 3 1 1 2200 1997 2 3 2 2 2300 2097 3 2 2 2 2400 2197 2 2 2 2 2500 2297 3 3 1 1 2600 2397 3 2 2 2 2700 2497 1 2 2 2 2800 2597 3 2 1 1

Rev. 0 | Page 24 of 28

ADL5811

VCC

EVALUATION BOARD

An evaluation board is available for the ADL5811. The standard evaluation board schematic is presented in Figure 61. The USB interface circuitry schematic is presented in Figure 64. The evaluation board layout is shown in Figure 62 and Figure 63.

L1

470nH

C8

0.1µF

C2

0.1µF

C7

100pF

C6

22pF

L2

470nH

910

PAD

1

NC

2

RFCT

3

NC

4

RFIN

5

NC

6

NC

7

NC

8

NC

C1

0.1µF

RFIN

R1

32313029282726

PAD

VPIF

IFGM

ADL5811

The evaluation board is fabricated using Rogers® 3003 material. Tabl e 12 details the configuration for the mixer characterization. The evaluation board software is available on www.analog.com.

C3

NC

IFOP

120pF

C4

120pF

IFONNCIFGD

T1

TC4-1W+

3

2 1

C5 120pF

25

COMM

NC NC

NC LOIP LOIN

LE

DATA

CLK

4

6

24 23 22 21 20 19 18 17

R20 OPEN

R21 0

LE DATA CLK

IFOP

IFON

C17

22pF

LOIP

VLO4

COMM

VLO3

COMM

VLO2

COMM

VOL1

9

VCC

C23

10pF

VPOSAGND

REDBLK

VCC

10111213141516

VCC

C20 10pF

COMM

VCC

C19 10pF

VCC

C18 10pF

09912-060

Figure 61. Evaluation Board Schematic

Table 12. Evaluation Board Configuration

Components Description Default Conditions

C1, C2, C8, C18, C19, C20, C23

Power supply decoupling. Nominal supply decoupling consists of a

0.1 μF capacitor to ground in parallel with a 10 pF capacitor to

C1, C2 = 0.1 μF (size 0402), C8, C18, C19, C20, C23 = 10 pF (size 0402)

ground positioned as close to the device as possible.

C6, C7, RFIN

RF input interface. The input channel is ac-coupled through C6.

C6 = 22 pF (size 0402), C7 = 100 pF (size 0402)

C7 provides bypassing for the center tap of the RF input balun.

C3, C4, C5, L1, L2, R20, R21, T1, IFOP, IFON

IF output interface. The open-collector IF output interfaces are biased through pull-up choke inductors, L1 and L2. T1 is a 4:1 impedance transformer used to provide a single-ended IF output interface, with C5 providing center-tap bypassing. Remove R21 for balanced output operation.

C3, C4, C5 = 120 pF (size 0402), L1, L2 = 470 nH (size 0603), R20 = open, R21 = 0 Ω (size 0402),

T1 = TC4-1W+ (Mini-Circuits®) C17, LOIP LO interface. C17 provides ac coupling for the LOIP local oscillator input. C17 = 22 pF (size 0402) R1 Bias control. R1 sets the bias point for the internal IF amplifier. R1 = 910 Ω (size 0402)

Rev. 0 | Page 25 of 28

ADL5811

09912-062

Figure 62. Evaluation Board Top Layer

Figure 63. Evaluation Board Bottom Layer

09912-063

Rev. 0 | Page 26 of 28

ADL5811

Y

U7

8

VCC

1

A0

2

A1

3

A2

SCL SDA

7

WC_N

GND

4

DGND

R9

100K

C38

0.1UF 0.1UF

DGND

0.1UF

56

C34

10PF C35

100K

3V3_USB

DGND

R10

C39

C36

10PF C37

DGND

0.1UF

7

3

AVCC

15

SCL

16

SDA

5

XTALIN

42

RESET_N

44

WAKE U P

14

RESERVED

1

RDY0_SLRD

2

RDY1_SLWR

DGND

AGND

6

10

DGND

3V3_USB

R7 R8 2K 2K

3V3_USB

24LC64-I-SN

24.000000MHZ

1

C40 22PF

DGND

3V3_USB

17

11

27

VCC

CTL0_FLAGA CTL1_FLAGB CTL2_FLAGC

PA0_INT0_N PA1_INT1_N

PA4_FIFOADR0 PA5_FIFOADR1

PA6_PKTEND

PA7_FLAGD_SLCS_N

GND

12

CASE

24

XTALOUT

DMINUS

IFCLK

CLKOUT

PA2_SLOE

PA3_WU2

PB0_FD0 PB1_FD1 PB2_FD2 PB3_FD3 PB4_FD4 PB5_FD5 PB6_FD6 PB7_FD7 PD0_FD8

PD1_FD9 PD2_FD10 PD3_FD11 PD4_FD12 PD5_FD13 PD6_FD14 PD7_FD15

5653412826

2

DGND

554332

DPLUS

PAD

3

C41

22PF

DGND

U6

4 8 9

13 54 29 30 31

33 34 35 36 37 38 39 40

18 19 20 21 22 23 24 25 45 46

DGND

47 48 49 50 51 52

CY7C68013A-56LTXC

5V_USB

J6

1

2 3 4 5

G1 G2

GND PINS

G3 G4

897-43-005-00-100001

DGND

R11

0

R12

0

R13

0

C49

R14

TBD0402

1K

DNI

DGND DGND DGND DGND DGND DGND

C50

R15

TBD0402

1K

330PF330PF

DNI

P1

1

2 3

SAMTECTSW10608GS3PIN

R17

R18

R19

C51

R16

1K

TBD0402

330PF

DNI

LE

0

DATA

0

CLK

0

5V_USB

7 8 6

PAD

DGND

ADP3334ACPZ

U5

IN1

IN2 OUT2

SD_N PADFBGND

OUT1

5

R3

0

AGND

DGND

R4 2K

A

D1

C

DGND

C31

1.0UF

DGND

SML-210MTT86

3V3_USB

3P3V

1

ORG

DNI

C33

C32

1000PF

1

2 3

R5

78.7K

DGND

R6

140K

1.0UF

DGND

DGND BLK

1

DNI

DGND

3V3_USB

DECOUPLING FOR U6

DGND

C48C46 C47C44 C45C42 C43

0.1UF0.1UF0.1UF0.1UF0.1UF0.1UF0.1UF

09912-161

Figure 64. USB Interface Circuitry on the Evaluation Board

Rev. 0 | Page 27 of 28

ADL5811

C

OUTLINE DIMENSIONS

INDI

PIN 1

ATO R

5.10

5.00 SQ

4.90

0.50

BSC

24

0.30

0.25

0.18

25

EXPOSED

PAD

1

P

N

32

I

A

R

O

T

N

D

C

I

1

3.45

3.30 SQ

3.15

0.80

0.75

0.70

SEATING

PLANE

0.50

0.40

0.30

0.05 MAX

0.02 NOM COPLANARIT Y

0.20 REF

COMPLI ANT TO JE DEC STANDARDS M O-220-W HHD.

17

BOTTOM VIEWTOP VIEW

0.08

8

916

0.25 MIN

FOR PROP ER CONNECTI ON OF THE EXPOSED PAD, REFER TO THE PIN CO NFIGURAT ION AND FUNCTION DESCRIPTIONS SECTION OF THI S DATA SHEET .

033009-A

Figure 65. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

5 mm × 5 mm Body, Very Very Thin Quad (CP-32-13)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option Quantity

ADL5811ACPZ-R7 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-13 1500 ADL5811-EVALZ Evaluation Board

1

Z = RoHS Compliant Part.

Rev. 0 | Page 28 of 28

Datasheet ADL5811 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING CHARACTERISTICS

Timing Diagram

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

3.6 V PERFORMANCE

SPURIOUS PERFORMANCE

5 V Performance

3.6 V Performance

CIRCUIT DESCRIPTION

RF SUBSYSTEM

LO SUBSYSTEM

APPLICATIONS INFORMATION

BASIC CONNECTIONS

IF PORT

BIAS RESISTOR SELECTION

VGS PROGRAMMING

LOW-PASS FILTER PROGRAMMING

RF BALUN PROGRAMMING

REGISTER STRUCTURE

EVALUATION BOARD

OUTLINE DIMENSIONS

ORDERING GUIDE