High IP3,
V
FEATURES
Broadband upconverter/downconverter
Power conversion gain of 1.8 dB
Broadband RF, LO, and IF ports
SSB noise figure (NF) of 9.75 dB
Input IP3: 28.5 dBm
Input P1dB: 13.3 dBm
Typical LO drive: 0 dBm
Single-supply operation: 5 V at 130 mA
Adjustable bias for low power operation
Exposed paddle, 4 mm × 4 mm, 24-lead LFCSP package
APPLICATIONS
Cellular base station receivers
Radio link downconverters
Broadband block conversion
Instrumentation
GENERAL DESCRIPTION
The ADL5801 uses a high linearity, doubly balanced, active
mixer core with integrated LO buffer amplifier to provide high
dynamic range frequency conversion from 10 MHz to 6 GHz.
The mixer benefits from a proprietary linearization architecture
that provides enhanced input IP3 performance when subject to
high input levels. A bias adjust feature allows the input linearity,
SSB noise figure, and dc current to be optimized using a single
control pin. An optional input power detector is provided for
adaptive bias control. The high input linearity allows the device
to be used in demanding cellular applications where in-band
blocking signals may otherwise result in degradation in
dynamic performance. The adaptive bias feature allows the part
to provide high input IP3 performance when presented with
large blocking signals. When blockers are removed, the
ADL5801 can automatically bias down to provide low noise
figure and low power consumption.
10 MHz to 6 GHz, Active Mixer
ADL5801
FUNCTIONAL BLOCK DIAGRAM
GND
GND
LOIP
LOIN
GND
GND
1
ADL5801
2
3
4
5
6
PLO
24
78
NCGND
9101112
GNDVPLO ENBL VSET
Figure 1.
The balanced active mixer arrangement provides superb LO-toRF and LO-to-IF leakage, typically better than −40 dBm. The IF
outputs are designed to provide a typical voltage conversion
gain of 7.8 dB when loaded into a 200 load. The broad
frequency range of the open-collector IF outputs allows the
ADL5801 to be applied as an upconverter for various transmit
applications.
The ADL5801 is fabricated using a SiGe high performance IC
process. The device is available in a compact 4 mm × 4 mm,
24-lead LFCSP package and operates over a −40°C to +85°C
temperature range. An evaluation board is also available.
212223
GNDIFON
IFOP
1920
V2I
DET
DETO GND
18
VPRF
17
GND
16
RFIP
RFIN
15
14
GND
VPDT
13
8079-001
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2010-2011 Analog Devices, Inc. All rights reserved.
ADL5801
TABLE OF CONTENTS
Features.............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Downcoverter Mode with a Broadband Balun......................... 8
Downconverter Mode with a Mini-Circuits® TC1-1-43M+
Input Balun.................................................................................. 12
Downconverter Mode with a Johanson 3.5 GHz Input Balun
....................................................................................................... 14
Downconverter Mode with a Johanson 5.7 GHz Input Balun
....................................................................................................... 16
Upconverter Mode with a 900 MHz Output Match .............. 18
Upconverter Mode with a 2.1 GHz Output Match................ 20
Spur Performance....................................................................... 23
Circuit Description......................................................................... 27
LO Amplifier and Splitter.......................................................... 27
RF Voltage-to-Current (V-to-I) Converter............................. 27
Mixer Core .................................................................................. 28
Mixer Output Load .................................................................... 28
RF Detector ................................................................................. 28
Bias Circuit.................................................................................. 29
Applications Information.............................................................. 30
Basic Connections...................................................................... 30
RF and LO Ports......................................................................... 30
IF Port.......................................................................................... 31
Evaluation Board............................................................................ 32
Outline Dimensions....................................................................... 34
Ordering Guide .......................................................................... 34
REVISION HISTORY
7/11—Rev. 0 to Rev. A
Changes to Specifications Section.................................................. 3
Changes to Typical Performance Characteristics Section........... 8
Changes to Spur Performance Section ........................................ 23
Changes to RF Voltage-to-Current (V-to-I) Converter
Section.............................................................................................. 27
Changes to RF Detector Section................................................... 28
Changes to RF and LO Ports Section........................................... 30
2/10—Revision 0: Initial Version
Rev. A | Page 2 of 36
ADL5801
SPECIFICATIONS
VS = 5 V, TA = 25C, fRF = 900 MHz, fLO = (fRF − 153 MHz), LO power = 0 dBm, Z
Table 1.
Parameter Test Conditions Min Typ Max Unit
RF INPUT INTERFACE
Return Loss Tunable to >20 dB over a limited bandwidth 12 dB
Input Impedance 50 Ω
RF Frequency Range 10 6000 MHz
OUTPUT INTERFACE
Output Impedance Differential impedance, f = 200 MHz 230 Ω
IF Frequency Range Can be matched externally to 3000 MHz LF 600 MHz
DC Bias Voltage2 Externally generated 4.75 VS 5.25 V
LO INTERFACE
LO Power −10 0 +10 dBm
Return Loss 15 dB
Input Impedance 50 Ω
LO Frequency Range 10 6000 MHz
POWER INTERFACE
Supply Voltage 4.75 5 5.25 V
Quiescent Current Resistor programmable 130 200 mA
Disable Current ENBL pin high 50 mA
Enable Time Time from ENBL pin low to enable 182 ns
Disable Time Time from ENBL pin high to disable 28 ns
DYNAMIC PERFORMANCE at fRF = 900 MHz/1900 MHz3
Power Conversion Gain4 f
= 900 MHz 1.8 dB
RF
fRF = 1900 MHz 1.8 dB
Voltage Conversion Gain5 f
= 900 MHz 7.8 dB
RF
fRF = 1900 MHz 7.8 dB
SSB Noise Figure f
SSB Noise Figure Under Blocking
6
Input Third-Order Intercept7 f
Input Second-Order Intercept8 f
= 900 MHz, VSET = 2.0 V 9.75 dB
CENT
f
= 1900 MHz, VSET = 2.0 V 11.5 dB
CENT
f
= 900 MHz 19.5 dB
CENT
f
= 1900 MHz 20 dB
CENT
= 900 MHz 28.5 dBm
CENT
f
= 1900 MHz 26.4 dBm
CENT
= 900 MHz 63 dBm
CENT
f
= 1900 MHz 49.7 dBm
CENT
Input 1 dB Compression Point fRF = 900 MHz 13.3 dBm
f
= 1900 MHz 12.7 dBm
RF
LO-to-IF Output Leakage Unfiltered IF output −27 dBm
LO-to-RF Input Leakage −30 dBm
RF-to-IF Output Isolation −35 dBc
IF/2 Spurious9 0 dBm input power, fRF = 900 MHz −67.5 dBc
0 dBm input power, fRF = 1900 MHz −53 dBc
IF/3 Spurious9 0 dBm input power, fRF = 900 MHz −65.5 dBc
0 dBm input power, fRF = 1900 MHz −72.6 dBc
DYNAMIC PERFORMANCE at fRF = 2500 MHz10
Power Conversion Gain11 −0.1 dB
Voltage Conversion Gain5 −6.1 dB
SSB Noise Figure f
Input Third-Order Intercept12 f
Input Second-Order Intercept13 f
Input 1 dB Compression Point f
= 2500 MHz, VSET = 2.0 V 10.6 dB
CENT
= 2500 MHz 25.5 dBm
CENT
= 2500 MHz 45.3 dBm
CENT
= 2500 MHz 13.8 dBm
CENT
1
= 50 Ω, VSET = 3.6 V, unless otherwise noted.
0
Rev. A | Page 3 of 36
ADL5801
Parameter Test Conditions Min Typ Max Unit
LO-to-IF Output Leakage Unfiltered IF output −31.5 dBm
LO-to-RF Input Leakage −31.2 dBm
RF-to-IF Output Isolation −42.5 dBc
IF/2 Spurious9 0 dBm input power, fRF = 2600 MHz −50.6 dBc
IF/3 Spurious9 0 dBm input power, fRF = 2600 MHz −59.8 dBc
DYNAMIC PERFORMANCE at fRF = 3500 MHz14
Power Conversion Gain15 −0.44 dB
Voltage Conversion Gain5 −6.44 dB
SSB Noise Figure f
Input Third-Order Intercept7 f
Input Second-Order Intercept8 f
Input 1 dB Compression Point 12.5 dBm
LO-to-IF Output Leakage Unfiltered IF output −30.2 dBm
LO-to-RF Input Leakage −29.4 dBm
RF-to-IF Output Isolation −29.7 dBc
IF/2 Spurious9 0 dBm input power, fRF = 3800 MHz −47.1 dBc
IF/3 Spurious9 0 dBm input power, fRF = 3800 MHz −57.8 dBc
DYNAMIC PERFORMANCE at fRF = 5500 MHz16
Power Conversion Gain17 0.8 dB
Voltage Conversion Gain5 −5.2 dB
SSB Noise Figure f
Input Third-Order Intercept7 f
Input Second-Order Intercept 8 f
Input 1 dB Compression Point 11.3 dBm
LO-to-IF Output Leakage Unfiltered IF output −42.6 dBm
LO-to-RF Input Leakage −28.9 dBm
RF-to-IF Output Isolation −46.7 dBc
IF/2 Spurious9 0 dBm input power, fRF = 5800 MHz −44 dBc
IF/3 Spurious9 0 dBm input power, fRF = 5800 MHz −47 dBc
DYNAMIC PERFORMANCE at fIF = 900 MHz18
Power Conversion Gain19 0 dB
Voltage Conversion Gain5 −6 dB
SSB Noise Figure fIF = 900 MHz, fRF = 250 MHz, VSET = 2.0 V 10.6 dB
Output Third-Order Intercept20 f
Output Second-Order Intercept 21 f
Output 1 dB Compression Point 11.1 dBm
LO-to-IF Output Leakage Unfiltered IF output −33.8 dBm
LO-to-RF Input Leakage −33.4 dBm
IF/2 Spurious9
IF/3 Spurious9
DYNAMIC PERFORMANCE at fIF = 2140 MHz22
Power Conversion Gain23 −1.25 dB
Voltage Conversion Gain5 −7.25 dB
SSB Noise Figure fIF = 2140 MHz, fRF = 190 MHz, VSET = 2.0 V 13.6 dB
Output Third-Order Intercept24 f
Output Second-Order Intercept25 f
Output 1 dB Compression Point 9.9 dBm
LO-to-IF Output Leakage Unfiltered IF output −23.8 dBm
LO-to-RF Input Leakage −33.2 dBm
IF/2 Spurious9
= 3500 MHz, VSET = 3.6 V 15.8 dB
CENT
= 3500 MHz, VSET = 3.6 V 26.5 dBm
CENT
= 3500 MHz, VSET = 3.6 V 42.3 dBm
CENT
= 5500 MHz, VSET = 3.6 V 16.2 dB
CENT
= 5500 MHz, VSET = 3.6 V 22.7 dBm
CENT
= 5500 MHz, VSET = 3.6 V 35.4 dBm
CENT
= 153 MHz, VSET = 3.6 V 30.6 dBm
CENT
= 153 MHz, VSET = 3.6 V 68.7 dBm
CENT
0 dBm input power, f
f
= 806 MHz
IF
0 dBm input power, f
= 806 MHz
f
IF
= 170 MHz, VSET = 3.6 V 24 dBm
CENT
= 170 MHz, VSET = 3.6 V 70 dBm
CENT
0 dBm input power, f
= 2210 MHz
f
IF
= 140 MHz,
RF
= 140 MHz,
RF
= 140 MHz,
RF
−62.6 dBc
−68.9 dBc
−51.5 dBc
Rev. A | Page 4 of 36
ADL5801
1
Z0 is the characteristic impedance assumed for all measurements and the PCB.
2
Supply voltage must be applied from an external circuit through choke inductors
3
VS = 5 V, TA = 25°C, fRF = 900 MHz/1900 MHz, fLO = (f
4
Excluding 4:1 IF port transformer (TC4-1W+), RF and LO port transformers (TC1-1-13M+), and PCB loss.
5
Z
= 50 Ω, differential; Z
SOURCE
6
fRF = f
, f
BLOCKER
− 1) MHz, f
CENT
) MHz, f
CENT
− 1) MHz, f
CENT
) MHz, f
CENT
− 1) MHz, f
CENT
) MHz, f
CENT
− 1) MHz, f
CENT
) MHz, f
CENT
= (f
CENT
RF2
= (f
RF2
= (f
RF2
= (f
RF2
= (f
RF2
CENT
7
f
= (f
RF1
8
f
= (f
RF1
9
For details, see the Spur Per section. formance
10
VS = 5 V, TA = 25°C, fRF = 2500 MHz, fLO = (fRF – 211 MHz), LO power = 0 dBm, Z
11
Including 4:1 IF port transformer (TC4-1W+), RF and LO port transformers (TC1-1-43M+ and TC1-1-13M+ respectively), and PCB loss.
12
f
= (f
RF1
13
f
= (f
RF1
14
VS = 5 V, TA = 25°C, fRF = 3500 MHz, fLO = (fRF – 153 MHz), LO power = 0 dBm, Z
15
Including 4:1 IF port transformer (TC4-1W+), RF and LO port transformers (3600BL14M050), and PCB loss.
16
VS = 5 V, TA = 25°C, fRF = 5500 MHz, fLO = (fRF – 153 MHz), LO power = 0 dBm, Z
17
Including 4:1 IF port transformer (TC4-1W+), RF and LO port transformers (5400BL14B050), and PCB loss.
18
VS = 5 V, TA = 25°C, fRF = 153 MHz, fLO = (fRF + 900 MHz), LO power = 0 dBm, Z
19
Including 4:1 IF port transformer (TC4-14+), RF and LO transformers (TC1-1-13M+), and PCB loss.
20
f
= (f
RF1
21
f
= (f
RF1
22
VS = 5 V, TA = 25°C, fRF = 153MHz, fLO = (fRF + 2140 MHz), LO power = 0 dBm, Z
23
Including 4:1 IF port transformer (1850BL15B200), RF and LO port transformers (TC1-1-13M+), and PCB loss.
24
f
= (f
RF1
25
f
= (f
RF1
= 200 Ω differential; Z
LOAD
− 5) MHz, fLO = (f
= (f
) MHz, fLO = (f
CENT
+ 100) MHz, fLO = (f
CENT
= (f
) MHz, fLO = (f
RF2
CENT
+ 100) MHz, fLO = (f
CENT
= (f
) MHz, fLO = (f
RF2
CENT
+ 100) MHz, fLO = (f
CENT
= (f
) MHz, fLO = (f
RF2
CENT
+ 100) MHz, fLO = (f
CENT
CENT
– 153 MHz), LO power = 0 dBm, Z
RF
is the impedance of the source instrument; Z
− 153) MHz, blocker level = 0 dBm.
CENT
SOURCE
– 153) MHz, each RF tone at −10 dBm.
– 153) MHz, each RF tone at −10 dBm.
CENT
– 211) MHz, each RF tone at −10 dBm.
CENT
– 211) MHz, each RF tone at −10 dBm
CENT
0
+ 900 MHz), each RF tone at −10 dBm.
CENT
+ 900) MHz, each RF tone at −10 dBm.
CENT
+ 2140 MHz), each RF tone at −10 dBm.
CENT
+ 2140) MHz, each RF tone at −10 dBm.
CENT
1
0
1
= 50 Ω, VSET = 3.8 V, unless otherwise noted.
0
is the load impedance at the output.
LOAD
1
= 50 Ω, VSET = 3.8 V, unless otherwise noted.
0
1
= 50 Ω, VSET = 3.6 V, unless otherwise noted.
0
1
= 50 Ω, VSET = 3.6 V, unless otherwise noted.
0
= 50 Ω, VSET = 3.6 V, unless otherwise noted.
1
= 50 Ω, VSET = 4 V, unless otherwise noted.
Rev. A | Page 5 of 36
ADL5801
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage, VPOS 5.5 V
VSET, ENBL 5.5 V
IFOP, IFON 5.5 V
RFIN Power 20 dBm
Internal Power Dissipation 1.2 W
θJA (Exposed Paddle Soldered Down)1 26.5°C/W
θJC (at Exposed Paddle) 8.7°C/W
Maximum Junction Temperature 150°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
1
As measured on the evaluation board. For details, see the Evaluation Board
section.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. A | Page 6 of 36
ADL5801
O
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
IFOP
GND
NC
IFON
GND
VPL
20
19
22
21
23
24
PIN 1
INDICATOR
1GND
2GND
ADL5801
3LOIP
TOP VIEW
4LOIN
(Not to Scale)
5GND
6GND
9
7
8
L
GND
ENB
VPLO
NOTES
1. THERE IS AN EXPOSED PADDLE THAT
MUST BE SOLDERED TO GROUND.
2. NC = NO CONNECT.
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1, 2, 5, 6, 8, 12,
GND Device Common (DC Ground).
14, 17, 19, 23
3, 4 LOIP, LOIN Differential LO Input Terminal. Internally matched to 50 Ω. Must be ac-coupled.
7, 24 VPLO Positive Supply Voltage for LO System.
9 ENBL Device Enable. Pull high to disable the device; pull low to enable.
10 VSET
Input IP3 Bias Adjustment. The voltage presented to the VSET pin sets the internal bias of the mixer core
and allows for adaptive control of the input IP3 and NF characteristics of the mixer core.
11 DETO
Detector Output. The DETO pin should be loaded with a capacitor to ground. The developed voltage is
proportional to the rms input level. When the DETO output voltage is connected to the VSET input pin,
the part auto biases and increases input IP3 performance when presented with large signal input levels.
13 VPDT Positive Supply Voltage for Detector.
15, 16 RFIN, RFIP
Differential RF Input Terminal. Internally matched to 50 Ω differential input impedance. Must be
ac-coupled.
18 VPRF Positive Supply Voltage for RF Input System.
20, 21 IFOP, IFON
Differential IF Output Terminal. Bias must be applied through pull-up choke inductors or the center tap
of the IF transformer.
22 NC Not Connected.
EPAD The exposed paddle must be soldered to ground.
18 VPRF
17 GND
16 RFIP
15 RFIN
14 G ND
13 VP DT
11
12
10
GND
VSET
DETO
8079-002
Rev. A | Page 7 of 36
ADL5801
C
TYPICAL PERFORMANCE CHARACTERISTICS
DOWNCOVERTER MODE WITH A BROADBAND BALUN
VS = 5 V, TA = 25°C, VSET = 3.8 V, IF = 153 MHz, as measured using a typical circuit schematic with low-side local oscillator (LO), unless
otherwise noted. Insertion loss of input and output baluns (TC1-1-13M+, TC4-1W+) is extracted from the gain measurement.
6
5
4
3
2
1
GAIN (dB)
0
–1
–2
–3
–4
500 1000 1500 2000 2500 3000
TA = –40°C
T
= +85°C
A
RF FREQUENCY (MHz)
TA = +25°C
Figure 3. Power Conversion Gain vs. RF Frequency
4.0
3.5
3.0
2.5
2.0
GAIN (dB)
1.5
1.0
0.5
0
0 50 100 150 200 250
900MHz
1900MHz
IF FREQUENCY (MHz)
Figure 4. Power Conversion Gain vs. IF Frequency
3.0
2.5
2.0
1.5
1.0
GAIN (dB)
0.5
0
–0.5
GAIN = 900MHz
GAIN = 1900M Hz
I
= 900MHz
POS
I
= 1900MHz
POS
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
8079-003
08079-004
SUPPLY CURRENT (A)
6
5
4
GAIN = 900MHz
GAIN = 1900MHz
3
INPUT IP 3 = 900MHz
GAIN (dB)
INPUT IP 3 = 1900MHz
2
1
0
–15 –1 0 –5 0 5 10 15
LO LEVEL (dBm)
Figure 6. Power Conversion Gain and Input IP3 vs. LO Power
100
90
1.700
MEAN = 1.87
SD = 0.03
1.740
1.780
1.820
POWER CONVERSION GAIN (dB)
1.860
1.900
1.940
1.980
80
70
60
Y (%)
50
40
FREQUEN
30
20
10
0
Figure 7. Power Conversion Gain Distribution
3.0
2.5
2.0
1.5
GAIN (dB)
1.0
0.5
TA = –40°C
TA = +25°C
= +85°C
T
A
35
30
25
20
INPUT IP3 (dBm)
15
10
5
2.020
2.060
2.100
08079-007
08079-006
–1.0
2.0 3.02.5 3.5 4.0 4.5 5.0
VSET (V)
Figure 5. Power Conversion Gain and Supply Current vs. VSET
0.02
0
4.7 4.8 4.9 5.0 5.1 5.2 5.3
8079-005
SUPPLY (V)
08079-008
Figure 8. Power Conversion Gain vs. Supply Voltage
Rev. A | Page 8 of 36
ADL5801
35
30
25
20
15
INPUT IP3 (dBm)
10
5
0
500 1000 1500 2000 2500 3000
TA = –40°C
RF FREQUENCY (MHz)
= +85°C
T
A
TA = +25°C
Figure 9. Input IP3 vs. RF Frequency
40
35
30
25
INPUT IP3 (dBm)
20
15
900MHz
1900MHz
08079-009
70
60
TA = –40°C
= +25°C
T
50
A
T
= +85°C
A
40
30
INPUT IP2 (dBm)
20
10
0
500 1000 1500 2000 2500 3000
RF FREQUENCY (MHz)
Figure 12. Input IP2 vs. RF Frequency
80
70
60
50
40
30
INPUT IP2 (dBm)
20
10
900MHz
1900MHz
8079-012
10
0 50 100 150 200 250
IF FRE QUENCY (MH z)
Figure 10. Input IP3 vs. IF Frequency
30
25
20
15
INPUT IP3 (dBm)
10
5
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0
INPUT IP3 = 900MHz
INPUT IP3 = 1900MHz
NF = 900MHz
NF = 1900MHz
VSET (V)
Figure 11. Input IP3 and Noise Figure vs. VSET
0
0 50 100 150 200 250
08079-010
IF FREQUENCY (MHz)
08079-013
Figure 13. Input IP2 vs. IF Frequency
20
18
16
14
12
NOISE FI GURE (dB)
10
8
08079-011
80
70
60
50
40
30
INPUT IP2 (dBm)
20
10
0
2.0 2.5 3.53.0 4. 0 4.5 5.0
900MHz
1900MHz
VSET (V)
8079-014
Figure 14. Input IP2 vs. VSET
Rev. A | Page 9 of 36
ADL5801
20
18
16
14
12
10
8
INPUT P1dB (dBm)
6
4
2
0
500 1000 1500 2000 2500 3000
20
18
16
14
12
10
8
INPUT P1dB (dBm)
6
4
2
0
0 50 100 150 200 250
18
16
14
12
10
8
6
SSB NOISE F IGURE (dB)
4
2
0
500 1000 1500 2000 2500 3000
Figure 17. SSB Noise Figure vs. RF Frequency (VSET = 2.0 V)
= +25°C
T
= +85°C
T
A
RF FREQUENCY (MHz)
A
TA = –40°C
Figure 15. Input P1dB vs. RF Frequency
900MHz
1900MHz
IF FREQUENCY (MHz)
Figure 16. Input P1dB vs. IF Frequency
= +85°C
T
A
T
= +25°C
A
TA = –40°C
RF FREQUENCY (MHz)
25
20
15
10
SSB NOISE F IGURE (dB)
5
0
0 100 200 300 400 500 600 700
08079-015
1900MHz
900MHz
IF FREQUENCY (MHz)
8079-018
Figure 18. SSB Noise Figure vs. IF Frequency (VSET = 2.0 V)
30
25
20
15
10
SSB NOISE FIGURE (dB)
5
0
–30 –25 –20 –15 –10 –5 0 5
08079-016
RF = 1846MHz, I F = 153 MHz
BLOCKER = 1841MHz
RF = 951MHz, I F = 153 MHz
BLOCKER = 946MHz
BLOCKER LEVE L (dBm)
08079-019
Figure 19. SSB Noise Figure vs. Blocker Level (VSET = 2.0 V)
20
18
16
14
12
10
8
6
SSB NOISE F IGURE (dB)
4
2
0
–15 –10 –5 0 5 10 15
08079-017
1900MHz
900MHz
LO LEVEL (dBm)
8079-020
Figure 20. SSB Noise Figure vs. LO Power (VSET = 2.0 V)
Rev. A | Page 10 of 36
ADL5801
–
–
A
0
5
10
15
20
25
RF RETURN LOSS (dB)
30
35
0 500 1000 1500 2000 2500 3000
RF FREQUENCY ( MHz)
Figure 21. RF Return Loss vs. RF Frequency
0
5
10
15
20
25
LO RETURN LOSS (dB)
30
35
0 500 1000 1500 2000 2500 3000
LO FREQUENCY (MHz)
Figure 22. LO Return Loss vs. LO Frequency
500
8079-021
08079-022
4
10
LO-TO-IF LEAKAGE (dBm)
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
500
TA = –40°C
= +25°C
T
A
T
= +85°C
A
1000 1500 2000 2500 3000
LO FREQ UENCY (MHz)
Figure 24. LO-to-IF Leakage vs. LO Frequency
10
–15
–20
–25
–30
–35
–40
–45
LO-TO-RF LE AKAGE (dBm)
–50
–55
–60
500 1000 1500 2000 2500 3000
TA = –40°C
T
= +25°C
A
T
= +85°C
A
LO FREQUENCY ( MHz)
Figure 25. LO-to-RF Leakage vs. LO Frequency
0
08079-024
08079-025
400
300
200
RESISTANCE (Ω)
100
0
100 100010 3000
IF FREQUENCY (MHz)
Figure 23. IF Differential Output Impedance (R Parallel C Equivalent)
2
0
–2
CAPACITANCE (pF)
–4
–6
08079-023
Rev. A | Page 11 of 36
–10
–20
TION (dBc)
–30
–40
–50
RF-TO-IF OUTPUT ISOL
–60
500 1000 1500 2000 2500 3000
TA = +85°C
TA = –40°C
RF FREQUENCY (MHz)
TA = +25°C
08079-026
Figure 26. RF-to-IF Leakage vs. RF Frequency
ADL5801
DOWNCONVERTER MODE WITH A MINI-CIRCUITS® TC1-1-43M+ INPUT BALUN
VS = 5 V, TA = 25°C, VSET = 3.8 V, IF = 211 MHz, as measured using a typical circuit schematic with low-side local oscillator (LO), unless
otherwise noted. Insertion loss of input and output baluns (TC1-1-43M+, TC4-1W+) is included in the gain measurement.
6
5
4
3
2
1
GAIN (dB)
0
–1
–2
–3
–4
2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000
RF FREQUENCY ( MHz)
Figure 27. Power Conversion Gain vs. RF Frequency
1.0
0.5
0
–0.5
–1.0
GAIN (dB)
–1.5
–2.0
–2.5
–3.0
2.02.53.03.54.04.55.0
30
29
28
27
26
25
24
INPUT IP3 (dBm)
23
22
21
20
2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000
GAIN 2500M
IPOS 2500M
V
(V)
SET
Figure 28. Power Conversion Gain and IPOS vs. V
RF FREQUENCY (MHz)
SET
Figure 29. Input IP3 vs. RF Frequency
30
25
IIP3 2500MHz
20
15
INPUT IP3 (dBm)
10
NF 2500MHz
5
0
08079-027
2.0 2. 5 3.0 3.5 4. 0 4.5 5.0
V
(V)
SET
Figure 30. Input IP3 and Noise Figure vs. V
0.18
0.16
0.14
0.12
0.10
0.08
0.06
SUPPLY CURRENT (A)
0.04
0.02
0
08079-028
08079-029
60
50
40
30
INPUT IP2 (dBm)
20
10
0
2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000
RF FREQUENCY (MHz)
Figure 31. Input IP2 vs. RF Frequency
80
70
60
50
40
30
INPUT IP2 (dBm)
20
10
0
2.0 2. 5 3.0 3.5 4.0 4. 5 5.0
Figure 32. Input IP2 vs. V
V
(V)
SET
SET
20
18
16
14
12
NOISE FI GURE (dB)
10
8
08079-030
SET
08079-031
08079-032
Rev. A | Page 12 of 36
ADL5801
–
–
–
A
20
18
16
14
12
10
8
INPUT P1dB (dBm)
6
4
2
0
2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000
RF FREQUENCY (MHz)
Figure 33. Input P1dB vs. RF Frequency
25
SET
SET
SET
3.6V
3.6V
3.6V
+85°C V
20
15
10
NOISE FI GURE (dB)
+25°C V
–40°C V
+85°C V
+25°C V
–40°C V
SET
SET
SET
2V
2V
2V
10
–15
–20
–25
–30
–35
–40
–45
LO TO RF LEAKAGE (dBm)
–50
–55
–60
2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000
08079-033
LO FREQ UENCY (MHz)
08079-036
Figure 36.LO to RF Leakage vs. LO Frequency
20
–30
–40
TION (dBc)
–50
–60
5
0
2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000
RF FREQUENCY (MHz)
Figure 34. Noise Figure vs. RF Frequency
10
–15
–20
–25
–30
–35
–40
–45
LO TO IF LE AKAGE (dBm)
–50
–55
–60
2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000
LO FREQ UENCY (MHz)
Figure 35. LO to IF Leakage vs. LO Frequency
–70
RF TO IF OUTPUT ISOL
–80
2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000
08079-034
RF FREQ UENCY (MHz)
08079-037
Figure 37. RF to IF Output Isolation vs. RF Frequency
08079-035
Rev. A | Page 13 of 36
ADL5801
DOWNCONVERTER MODE WITH A JOHANSON 3.5 GHZ INPUT BALUN
VS = 5 V, TA = 25°C, VSET = 3.6 V, IF = 153 MHz, as measured using a typical circuit schematic with low-side local oscillator (LO), unless
otherwise noted. Insertion loss of input and output baluns (3600BL14M050, TC4-1W+) is included in the gain measurement.
6
5
4
3
2
1
GAIN (dB)
0
–1
–2
–3
–4
3000 3100 3200 3300 3400 3500 3600 3700 3800 3900 4000
–40°C
+25°C
+85°C
RF FREQUENCY (MHz)
Figure 38. Power Conversion Gain vs. RF Frequency
2
0
–2
–4
–6
GAIN (dB)
GAIN –40°C
–8
GAIN +25°C
GAIN +85°C
IPOS –40°C
–10
IPOS +25°C
IPOS +85°C
–12
2.0 2. 5 3.0 3.5 4. 0 4.5 5.0
V
(V)
SET
Figure 39. Power Conversion Gain and IPOS vs. V
30
–40°C
25
20
+25°C
+85°C
30
25
20
15
INPUT IP3 (dBm)
10
5
0
2.02.53.03.54.04.55.0
08079-038
IIP3, –40°C
IIP3, +25°C
IIP3, +85°C
NF, –40°C
NF, +25°C
NF, +85°C
V
(V)
SET
Figure 41. Input IP3 and Noise Figure vs. V
0.20
0.18
0.16
0.14
0.12
0.10
0.08
0.06
SUPPLY CURRENT (A)
0.04
0.02
0
08079-039
SET
50
45
40
35
INPUT IP2 (dBm)
30
25
20
3000 3100 3200 3300 3400 3500 3600 3700 3800 3900 4000
RF FREQUENCY (MHz)
+85°C
+25°C
–40°C
Figure 42. Input IP2 vs. RF Frequency
80
70
60
50
+85°C
+25°C
–40°C
28
23
18
NOISE FI GURE (dB)
13
8
SET
08079-042
08079-041
15
INPUT IP3 (dBm)
10
5
0
3000 3100 3200 3300 3400 3500 3600 3700 3800 3900 4000
RF FREQUENCY (MHz)
Figure 40. Input IP3 vs. RF Frequency
08079-040
Rev. A | Page 14 of 36
40
30
INPUT IP2 (dBm)
20
10
0
2.0 2. 5 3.0 3.5 4.0 4.5 5.0
Figure 43. Input IP2 vs. V
V
(V)
SET
SET
08079-043
ADL5801
–
–
–
A
LO TO RF LEAKAG E (dBm)
10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
+85°C
+25°C
–40°C
3000 3100 3200 3300 3400 3500 3600 3700 3800 3900 4000
LO FREQUE NCY (MHz)
Figure 47. LO to RF Leakage vs. LO Frequency
20
–30
–40
TION (dBc)
–50
–60
+85°C
+25°C
–40°C
08079-047
20
18
16
14
12
10
8
INPUT P1dB (dBm)
6
4
2
0
3000 3100 3200 3300 3400 3500 3600 3700 3800 3900 4000
+85°C
+25°C
–40°C
RF FREQUENCY (MHz)
Figure 44. Input P1dB vs. RF Frequency
25
–40°C, 3.6V+25°C, 3.6V+85°C, 3.6V
20
15
–40°C, 2.0V+25°C, 2.0V+85°C, 2.0V
10
NOISE FI GURE (dB)
08079-044
5
0
3000 3100 3200 3300 3400 3500 3600 3700 3800 3900 4000
RF FREQUENCY (MHz)
Figure 45. Noise Figure vs. RF Frequency
10
–15
–20
–25
–30
–35
–40
–45
LO TO IF LE AKAGE (dBm)
–50
–55
–60
+85°C
+25°C
–40°C
3000 3100 3200 3300 3400 3500 3600 3700 3800 3900 4000
LO FREQUENCY (MHz)
Figure 46. LO to IF Leakage vs. LO Frequency
–70
RF TO IF OUTPUT ISOL
–80
3000 3100 3200 3300 3400 3500 3600 3700 3800 3900 4000
08079-045
RF FREQUENCY ( MHz)
08079-048
Figure 48. RF to IF Output Isolation vs. RF Frequency
08079-046
Rev. A | Page 15 of 36
ADL5801
DOWNCONVERTER MODE WITH A JOHANSON 5.7 GHZ INPUT BALUN
VS = 5 V, TA = 25°C, VSET = 3.6 V, IF = 153 MHz, as measured using a typical circuit schematic with low-side local oscillator (LO), unless
otherwise noted. Insertion loss of input and output baluns (5400BL14B050, TC4-1W+) is included in the gain measurement.
6
5
–40°C
+25°C
+85°C
4
3
2
1
GAIN (dB)
0
–1
–2
–3
–4
5000 5100 5200 5300 5400 5500 5600 5700 5800 5900 6000
RF FREQUENC Y (MHz)
Figure 49. Power Conversion Gain vs. RF Frequency
2
0
–2
–4
–6
–8
GAIN (dB)
–10
GAIN –40°C
GAIN +25°C
–12
GAIN +85°C
IPOS –40°C
–14
IPOS +25°C
IPOS +85°C
–16
2.0 2.5 3.0 3.5 4.0 4.5 5.0
V
(V)
SET
Figure 50. Power Conversion Gain and IPOS vs V
30
25
20
–40°C
+25°C
+85°C
25
20
15
10
INPUT IP3 (dBm)
IIP3, –40°C
V
SET
IIP3, +25°C
IIP3, +85°C
NF, –40°C
NF, +25°C
NF, +85°C
(V)
SET
5
0
2.0 2. 5 3.0 3.5 4.0 4. 5 5.0
08079-049
Figure 52. Input IP3 and Noise Figure vs. V
0.20
0.18
0.16
0.14
0.12
0.10
0.08
0.06
SUPPLY CURRENT (A)
0.04
0.02
0
08079-050
SET
70
65
60
55
50
45
40
INPUT IP2 (dBm)
35
30
25
20
5000 5100 5200 5300 5400 5500 5600 5700 5800 5900 6000
+85°C
+25°C
–40°C
RF FREQUENCY (MHz)
Figure 53. Input IP2 vs. RF Frequency
80
70
60
50
+85°C
+25°C
–40°C
35
30
25
20
15
NOISE FI GURE (dB)
10
5
08079-052
08079-053
15
INPUT IP3 (dBm)
10
5
0
5000 5100 5200 5300 5400 5500 5600 5700 5800 5900 6000
RF FREQUENCY (MHz)
Figure 51. Input IP3 vs. RF Frequency
08079-051
Rev. A | Page 16 of 36
40
30
INPUT IP2 (dBm)
20
10
0
2.0 2. 5 3.0 3.5 4. 0 4.5 5.0
V
(V)
SET
Figure 54.Input IP2 vs. V
SET
08079-054
ADL5801
–
–
–
A
20
18
16
14
12
10
8
INPUT P1dB (dBm)
6
4
2
0
5000 5100 5200 5300 5400 5500 5600 5700 5800 5900 6000
+85°C
+25°C
–40°C
RF FREQUENCY (MHz)
Figure 55. Input P1dB vs. RF Frequency
25
–40°C, 3.6V+25°C, 3.6V+85°C, 3.6V
20
15
–40°C, 2.0V+25°C, 2.0V+85°C, 2.0V
10
NOISE FI GURE (dB)
08079-055
10
–15
–20
–25
–30
–35
–40
–45
LO TO RF LEAKAG E (dBm)
–50
–55
–60
5000 5100 5200 5300 5400 5500 5600 5700 5800 5900 6000
+85°C
+25°C
–40°C
LO FREQUE NCY (MHz)
Figure 58. LO to RF Leakage vs. LO Frequency
20
+85°C
–30
–40
TION (dBc)
–50
–60
+25°C
–40°C
08079-058
5
0
5000 5100 5200 5300 5400 5500 5600 5700 5800 5900 6000
RF FREQ UENCY (MHz)
Figure 56. Noise Figure vs. RF Frequency, V
10
–15
–20
–25
–30
–35
–40
–45
LO TO IF LEAKAGE (dBm)
–50
–55
–60
+85°C
+25°C
–40°C
5000 5100 5200 5300 5400 5500 5600 5700 5800 5900 6000
LO FREQUENCY (MHz)
Figure 57. LO to IF Leakage vs. LO Frequency
= 3.6 V
SET
–70
RF TO IF OUTPUT ISOL
–80
5000 5100 5200 5300 5400 5500 5600 5700 5800 5900 6000
08079-056
RF FREQUENCY (MHz)
08079-059
Figure 59. RF to IF Output Isolation vs. RF Frequency
08079-057
Rev. A | Page 17 of 36
ADL5801
UPCONVERTER MODE WITH A 900 MHZ OUTPUT MATCH
VS = 5 V, TA = 25°C, VSET = 3.6 V, RF = 153 MHz, as measured using a typical circuit schematic with low-side local oscillator (LO),
unless otherwise noted. Insertion loss of input and output baluns (TC1-1-13M+, TC4-14) is included in the gain measurement.
2
1
0
–1
–2
–3
GAIN (dB)
–4
–5
–6
–7
–8
+85°C
+25°C
–40°C
300 400 500 600 700 800 900 1000 1100 1200 1300
IF FREQ UENCY (MHz)
Figure 60. Power Conversion Gain vs. IF Frequency
1.0
GAIN –40°C
0.8
GAIN +25°C
GAIN +85°C
0.6
IPOS –40°C
IPOS +25°C
IPOS +85°C
0.4
0.2
0
GAIN (dB)
–0.2
–0.4
–0.6
–0.8
–1.0
2.0 2. 5 3.0 3.5 4. 0 4.5 5.0
V
(V)
SET
Figure 61. Power Conversion Gain and IPOS vs. V
35
08079-077
0.18
0.16
0.14
0.12
0.1
0.08
0.06
SUPPLY CURRENT (A)
0.04
0.02
0
SET
35
30
25
20
15
OUTPUT IP3 (dBm)
10
5
0
2.02.53.03.54.04.55.0
80
75
70
65
60
OUTPUT IP2 (dBm)
55
50
300 400 500 600 700 800 900 1000 1100 1200 1300
OUTPUT IP3, –40°C
OUTPUT IP3, +25°C
OUTPUT IP3, +85°C
V
SET
Figure 63. Output IP3 vs. V
+85°C
+25°C
–40°C
IF FREQUENCY (MHz)
(V)
SET
Figure 64. Output IP2 vs. IF Frequency
80
08079-080
08079-081
30
25
20
+85°C
15
OUTPUT IP3 (dBm)
10
5
0
300 400 500 600 700 800 900 1000 1100 1200 1300
+25°C
–40°C
IF FREQ UENCY (MHz)
Figure 62. Output IP3 vs. IF Frequency
08079-079
Rev. A | Page 18 of 36
75
70
65
60
55
OUTPUT IP2 (dBm)
50
45
40
2.0 2. 5 3.0 3.5 4. 0 4.5 5.0
+85°C
+25°C
–40°C
V
(V)
SET
Figure 65. Output IP2 vs. V
SET
08079-082
ADL5801
–
–
12
10
8
6
4
OUTPUT P1dB (dBm)
2
0
300 400 500 600 700 800 900 1000 1100
+85°C
+25°C
–40°C
IF FREQUENCY (MHz)
Figure 66. Output P1dB vs. IF Frequency
16
14
12
10
8
6
NOISE FI GURE (dB)
NF V
= 3.6V, –40° C NF V
SET
NF V
4
2
0
700 750 800 850 900 950 1000
= 3.6V, +25° C NF V
SET
NF V
= 3.6V, +85° C NF V
SET
IF FREQUENCY (MHz)
SET
SET
SET
Figure 67. Noise Figure vs. IF Frequency, F
= 2.0V, –40° C
= 2.0V, + 25°C
= 2.0V, + 85°C
= 650 MHz
LO
10
–15
–20
–25
–30
–35
–40
–45
LO TO IF LEAKAGE (dBm)
–50
–55
–60
08079-083
+85°C
+25°C
–40°C
453 553 653 753 853 953 1053 1153 1253 1353 1453
LO FREQ UENCY (MHz)
08079-085
Figure 68. LO to IF Leakage vs. LO Frequency
10
–15
–20
–25
–30
–35
–40
–45
LO TO RF LEAKAG E (dBm)
–50
–55
–60
453 553 653 753 853 953 1053 1153 1253 1353 1453
08079-084
+85°C
+25°C
–40°C
LO FREQUENCY (MHz)
08079-086
Figure 69. LO to RF Leakage vs. LO Frequency
Rev. A | Page 19 of 36
ADL5801
UPCONVERTER MODE WITH A 2.1 GHZ OUTPUT MATCH
VS = 5 V, TA = 25°C, VSET = 4 V, RF = 170 MHz, as measured using a typical circuit schematic with low-side local oscillator (LO), unless
otherwise noted. Insertion loss of input and output baluns (TC1-1-13M+, 1850BL15B200) is included in the gain measurement.
4
3
2
1
0
–1
GAIN (dB)
–2
–3
–4
–5
–6
110 130 150 170 190 210 230 250 270 290
–40°C
+25°C
+85°C
RF FREQUENCY (MHz)
Figure 70. Power Conversion Gain vs. RF Frequency
0
–0.5
–1.0
–1.5
GAIN (dB)
2
.0
GAIN –40°C
GAIN +25°C
GAIN +85°C
IPOS –40°C
IPOS +25°C
IPOS +85°C
2.5 3
.0
3.5 4
V
SET
.0
(V)
–2.0
–2.5
–3.0
Figure 71. Power Conversion Gain and IPOS vs. V
35
30
25
20
15
OUTPUT IP 3 (dBm)
10
OUTPUT IP3 –40°C
5
OUTPUT IP3 +25°C
OUTPUT IP3 +85°C
0
2.0 2. 5 3.0 3.5 4.0 4. 5 5.0
Figure 72. Output IP3 vs. V
V
(V)
SET
SET
4.5 5
08079-060
0.18
0.16
0.14
0.12
0.10
0.08
0.06
SUPPLY CURRENT (A)
0.04
0.02
0
.0
08079-062
SET
08079-067
35
30
25
20
–40°C
15
OUTPUT IP 3 (dBm)
10
5
0
110 130 150 170 190 210 230 250 270 290
+25°C
+85°C
RF FREQUENCY (MHz)
Figure 73. Output IP3 vs. RF Frequency
80
75
70
65
60
OUTPUT IP2 (dBm)
55
50
+85°C
+25°C
–40°C
1900 2000 2100 2200 2300 2400 2500 2600 2700
IF FREQUENCY (MHz)
Figure 74. Output IP2 vs. IF Frequency
80
75
70
65
60
55
OUTPUT IP2 (dBm)
50
45
40
2.0 2. 5 3.0 3.5 4.0 4.5 5.0
+85°C
+25°C
–40°C
V
SET
Figure 75. Output IP2 vs. V
(V)
SET
08079-065
08079-069
08079-070
Rev. A | Page 20 of 36
ADL5801
–
–
–
A
12
10
+85°C
8
6
4
OUTPUT P1DB (d Bm)
2
0
1900 2000 2100 2200 2300 2400 2500 2600 2700
+25°C
–40°C
IF FREQ UENCY (MHz)
Figure 76. Output P1dB vs. IF Frequency
25
20
15
10
NOISE FI GURE (dB)
5
0
10
–15
–20
–25
–30
–35
–40
–45
LO TO IF LEAKAGE (dBm)
–50
–55
–60
NF V
= 3.6V, –40° C NF V
SET
NF V
= 3.6V, + 25°C NF V
SET
NF V
= 3.6V, + 85°C NF V
SET
2000 2050 2100 2150 2200 2250 2300
IF FREQUENCY (MHz)
Figure 77. Noise Figure vs. IF Frequency, F
+85°C
+25°C
–40°C
2070 2170 2270 2370 2470 2570 2670 2770 2870
LO FREQUENCY (MHz)
= 2.0V, –40° C
SET
= 2.0V, +25 °C
SET
= 2.0V, +85 °C
SET
= 1950 MHz
LO
Figure 78. LO to IF Leakage vs. LO Frequency
08079-072
08079-073
08079-074
10
–15
–20
–25
–30
–35
–40
–45
LO TO RF LEAKAG E (dBm)
–50
–55
–60
2070 2170 2270 2370 2470 2570 2670 2770 2870
+85°C
+25°C
–40°C
LO FREQ UENCY (MHz)
Figure 79. LO to RF Leakage vs. LO Frequency
65
–66
–67
–68
TION (dBc)
–69
–70
–71
–72
–73
RF TO IF OUTPUT ISOL
–74
–75
110 130 150 170 190 210 230 250 270 290
+85°C
+25°C
–40°C
RF FREQUENCY (MHz)
Figure 80. RF to IF Output Isolation vs. RF Frequency
2
–40°C
1
+25°C
+85°C
0
–1
–2
–3
GAIN (dB)
–4
–5
–6
–7
–8
1900 2000 2100 2200 2300 2400 2500 2600 2700
IF FREQUENCY (MHz)
Figure 81. Power Conversion Gain vs. IF Frequency
08079-075
08079-076
08079-061
Rev. A | Page 21 of 36
ADL5801
5
4
3
2
1
0
GAIN (dB)
–1
–2
GAIN –40°C
GAIN +25°C
–3
GAIN +85°C
–4
–10–8–6–4–20246810
Figure 82. Power Conversion Gain and Output IP3 vs. LO Power
0
–40°C
–0.2
–0.4
–0.6
–0.8
GAIN (dB)
–1.0
–1.2
–1.4
+25°C
+85°C
4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25
Figure 83. Power Conversion Gain vs. Supply
35
–40°C
+25°C
30
+85°C
OUTPUT IP3 –40°C
OUTPUT IP3 +25°C
OUTPUT IP3 +85°C
LO POWER (dBm)
SUPPLY (V)
40
35
30
25
20
15
OUTPUT I P3 (dBm)
10
5
0
08079-063
80
78
–40°C
76
74
72
OUTPUT IP2 (dBm)
70
68
66
110 130 150 170 190 210 230 250 270 290
+25°C
+85°C
RF FREQUENCY (MHz)
08079-068
Figure 85. Output IP2 vs. RF Frequency
20
18
16
14
12
10
8
OUTPUT P1dB ( dBm)
6
4
2
0
08079-064
+85°C
+25°C
–40°C
110 130 150 170 190 210 230 250 270 290
RF FREQUENCY (MHz)
08079-071
Figure 86. Output P1dB vs. RF Frequency
25
20
15
OUTPUT IP3 (dBm)
10
5
0
1900 2000 2100 2200 2300 2400 2500 2600 2700
IF FREQUENCY (MHz)
Figure 84. Output IP3 vs. IF Frequency
08079-066
Rev. A | Page 22 of 36
ADL5801
SPUR PERFORMANCE
All spur tables are (N × fRF) − (M × fLO) and were measured using the standard evaluation board (see the Evaluation Board section). Mixer
spurious products are measured in decibels relative to the carrier (dBc) from the IF output power level. Data was measured for frequencies
less than 6 GHz only. The typical noise floor of the measurement system is −100 dBm.
900 MHz Downconvert Performance
VS = 5 V, VSET = 3.8 V, TA = 25°C, RF power = 0 dBm, LO power = 0 dBm, fRF = 900 MHz, fLO = 703 MHz, Z0 = 50 Ω.
M
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
N 7
−33.1 −23.3 −45.8 −23.6 −45.9 −30.7 −55.4 −41.5
0
−48.8 0.0 −51.5 −19.0 −65.1 −29.6 −78.0 −50.3 −74.4 −57.7
1
−35.9 −74.9 −67.5 −66.1 −73.5 −80.5 −65.0 −89.8 −71.3 −88.5 −86.8 −98.8
2
−68.8 −64.8 −94.3 −65.9 −86.3 −70.2 −76.3 −70.6 −74.5 −81.4 ≤−100 −99.6 ≤−100
3
−47.5 −80.7 −78.0 −78.4 −95.1 −73.5 −89.4 −87.3 ≤−100 −92.7 −99.5 −99.4 ≤−100 ≤−100
4
−95.6 −74.7 −89.8 −70.7 −84.8 −90.7 −86.7 −86.4 −83.1 −73.7 −78.7 −80.7 −91.1 ≤−100 ≤−100
5
−85.7 −96.4 −83.1 −98.5 −83.3 −96.7 ≤−100 −89.4 −99.6 −96.1 −96.1 −95.4 −95.5 ≤−100 ≤−100
6
≤−100 ≤−100 −95.9 ≤−100 −97.2 −83.1 −84.1 ≤−100 ≤−100 −99.7 −87.9 −88.8 −85.7 ≤−100
≤−100 ≤−100 −99.0 −99.8 −86.0 ≤−100 ≤−100 ≤−100 ≤−100 ≤−100 ≤−100 ≤−100 ≤−100
8
≤−100 ≤−100 ≤−100 −90.9 −88.4 −83.5 −87.6 ≤−100 ≤−100 ≤−100 ≤−100 ≤−100
9
≤−100 ≤−100 ≤−100 −97.9 −95.5 −99.0 ≤−100 ≤−100 ≤−100 ≤−100
10
≤−100 ≤−100 −92.6 −87.4 −88.2 −92.3 −99.3 ≤−100 ≤−100
11
≤−100 ≤−100 ≤−100 ≤−100 ≤−100 ≤−100 ≤−100 ≤−100
12
≤−100 ≤−100 −95.1 −96.5 −90.4 ≤−100
13
≤−100 ≤−100 ≤−100 ≤−100 ≤−100
14
≤−100 ≤−100 ≤−100 ≤−100
15
1900 MHz Downconvert Performance
VS = 5 V, VSET = 3.8 V, TA = 25°C, RF power = 0 dBm, LO power = 0 dBm, fRF = 1900 MHz, fLO = 1703 MHz, Z0 = 50 Ω.
0 −31.4 −17.1 −51.4
1 −40.4 0.0 −53.6 −38.5 −71.0
2 −38.4 −66.0 −52.9 −68.1 −64.2 −86.8
3 ≤−100 −66.2 −73.2 −72.6 −79.9 −65.2 −92.8
4 ≤−100 −89.4 −86.4 −94.6 −87.4 −81.5 ≤−100
5 −83.7 −66.2 −79.3 −89.0 −75.2 ≤−100 ≤−100
6 ≤−100 −86.4 ≤−100 −99.0 −87.7 ≤−100 ≤−100
N
8 ≤−100 ≤−100 −97.5 ≤−100 −95.4 ≤−100 ≤−100
9 ≤−100 ≤−100 ≤−100 ≤−100 ≤−100 ≤−100 ≤−100
10 ≤−100 −97.2 −95.6 ≤−100 ≤−100 ≤−100 ≤−100
11 ≤−100 ≤−100 ≤−100 ≤−100 ≤−100 ≤−100
12 ≤−100 ≤−100 ≤−100 ≤−100 ≤−100
13 ≤−100 ≤−100 ≤−100 ≤−100
14 ≤−100 ≤−100
15 ≤−100
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
7 ≤−100 −92.4 −92.7 ≤−100 −98.4 ≤−100 ≤−100
M
Rev. A | Page 23 of 36
ADL5801
2600 MHz Downconvert Performance
VS = 5 V, VSET = 3.8 V, TA = 25°C, RF power = 0 dBm, LO power = 0 dBm, fRF = 2600 MHz, fLO = 2350 MHz, Z0 = 50 Ω.
M
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
−31.5 −30.3
0
−40.3 0.0 −55.8 −33.8
1
−71.7 −73.6 −50.6 −70.4 −64.8
2
−83.9 −66.5 −59.8 −71.3 −84.7
3
−94.7 −77.6 −92.6 −83.8 −90.6
4
−91.4 −71.1 −89.7 −98.2 −96.3 <100
5
−83.1 −90.3 −92.9 −97.3 <100
6
<100 −91.4 <100 <100 <100
7
N
3800 MHz Downconvert Performance
VS = 5 V, VSET = 3.8 V, TA = 25°C, RF power = 0 dBm, LO power = 0 dBm, fRF = 3800 MHz, fLO = 3500 MHz, Z0 = 50 Ω.
M
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
N
<100 −96.6 <100 −91.8 <100
8
<100 −97.9 <100 −98.5 <100
9
<100 −93.5 <100 −98.8 <100
10
<100 <100 <100 <100 <100
11
<100 <100 <100 <100 <100
12
<100 <100 <100 <100
13
<100 <100 <100
14
<100
15
−27.3
0
−33.7 0.0 −54.9
1
−78.5 −47.1 −66.4
2
−63.6 −57.8 −81.4
3
−89.6 −77.2 −72.2 −99.2
4
<100 −88.0 −80.4 <100
5
<100 −90.0 −90.4 <100
6
<100 −79.1 <100 <100
7
<100 −85.2 <100 <100
8
<100 <100 <100
9
<100 −95.9 <100
10
<100 <100 <100
11
<100 <100 <100
12
<100 <100 <100
13
<100 <100
14
<100
15
Rev. A | Page 24 of 36
ADL5801
5800 MHz Downconvert Performance
VS = 5 V, VSET = 3.8 V, TA = 25°C, RF power = 0 dBm, LO power = 0 dBm, fRF = 5800 MHz, fLO = 5600 MHz, Z0 = 50 Ω.
M
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
−44.9
0
−43.9 0.0 −68.9
1
−44.0 −78.0
2
−47.0 −93.3
3
−60.6 −87.8
4
−62.7 −85.7
5
−70.2 −97.8
6
−79.5 −85.3
7
N
806 MHz Upconvert Performance
VS = 5 V, VSET = 3.8 V, TA = 25°C, RF power = 0 dBm, LO power = 0 dBm, fRF = 140 MHz, fLO = 946 MHz, Z0 = 50 Ω.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
N
−71.2 <100
8
<100 <100
9
<100 <100
10
<100 <100
11
<100 <100
12
−100.3 <100
13
−95.6 −96.0
14
<100
15
M
−35.2 −22.9 −42.8 −28.4 −59.1 −40.1
0
−66.0 0.0 −67.7 −14.0 −70.0 −37.1 −74.3
1
−67.8 −66.0 −62.9 −65.3 −61.1 −84.1 −81.2
2
−99.2 −66.2 −92.2 −69.2 −84.9 −84.3 <100
3
−77.1 −97.2 −85.1 −97.8 −82.0 <100 <100
4
−88.7 <100 −88.5 −92.9 −96.4 −93.6 <100 <100
5
−86.1 <100 −92.7 −95.8 −87.5 −99.5 <100 <100
6
−90.2 <100 <100 −84.6 <100 −88.0 <100 <100
7
−73.8 <100 −94.8 −96.4 −93.4 −99.6 <100 <100
8
−91.1 −96.3 <100 −91.5 −100.3 −93.3 <100 <100
9
−66.2 <100 <100 <100 −88.3 −100.0 <100 <100
10
−87.7 −93.6 <100 −95.9 <100 <100 <100 <100
11
−69.5 −89.1 <100 <100 −93.8 <100 <100 <100 <100
12
−85.2 −95.7 <100 <100 −97.7 −90.5 −96.0 <100 <100
13
−65.2 −85.9 <100 −93.1 −94.5 <100 <100 <100 <100
14
−91.3 −93.5 <100 −96.6 v98.7 −93.5 −99.6 <100 <100
15
Rev. A | Page 25 of 36
ADL5801
2210 MHz Upconvert Performance
VS = 5 V, VSET = 4.0 V, TA = 25°C, RF power = 0 dBm, LO power = 0 dBm, fRF = 140 MHz, fLO = 2350 MHz, Z0 = 50 Ω.
M
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 −21.0 −12.8
1 −81.3 0.0 −70.1
2 −66.0 −58.8 −51.5
3 <100 −56.7 −78.2
4 −74.4 −86.3 −76.5
5 <100 −75.3 −88.0
6 −90.9 −81.4 −91.5
7 −96.4 −71.2 −85.9
N
8 −75.8 −89.7 −86.3 <100
9 −92.9 −86.2 −92.2 <100
10 −66.5 <100 −97.5 <100
11 −83.7 −98.4 −97.9 <100
12 −64.8 <100 −93.1 <100
13 −81.2 <100 <100 <100
14 −64.5 <100 −91.0 <100
15 −85.3 <100 <100 −95.4
Rev. A | Page 26 of 36
ADL5801
V
CIRCUIT DESCRIPTION
The ADL5801 includes a double-balanced active mixer with a
50 input impedance and 250 output impedance. In addition,
the ADL5801 integrates a local oscillator (LO) amplifier and
an RF power detector that can be used to optimize the mixer
dynamic range. The RF and LO are differential, providing maximum usable bandwidth at the input and output ports. The LO
also operates with a 50 input impedance and can, optionally,
be operated differentially or single ended. The input, output, and
LO ports can be operated over an exceptionally wide frequency
range. The ADL5801 can be configured as a downconvert mixer
or as an upconvert mixer.
The ADL5801 can be divided into the following sections: the
LO amplifier and splitter, the RF voltage-to-current (V-to-I)
converter, the mixer core, the output loads, the RF detector, and
the bias circuit. A simplified block diagram of the device is
shown in Figure 87. The LO block generates a pair of
differential LO signals to drive two mixer cores. The RF input
power is converted into RF currents by the V-to-I converter that
then feed into the two-mixer core. The internal differential load
of the mixer provides a wideband 250 output impedance from
the mixer. Reference currents to each section are generated by
the bias circuit, which can be enabled or disabled using the ENBL
pin. A detailed description of each section of the ADL5801
follows.
GND
GND
LOIP
LOIN
GND
GND
1
ADL5801
2
3
4
5
6
PLO
24
78
NCGND
GNDVPLO ENBL VSET
Figure 87. Block Diagram
IFOP
GNDIFON
212223
9101112
1920
V2I
DET
DETO GND
18
VPRF
17
GND
16
RFIP
RFIN
15
14
GND
VPDT
13
8079-127
LO AMPLIFIER AND SPLITTER
The LO input is conditioned by a series of amplifiers to provide
a well controlled and limited LO swing to the mixer core, resulting in excellent input IP3. The LO input is amplified using a
broadband low noise amplifier (LNA) and is then followed by
LO limiting amplifiers. The LNA input impedance is nominally
50 . The LO circuit exhibits low additive noise, resulting in an
excellent mixer noise figure and output noise under RF
blocking. For optimal performance, the LO inputs should be
driven differentially but at lower frequencies; single-ended drive
is acceptable.
RF VOLTAGE-TO-CURRENT (V-TO-I) CONVERTER
The differential RF input signal is applied to a V-to-I converter
that converts the differential input voltage to output currents.
The V-to-I converter provides a 50 Ω input impedance. The V-toI section bias current can be adjusted up or down using the
VSET pin. Adjusting the current up improves IP3 and P1dB
input but degrades the SSB noise figure. Adjusting the current
down improves the SSB noise figure but degrades IP3 and P1dB
input. Conversion gain remains nearly constant over a wide
range of VSET pin settings, allowing the part to be adjusted
dynamically without affecting conversion gain.
Internally, the VSET pin features a series resistance and diode to
ground; hence a simple voltage divider driving the pin is not
sufficient. Current adjustment can be made by connecting a
resistor from the VSET pin to the positive supply, however. Tab l e 4
lists some typical values for this resistor and the resulting VSET
value and supply current. Use Ta b le 4 to select the appropriate
value of R10 (see Figure 97) to achieve the desired mixer bias
level. In this mode of operation, R7 and R9 should remain open.
Table 4. Suggested Values of R10 to Achieve the Desired
Mixer Bias Level
R10 (Ω) VSET (V) I
POS
226 4.5 160
562 4.01 146
568 4 145
659 3.9 142
665 3.89 142
694 3.85 142
760 3.8 139
768 3.79 139
1000 3.6 133
1100 3.53 131
1150 3.5 130
1200 3.47 129
1300 3.4 127
1400 3.35 126
1500 3.3 124
1600 3.26 122
1700 3.21 121
1800 3.17 120
1900 3.14 119
2000 3.1 118
2300 3 114
5900 2.5 98
Open 2.03 82
1
I
is the mixer supply current.
POS
(mA)
1
Rev. A | Page 27 of 36
ADL5801
Optionally, the VSET pin can be connected to the DETO pin to
provide automatic setting of the mixer core current.
MIXER CORE
The ADL5801 has a double-balanced mixer that uses high performance SiGe NPN transistors. This mixer is based on the
Gilbert cell design of four cross-connected transistors.
MIXER OUTPUT LOAD
The mixer load uses a pair of 125 resistors connected to the
positive supply. This provides a 250 differential output resistance. The mixer output should be pulled to the positive supply
externally using a pair of RF chokes or using an output transformer with the center tap connected to the positive supply. It
is possible to exclude these components when the mixer core
current is low, but both P1dB input and IP3 input are then
reduced.
The mixer load output can operate from direct current (dc) up
to approximately 600 MHz into a 200 load. For upconversion
applications, the mixer load can be matched using off-chip
matching components. Transmit operation up to 3 GHz is
possible. See the Applications Information section for matching
circuit details.
RF DETECTOR
An RF power detector is buffered from the V-to-I converter
section. This detector has a power response range from
approximately −25 dBm up to 0 dBm and provides a current
output. The output current is designed to be connected to the
VSET pin to boost the mixer core current when large RF signals
are present at the mixer input. An external capacitor can be
used to adjust the response time of this function. If not used,
the DETO pin can be left open or connected to ground.
The detector was characterized under the conditions specified
in the Downcoverter Mode with a Broadband Balun section.
Pin 11 (DETO) was connected to Pin 10 (VSET), and the
voltage on these pins was plotted vs. the RF input power level
over temperature and a number of devices.
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
DETECTOR OUT PUT VOLTAGE (V)
2.2
2.0
–35 –30 –25 –20 –15 –10 –5 0 5
Figure 88. Detector Output Voltage vs. RF Input
+85°C
+25°C
–40°C
RF INPUT (d Bm)
08079-087
The input IP3, gain and supply current were also recorded
under these conditions. The result can be seen in Figure 89
through Figure 91.
40
35
30
25
20
15
INPUT IP3 (dBm)
10
–5
5.0
4.0
3.0
2.0
1.0
GAIN (dB)
–1.0
–2.0
–3.0
–4.0
–5.0
160
140
120
100
80
60
SUPPLY CURRENT (mA)
40
20
+85°C
+25°C
–40°C
5
0
–35 –30 –25 –20 –15 –10 –5 0 5
RF INPUT (dBm)
Figure 89. Input IP3 vs. RF Input
+85°C
+25°C
–40°C
0
–35 –30 –25 –20 –15 –10 –5 0 5
RF INPUT (dBm)
Figure 90.Power Conversion Gain vs. RF Input
+85°C
+25°C
–40°C
0
–35 –30 –25 –20 –15 –10 –5 0 5
RF INPUT (dBm)
Figure 91. Supply Current vs. RF Input
08079-088
8079-090
08079-089
Rev. A | Page 28 of 36
ADL5801
BIAS CIRCUIT
A band gap reference circuit generates the reference currents
used by mixers. The bias circuit can be enabled and disabled
using the ENBL pin. If the ENBL pin is grounded or left open,
the part is enabled. Pulling the ENBL pin high shuts off the bias
circuit and disables the part. However, the ENBL pin does not
alter the current in the LO section and, therefore, does not
provide a true power-down feature. In addition, if the VSET pin
is connected to the positive supply through a resistor to increase
the mixer core current, this continues to provide bias current to
the mixer core unless the resistor supply is also removed.
Rev. A | Page 29 of 36
ADL5801
APPLICATIONS INFORMATION
BASIC CONNECTIONS
The ADL5801 is designed to translate between radio frequencies
(RF) and intermediate frequencies (IF). For both upconversion
and downconversion applications, RFIP (Pin 16) and RFIN
(Pin 15) must be configured as the input interfaces. IFOP
(Pin 20) and IFON (Pin 21) must be configured as the output
interfaces. Individual bypass capacitors are needed in close
proximity to each supply pin (Pin 7, Pin 13, Pin 18, and Pin 24),
the VSET control pin (Pin 10), and the DETO detector output pin
(Pin 11). When the on-chip detector is chosen to form a closed
loop, automatically controlling the VSET pin, R7 can be
populated with a 0 Ω resistor. Alternatively, simply use a jumper
between the VSET and DETO test points for evaluation. Figure 92
illustrates the basic connections for ADL5801 operation.
VPOS
C2
C3
24
1
GND
C50
R50
L1
C20
23 22 21 20 19
NC
GNDVPLO
R3
IFOP
RF AND LO PORTS
The RF and LO input ports are designed for a differential input
impedance of approximately 50 Ω. Figure 93 and Figure 94
illustrate the RF and LO interfaces, respectively. It is recommended
that each of the RF and LO differential ports be driven through a
balun for optimum performance. It is also necessary to ac couple
both RF and LO ports. Using proper value capacitors may help
improve the input return loss over desired frequencies. Tabl e 5
and Tabl e 8 list the recommended components for various RF
and LO frequency bands in upconvert and downconvert modes.
The characterization data is available in the Typ i c al Pe rformance
Characteristics section.
IFON
T1
T5
R13R11
T8
R2
L3
C13
IFOP
L2
GNDIFON
VPRF
C19
18
VPOS
C10
VPOS
LOIN
LOIP
R14
R16
GND
2
C4
LOIP
3
ADL5801
4
T2
T4
T7
VPOS
LOIN
C5
5
GND
6
GND
VPLO ENBL VSET
7 8 9 10 11 12
C7
C6
GND
ENBL
DETO
DETO GND
C1 C12
R7
GND
RFIP
RFIN
GND
VPDT
C18
17
C8
R10
C17
R9
L4
L5
C9
VSET
16
15
14
13
T3
T6
T9
VPOS
R12
R8
RFIP
R4
RFIN
08079-128
Figure 92. Basic Connections Schematic
Rev. A | Page 30 of 36
ADL5801
V
17
GND
C8
RFIP
16
RFIP
ADL5801
15
RFIN
GND
14
T3
C9
08079-129
Figure 93. RF Interface
GND
1
GND
2
C4
LOIP
3
ADL5801
4
LOIP
T2
LOIN
C5
5
GND
6
GND
08079-130
Figure 94. LO Interface
Table 5. Suggested Components for the RF and LO Interfaces
in Downconvert Mode
RF and LO
Frequency T2, T3 C8, C9 C4, C5
900 MHz Mini-Circuits TC1-1-13M+ 5.6 pF 100 pF
1900 MHz Mini-Circuits TC1-1-13M+ 5.6 pF 100 pF
2500 MHz Mini-Circuits TC1-1-43M+ 2 pF 8 pF
3500 MHz 3600BL14M050 1.5 pF 1.5 pF
5500 MHz 5400BL14B050 3 pF 3 pF
Table 6. Suggested Components for the RF Interface in
Upconvert Mode
RF Frequency T3 C8, C9
153 MHz TC1-1-13M+ 470 pF
IF PORT
The IF port features an open-collector, differential output
interface. It is necessary to bias the open collector outputs using
one of the schemes presented in Figure 95 and Figure 96.
Figure 95 shows the use of center-tapped impedance transformers.
The turns ratio of the transformer should be selected to provide
the desired impedance transformation. In the case of a 50
load impedance, a 4:1 impedance ratio transformer should be
used to transform the 50 Ω load into a 200 Ω differential load at
the IF output pins.
Figure 96 shows a differential IF interface where pull-up choke
inductors are used to bias the open-collector outputs. The
shunting impedance of the choke inductors used to couple dc
current into the mixer core should be large enough at the IF
frequency of operation not to load down the output current
before it reaches the intended load. Additionally, the dc current
handling capability of the selected choke inductors must be at
least 45 mA.
The self-resonant frequency of the selected choke inductors
must be higher than the intended IF frequency. A variety of
suitable choke inductors is commercially available from
manufacturers such as Coilcraft® and Murata. An impedance
transforming network may be required to transform the final
load impedance to 200 Ω at the IF outputs.
Tabl e 7 lists suggested components for the IF port in the
upconvert and downconvert modes.
IFOP
T1
T5
R3 R2
C13
NCGND
ADL5801
T8
L3
GNDIFON IFOP
08079-131
VPOS
C50
23 22 21 20 19
Figure 95. Biasing the IF Port Open-Collector Outputs
Using a Center-Tapped Impedance Transformer
Z
L
IMPEDANCE
TRANSFORMI NG
NETWORK
R3 R2
POS VPOS
L1 L2
C20
23 22 21 20 19
L3
C13
NCGND
ADL5801
T1
T5
T8
C19
GNDIFON IFOP
08079-132
Figure 96. Biasing the IF Port Open-Collector Outputs
Using Pull-Up Choke Inductors
Table 7. Suggested Components for the IF Port in Upconvert
and Downconvert Modes
Mode of
IF Frequency
Operation
T1 L3
0 MHz to 500 MHz Downconvert TC4-1W+ Open
900 MHz Upconvert TC4-14+ 27 nH
2140 MHz Upconvert 1850BL15B200 3.3 nH
Rev. A | Page 31 of 36
ADL5801
EVALUATION BOARD
An evaluation board is available for the ADL5801. The standard evaluation board is fabricated using Rogers® RO3003 material. Each RF,
LO, and IF port is configured for single-ended signaling via a balun transformer. The schematic for the evaluation board is shown in
Figure 97. Ta b le 8 describes the various configuration options for the evaluation board. Layout for the board is shown in Figure 98 and
Figure 99.
IFON
IFOP
T1
T5
R13R11
T8
C50
R50
C20
GNDVPLO
R3
L1 L2
L3
C13
23 22 21 20 19
NC
IFOP
ADL5801
R2
VPOS
C19
VPRF
GND
RFIP
RFIN
GND
C10
18
17
16
15
14
VPOS
L4
C8
L5
C9
R8
RFIP
T3
T6
R12
T9
RFIN
GNDIFON
LOIN
LOIP
R14
R16
VPOS
C2
C3
24
1
GND
GND
2
C4
LOIP
3
4
T2
T4
T7
LOIN
C5
5
GND
VPOS
6
GND
VPLO ENBL VSET
7 8 9 10 11 12
C7
C6
Figure 97. Evaluation Board Schematic
GND
ENBL
DETO
C1 C12
VPDT
DETO GND
R7
C18
13
R10
C17
R9
C11
VSET
VPOS
08079-133
Rev. A | Page 32 of 36
ADL5801
Table 8. Evaluation Board Configuration
Components Function Default Conditions
C2, C3, C6, C7, C10, C11
C8, C9, L4, L5, R4, R8,
R12, T3, T6, T9, RFIN,
RFIP
C13, C19, C20, C50, L1,
L2, L3, R2, R3, R11, R13,
R50, T1, T5, T8, IFON,
IFOP
C4, C5, R14, R16, T2, T4,
T7, LOIN, LOIP
C1, C12, R7, DETO
C17, C18, R9, R10, VSET
Power supply decoupling. Nominal supply decoupling consists of a
0.1 μF capacitor to ground in parallel with 100 pF capacitors to ground,
positioned as close to the device as possible. Series resistors are provided
for enhanced supply decoupling using optional ferrite chip inductors.
RF input interfaces. Input channels are ac-coupled through C8 and C9.
R8 and R12 provide options when additional matching is needed. T3 is
a 1:1 balun used to interface to the 50 Ω differential inputs. T6 and T9
provide options when high frequency baluns are used and require smaller
balun footprints.
IF output interfaces. The 200 Ω open collector IF output interfaces are
biased through the center tap of a 4:1 impedance transformer at T1. C50
provides local bypassing with R50 available for additional supply
bypassing. L1 and L2 provide options when pull-up choke inductors are
used to bias the open-collector outputs. C13, L3, R2, and R3 are provided
for IF filtering and matching options. T5 and T8 provide options when high
frequency baluns are used and require smaller balun footprints.
LO interface. C4 and C5 provide ac coupling for the local oscillator input.
T2 is a 1:1 balun that allows single-ended interfacing to the differential
50 Ω local oscillator input. T4 and T7 provide options when high frequency
baluns are used and require smaller balun footprints.
DETO interface. C1 and C12 provide decoupling for the DETO pin. R7
provides access to the VSET pin when automatic input IP3 control is
needed.
VSET bias control. C17 and C18 provide decoupling for the VSET pin. R9
and R10 form an optional resistor divider network between VPOS and
GND, allowing for a fixed bias setting. Supply 3.8 V at the VSET pin when
the DETO pin is not connected for automatic input IP3 control.
C2, C6, C10, C11 = 0.1 μF (size 0402)
C3, C7 = 100 pF (size 0402)
C8, C9 = 5.6 pF (size 0402)
L4, L5, R12 = 0 Ω (size 0402)
R4, R8 = open (size 0402)
T3 = TC1-1-13M+ (Mini-Circuits)
C13 = open (size 0402)
C19, C20 = 100 pF (size 0402)
C50 = 0.1 μF (size 0402)
L1, L2 = open (size 0805)
L3 = open (size 0402)
R2, R3, R13, R50 = 0 Ω (size 0402)
R11 = open (size 0402)
T1 = TC4-1W+ (Mini-Circuits)
C4, C5 = 100 pF (size 0402)
R14 = 0 Ω (size 0402)
R16 = open (size 0402)
T2 = TC1-1-13M+ (Mini-Circuits)
C1 = 0.1 μF (size 0603)
C12 = 100 pF (size 0402)
R7 = open (size 0402)
C17 = 100 pF (size 0402)
C18 = 0.1 μF (size 0603)
R9, R10 = open (size 0402)
8079-134
Figure 98. Evaluation Board Top Layer
Figure 99. Evaluation Board Bottom Layer
08079-135
Rev. A | Page 33 of 36
ADL5801
OUTLINE DIMENSIONS
0.60 MAX
PIN 1
INDICATOR
1
19
18
(BOTTOMVIEW)
13
12
24
EXPOSED
PA D
6
7
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
2.65
2.50 SQ
2.35
0.23 MIN
082908-A
PIN 1
INDICATOR
1.00
0.85
0.80
SEATING
PLANE
12° MAX
4.00
BSC SQ
TOP
VIEW
0.80 MAX
0.65 TYP
0.30
0.23
0.18
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-8
3.75
BSC SQ
0.20 REF
0.60 MAX
0.05 MAX
0.02 NOM
COPLANARITY
0.50
BSC
0.08
0.50
0.40
0.30
2.50 REF
Figure 100. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad (CP-24-3)
Dimensions shown in millimeters
ORDERING GUIDE
Package
Model1 Temperature Range Package Description
Option
ADL5801ACPZ-R7 −40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-24-3 1,500 per Reel
ADL5801-EVALZ Evaluation Board 1
1
Z = RoHS Compliant Part.
Ordering
Quantity
Rev. A | Page 34 of 36
ADL5801
NOTES
Rev. A | Page 35 of 36
ADL5801
NOTES
©2010-2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08079-0-6/11(A)
Rev. A | Page 36 of 36
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