Fixed gain of 29 dB
Operation from 2.3 GHz to 2.4 GHz
EVM ≤ 3% at P
Input internally matched to 50 Ω
Power supply: 3.2 V to 4.2 V
Quiescent current
130 mA in high power mode
70 mA in low power mode
Power-added efficiency (PAE): 20%
Multiple operating modes to reduce battery drain
Low power mode: 100 mA
Standby mode: 1mA
Sleep mode: <1 μA
APPLICATIONS
WiMAX/WiBro mobile terminals
= 25 dBm with 16 QAM OFDMA
OUT
WiMAX Power Amplifier
FUNCTIONAL BLOCK DIAGRAM
FIRST
IM1IM2IM3
RFIN
STBY
VREG
MODE
STAGE
CC1
SECOND
STAGE
BIAS_2BIAS_1BIAS_3
Figure 1.
THIRD
STAGE
ADL5570
CC2
RFOUT
OM
CFLT
06729-001
GENERAL DESCRIPTION
The ADL5570 is a high linearity 2.3 GHz to 2.4 GHz power
amplifier designed for WiMAX terminals using TDD operation
at a duty cycle of 31%. With a gain of 29 dB and an output
compression point of 31 dBm at 2.35 GHz, it can operate at
an output power level up to 26 dBm while maintaining an EVM
of ≤3% (OFDM 16 or 64 QAM) with a supply voltage of 3.5 V.
PAE is 20% @ P
The ADL5570 RF input is matched on-chip and provides an
input return loss of less than −10 dB. The open-collector output is
externally matched with strip-line and external shunt capacitance.
= 25 dBm.
OUT
The ADL5570 operates over a supply voltage range from 3.2 V
to 4.2 V with a supply current of 440 mA burst rms when
delivering 25 dBm (3.5 V supply). A low power mode is also
available for operation at power levels of ≤10 dBm with
optimized operating and quiescent currents of 100 mA and
70 mA, respectively. A standby mode is available that reduces
the quiescent current to 1 mA, which is useful when a TDD
terminal is receiving data.
The ADL5570 is fabricated in a GaAs HBT process and is packaged
in a 4 mm × 4 mm, 16-lead, Pb-free RoHS-compliant LFCSP
that uses an exposed paddle for excellent thermal impedance.
It operates from −40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
MODE 3 V
RFOUT (Modulated—High Power Mode)
Output Load VSWR 10:1
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Maximum Solder Reflow Temperature 260°C (30 sec)
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. 0 | Page 4 of 12
Page 5
ADL5570
V
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
2
GND
STBY
NC
VCC
2
1
4
3
PIN 1
5VCC1
INDICATOR
6RFIN
ADL5570
7GND
TOP VIEW
8
REG
NC = NO CONNECT
(Not to Scale)
9
CFLT
10
MODE
16 NC
15 RFOUT
14 RFOUT
13 NC
11
12
NC
NC
06729-002
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1, 11 to 13, 16 NC No Connect. Do not connect these pins.
2 VCC2 This power supply pin should be connected to the supply via a choke circuit (see Figure 10).
3, 7 GND Connected to Ground.
4 STBY
When STBY is low (0 V), the device operates in transmit mode. When the radio is receiving data,
STBY can be taken high (2.5 V), reducing supply current to 1 mA.
5 VCC1 Connect to Power Supply.
6 RFIN Matched RF Input.
8 VREG
When VREG is low, the device goes into sleep mode, reducing supply current to 10 μA. When VREG
is high (2.85 V), the device operates in its normal transmit mode. When high, VREG draws a bias
current of approximately 10 mA.
9 CFLT A ground-referenced capacitor should be connected to this pin to reduce bias line noise (see Figure 10).
10 MODE
Switches Between High Power and Low Power Modes. When MODE is low (0 V), the device operates
in high power mode. When MODE is high (2.5 V), the device operates in low power mode. See
Table 4
for appropriate biasing. In cases where the MODE feature is not used, this pin should be connected
to ground through a 50 kΩ resistor.
14, 15 RFOUT
Unmatched RF Output. These parallel outputs can be matched to 50 Ω using strip-line and shunt
capacitance. The power supply voltage should be connected to these pins through a choke inductor.
Exposed Paddle
The exposed paddle should be soldered down to a low impedance ground plane (if multiple
ground layers are present, use multiple vias (9 minimum) to stitch together the ground planes) for
optimum electrical and thermal performance.
Table 4. V
= 3.5 V Operating Modes
CC
Mnemonic High Power Mode, P
1
> 10 dBm Low Power Mode, P
OUT
≤ 10 dBm Standby Mode Sleep Mode
OUT
VREG High High High Low
MODE Low High X X
STBY Low Low High X
1
X = don’t care.
Table 5. VREG, MODE, and STBY Pins
Mnemonic Nominal High (V) High Range (V) Nominal Low (V) Low Range (V)
VREG 2.85 2.75 to 2.95 0 NA
MODE 2.5 >2.4 0 <1
STBY 2.5 >2.4 0 <1
Figure 9. WiMAX Spectrum with WiBro Spectral Mask at
2.35 GHz, V
= 3.5 V, P
CC
= 25 dBm
OUT
Rev. 0 | Page 7 of 12
Page 8
ADL5570
V
V
APPLICATIONS
BASIC CONNECTIONS
Figure 10 shows the basic connections for the ADL5570.
POS
STBY
C6
L1
VCC1
RFIN
GND
VREG
C2
C10
0.01µF
4
STBY
ADL5570
CFLT
9
1nH
3
GND
E
MOD
10
R1
50kΩ
2
VCC2
NC
11
MODE
RFOUT
RFOUT
VPOS1
VPOS
C7
0.01µF
RFIN
L3
2.7nH
VREG
C9
0.01µF
NC = NO CONNEC T
C8
0.01µF
5
6
7
8
2.2pF
Figure 10. ADL5570 Basic Connections
Power Supply
The voltage supply on the ADL5570, which ranges from
3.2 V to 4.2 V, should be connected to the VCCx pins. VCC1 is
decoupled with Capacitor C7, whereas VCC2 uses a tank circuit
to prevent RF signals from propagating on the dc lines.
RF Input Interface
The RFIN pin is the port for the RF input signal to the
power amplifier. The L3 inductor, 2.7 nH, matches the input
impedance to 50 Ω.
2.7nH
L3
Figure 11. RF Input with Matching Component
3.6pF
1
NC
NC
12
C11
1µF
VPOS1
L2
C5
11nH
NC
16
15
14
NC
13
W1
6
RFIN
06729-004
3.3pF
C4
39pF
C3
OPEN
VPOS
RFOUT
C12
1µF
06729-003
RF Output Interface
The parallel RF output ports have a shunt capacitance, C3 (3.3 pF),
and the line inductance of the microstrip-line for optimized
output power and linearity. The characteristics of the ADL5570
are described for 50 Ω impedance after the output matching
capacitor (load after C3).
POS1
RFOUT
RFOUT
15
14
11pF
L2
C4
39pF
C3
3.3pF
C5
OPEN
C12
1µF
RFOUT
06729-005
Figure 12. RF Output
C4 provides dc blocking on the RF output.
Transmit/Standby Enable
During normal transmit mode, the STBY pin is biased low
(0 V). However, during receive mode, the pin can be biased
high (2.5 V) to shift the device into standby mode, which
reduces current consumption to less than 1 mA.
VREG Enable
During normal transmit, the VREG pin is biased to 2.85 V and
draws 10 mA of current. When the VREG pin is low (0 V), the
device suspends itself into sleep mode (irrespective of supply
and MODE biasing). In this mode, the device draws 10 μA of
current.
MODE High Power/Low Power Enable
The MODE pin is used to choose between high power mode
and low power mode. When MODE is biased low (0 V), the
device operates in high power mode. When MODE is biased
high (2.5 V), the device operates in low power mode. Appropriate
biasing must be followed for 3.5 V and 4.2 V operation. See
Tabl e 4 and Ta b le 5 for configuration of the MODE pin.
Rev. 0 | Page 8 of 12
Page 9
ADL5570
−
Ι
64 QAM OFDMA PERFORMANCE
The ADL5570 shows exceptional performance when used with
a higher order modulation scheme, such as a 64 QAM system.
Figure 13, Figure 14, and Figure 15 illuminate the EVM, gain,
and current consumption performance within the context of
a 64 QAM OFDMA system.
19
18
17
16
15
14
13
12
11
10
9
EVM (%)
8
7
6
5
4
3
2
1
0
05101520253035
P
(dBm)
OUT
Figure 13. EVM vs. P
V
= 3.5 V and 64 QAM OFDMA Signal
CC
32
31
30
GAIN (dB)
29
28
22802300232023402360238024002420
OUT
FREQUENCY (M Hz)
Figure 14. Gain vs. Frequency Performance at
= 3.5 V and 64 QAM OFDMA Signal
V
CC
2350MHz
2400MHz
Performance at
2300MHz
06729-006
6729-007
0.9
0.8
0.7
0.6
0.5
0.4
CURRENT (A)
0.3
0.2
0.1
0
05101520253035
P
(dBm)
OUT
Figure 15. Burst Current vs. P
at VCC = 3.5 V, 64 QAM,
OUT
06729-008
2350 MHz, 31% 802.16e OFDMA Signal
POWER-ADDED EFFICIENCY
The efficiency of the ADL5570 is defined on the current that it
draws during the data burst of an 802.16e OFDMA signal. In
typical test setup, the average rms current, I
However,
= Duty Cycle (in decimal) × I
I
AVG
(1 − Duty Cycle [in decimal]) × I
BURST
DEFAULT
where:
is the rms current during the data burst of an
I
BURST
OFDMA signal.
I
can be the quiescent current drawn when there is no
DEFAULT
data burst and the device remains biased, the sleep current
(1 mA) if the device is defaulted to sleep mode, or the
standby current.
For example, in a 31% duty cycle 802.16e OFDMA signal,
the burst current is calculated by rearranging the previous
equation to get
BURST
0.31
AVG
=
II×
DEFAULT
)0.69(
Finally, the PAE is calculated by
(%)×
PAE
=
CC
−
×
IV
BURST
When RF = 2.35 GHz, 31% 16 QAM OFDMA signal,
V
= 3.5 V, RF output power = 25 dBm, and RF input
CC
power = −4 dBm, the ADL5570 consumes a burst current,
= 450 mA and PAE = 21%.
I
BURST
AVG
+
(mA)(V)
, is measured.
(mW)(mW)
PowerInputRFPowerOutputRF
100
Rev. 0 | Page 9 of 12
Page 10
ADL5570
EVALUATION BOARD
The evaluation board layout is shown in Figure 16. The ADL5570
performance data was taken on a FR4 board. During board
layout, 50 Ω RF trace impedance must be ensured. The output
matching capacitor, C3, is placed 30 mils from the package edge.
L3 Input Interface: L3 matches the input to 50 Ω. L3 = 2.7 nH (Size 0402)
C3, C4 Output Interface: C4 provides dc blocking, and C3 matches the output to 50 Ω.
C2
C7 to C12
L1, L2, C6, C5
Transmit/Standby Mode: When STBY is low (0 V), the device operates in transmit
mode. When the radio is receiving data, STBY can be taken high (2.5 V), reducing
the supply current to 10 mA.
Normal/Sleep Mode: When VREG is low, the device goes into sleep mode,
reducing the supply current to 10 μA. When VREG is high (2.85 V), the device
operates in its normal transmit mode. When high, VREG draws a bias current of
approximately 10 mA.
High/Low Power Mode: Switches between high power mode and low power
mode. When MODE is low (0 V), the device operates in high power mode.
When MODE is high (2.5 V), the device operates in low power mode.
Filter Interface: A ground-referenced capacitor should be connected to this
node to reduce bias line noise.
Power Supply Decoupling: The capacitors, C7 through C12, are used for power
supply decoupling. They should be placed as close as possible to the DUT.
RF Trap: L1, C6 and L2, C5 form tank circuits and prevent RF from propagating
on the dc supply lines.