Page 1
6 GHz Ultrahigh Dynamic Range
V
V
V
Data Sheet
FEATURES
3 dB bandwidth of 6 GHz (AV = 6 dB)
Pin strappable gain adjust: 6 dB, 12 dB, and 15.5 dB
Gain range from 0 dB to 15.5 dB using two external resistors
Differential or single-ended input to differential output
Low noise input stage: NF = 8.7 dB at 15.5 dB gain
Low broadband distortion (A
10 MHz: −107 dBc (HD2), −110 dBc (HD3)
100 MHz: −108 dBc (HD2), −103 dBc (HD3)
200 MHz: −82 dBc (HD2), −87 dBc (HD3)
500 MHz: −68 dBc (HD2), −63 dBc (HD3)
IMD3 of −113 dBc at 100 MHz center
Slew rate: 11 V/ns
Fast settling and overdrive recovery of 2 ns
Single-supply operation: 2.8 V to 5.2 V
Power down
Fabricated using the high speed XFCB3 SiGe process
APPLICATIONS
Differential ADC drivers
Single-ended-to-differential conversion
RF/IF gain blocks
SAW filter interfacing
GENERAL DESCRIPTION
The ADL5565 is a high performance differential amplifier
optimized for RF and IF applications. The amplifier offers low
noise of 1.5 nV/√Hz and excellent distortion performance over
a wide frequency range making it an ideal driver for high speed
8-bit to 16-bit analog-to-digital converters (ADCs).
The ADL5565 provides three gain levels of 6 dB, 12 dB, and 15.5 dB
through a pin strappable configuration. For the single-ended
input configuration, the gains are reduced to 5.3 dB, 10.3 dB,
and 13 dB. Using two external series resistors expands the gain
flexibility of the amplifier and allows for any gain selection from
0 dB to 15.5 dB for a differential input and 0 dB to 13 dB for a
single-ended input.
= 6 dB)
V
Differential Amplifier
ADL5565
FUNCTIONAL BLOCK DIAGRAM
CC
R
F
R
G2
VIP2
R
G1
VIP1
R
G1
IN1
R
G2
IN2
R
F
ADL5565
GND
Figure 1.
The quiescent current of the ADL5565 is typically 70 mA, and
when disabled, consumes less than 5 mA with −25 dB of inputto-output isolation at 100 MHz.
The device is optimized for wideband, low distortion, and noise
performance, giving it unprecedented performance for overall
spurious-free dynamic range. These attributes, together with its
adjustable gain capability, make this device the amplifier of
choice for driving a wide variety of ADCs, mixers, pin diode
attenuators, SAW filters, and multielement discrete devices.
Fabricated on an Analog Devices, Inc., high speed SiGe process,
the ADL5565 is supplied in a compact 3 mm × 3 mm, 16-lead
LFCSP package and operates over the −40°C to +85°C
temperature range.
ENBL
VON
VCOM
VOP
09959-001
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved.
Page 2
ADL5565 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
3.3 V Specifications ...................................................................... 3
5 V Specifications ......................................................................... 6
Absolute Maximum Ratings ............................................................ 9
ESD Caution .................................................................................. 9
Pin Configuration and Function Descriptions ........................... 10
Typical Performance Characteristics ........................................... 11
Circuit Description ......................................................................... 16
REVISION HISTORY
6/12—Rev. A to Rev. B
Changes to Ordering Guide .......................................................... 26
4/12—Rev. 0 to Rev. A
Changes to Table 3; Added Thermal Resistance Section and
Table 4, Renumbered Sequentially ................................................. 9
Deleted Soldering Information Section ....................................... 23
Added Soldering Information and Recommended PCB
Land Pattern Section and Figure 44, Renumbered
Sequentially ..................................................................................... 23
Updated Outline Dimensions ....................................................... 26
10/11— Revision 0: Initial Version
Basic Structure ............................................................................ 16
Applications Information .............................................................. 17
Basic Connections ...................................................................... 17
Input and Output Interfacing ................................................... 18
Gain Adjustment and Interfacing ............................................ 19
ADC Interfacing ......................................................................... 20
Layout Considerations ............................................................... 22
Soldering Information and Recommended PCB Land
Pattern .......................................................................................... 23
Evaluation Board ........................................................................ 23
Outline Dimensions ....................................................................... 26
Ordering Guide .......................................................................... 26
Rev. B | Page 2 of 28
Page 3
Data Sheet ADL5565
AV = 12 dB, V
≤ 1.0 V p-p
6500
MHz
Input Common-Mode Range
AV = 6 dB, 12 dB, and 15.5 dB
1.2 to 2
V
CMRR
60 dB
ENBL Input Bias Current
ENBL high
500 nA
B
SPECIFICATIONS
3.3 V SPECIFICATIONS
VS = 3.3 V, VCM = 1.65 V, RL = 200 Ω differential, AV = 6 dB, CL = 1 pF differential, f = 100 MHz, TA = 25°C; parameters specified
ac-coupled differential input and differential output, unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth AV = 6 dB, V
AV = 15.5 dB, V
Bandwidth for 0.1 dB Flatness V
≤ 1.0 V p-p 1000 MHz
OUT
Gain Accuracy ±1 dB
Gain Supply Sensitivity VS ± 5% 1.9 mdB/V
Gain Temperature Sensitivity −40°C to +85°C 0.35 mdB/°C
Slew Rate
Rise, A
V
= 2 V step
V
OUT
= 15.5 dB, RL = 200 Ω,
Fall, A
V
= 2 V step
V
OUT
Settling Time 2 V step to 1% 2 ns
Overdrive Recovery Time VIN = 4 V to 0 V step, V
Reverse Isolation (S12) 70 dB
INPUT/OUTPUT CHARACTERISTICS
≤ 1.0 V p-p 6750 MHz
OUT
OUT
≤ 1.0 V p-p 6250 MHz
OUT
= 15.5 dB, RL = 200 Ω,
11 V/ns
11 V/ns
≤ ±10 mV <3 ns
OUT
Output Common-Mode Range 1.4 to 1.8 V
Maximum Output Voltage Swing 1 dB compressed 4 V p-p
Output Common-Mode Offset Referenced to VCC/2 −100 +20 mV
Output Common-Mode Drift −40°C to +85°C 0.34 mV/°C
Output Differential Offset Voltage −20 +20 mV
Output Differential Offset Drift −40°C to +85°C 1.5 mV/°C
Input Bias Current ±5 µA
Input Resistance (Differential) AV = 6 dB 200 Ω
AV = 12 dB 100 Ω
AV = 15.5 dB 67 Ω
Input Resistance (Single-Ended) AV = 5.6 dB 158 Ω
AV = 11.1 dB 96 Ω
AV = 14.1 dB 74 Ω
Input Capacitance (Single-Ended) 0.3 pF
Output Resistance (Differential) 10 Ω
POWER INTERFACE
Supply Voltage 2.8 3.3 5.2 V
ENBL Threshold 1.5 V
ENBL low −165 µA
Quiescent Current ENBL high 70 mA
ENBL low 5 mA
Rev. | Page 3 of 28
Page 4
ADL5565 Data Sheet
AV = 15.5 dB, RL = 200 Ω, V
= 2 V p-p
−106/−112
dBc
Second/Third Harmonic Distortion (HD2/HD3)
AV = 6 dB, RL = 200 Ω, V
= 2 V p-p
−108/−103
dBc
AV = 12 dB, RL = 200 Ω, V
=
+53/−112
dBm/dBc
−85 dBc
AV = 12 dB
12.8 dBm
B
Parameter Test Conditions/Comments Min Typ Max Unit
NOISE/HARMONIC PERFORMANCE
10 MHz
Second/Third Harmonic Distortion (HD2/HD3) AV = 6 dB, RL = 200 Ω, V
AV = 12 dB, RL = 200 Ω, V
Output IP3/Third-Order Intermodulation
Distortion (OIP3/IMD3)
AV = 6 dB, RL = 200 Ω, V
2 V p-p composite (2 MHz spacing)
= 12 dB, RL = 200 Ω, V
A
V
2 V p-p composite (2 MHz spacing)
= 15.5 dB, RL = 200 Ω, V
A
V
2 V p-p composite (2 MHz spacing)
Second-Order Intermodulation Distortion (IMD2)
= 6 dB, RL = 200 Ω, V
A
V
2 V p-p composite (2 MHz spacing)
= 12 dB, RL = 200 Ω, V
A
V
2 V p-p composite (2 MHz spacing)
= 15.5 dB, RL = 200 Ω, V
A
V
2 V p-p composite (2 MHz spacing)
Noise Spectral Density, RTI (NSD) AV = 6 dB 2.24 nV/√Hz
AV = 12 dB 1.52 nV/√Hz
AV = 15.5 dB 1.53 nV/√Hz
Noise Figure (NF) AV = 6 dB 10.24 dB
AV = 12 dB 8.66 dB
AV = 15.5 dB 8.78 dB
1 dB Compression Point, RTO (OP1dB) AV = 6 dB 13.1 dBm
AV = 12 dB 12.8 dBm
AV = 15.5 dB 13.1 dBm
100 MHz
AV = 12 dB, RL = 200 Ω, V
AV = 15.5 dB, RL = 200 Ω, V
Output IP3/Third-Order Intermodulation
Distortion (OIP3/IMD3)
AV = 6 dB, RL = 200 Ω, V
2 V p-p composite (2 MHz spacing)
2 V p-p composite (2 MHz spacing)
= 15.5 dB, RL = 200 Ω, V
A
V
2 V p-p composite (2 MHz spacing)
Second-Order Intermodulation Distortion (IMD2)
= 6 dB, RL = 200 Ω, V
A
V
2 V p-p composite (2 MHz spacing)
AV = 12 dB, RL = 200 Ω, V
2 V p-p composite (2 MHz spacing)
= 15.5 dB, RL = 200 Ω, V
A
V
2 V p-p composite (2 MHz spacing)
Noise Spectral Density, RTI (NSD) AV = 6 dB 2.25 nV/√Hz
AV = 12 dB 1.53 nV/√Hz
AV = 15.5 dB 1.52 nV/√Hz
Noise Figure (NF) AV = 6 dB 10.27 dB
AV = 12 dB 8.69 dB
AV = 15.5 dB 8.7 dB
1 dB Compression Point, RTO (OP1dB) AV = 6 dB 13 dBm
= 2 V p-p −107/−110 dBc
OUT
= 2 V p-p −101/−107 dBc
OUT
OUT
=
OUT
=
OUT
=
OUT
=
OUT
=
OUT
=
OUT
OUT
= 2 V p-p −91/−99 dBc
OUT
= 2 V p-p −89/−100 dBc
OUT
=
OUT
OUT
=
OUT
=
OUT
=
OUT
=
OUT
+48/−100 dBm/dBc
+52/−108 dBm/dBc
+50/−105 dBm/dBc
−86 dBc
−86 dBc
−86 dBc
+54/−113 dBm/dBc
+52/−111 dBm/dBc
−85 dBc
−86 dBc
AV = 15.5 dB 12.8 dBm
Rev. | Page 4 of 28
Page 5
Data Sheet ADL5565
Output IP3/Third-Order Intermodulation
AV = 6 dB, RL = 200 Ω, V
=
+46/−97
dBm/dBc
Second-Order Intermodulation Distortion (IMD2)
−85 dBc
Noise Spectral Density, RTI (NSD)
AV = 6 dB
2.62 nV/√Hz
B
Parameter Test Conditions/Comments Min Typ Max Unit
200 MHz
Second/Third Harmonic Distortion (HD2/HD3) AV = 6 dB, RL = 200 Ω, V
AV = 12 dB, RL = 200 Ω, V
AV = 15.5 dB, RL = 200 Ω, V
Distortion (OIP3/IMD3)
2 V p-p composite
= 12 dB, RL = 200 Ω, V
A
V
2 V p-p composite
= 15.5 dB, RL = 200 Ω, V
A
V
2 V p-p composite
AV = 6 dB, RL = 200 Ω, V
2 V p-p composite (2 MHz spacing)
= 12 dB, RL = 200 Ω, V
A
V
2 V p-p composite (2 MHz spacing)
= 15.5 dB, RL = 200 Ω, V
A
V
2 V p-p composite (2 MHz spacing)
Noise Spectral Density, RTI (NSD) AV = 6 dB 2.36 nV/√Hz
AV = 12 dB 1.64 nV/√Hz
AV = 15.5 dB 1.51 nV/√Hz
Noise Figure (NF) AV = 6 dB 10.65 dB
AV = 12 dB 9.25 dB
AV = 15.5 dB 8.49 dB
500 MHz
Second/Third Harmonic Distortion (HD2/HD3) AV = 6 dB, RL = 200 Ω, V
AV = 12 dB, RL = 200 Ω, V
AV = 15.5 dB, RL = 200 Ω, V
Output IP3/Third-Order Intermodulation
Distortion (OIP3/IMD3)
AV = 6 dB, RL = 200 Ω, V
2 V p-p composite
= 12 dB, RL = 200 Ω, V
A
V
2 V p-p composite
= 15.5 dB, RL = 200 Ω, V
A
V
2 V p-p composite
Second-Order Intermodulation Distortion (IMD2)
= 6 dB, RL = 200 Ω, V
A
V
2 V p-p composite (2 MHz spacing)
= 12 dB, RL = 200 Ω, V
A
V
2 V p-p composite (2 MHz spacing)
= 15.5 dB, RL = 200 Ω, V
A
V
2 V p-p composite (2 MHz spacing)
= 2 V p-p −82/−87 dBc
OUT
= 2 V p-p −72/−86 dBc
OUT
= 2 V p-p −71/−86 dBc
OUT
OUT
=
OUT
=
OUT
=
OUT
=
OUT
=
OUT
= 2 V p-p −68/−63 dBc
OUT
= 2 V p-p −56/−62 dBc
OUT
= 2 V p-p −57/−63 dBc
OUT
=
OUT
=
OUT
=
OUT
=
OUT
=
OUT
=
OUT
+46/−99 dBm/dBc
+46/−98 dBm/dBc
−73 dBc
−70 dBc
+34/−77 dBm/dBc
+36/−82 dBm/dBc
+39/−88 dBm/dBc
−75 dBc
−70 dBc
−70 dBc
AV = 12 dB 1.57 nV/√Hz
AV = 15.5 dB 1.47 nV/√Hz
Noise Figure (NF) AV = 6 dB 11.47 dB
AV = 12 dB 8.93 dB
AV = 15.5 dB 8.07 dB
Rev. | Page 5 of 28
Page 6
ADL5565 Data Sheet
Bandwidth for 0.1 dB Flatness
V
≤ 1.0 V p-p
1000
MHz
11 V/ns
Input Bias Current
±5 µA
Quiescent Current
ENBL high
80 mA
B
5 V SPECIFICATIONS
VS = 5.0 V, VCM = 2.5 V, RL = 200 Ω differential, AV = 6 dB, CL = 1 pF differential, f = 100 MHz, TA = 25°C; parameters specified
ac-coupled differential input and differential output, unless otherwise noted.
Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth AV = 6 dB, V
AV = 12 dB, V
AV = 15.5 dB, V
OUT
Gain Accuracy ±1 dB
Gain Supply Sensitivity VS ± 5% 1.6 mdB/V
Gain Temperature Sensitivity −40°C to +85°C 0.37 mdB/°C
Slew Rate
Rise, A
= 2 V step
V
OUT
Fall, AV = 15.5 dB, RL = 200 Ω,
= 2 V step
V
OUT
Settling Time 2 V step to 1% 2 ns
Overdrive Recovery Time VIN = 4 V to 0 V step, V
Reverse Isolation (S12) 70 dB
INPUT/OUTPUT CHARACTERISTICS
Input Common-Mode Range AV = 6 dB, 12 dB, and 15.5 dB 1.2 to 3.8 V
Output Common-Mode Range 1.4 to 3 V
Maximum Output Voltage Swing 1 dB compressed 8 V p-p
Output Common-Mode Offset Referenced to VCC/2 −100 +20 mV
Output Common-Mode Drift −40°C to +85°C 0.4 mV/°C
Output Differential Offset Voltage −20 +20 mV
CMRR 60 dB
Output Differential Offset Drift −40°C to +85°C 1.5 mV/°C
≤ 1.0 V p-p 7000 MHz
OUT
≤ 1.0 V p-p 6750 MHz
OUT
≤ 1.0 V p-p 6500 MHz
OUT
= 15.5 dB, RL = 200 Ω,
V
≤ ±10 mV <3 ns
OUT
11 V/ns
Input Resistance (Differential) AV = 6 dB 200 Ω
AV = 12 dB 100 Ω
AV = 15.5 dB 67 Ω
Input Resistance (Single-Ended) AV = 5.6 dB 158 Ω
AV = 11.1 dB 96 Ω
AV = 14.1 dB 74 Ω
Input Capacitance (Single-Ended) 0.3 pF
Output Resistance (Differential) 10 Ω
POWER INTERFACE
Supply Voltage 2.8 5 5.2 V
ENBL Threshold 1.5 V
ENBL Input Bias Current ENBL high 1 µA
ENBL low −250 µA
ENBL low 6 mA
Rev. | Page 6 of 28
Page 7
Data Sheet ADL5565
AV = 15.5 dB, RL = 200 Ω, V
= 2 V p-p
−105/−106
dBc
Second/Third Harmonic Distortion (HD2/HD3)
AV = 6 dB, RL = 200 Ω, V
= 2 V p-p
−108/−109
dBc
AV = 12 dB, RL = 200 Ω, V
=
+53/−112
dBm/dBc
−91 dBc
AV = 12 dB
16.5 dBm
B
Parameter Test Conditions/Comments Min Typ Max Unit
NOISE/HARMONIC PERFORMANCE
10 MHz
Second/Third Harmonic Distortion (HD2/HD3) AV = 6 dB, RL = 200 Ω, V
AV = 12 dB, RL = 200 Ω, V
Output IP3/Third-Order Intermodulation
Distortion (OIP3/IMD3)
AV = 6 dB, RL = 200 Ω, V
2 V p-p composite (2 MHz spacing)
= 12 dB, RL = 200 Ω, V
A
V
2 V p-p composite (2 MHz spacing)
= 15.5 dB, RL = 200 Ω, V
A
V
2 V p-p composite (2 MHz spacing)
Second-Order Intermodulation Distortion (IMD2)
= 6 dB, RL = 200 Ω, V
A
V
2 V p-p composite (2 MHz spacing)
= 12 dB, RL = 200 Ω, V
A
V
2 V p-p composite (2 MHz spacing)
= 15.5 dB, RL = 200 Ω, V
A
V
2 V p-p composite (2 MHz spacing)
Noise Spectral Density, RTI (NSD) AV = 6 dB 2.25 nV/√Hz
AV = 12 dB 1.54 nV/√Hz
AV = 15.5 dB 1.55 nV/√Hz
Noise Figure (NF) AV = 6 dB 10.29 dB
AV = 12 dB 8.77 dB
AV = 15.5 dB 9.04 dB
1 dB Compression Point, RTO (OP1dB) AV = 6 dB 16.8 dBm
AV = 12 dB 16.7 dBm
AV = 15.5 dB 16.6 dBm
100 MHz
AV = 12 dB, RL = 200 Ω, V
AV = 15.5 dB, RL = 200 Ω, V
Output IP3/Third-Order Intermodulation
Distortion (OIP3/IMD3)
AV = 6 dB, RL = 200 Ω, V
2 V p-p composite (2 MHz spacing)
2 V p-p composite (2 MHz spacing)
= 15.5 dB, RL = 200 Ω, V
A
V
2 V p-p composite (2 MHz spacing)
Second-Order Intermodulation Distortion (IMD2)
= 6 dB, RL = 200 Ω, V
A
V
2 V p-p composite (2 MHz spacing)
AV = 12 dB, RL = 200 Ω, V
2 V p-p composite (2 MHz spacing)
= 15.5 dB, RL = 200 Ω, V
A
V
2 V p-p composite (2 MHz spacing)
Noise Spectral Density, RTI (NSD) AV = 6 dB 2.28 nV/√Hz
AV = 12 dB 1.53 nV/√Hz
AV = 15.5 dB 1.52 nV/√Hz
Noise Figure (NF) AV = 6 dB 10.39 dB
AV = 12 dB 8.73 dB
AV = 15.5 dB 8.7 dB
1 dB Compression Point, RTO (OP1dB) AV = 6 dB 16.8 dBm
= 2 V p-p −111/−116 dBc
OUT
= 2 V p-p −100/−104 dBc
OUT
OUT
=
OUT
=
OUT
=
OUT
=
OUT
=
OUT
=
OUT
OUT
= 2 V p-p −92/−103 dBc
OUT
= 2 V p-p −89.5/−105 dBc
OUT
=
OUT
OUT
=
OUT
=
OUT
=
OUT
=
OUT
+47/−99 dBm/dBc
+50/−105 dBm/dBc
+50/−105 dBm/dBc
−78 dBc
−86 dBc
−91 dBc
+53/−112 dBm/dBc
+52/−110 dBm/dBc
−87 dBc
−87 dBc
AV = 15.5 dB 16.4 dBm
Rev. | Page 7 of 28
Page 8
ADL5565 Data Sheet
Output IP3/Third-Order Intermodulation
AV = 6 dB, RL = 200 Ω, V
=
+46/−97
dBm/dBc
Second-Order Intermodulation Distortion (IMD2)
−85 dBc
Noise Spectral Density, RTI (NSD)
AV = 6 dB
2.64 nV/√Hz
B
Parameter Test Conditions/Comments Min Typ Max Unit
200 MHz
Second/Third Harmonic Distortion (HD2/HD3) AV = 6 dB, RL = 200 Ω, V
AV = 12 dB, RL = 200 Ω, V
AV = 15.5 dB, RL = 200 Ω, V
Distortion (OIP3/IMD3)
2 V p-p composite
= 12 dB, RL = 200 Ω, V
A
V
2 V p-p composite
= 15.5 dB, RL = 200 Ω, V
A
V
2 V p-p composite
AV = 6 dB, RL = 200 Ω, V
2 V p-p composite (2 MHz spacing)
= 12 dB, RL = 200 Ω, V
A
V
2 V p-p composite (2 MHz spacing)
= 15.5 dB, RL = 200 Ω, V
A
V
2 V p-p composite (2 MHz spacing)
Noise Spectral Density, RTI (NSD) AV = 6 dB 2.43 nV/√Hz
AV = 12 dB 1.63 nV/√Hz
AV = 15.5 dB 1.51 nV/√Hz
Noise Figure (NF) AV = 6 dB 10.88 dB
AV = 12 dB 9.2 dB
AV = 15.5 dB 8.54 dB
500 MHz
Second/Third Harmonic Distortion (HD2/HD3) AV = 6 dB, RL = 200 Ω, V
AV = 12 dB, RL = 200 Ω, V
AV = 15.5 dB, RL = 200 Ω, V
Output IP3/Third-Order Intermodulation
Distortion (OIP3/IMD3)
AV = 6 dB, RL = 200 Ω, V
2 V p-p composite
= 12 dB, RL = 200 Ω, V
A
V
2 V p-p composite
= 15.5 dB, RL = 200 Ω, V
A
V
2 V p-p composite
Second-Order Intermodulation Distortion (IMD2)
= 6 dB, RL = 200 Ω, V
A
V
2 V p-p composite (2 MHz spacing)
= 12 dB, RL = 200 Ω, V
A
V
2 V p-p composite (2 MHz spacing)
= 15.5 dB, RL = 200 Ω, V
A
V
2 V p-p composite (2 MHz spacing)
= 2 V p-p −82/−87 dBc
OUT
= 2 V p-p −72/−86 dBc
OUT
= 2 V p-p −71/−86 dBc
OUT
OUT
=
OUT
=
OUT
=
OUT
=
OUT
=
OUT
= 2 V p-p −69/−66 dBc
OUT
= 2 V p-p −56/−65 dBc
OUT
= 2 V p-p −58/−66 dBc
OUT
=
OUT
=
OUT
=
OUT
=
OUT
=
OUT
=
OUT
+46/−99 dBm/dBc
+46/−98 dBm/dBc
−74 dBc
−70 dBc
+35/−78 dBm/dBc
+35/−81 dBm/dBc
+37/−85 dBm/dBc
−73 dBc
−75 dBc
−72 dBc
AV = 12 dB 1.6 nV/√Hz
AV = 15.5 dB 1.48 nV/√Hz
Noise Figure (NF) AV = 6 dB 11.56 dB
AV = 12 dB 9.06 dB
AV = 15.5 dB 8.17 dB
Rev. | Page 8 of 28
Page 9
Data Sheet ADL5565
Storage Temperature Range
−65°C to +150°C
B
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Output Voltage Swing × Bandwidth Product 2000 V p-p MHz
Supply Voltage, VCC 5.25 V
VIPx, VINx VCC + 0.5 V
±I
Maximum 30 mA
OUT
Internal Power Dissipation 525 mW
Maximum Junction Temperature 125°C
Operating Temperature Range −40°C to +100°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
Table 4 lists the junction-to-air thermal resistance (θJA) and the
junction-to-paddle thermal resistance (θ
) for the ADL5565.
JC
Table 4. Thermal Resistance
Package Type θ
1
θ
JA
2
Unit
JC
16 LFCSP 60 12 °C/W
1
Measured on Analog Devices evaluation board. For more information about
board layout, see the Soldering Information and Recommended PCB Land
Pattern section.
2
Based on simulation with JEDEC standard JESD51.
ESD CAUTION
Rev. | Page 9 of 28
Page 10
ADL5565 Data Sheet
VIP2
VIP1
VIN1
VIN2
VOP
E
NBL
VON
VCOM
VCC
VCC
VCC
VCC
GND
GND
GND
GND
NOTES
1. EXPOSED PADDLE IS INTERNALLY
CONNECT TO GND AND MUS T BE
SOLDERED TO A LOW IMPEDANCE
GROUND PLANE .
12
11
10
1
3
4
9
2
6
5
7
8
16
15
14
13
TOP
VIEW
ADL5565
09959-002
Pin No.
Mnemonic
Description
10
VON
Balanced Differential Output. Biased to VCOM, typically ac-coupled.
B
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
1 VIP2
2 VIP1
3 VIN1
4 VIN2
Balanced Differential Input. Biased to VCOM, typically ac-coupled. Input for A
VIP1 for A
= 15.5 dB.
V
Balanced Differential Input. Biased to VCOM, typically ac-coupled. Input for A
VIP2 for A
= 15.5 dB.
V
Balanced Differential Input. Biased to VCOM, typically ac-coupled. Input for A
VIN2 for A
= 15.5 dB.
V
Balanced Differential Input. Biased to VCOM, typically ac-coupled. Input for A
VIN1 for A
= 15.5 dB.
V
5, 6, 7, 8 VCC Positive Supply.
9 VCOM
Common-Mode Voltage. A voltage applied to this pin sets the common-mode voltage of the input and
output. Typically decoupled to ground with a 0.1 µF capacitor. With no reference applied, input and
output common mode floats to midsupply (VCC/2).
11 VOP Balanced Differential Output. Biased to VCOM, typically ac-coupled.
12 ENBL Enable. Apply positive voltage (1.3 V < ENBL < VCC) to activate device.
13, 14, 15, 16,
Exposed Paddle
GND
Ground. Exposed paddle is internally connected to GND and must be soldered to a low impedance
ground plane.
= 12 dB gain, strapped to
V
= 6 dB gain, strapped to
V
= 6 dB gain, strapped to
V
= 12 dB gain, strapped to
V
Rev. | Page 10 of 28
Page 11
Data Sheet ADL5565
–25
–20
–15
–10
–5
0
5
10
15
20
25
10 100 1000 10000
VOLTAGE GAIN (dB)
FREQUENCY (MHz)
A
V
= 15dB
A
V
= 12dB
A
V
= 6dB
09959-003
–20
–15
–10
–5
0
5
10
15
20
10 100 100001000
VOLTAGE GAIN (dB)
FREQUENCY (MHz)
–40°C
+85°C
+25°C
+100°C
09959-004
10 100 100001000
VOLTAGE GAIN (dB)
FREQUENCY (MHz)
–25
–20
–15
–10
–5
0
5
10
15
20
–40°C
+25°C
+85°C
+100°C
09959-105
0
5
10
15
20
25
0 50 100 150 200 250
OP1dB (d Bm)
FREQUENCY (MHz)
09959-005
AV = 15.5dB
AV = 12dB
A
V
= 6dB
0
5
10
15
20
25
0 50 100 150 200 250
OP1dB (d Bm)
FREQUENCY (MHz)
–40°C
+25°C
+85°C
+100°C
09959-006
0
2
4
6
8
10
12
14
16
18
10 100 1000
NOISE FIGURE (dB)
FREQUENCY (MHz)
09959-007
AV = 6dB
AV = 12dB
AV = 15.5dB
B
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 3.3 V, VCM = 1.65 V, RL = 200 Ω differential, AV = 6 dB, CL = 1 pF differential, f = 100 MHz, TA = 25°C; parameters specified
ac-coupled differential input and differential output, unless otherwise noted.
Figure 3. Gain vs. Frequency Response for 200 Ω Differential Load,
= 6 dB, AV = 12 dB, and AV = 15.5 dB, VPOS = 3.3 V and VPOS = 5 V, 25°C
A
V
Figure 4. Gain vs. Frequency Response for 200 Ω Differential Load,
= 6 dB, Four Temperatures, VPOS = 3.3 V, 25°C
A
V
Figure 6. OP1dB vs. Frequency at Three Gains,
25°C, 200 Ω Differential Load, VPOS = 3.3 V
Figure 7. OP1dB vs. Frequency for 200 Ω Differential Load, AV = 6 dB,
Four Temperatures, VPOS = 3.3 V
Figure 5. Gain vs. Frequency Response for 200 Ω Differential Load,
= 6 dB, Four Temperatures, VPOS = 5 V, 25°C
A
V
Figure 8. Noise Figure vs. Frequency at AV = 6 dB, AV = 12 dB, and AV = 15.5 dB,
VPOS = 3.3 V
Rev. | Page 11 of 28
Page 12
ADL5565 Data Sheet
0
2
4
6
8
10
12
14
16
18
10M 100M 1G
NOISE FIGURE (dB)
FREQUENCY (Hz)
AV = 6dB
A
V
= 12dB
A
V
= 15.5dB
09959-008
10 100 1000
FREQUENCY (MHz)
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
NOISE SPECTRAL DENSITY (nV/√Hz)
AV = 6dB
AV = 12dB
A
V
= 15.5dB
AV = 6dB
AV = 12dB
AV = 15.5dB
09959-009
0
10
20
30
40
50
60
0 50 100 150 200 250 300 350 400 450 500
OIP3 (d Bm)
FREQUENCY (MHz)
5V, AV = 6dB
5V, AV = 12dB
5V, A
V
= 15.5dB
3.3V, A
V
= 6dB
3.3V, AV = 12dB
3.3V, A
V
= 15.5dB
09959-010
0
10
20
30
40
50
60
0 50 100 150 200 250 300 350 400 450 500
OIP3 (d Bm)
FREQUENCY (MHz)
5V, –40°C
5V, +25°C
5V, +85°C
5V, +100°C
3.3V, –40°C
3.3V, +25° C
3.3V, +85° C
3.3V, +100° C
09959-011
0
10
20
30
40
50
60
70
0 1 2 3 4 5 6 7 8 9 10
OIP3 (d Bm)
P
OUT
/TONE (dBm)
3.3V, A
V
= 6dB
3.3V, A
V
= 12dB
3.3V, A
V
= 15.5dB
5V, A
V
= 6dB
5V, A
V
= 12dB
5V, A
V
= 15.5dB
09959-012
–140
–120
–100
–80
–60
–40
–20
0
0 50 100 150 200 250 300 350 400 450 500
IMD3 (dBc)
FREQUENCY (MHz)
3.3V, AV = 6dB
3.3V, AV = 12dB
3.3V, A
V
= 15.5dB
5V, A
V
= 6dB
5V, A
V
= 12dB
5V, AV = 15.5dB
09959-013
B
Figure 9. Noise Figure vs. Frequency at AV = 6 dB, AV = 12 dB, and
= 15.5 dB, VPOS = 5 V
A
V
Figure 10. Noise Spectral Density vs. Frequency at AV = 6 dB, AV = 12 dB, and
= 15.5 dB, VPOS = 3.3 V and VPOS = 5 V
A
V
Figure 12. Output Third-Order Intercept (OIP3) vs. Frequency,
Over Temperature, Output Level at 2 V p-p Composite, R
VPOS = 3.3 V and VPOS = 5 V, Four Temperatures
Figure 13. Output Third-Order Intercept (OIP3) vs. Power (P
Frequency 100 MHz, A
= 15.5 dB, VPOS = 3.3 V and VPOS = 5 V
V
= 200 Ω, Av = 6 dB,
L
),
OUT
Figure 11. Output Third-Order Intercept (OIP3) at Three Gains,
Output Level at 2 V p-p Composite, R
= 200 Ω, VPOS = 3.3 V and VPOS = 5 V
L
Figure 14. Output IMD3 vs. Frequency, Output Level at 2 V p-p Composite,
= 200 Ω, VPOS = 3.3 V and VPOS = 5 V
R
L
Rev. | Page 12 of 28
Page 13
Data Sheet ADL5565
–140
–120
–100
–80
–60
–40
–20
0
0 50 100 150 200 250 300 350 400 450 500
IMD3 (dBm)
FREQUENCY (MHz)
3.3V, –40°C
3.3V, +25° C
3.3V, +85° C
3.3V, +100° C
5V, –40°C
5V, +25°C
5V, +85°C
5V, +100°C
09959-014
25
30
35
40
45
50
55
0 50 100 150 200 250
OIP3 (d Bm)
FREQUENCY (MHz)
09959-015
AV = 5.3dB
AV = 10.3dB
A
V
= 13dB
–140
–120
–100
–80
–60
–40
–20
0
–180
–160
–140
–120
–100
–80
–60
–40
0 50 100 150 200 250 300 350 400 450 500
HD3 (dBc)
HD2 (dBc)
FREQUENCY (MHz)
HD2, 3.3V, AV = 6dB
HD2, 3.3V, A
V
= 12dB
HD2, 3.3V, A
V
= 15.5dB
HD2, 5V, AV = 6dB
HD2, 5V, AV = 12dB
HD2, 5V, AV = 15.5dB
HD3, 3.3V, A
V
= 6dB
HD3, 3.3V, AV = 12dB
HD3, 3.3V, AV = 15.5dB
HD3, 5V, AV = 6dB
HD3, 5V, AV = 12dB
HD3, 5V, AV = 15.5dB
09959-016
–140
–120
–100
–80
–60
–40
–20
0
–180
–160
–140
–120
–100
–80
–60
–40
0 50 100 150 200 250 300 350 400 450 500
HD3 (dBc)
HD2 (dBc)
FREQUENCY (MHz)
HD2, 5V, –40°C
HD2, 5V, +25°C
HD2, 5V, +85°C
HD2, 5V, +100°C
HD2, 3.3V, –40°C
HD2, 3.3V, +25°C
HD2, 3.3V, +85°C
HD2, 3.3V, +100°C
HD3, 5V, –40°C
HD3, 5V, +25°C
HD3, 5V, +85C
HD3, 5V, +100°C
HD3, 3.3V, –40°C
HD3, 3.3V, +25°C
HD3, 3.3V, +85°C
HD3, 3.3V, +100°C
09959-017
P
OUT
/TONE (dBm)
–140
–120
–100
–80
–60
–40
–20
0
–200
–180
–160
–140
–120
–100
–80
–60
–6 –4 –2 0 2 4 6 8 10
HD3 (dBc)
HD2 (dBc)
3.3V, HD2
5V, HD2
3.3V, HD3
5V, HD3
09959-018
–120
–100
–80
–60
–40
–20
0
1.0 1.5 2.0 2.5 3.0
HD2 AND HD3 (dBc)
VCOM
HD2, 5V
HD3, 5V
HD2, 3.3V
HD3, 3.3V
09959-019
B
Figure 15. IMD3 vs. Frequency, Over Temperature, Output Level at
2 V p-p Composite, R
= 200 Ω, AV = 6 dB, VPOS = 3.3 V and VPOS = 5 V,
L
Four Temperatures
Figure 16. Single-Ended OIP3 vs. Frequency
Figure 18. Harmonic Distortion (HD2/HD3) vs. Frequency, Over Temperature,
Output Level at 2 V p-p Composite, R
= 200 Ω, AV = 6 dB, VPOS = 3.3 V and
L
VPOS = 5 V, Four Temperatures
Figure 19. Harmonic Distortion vs. Output Power per Tone,
Frequency = 100 MHz, R
= 200 Ω, VPOS = 3.3 V and VPOS = 5 V
L
Figure 17. Harmonic Distortion (HD2/HD3) vs. Frequency,
Output Level at 2 V p-p Composite, R
Rev. | Page 13 of 28
= 200 Ω, VPOS = 3.3 V and VPOS = 5 V
L
Figure 20. Harmonic Distortion (HD2/HD3) vs. VCOM,
= 6 dB, VPOS = 3.3 V and VPOS = 5 V
A
V
Page 14
ADL5565 Data Sheet
–105
–100
–95
–90
–85
–80
–75
–70
–65
–60
0 50 100 150 200 250 300
HARMONIC DISTORTIO N HD2, HD3 (dBc)
HD2 A
V
= 5.3dB
HD2 A
V
= 10.3dB
HD2 A
V
= 13dB
HD3 A
V
= 5.3dB
HD3 A
V
= 10.3dB
HD3 A
V
= 13dB
FREQUENCY (MHz)
09959-020
CH3 400mV/DI V 25GS/s
8:0G
A CH3 832mV
1
3
50Ω
CH1 70.4mV 2ns/DIV
B
W
09959-022
25GS/s
CH1 340mV A CH2 10mV
1
CH2 1.025V
2ns/DIV
09959-023
0
10
20
30
40
50
60
70
80
90
10 100 1000
CMRR (dB)
FREQUENCY (MHz)
09959-021
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0 500 100 1500 2000 2500 3000
GROUP DELAY (n s)
FREQUENCY (MHz)
09959-024
–80
–70
–60
–50
–40
–30
–20
–10
0
10 100 1000
REVERSE ISOLATION (dB)
FREQUENCY (GHz)
09959-025
B
Figure 21. Single-Ended Harmonic Distortion (HD2/HD3) vs. Frequency,
Figure 22. ENBL Time Domain Response
Figure 24. Common-Mode Rejection Ratio (CMRR) vs. Frequency
Figure 25. Group Delay vs. Frequency
Figure 23. Large Signal Pulse Response, A
= 15.5 dB
V
Rev. | Page 14 of 28
Figure 26. Reverse Isolation (S12) vs. Frequency AV = 6 dB
Page 15
Data Sheet ADL5565
10
15
20
25
30
35
40
45
50
0
100
200
300
400
500
600
700
800
10 100 1000
EQUIVALENT PARALLEL INPUT CAPACITANCE (pF)
EQUIVALENT PARALLEL INPUT RESISTANCE (Ω)
FREQUENCY (MHz)
09959-026
0
1
2
3
4
5
6
7
8
9
10
0
15
30
45
60
75
90
105
120
135
150
10 100 1000
EQUIVALENT SERIE S OUTPUT I NDUCTANCE (nH)
EQUIVALENT SERIES OUTPUT RESISTANCE (Ω)
FREQUENCY (MHz)
RS
LS
09959-128
60
65
70
75
80
85
–40 –20 0 20 40 60 80 100
I
SUPPLY
(mA)
TEMPERATURE (°C)
5V
3.3V
09959-027
B
Figure 27. S11 Equivalent RLC Parallel Network, AV = 6 dB
Figure 29. I
vs. Temperature, RL = 200 Ω, AV = 6 dB,
SUPPLY
VPOS = 3.3 V and VPOS = 5 V
Figure 28. S22 Equivalent RLC Parallel Network, AV = 6 dB
Rev. | Page 15 of 28
Page 16
ADL5565 Data Sheet
R
L
1
/2 R
S
1
/2 R
S
AC
100Ω
200Ω
0.1µF
0.1µF
200Ω
100Ω
50Ω
50ΩVIP2
VIP1
VIN1
VIN2
5Ω
5Ω
++
09959-032
B
CIRCUIT DESCRIPTION
BASIC STRUCTURE
The ADL5565 is a low noise, fully differential amplifier/ADC
driver that can operate from 2.8 V to 5.2 V. It provides three
gain options, 6 dB, 12 dB, and 15.5 dB, without the need for
external resistors and has wide bandwidths of greater than 6
GHz for all gains. Differential input impedance is 200 Ω for 6
dB, 100 Ω for 12 dB, and 67 Ω for 15.5 dB. It has a differential
output impedance of 10 Ω.
Figure 30. Basic Structure
The ADL5565 is composed of a fully differential amplifier with
on-chip feedback and feed forward resistors. The two feedforward
resistors on each input set this pin-strappable amplifier in three
different gain configurations of 6 dB, 12 dB, and 15.5 dB, and by
using two external resistors, any gain from 0 dB to 15.5 dB can be
realized. The amplifier is designed to provide high differential
open-loop gain and an output common-mode circuit that enables
the user to change the common-mode voltage from the VCOM
pin. The amplifier is designed to provide superior low distortion at
frequencies up to and beyond 300 MHz with low noise and low
power consumption from a 3.3 V power supply at 70 mA.
The ADL5565 is very flexible in terms of I/O coupling. It can be
ac-coupled or dc-coupled at the inputs and/or the outputs within
the specified input and output common-mode levels. The input
of the device can be configured as single-ended or differential
with similar third-order distortion performance. Due to the
internal connections between the inputs and outputs, an output
common-mode voltage between 1.4 V and 1.8 V at 3.3 V and
1.4 V to 3 V at 5 V must be maintained for the best distortion.
For a dc-coupled input, the input common mode should be
between 1.2 V and 2 V at the 3.3 V supply, and 1.2 V to 3.8 V at
the 5 V supply. The device has been characterized using 2 V p-p
into a 200 Ω ac-coupled output. If the inputs are ac-coupled, the
input and output common-mode voltages are set by VCC/2 when
no external circuitry is used. The ADL5565 provides an output
common-mode voltage set by VCOM, which allows driving an
ADC directly without external components. Although distortion is
similar over the specified frequency range at both 3.3 V and 5 V,
lower distortion results on the 5 V supply for signal swings larger
than 2 V p-p.
Rev. | Page 16 of 28
Page 17
Data Sheet ADL5565
1
2
3
4
11
12
10
9
5
6
7
8
15
16
14
13
VIP2
VIP1
VIN1
VIN2
VOP
ENBL
VON
VCOM
VCC
VCC
VCC
VCC
AC
VCC
GND
GND
GND
GND
ADL5565
VCC
BALANCED
LOAD
R
L
0.1µF
0.1µF
0.1µF
A
B
0.1µF
0.1µF0.1µF10µF
0.1µF
RS/2
R
S
/2
BALANCED
SOURCE
09959-033
B
APPLICATIONS INFORMATION
BASIC CONNECTIONS
Figure 31 shows the basic connections for operating the
ADL5565. Apply a voltage between 3 V and 5 V to the VCC pins,
and decouple each supply pin with at least one low inductance,
0.1 µF surface-mount ceramic capacitor, placed as close as
possible to the device. Also, decouple the VCOM pin (Pin 9)
using a 0.1 µF capacitor.
The gain of the part is determined by the pin-strappable input
configuration. When Input A is applied to VIP1 and Input B is
applied to VIN1, the gain is 6 dB (minimum gain, see Equation 1
and Equation 2). When Input A is applied to VIP2 and Input B
is applied to VIN2, the gain is 12 dB (middle gain). When Input A
is applied to both VIP1 and VIP2 and Input B is applied to both
VIN1 and VIN2, the gain is 15.5 dB (maximum gain).
Pin 1 to Pin 4, Pin 10, and Pin 11 are biased at 1/2 VCC above
ground and can be dc-coupled (if within the specified input or
output common-mode voltage levels) or ac-coupled as shown in
Figure 31.
To enable the ADL5565, the ENBL pin must be pulled high.
Pulling the ENBL pin low puts the ADL5565 in sleep mode,
reducing the current consumption to 5 mA at ambient.
Figure 31. Basic Connections
Rev. | Page 17 of 28
Page 18
ADL5565 Data Sheet
3V TO 5V
VIP2
VIP1
VIN1
VIN2
A
B
50Ω
AC
R2
++
0.1µF
ETC1-1-13
0.1µF
+
R1
+
0.1µF
0.1µF
NOTES
1. FOR 6dB GAIN (A
V
= 2), CONNECT INPUT A TO V IP1 AND INPUT B TO VIN1.
2. FOR 12dB GAIN (A
V
= 4), CONNECT INPUT A TO V IP2 AND INPUT B TO VIN2.
3. FOR 15.5dB GAIN (A
V
= 6), CONNECT INPUT A TO BOTH VIP1 AND V IP2
AND INPUT B TO BOTH VIN1 AND VIN2.
R
L
2
R
L
2
09959-034
100Ω
200Ω
200Ω
100Ω
50Ω
50ΩVIP2
VIP1
VIN1
VIN2
5Ω
5Ω
R
L
AC
1
/2 R
S
1
/2 R
S
0.1µF
+
0.1µF
+
09959-035
L
L
G
V
R
R
R
A
+×=10
200
6
100
VIP2
VIP1
VIN1
VIN2
A
B
50Ω
AC
R2
+
+
0.1µF
0.1µF
0.1µF
3V TO 5V
+
R1
NOTES
1. FOR 5. 3dB GAIN (A
V
= 1.84), CONNE CT INPUT A T O VIP1
AND INPUT B TO VIN1.
2. FOR 10. 3dB GAIN (A
V
= 3.3), CONNE CT INPUT A T O VIP2
AND INPUT B TO VIN2.
3. FOR 13d B GAIN (A
V
= 4.5), CONNE CT INPUT A T O BOTH
VIP1 AND VIP 2 AND INPUT B TO BOTH VIN1 AND VIN2.
+
0.1µF
R
L
2
R
L
2
09959-036
5.3
30
73
R
L
200Ω
200Ω
VIP2
VIP1
VIN1
VIN2
5Ω
5Ω
R
S
AC
R2
++
0.1µF
0.1µF
0.1µF
0.1µF
+
R1
+
2
R
L
2
100Ω
100Ω
50Ω
50Ω
09959-037
B
INPUT AND OUTPUT INTERFACING
The ADL5565 can be configured as a differential input to
differential output driver, as shown in Figure 32. The resistors,
R1 and R2, combined with the ETC1-1-13 balun transformer,
provide a 50 Ω input match for the three input impedances that
change with the variable gain strapping. The input and output
0.1 µF capacitors isolate the VCC/2 bias from the source and
balanced load. The load should equal 200 Ω to provide the
expected ac performance (see the Specifications section and the
Typical Performance Characteristics section).
Single-Ended Input to Differential Output
The ADL5565 can also be configured in a single-ended input
to differential output driver, as shown in Figure 34. In this
configuration, the gain of the part is reduced due to the application
of the signal to only one side of the amplifier. The strappable
gain values are listed in Table 8 with the required terminations
to match to a 50 Ω source using R1 and R2. The input and output
0.1 µF capacitors isolate the VCC/2 bias from the source and the
balanced load. The performance for this configuration is shown
in Figure 16 and Figure 21.
Figure 32. Differential Input to Differential Output Configuration
Table 6. Differential Termination Values for Figure 32
Gain (dB) R1 (Ω) R2 (Ω)
6 29 29
12 33 33
15.5 40.2 40.2
The differential gain of the ADL5565 is dependent on the source
impedance and load, as shown in Figure 33.
Figure 33. Differential Input Loading Circuit
The differential gain can be determined using the following
formula. The values of R
for each gain configuration are shown
G
in Tabl e 7.
In Equation 1, R
Table 7. Values of R
Gain (dB) RG (Ω)
12 50
15.5 33.5
G
(1)
is the gain setting resistor (see Figure 1).
for Differential Gain
G
Figure 34. Single-Ended Input to Differential Output Configuration
Table 8. Single-Ended Termination Values for Figure 34
Gain (dB) R1 (Ω) R2 (Ω)
10.3 30 104
13 30 154
The single-ended gain configuration of the ADL5565 is dependent
on the source impedance and load, as shown in Figure 35.
Figure 35. Single-Ended Input Loading Circuit
Rev. | Page 18 of 28
Page 19
Data Sheet ADL5565
L
L
X
S
X
S
S
S
G
V
R
R
R
RR
RR
R
RR
RR
R
A
+
×
+
×
+
×
+
×
+
=
102
2
2
2
200
1
0.1µF
1
/2 R
SHUNT
1
/2 R
S
1
/2 R
S
AC
0.1
µF
1
/
2RSERIES
VIP1
VIN2
VIN1
VIP2
1
/
2
R
SERIES
1
/2 R
SHUNT
ADL5565
09959-038
+
=
GSERIES
G
RR
R
dBIl log20)(
GSERIESS
SHUNT
RRR
R
+
−
=
11
1
31
200
50
84.5
60.4
82
100
50
59
73.2
143
66.7
50
13.7
133
B
The single-ended gain can be determined using the following
formula. The values of R
and RX for each gain configuration
G
are shown in Ta ble 9.
(2)
The necessary shunt component, R
impedance, R
, can be expressed as
S
, to match to the source
SHUNT
(5)
In Equation 2, R
Table 9. Values of R
is the gain setting resistor (see Figure 1).
G
and RX for Single-Ended Gain
G
Gain (dB) RG (Ω)1 RX (Ω)
5.3 100 R2 || 1582
10.3 50 R2 || 962
13 33.5 R2 || 742
1
RG is the gain setting resistor (see Figure 1).
2
These values are based on a 50 Ω input match.
GAIN ADJUSTMENT AND INTERFACING
The effective gain of the ADL5565 can be reduced using a number
of techniques. A matched attenuator network can reduce the
effective gain; however, this requires the addition of a separate
component that can be prohibitive in size and cost. Instead, a
simple voltage divider can be implemented using the combination
of additional series resistors at the amplifier input and the input
impedance of the ADL5565, as shown in Figure 36. A pair of
resistors is used to match to the impedance of the previous stage.
Figure 36. Gain Adjustment Using a Series Resistor
Figure 36 shows a typical implementation of the divider concept
that effectively reduces the gain by adding attenuation at the
input. For frequencies less than 100 MHz, the input impedance
of the ADL5565 can be modeled as a real 66 Ω, 100 Ω, or 200 Ω
resistance (differential) for maximum, middle, and minimum
gains, respectively. Assuming that the frequency is low enough
to ignore the shunt reactance of the input and high enough so
that the reactance of moderately sized ac coupling capacitors
can be considered negligible, the insertion loss, Il, due to the
shunt divider can be expressed as
In Equation 5, R
is the gain setting resistor (see Figure 1).
G
The insertion loss and the resultant power gain for multiple
shunt resistor values are summarized in Tab le 10. The source
resistance and input impedance need careful attention when
using Equation 3, Equation 4, and Equation 5. The reactance
of the input impedance of the ADL5565 and the ac coupling
capacitors must be considered before assuming that they make
a negligible contribution.
Table 10. Differential Gain Adjustment Using Series Resistor
Gain
(dB)
Differential
(Ω)4 RS (Ω)
R
G
Differential
R
(Ω)
SERIES
Differential
R
(Ω)5
SHUNT
01 200 50 200 57.6
11 200 50 154 57.6
21 200 50 118 59
41 200 50 52.3 61.9
51 200 50 24.9 64.9
61 200 50 0 66.5
72 100 50 78.7 69.8
92 100 50 42.2 76.8
102 100 50 26.7 82.5
112 100 50 12.7 88.7
122 100 50 0 100
133 66.7 50 23.7 113
15.53 66.7 50 0 200
1
Amplifier is configured for 6 dB gain setting.
2
Amplifier is configured for 12 dB gain setting.
3
Amplifier is configured for 15.5 dB gain setting.
4
RG is the gain setting resistor (see Figure 1).
5
The resistor values are rounded to the nearest real resistor value.
(3)
In Equation 3, R
is the gain setting resistor (see Figure 1).
G
Adjusted Gain (dB) =
6 dB, 12 dB, or 15.5 dB Gain – Il (dB) (4)
Rev. | Page 19 of 28
Page 20
ADL5565 Data Sheet
0
150 30 45 60 75 90 105 120
GAIN = 6dB
SNR = 69.44dBc
SFDR = 89.2dBc
SECOND = –85.1d Bc
THIRD = –89.3d Bc
NOISE FLOOR = –115.7dB
AMPLITUDE (dBFS)
FREQUENCY (MHz)
–15
–30
–45
–60
–75
–90
–105
–120
–135
–150
2
4
+
6
3
5
09959-049
0
150 30 45 60 75 90 105 120
FUNDAMENTAL 1 = –7.078dBFS
FUNDAMENTAL 2 = –7.169dBFS
IMD (2f1 – f2) = –88.237dBc
IMD (2f2 + f1) = –91.37dBc
NOISE F LOOR = –115.96dB
AMPLITUDE (dBFS)
FREQUENCY (MHz)
–15
–30
–45
–60
–75
–90
–105
–120
–135
–150
09959-041
2F2 – 2F1
F1 – F2
F2 – F1
2F1 – F2
2F2 – F1
2F1 – 2F2
–
5
–
4
–
3
–
2
–
1
0
0 100 200 300 400 500
NORMALIZED (dBFS)
FREQUENCY (MHz)
09959-042
0.1µF
40Ω
50Ω
AC
0.1
µF
ETC1-1-13
VIN1
VIP1
VIP2
A
B
VIN2
40Ω
ADL5565
+
+
0.1µF
0.1
µF
33Ω
VOP
VON
33Ω
+
+
AD9467
16-BIT ADC
16
VIN+
VIN–
09959-039
B
ADC INTERFACING
The ADL5565 is a high output linearity amplifier that is optimized
for ADC interfacing. There are several options available to the
designer when using the ADL5565. Figure 40 uses a wideband
1:1 transmission line balun followed by two 40 Ω resistors in
parallel with the three input impedances (which change with
the gain selection of the ADL5565) to provide a 50 Ω differential
impedance and provides a wideband match to a 50 Ω source.
The ADL5565 is ac-coupled from the AD9467 to avoid commonmode dc loading. The 33 Ω resistors improve the isolation between
the ADL5565 and any switching currents present at the analogto-digital, sample-and-hold circuitry. The AD9467 input presents a
530 Ω differential load impedance and requires a 2 V to 2.5 V
differential input swing to reach full scale (VREF = 1 V to 1.25 V).
This circuit provides variable gain, isolation, and source
matching for the AD9467.
Applying a full-scale, single-tone signal from the ADL5565, an
SFDR of 89.2 dBc is realized (see Figure 37). Applying two halfscale signals from the ADL5565 in a gain of 6 dB, an SFDR of
87.5 dBc is achieved at 100 MHz (see Figure 38). The bandwidth
of the circuit in Figure 40 is shown in Figure 39.
Figure 38. Measured Two-Tone Performance of the Circuit in Figure 40 for a
100 MHz Input Signal
Figure 37. Measured Single-Tone Performance of the
Circuit in Figure 40 for a 100 MHz Input Signal
Figure 39. Measured Frequency Response of the Wideband
The wideband frequency response is an advantage in broadband applications, such as predistortion receiver designs and
instrumentation applications. However, by designing for a wide
analog input frequency range, the cascaded SNR performance is
somewhat degraded due to high frequency noise aliasing into
the wanted Nyquist zone.
Figure 40. Wideband ADC Interfacing Example Featuring the AD9467
Rev. | Page 20 of 28
ADC Interface Depicted in Figure 40
Page 21
Data Sheet ADL5565
105Ω
L5
105Ω
AD9467
1nF
L1C2L3
1nF
L1 L3
C4
CML
ADL5565
4Ω
4Ω
09959-043
140
40
3.3
47
27
27
150
B
By designing a narrow band-pass antialiasing filter between the
ADL5565 and the target ADC, the output noise of the ADL5565
outside of the intended Nyquist zone can be attenuated, helping
to preserve the available SNR of the ADC. In general, the SNR
improves several decibels when including a reasonable order antialiasing filter. In this example, a low loss 1:1 input transformer is
used to match the ADL5565 balanced input to a 50 Ω unbalanced
source, resulting in minimum insertion loss at the input.
Figure 41 is optimized for driving some of Analog Devices popular
ADCs, such as the AD9467. Tab le 11 includes antialiasing filter
component recommendations for popular IF sampling frequencies.
Inductor L5 works in parallel with the on-chip ADC input
capacitance and a portion of the capacitance presented by C4 to
form a resonant tank circuit. The resonant tank helps to ensure
that the ADC input looks like a real resistance at the target center
frequency. The inductor, L5, shorts the ADC inputs at dc, which
introduces a zero into the transfer function. In addition, the ac
coupling capacitors introduce additional zeros into the transfer
function. The final overall frequency response takes on a bandpass characteristic, helping to reject noise outside of the intended
Nyquist zone. Table 11 provides initial suggestions for prototyping purposes. Some empirical optimization may be needed
to help compensate for actual PCB parasitics.
Figure 41. Narrow-Band IF Sampling Solution for an ADC Application
Table 11. Interface Filter Recommendations for Various IF Sampling Frequencies
Center Frequency (MHz) 1 dB Bandwidth (MHz) L1 (nH) C2 (pF) L3 (nH) C4 (pF) L5 (nH)
96 30 3.3 47 27 75 82
170 32 3.3 56 27 18 120
211 33 3.3 47 27 15 51
Rev. | Page 21 of 28
Page 22
ADL5565 Data Sheet
0.1µF
0.1µF
0.1µF
0.1µF
ADL5565
VIP2
VIP1
VIN1
VOP
VON
VIN2
R6
R5
R4
R3
R2
R1
R8
R7
R10
R9
ETC1-1-13
ETC1-1-13
SPECTRUM
ANALYZER
09959-044
6
29
29
Open
0 0 Open
ADL5565
VIP2
VIP1
VIN1
VOP
VON
VIN2
R6
R5
R4
R3
R2
R1
PORT 1
PORT 3
PORT 2
PORT 4
R8
R7
R10
R9
09959-045
B
LAYOUT CONSIDERATIONS
High-Q inductive drives and loads, as well as stray transmission
line capacitance in combination with package parasitics, can
potentially form a resonant circuit at high frequencies, resulting
in excessive gain peaking or possible oscillation. If RF transmission
lines connecting the input or output are used, design them such
that stray capacitance at the input/output pins is minimized. In
many board designs, the signal trace widths should be minimal
where the driver/receiver is no more than one-eighth of the
wave-length from the amplifier. This nontransmission line
configuration requires that underlying and adjacent ground and
low impedance planes be dropped from the signal lines.
Figure 42. General-Purpose Characterization Circuit
Table 12. Gain Setting and Input Termination Components for Figure 42
AV (dB) R1 (Ω) R2 (Ω) R3 (Ω) R4 (Ω) R5 (Ω) R6 (Ω)
12 33 33 0 Open Open 0
15.5 40.2 40.2 0 0 0 0
Table 13. Output Matching Network for Figure 42
RL (Ω) R7 (Ω) R8 (Ω) R9 (Ω) R10 (Ω)
200 84.5 84.5 34.8 34.8
Figure 43. Differential Characterization Circuit Using Agilent E8357A Four-Port PNA
Table 14. Gain Setting and Input Termination Components for Figure 43
AV (dB) R1 (Ω) R2 (Ω) R3 (Ω) R4 (Ω) R5 (Ω) R6 (Ω)
6 100 100 Open 0 0 Open
12 Open Open 0 Open Open 0
15.5 Open Open 0 0 0 0
Table 15. Output Matching Network for Figure 43
RL (Ω) R7 (Ω) R8 (Ω) R9 (Ω) R10 (Ω)
200 50 50 Open Open
Rev. | Page 22 of 28
Page 23
Data Sheet ADL5565
36mils
12mils
59mils
59mils
122mils
19.7mils
10mils
09959-050
59mils
B
SOLDERING INFORMATION AND RECOMMENDED PCB LAND PATTERN
Figure 44 show s the recommended land pattern for the ADL5565.
The ADL5565 is contained in a 3 × 3 mm LFCSP package, which
has an exposed ground paddle (EPAD). This paddle is internally
connected to the ground of the chip. To minimize thermal
impedance and ensure electrical performance, solder the paddle
to the low impedance ground plane on the PCB. To further
reduce thermal impedance, it is recommended that the ground
planes on all layers under the paddle be stitched together with vias.
For more information on land pattern design and layout, refer
to the AN-772 Application Note, A Design and Manufacturing
Guide for the Lead Frame Chip Scale Package (LFCSP).
This land pattern, on the ADL5565 evaluation board, provides
a measured thermal resistance (θ
the temperature at the top of the LFCSP package is found with
an IR temperature gun. Thermal simulation suggests a junction
temperature 1.5°C higher than the top of package temperature.
With additional ambient temperature and I/O power measurements, θ
could be determined.
JA
) of 60°C/W. To measure θJA,
JA
EVALUATION BOARD
Figure 45 shows the schematic of the ADL5565 evaluation board.
The board is powered by a single supply in the 3 V to 5 V range.
The power supply is decoupled by 10 µF and 0.1 µF capacitors.
Table 16 details the various configuration options of the evaluation
board. Figure 46 and Figure 47 show the component and circuit
side layouts of the evaluation board.
To realize the minimum gain (6 dB into a 200 Ω load), Input 1
(VIN1 and VIP1) must be used by installing 0 Ω resistors at R3
and R4, leaving R5 and R6 open. R1 and R2 must be 33.2 Ω for
a 50 Ω input impedance.
Likewise, driving Input 2 (VIN2 and VIP2) realizes the middle
gain (12 dB into a 200 Ω load) by installing 0 Ω at R5 and R6
and leaving R3 and R4 open. R1 and R2 must be 50 Ω for a
50 Ω input impedance.
For the maximum gain (15.5 dB into a 200 Ω load), both inputs
are driven by installing 0 Ω resistors at R3, R4, R5, and R6. R1
and R2 are open for a 50 Ω input impedance.
The balanced input and output interfaces are converted to
single ended with a pair of baluns (M/A-COM ETC1-1-13).
The balun at the input, T1, provides a 50 Ω single-ended-todifferential transformation. The output balun, T2, and the
matching components are configured to provide a 200 Ω to 50 Ω
impedance transformation with an insertion loss of about 11 dB.
As an alternative, the input transformer, T1, can be replaced with
one of the following transformers to provide a low loss balanced
input to the ADL5565.
• 6 dB gain configuration, Mini-Circuits TC4-1W+
• 12 dB gain configuration, Mini-Circuits, TC2-1T+
• 15.5 dB gain configuration, Mini-Circuits TC1.5-52T
Figure 44. Recommended Land Pattern
When using these alternative transformers, R1 and R2 are left
open. Replace C1 and C2 with 0 Ω jumpers and add a 0.1 µF
capacitor to C12.
Rev. | Page 23 of 28
Page 24
ADL5565 Data Sheet
C3
10µFC40.1µFC50.1µFC60.1µFC70.1µF
C8
0.1µF
C13
OPEN
C11
0.1µF
VPOS
R9
34.8Ω
R11
OPEN
R15
OPEN
R14
0Ω
J3
R10
34.8Ω
R8
84.5Ω
C10
0.01µF
C9
0.01µF
P1
T2
VCOM
AGND
VPOS
GND
R7
84.5Ω
ENBL
J4
OPEN
R12
OPEN
R13
0Ω
J2
OPEN
ADL5565
9
10
11
12
4
3
2
1
16 15 14 13
5 6 7 8
GND GND GND GND
VCC
V
IN1
VIN2
VIP2
VIP1
VON
VCOM
ENBL
VOP
VCC VCC VCC
C12
OPEN
J1
T1
R1
OPEN
R2
OPEN
R4
0Ω
R3
0Ω
R5
0Ω
R6
0Ω
C1
0.01µF
C2
0.01µF
09959-046
ENBL, P1, C8
Device enabled. C8 is a bypass capacitor. When the P1 jumper is set toward the VPOS label,
ENBL, P1 = installed,
15.5
Open
Open
B
Figure 45. Evaluation Board Schematic
Table 16. Evaluation Board Configuration Options
Component Description Default Condition
VPOS, GND Ground and supply vector pins. VPOS, GND = installed
C3, C4, C5,
C6, C7, C11
J1, J2, R1, R2,
R3, R4, R5, R6,
R12, R13, C1,
C2, C12, T1
Power supply decoupling. The supply decoupling consists of a 10 µF capacitor (C3) to
ground. C4 to C7 are bypass capacitors. C11 ac couples VREF to ground.
Input interface. The SMA labeled J1 is the input. T1 is a 1-to-1 impedance ratio balun
to transform a single-ended input into a balanced differential signal. Removing R13,
installing R12 (0 Ω), and installing an SMA connector (J2) allows driving from a
differential source. C1 and C2 provide ac coupling. C12 is a bypass capacitor. R1 and
R2 provide a differential 50 Ω input termination. R3 to R6 are used to select the input
for the pin-strappable gain. The maximum gain is R3, R4, R5, R6 = 0 Ω and R1 and R2 =
open. The middle gain is R5 and R6 = 0 Ω, R3 and R4 = open, and R1 and R2 = 50 Ω. The
C3 = 10 µF (Size D),
C4, C5, C6, C7, C11 = 0.1 µF (Size 0402)
J1 = installed, J2 = not installed,
R1, R2 = open,
R3, R4, R5, R6, R13 = 0 Ω (Size 0402),
R12, = open,
C1, C2 = 0.01 µF (Size 0402),
C12 = open,
T1 = ETC1-1-13 (M/A-COM)
minimum gain is R3 and R4 = 0 Ω, R5 and R6 = open, and R1 and R2 = 33.2 Ω.
J3, J4, R7, R8,
R9, R10, R11,
R14, R15 C9,
C10, C13, T2
Output interface. The SMA labeled J3 is the output. T2 is a 1-to-1 impedance ratio balun
to transform a balanced differential signal to a single-ended signal. Removing R14,
installing R15 (0 Ω), and installing an SMA connector (J4) allows differential loading. C13 is
a bypass capacitor. R7, R8, R9, and R10 are provided for generic placement of matching
components. The evaluation board is configured to provide a 200 Ω to 50 Ω impedance
transformation with an insertion loss of 17 dB. C9 and C10 provide ac coupling.
J3 = installed, J4 = not installed,
R7, R8 = 84.5 Ω (Size 0402),
R9, R10 = 34.8 Ω (Size 0402),
R11, R15 = open (Size 0402),
R14 = 0 Ω (Size 0402)
C9, C10 = 0.01 µF (Size 0402),
C13 = open
T2 = ETC1-1-13 (M/A-COM)
the ENBL pin is connected to the supply, enabling the device. In the opposite direction,
C8 = 0.1 µF (Size 0402)
toward the GND label, the ENBL pin is grounded, putting the device in power-down mode.
Table 17. Differential Values for Figure 45
Gain (dB) R1 (Ω) R2 (Ω)
6 29 29
12 33 33
Table 18. Alternative Differential Input Configuration for Figure 45
Gain (dB) R1 and R2 (Ω) C12 (µF) C1 and C2 (Ω) T1
6 Open 0.1 0 Mini Circuits TC4-1W+
12 Open 0.1 0 Mini Circuits TC2-1T+
15.5 Open 0.1 0 Mini Circuits TC1.5-52T+
Rev. | Page 24 of 28
Page 25
Data Sheet ADL5565
09959-047
09959-048
B
Figure 46. Layout of Evaluation Board, Component Side
Figure 47. Layout of Evaluation Board, Circuit Side
Rev. | Page 25 of 28
Page 26
ADL5565 Data Sheet
OUTLINE DIMENSIONS
PIN 1
INDICATOR
0.80
0.75
0.70
SEATING
PLANE
3.10
3.00 SQ
2.90
0.50
BSC
0.50
0.40
0.30
0.05 MAX
0.02 NOM
0.20 REF
0.30
0.25
0.20
13
12
9
8
BOTTOM VIEWTOP VIEW
COPLANARITY
0.08
N
1
I
P
C
I
N
I
16
EXPOSED
PAD
5
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURAT I O N AND
FUNCTIO N DES CRI P TIONS
SECTION OF THIS DATA SHEET.
D
1
1.65
1.50 SQ
1.45
4
0.20 MIN
R
O
A
T
COMPLIANTTOJEDEC STANDARDS M O-220-WEE D- 6 .
01-26-2012-A
Figure 48. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
3 mm × 3 mm Body, Very Very Thin Quad
(CP-16-27)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Model1
Range Package Description
ADL5565ACPZ-R7 −40°C to + 85°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ], 7” Tape and Reel CP-16-27 Q1Z
ADL5565-EVALZ Evaluation Board
1
Z = RoHS Compliant Part
Package
Option Branding
Rev. B | Page 26 of 28
Page 27
Data Sheet ADL5565
B
NOTES
Rev. | Page 27 of 28
Page 28
ADL5565 Data Sheet
NOTES
©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09959-0-6/12(B)
Rev. B | Page 28 of 28
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