Datasheet ADL5523 Datasheet (ANALOG DEVICES)

400 MHz to 4000 MHz

FEATURES

Operation from 400 MHz to 4000 MHz
Noise figure of 0.8 dB at 900 MHz
Requires few external components
Integrated active bias control circuit
Integrated dc blocking capacitors
Adjustable bias for low power applications
Single-supply operation from 3 V to 5 V
Gain of 21.5 dB at 900 MHz
OIP3 of 34.0 dBm at 900 MHz
P1dB of 21.0 dBm at 900 MHz
Small footprint LFCSP
Pin-compatible version with 20.8 dB gain available

GENERAL DESCRIPTION

The ADL5523 is a high performance GaAs pHEMT low noise
amplifier. It provides high gain and low noise figure for single­downconversion IF sampling receiver architectures as well as
direct-downconversion receivers.

The ADL5523 provides a high level of integration by incorporating
the active bias and the dc blocking capacitors, making it very
easy to use while not sacrificing design flexibility.

Low Noise Amplifier

ADL5523

FUNCTIONAL BLOCK DIAGRAM

ACTIVE

1VBIAS

BIAS

2RFIN
3NC

ADL5523

4NC

NC = NO CONNECT

Figure 1.

The ADL5523 is easy to tune, requiring only a few external
components. The device can support operation from 3 V to 5 V,
and the current draw can be adjusted with the external bias
resistor for applications requiring very low power consumption.

The ADL5523 comes in a compact, thermally enhanced, 3 mm ×
3 mm LFCSP and operates over the temperature range of

−40°C to +85°C.

A fully populated evaluation board is also available.

8VPOS
7RFOUT
6NC
5NC

06829-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2008–2009 Analog Devices, Inc. All rights reserved.

ADL5523

TABLE OF CONTENTS

Features .............................................................................................. 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

AC Specifications .......................................................................... 3

DC Specifications ......................................................................... 4

De-Embedded S-Parameters, VPOS = 3 V to 5 V, RFIN =

Port 1, VPOS = Port 2, RFOUT = Port 3 .................................. 4

Absolute Maximum Ratings ............................................................ 5

ESD Caution .................................................................................. 5

Pin Configuration And Function Descriptions ............................ 6

Typical Performance Characteristics ............................................. 7

900 MHz, VPOS = 5 V ................................................................. 7

1950 MHz, VPOS = 5 V .............................................................. 8

2600 MHz, VPOS = 5 V .............................................................. 9

3500 MHz, VPOS = 5 V ............................................................ 10

900 MHz, VPOS = 3 V .............................................................. 11

1950 MHz, VPOS = 3 V ............................................................ 12

2600 MHz, VPOS = 3 V ............................................................ 13

3500 MHz, VPOS = 3 V ............................................................ 14

DC Characteristics ..................................................................... 15

Basic Connections .......................................................................... 16

Evaluation Board ............................................................................ 17

Soldering Information and Recommended PCB

Land Pattern ................................................................................ 17

Tuning the ADL5523 for Optimal Noise Figure ........................ 18

Tuning S22 ................................................................................... 18

Tuning the LNA Input for Optimal Gain ................................ 19

Tuning the LNA Input for Optimal Noise Figure .................. 19

S11 of the LNA with S22 Matched ........................................... 20

Outline Dimensions ....................................................................... 21

Ordering Guide .......................................................................... 21

REVISION HISTORY

9/09—Rev. 0 to Rev. A

Updated Maximum Junction Temperature Unit (Table 4) ......... 5

10/08—Revision 0: Initial Version

Rev. A | Page 2 of 24

ADL5523

SPECIFICATIONS

AC SPECIFICATIONS

TA = 25°C, R1 = 1.3 kΩ; parameters include matching circuit, matched for optimal noise, unless otherwise noted.

Table 1.

3 V 5 V
Parameter Conditions Min Typ Max Min Typ Max Unit

FREQUENCY = 900 MHz

Gain (S21) 21.0 21.5 dB

vs. Frequency ±50 MHz ±0.35 ±0.37 dB

vs. Temperature −40°C ≤ TA ≤ +85°C ±0.60 ±0.51 dB
Noise Figure1 0.8 0.8 dB
Output Third-Order Intercept (OIP3) Δf = 1 MHz, P
Output 1 dB Compression Point (P1dB) 17.8 21.0 dBm
Input Return Loss (S11) −7.5 −8.0 dB
Output Return Loss (S22) −10.5 −11.0 dB
Isolation (S12) −24.0 −25.5 dB

FREQUENCY = 1950 MHz

Gain (S21) 16.5 15.8 17.0 18.0 dB

vs. Frequency ±30 MHz ±0.06 ±0.08 dB

vs. Temperature −40°C ≤ TA ≤ +85°C ±0.50 ±0.47 dB
Noise Figure1 0.9 1.0 dB
Output Third-Order Intercept (OIP3) Δf = MHz, P
Output 1 dB Compression Point (P1dB) 17.7 21.2 dBm
Input Return Loss (S11) −9.0 −10.0 dB
Output Return Loss (S22) −17.0 −20.0 dB
Isolation (S12) −20.5 −21.5 dB

FREQUENCY = 2600 MHz

Gain (S21) 12.8 13.2 dB

vs. Frequency ±100 MHz ±0.35 ±0.36 dB

vs. Temperature −40°C ≤ TA ≤ +85°C ±0.45 ±0.44 dB
Noise Figure1 0.9 0.9 dB
Output Third-Order Intercept (OIP3) Δf = 1 MHz, P
Output 1 dB Compression Point (P1dB) 17.0 21.2 dBm
Input Return Loss (S11) −5.0 −5.0 dB
Output Return Loss (S22) −10.0 −10.0 dB
Isolation (S12) −21.5 −22.0 dB

FREQUENCY = 3500 MHz

Gain (S21) 10.6 11.0 dB

vs. Frequency ±100 MHz ±0.73 ±0.78 dB

vs. Temperature −40°C ≤ TA ≤ +85°C ±0.78 ±0.77 dB
Noise Figure1 1.0 1.0 dB
Output Third-Order Intercept (OIP3) Δf = 1 MHz, P
Output 1 dB Compression Point (P1dB) 17.3 20.1 dBm
Input Return Loss (S11) −11.0 −11.5 dB
Output Return Loss (S22) −10.0 −10.5 dB
Isolation (S12) −19.0 −19.5 dB

1

Noise figure de-embedded to first matching component on input side.

= 0 dBm per tone 28.0 34.0 dBm

OUT

= 0 dBm per tone 28.0 34.0 dBm

OUT

= 0 dBm per tone 30.0 35.0 dBm

OUT

= 0 dBm per tone 30.0 33.5 dBm

OUT

Rev. A | Page 3 of 24

ADL5523

DC SPECIFICATIONS

Table 2.

3 V 5 V

Parameter Conditions

Supply Current 30 60 mA

vs. Temperature −40°C ≤ TA ≤ +85°C ±4 ±7 mA

DE-EMBEDDED S-PARAMETERS, VPOS = 3 V TO 5 V, RFIN = PORT 1, VPOS = PORT 2, RFOUT = PORT 3

Table 3.

Frequency
(GHz)

0.125 −4.2/−12.9 −37.1/−21.9 −40.6/+45.2 +19.3/+132 −6.2/+89.1 −10.6/+8.9 +15.9/−161 −10.5/−9.0 −8.6/−30.4

0.25 −5.8/−18.8 −40.0/−30.6 −38.3/+40.5 +15.4/+104 −2.3/+68.6 −13.2/−33.8 +16.6/+174 −13.2/−33.9 −11.0/−6.4

0.375 −7.6/−20.4 −42.0/−31.1 −37.5/+38.4 +11.4/+87.9 −1.1/+63.5 −16.2/−42.8 +16.0/+158.2 −16.2/−43.2 −11.3/+6.4

0.5 −9.5/−18.4 −43.9/−28.2 −36.7/+40.2 +7.6/+77.4 −0.6/+63.3 −19.0/−45.9 +14.9/+147 −19.0/−46.0 −11.7/+16.2

0.625 −11.4/−14.0 −46.5/−27.4 −36.2/+42.3 +3.84/+70.2 −0.3/+64.8 −21.7/−46.0 +13.8/+140 −21.7/−46.7 −12.1/+25.3

0.75 −13.2/−7.2 −48.8/−24.6 −35.8/+44.5 +0.0/+65.3 −0.2/+66.5 −24.6/+45.6 +12.8/+135 −24.5/−45.8 −12.5/+34.3

0.875 −15.1/+2.3 −51.1/−19.3 −35.4/+47.8 −4.2/+62.6 −0.1/+68.0 −27.8/−42.8 +11.8/+132 −27.8/−44.5 −12.8/+43.2

1.0 −16.8/+13.9 −56.6/−17.6 −35.1/+51.1 −9.7/+61.7 +0.0/+68.5 −32.3/−40.3 +10.9/+129 −32.5/−42.4 −13.1/+52.3

1.125 −18.2/+27.3 −64.4/−15.8 −34.6/+53.9 −19.0/+70.9 +0.1/+67.5 −41.4/−31.5 +10.1/+127 −41.6/−38.6 −13.4/+60.8

1.25 −19.3/+42.3 −66.5/−173 −34.5/+56.7 −22.0/−161 +0.2/+66.0 −45.0/+118 +9.3/+126 −42.8/+129 −13.6/+69.3

1.375 −19.9/+57.4 −56.2/+160 −34.1/+60.1 −13.6/−147 +0.3/+63.4 −34.3/+130 +8.6/+125 −33.8/+132 −13.9/+77.5

1.5 −20.0/+71.1 −52.2/+153 −33.9/+63.1 −10.2/−147 +0.4/+61.1 −30.0/+133 +7.9/+124 −29.8/+133 −14.0/+85.3

1.625 −20.2/+82.7 −49.0/+165 −33.5/+66.2 −8.5/−148 +0.5/+61.1 −27.5/+134 +7.3/+125 −27.2/+134 −14.2/+92.8

1.75 −20.1/+92.5 −46.7/+160 −33.3/+70.3 −7.4/−149 +0.6/+62.8 −25.9/+137 +6.8/+124 −25.5/+135 −14.4/+100

1.875 −19.9/+101 −45.3/+167 −32.9/+72.5 −6.8/−148 +0.6/+67.4 −24.5/+139 +6.3/+124 −24.2/+139 −14.5/+107

2.0 −19.7/+107 −44.6/+173 −32.6/+75.1 −6.4/−147 +0.6/+73.6 −23.5/+142 +5.8/+125 −23.3/+143 −14.6/+114

2.125 −19.6/+113 −43.5/+176 −32.1/+78.2 −6.1/−144 +0.7/+82.7 −22.7/+148 +5.4/+125 −22.5/+148 −14.7/+121

2.25 −19.3/+116 −42.3/−180 −31.7/+80.6 −6.0/−140 +0.7/+93.9 −22.0/+154 +5.0/+125 −21.8/+154 −14.8/+127

2.375 −19.0/+117 −41.8/−172 −31.5/+83.1 −5.9/−135 +0.7/+107 −21.3/+161 +4.7/+125 −21.1/+161 −14.8/+133

2.5 −18.6/+117 −41.2/−166 −31.1/+84.7 −5.7/−129 +0.7/+122 −20.6/+169 +4.3/+125 −20.5/+169 −14.8/+140

2.625 −18.1/+118 −40.0/−156 −30.8/+86.7 −5.6/−122 +0.7/+139 −20.0/+178 +4.0/+125 −19.8/+178 −14.8/+145

2.75 −17.5/+117 −39.3/−146 −30.4/+89.0 −5.4/−115 +0.7/+158 −19.3/−173 +3.6/+125 −19.1/−172 −14.7/+151

2.875 −16.8/+118 −38.6/−136 −30.3/+90.4 −5.1/−106 +0.8/+178 −18.6/+162 +3.3/+125 −18.5/−162 −14.7/+158

3.0 −15.9/+117 −37.6/−126 −30.0/+91.7 −5.0/−97.7 +0.8/−161 −18.0/−152 +2.9/+125 −17.8/−152 −14.7/+164

3.125 −14.9/+118 −37.1/−115 −29.8/+92.0 −4.9/−88.5 +0.7/−138 −17.5/−141 +2.6/+124 −17.3/−140 −14.5/+172

3.25 −13.9/+120 −36.5/−105 −29.4/+92.3 −4.9/−79.2 +0.5/−116 −16.8/−129 +2.2/+123 −16.7/−130 −14.4/+180

3.375 −13.0/+121 −35.8/−95.4 −29.3/+92.2 −4.7/−71.8 +0.1/−95.2 −16.3/−121 +1.7/+122 −16.2/−121 −14.0/−172

3.5 −12.0/+124 −35.1/−88.7 −29.3/+92.3 −4.4/−66.4 −0.3/−76.7 −15.4/−115 +1.2/+120 −15.3/−115 −13.4/−162

3.625 −11.3/+127 −33.7/−85.0 −29.6/+91.2 −3.6/−63.6 −0.8/−60.6 −14.2/−111 +0.4/+118 −14.1/−111 −12.4/−152

3.75 −10.7/+131 −31.4/−86.9 −30.5/+89.4 −1.9/−67.1 −1.7/−47.8 −12.1/−114 −0.9/+116 −11.9/−113 −10.8/−141

3.875 −10.4/+138 −28.6/−99.9 −32.9/+95.9 +0.7/−83.0 −4.9/−35.8 −8.9/−129 −3.9/+124 −8.8/−129 −7.9/−137

4.0 −9.3/+152 −27.3/−136 −30.9/+132 +1.3/−120 −6.3/+42.3 −7.8/−164 −1.4/+155 −7.7/−165 −5.8/−150

S11
(dB/Ang)

S12
(dB/Ang)

S13
(dB/Ang)

Min Typ Max Min Typ Max Unit

S21
(dB/Ang)

S22
(dB/Ang)

S23
(dB/Ang)

S31
(dB/Ang)

S32
(dB/Ang)

S33
(dB/Ang)

Rev. A | Page 4 of 24

ADL5523

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Rating

Supply Voltage, VPOS 5.5 V
RF Input Level 7 dBm
RF Input Level (with 8 Ω Series Resistor on VPOS) 20 dBm
Internal Power Dissipation 500 mW
θJA (Junction to Air) 50°C/W
Maximum Junction Temperature 150°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. A | Page 5 of 24

ADL5523

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1VBIAS

ADL5523

2RFIN
3NC
4NC

NOTES

1. NC = NO CONNECT .

2. CONNECT THE E X P OSED PAD TO A LOW
IMPEDANCE GROUND P LANE.

TOP VIEW

(Not to S cale)

EXPOSED PAD

8VPOS
7RFOUT
6NC
5NC

06829-002

Figure 2. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 VBIAS Internal DC Bias. This pin should be connected to VPOS through the R1 resistor.
2 RFIN RF Input. This is the input to the LNA.
3, 4, 5, 6 NC No Connection. No internal connection.
7 RFOUT RF Output.
8 VPOS

Supply Voltage. DC bias needs to be bypassed to ground using a low inductance capacitor. This pin is
also used for output matching. See the Basic Connections section.

9 (EPAD) Exposed Pad (EPAD) GND. Connect the exposed pad to a low impedance ground plane.

Rev. A | Page 6 of 24

ADL5523

TYPICAL PERFORMANCE CHARACTERISTICS

900 MHz, VPOS = 5 V

Matched for optimal noise figure, external matching circuit included.

25

S21

20
15
10

5
0

S11

–5
–10
–15

S-PARAMETERS ( dB)

–20
–25
–30
–35

600 650 700 750 800 850 900 950 1000 1050 1100 1150 1200

S22

FREQUENCY (MHz)

Figure 3. Typical S-Parameters, Log Magnitude

24
22
20
18
16
14
12
10

8
6

NOISE FI GURE AND GAIN (d B)

4
2
0

850 860 870 880 890 900 910 920 930 940 950

GAIN

OIP3

P1dB

NOISE FI GURE

FREQUENCY (MHz )

Figure 4. Noise Figure, Gain, OIP3, and P1dB vs. Frequency

2.0

1.8

1.6

1.4

1.2

1.0

0.8

NOISE FIGURE (dB)

0.6

0.4

0.2

0

800 820 840 860 880 900 920 940 960 980 1000

+85°C

+25°C

–40°C

FREQUENCY (MHz)

Figure 5. Noise Figure vs. Temperature

S12

06829-003

60
55
50
45
40
35
30
25
20

OIP3 AND P1dB (dBm)

15
10
5
0

06829-004

06829-005

2.0

1.8

1.6

1.4

1.2

1.0

0.8

NOISE FIGURE (dB)

0.6

0.4

0.2

0

800 820 840 860 880 900 920 940 960 980 1000

FREQUENCY (MHz)

Figure 6. Noise Figure vs. Frequency at 25°C, Multiple Devices

23.5
+25°C

23.0

22.5

22.0

21.5

21.0

GAIN (dB)

20.5

20.0

19.5

19.0

850 860 870 880 890 900 910 920 930 940 950

+85°C

+85°C

GAIN

–40°C

+25°C

FREQUENCY (MHz )

–40°C

–40°C

+25°C

+85°C

P1dB

Figure 7. Gain, OIP3, and P1dB vs. Temperature

40

38

36

34

32

30

28

OIP3 (dBm)

26

24

22

20

–4–20246810121416182022

Figure 8. OIP3 vs. Output Power (P

+25°C

+85°C

P

PER TONE (dBm)

OUT

) and Temperature

OUT

OIP3

–40°C

06829-006

36

34

32

30

28

26

24

OIP3 AND P1dB (dBm)

22

20

18

06829-008

06829-007

Rev. A | Page 7 of 24

ADL5523

1950 MHZ, VPOS = 5 V

Matched for optimal noise figure, external matching circuit included.

20
15
10

5
0

S11

–5
–10
–15
–20

S-PARAMETERS ( dB)

–25
–30
–35
–40

S22

1800 1850 1900 1950 2000 2050 2100 2150 2200

S21

FREQUENCY (MHz)

Figure 9. Typical S-Parameters, Log Magnitude

18

16

14

12

10

8

6

4

NOISE FI GURE AND GAIN (d B)

2

0
1920 1930 1940 1950 1960 1970 1980

GAIN

OIP3

P1dB

NOISE FI GURE

FREQUENCY (MHz )

Figure 10. Noise Figure, Gain, OIP3, and P1dB vs. Frequency

2.0

1.8

1.6

1.4

1.2

1.0

0.8

NOISE FI G URE (dB)

0.6

0.4

0.2

0
1800 1820 1840 1860 1880 1900 1920 1940 1960 1980 2000

+85°C

+25°C

–40°C

FREQUENCY (MHz)

Figure 11. Noise Figure vs. Temperature

S12

06829-009

45

40

35

30

25

20

15

OIP3 AND P1dB (dBm)

10

5

0

06829-010

06829-011

2.0

1.8

1.6

1.4

1.2

1.0

0.8

NOISE FI G URE (dB)

0.6

0.4

0.2

0
1800 1820 1840 1860 1880 1900 1920 1940 1960 1980 2000

FREQUENCY (MHz)

Figure 12. Noise Figure vs. Frequency at 25°C, Multiple Devices

20.5
–40°C

20.0

19.5

19.0

18.5

18.0

17.5

17.0

GAIN (dB)

16.5

–40°C

16.0

15.5

15.0

14.5

1920 1930 1940 1950 1960 1970 1980

+25°C

+85°C

GAIN

+25°C

FREQUENCY (MHz )

+25°C
+85°C

P1dB

OIP3

+85°C

Figure 13. Gain, OIP3, and P1dB vs. Temperature

42
40
38
36
34
32
30
28

OIP3 (dBm)

26
24
22
20
18

–8 –6 –4 0–2 246810121416182022

+85°C

Figure 14. OIP3 vs. Output Power (P

+25°C

P

PER TONE (dBm)

OUT

–40°C

) and Temperature

OUT

–40°C

06829-012

40
38
36
34
32
30
28
26
24

OIP3 AND P1dB (dBm)

22
20
18
16

06829-013

06829-014

Rev. A | Page 8 of 24

ADL5523

2600 MHz, VPOS = 5 V

Matched for optimal noise figure, external matching circuit included.

20

15

10

5

0

–5

–10

–15

S-PARAMETERS ( dB)

–20

–25

–30

2100 2200 2300 2400 2500 2600 2700 2800 2900

S21

S11

S22

S12

FREQUENCY (MHz)

Figure 15. Typical S-Parameters, Log Magnitude

16

14

12

10

8

6

4

NOISE FI GURE AND GAIN (d B)

2

0
2500 2520 2540 2560 2580 26202600 2640 2660 2680 2700

GAIN

OIP3

P1dB

NOISE FI GURE

FREQUENCY (MHz )

Figure 16. Noise Figure, Gain, OIP3, and P1dB vs. Frequency

2.0

1.8

1.6

1.4

1.2

1.0

0.8

NOISE FI G URE (dB)

0.6

0.4

0.2

0
2500 2520 2540 2560 2580 2600 2620 2640 2660 2680 2700

+85°C

+25°C

–40°C

FREQUENCY (MHz)

Figure 17. Noise Figure vs. Temperature

06829-015

50

45

40

35

30

25

OIP3 AND P1dB (dBm)

20

15

10

06829-016

06829-017

2.0

1.8

1.6

1.4

1.2

1.0

0.8

NOISE FI G URE (dB)

0.6

0.4

0.2

0
2500 2520 2540 2560 2580 2600 2620 2640 2660 2680 2700

FREQUENCY (MHz)

Figure 18. Noise Figure vs. Frequency at 25°C, Multiple Devices

16.5
–40°C

16.0

P1dB

+25°C

+85°C

FREQUENCY (MHz )

+25°C

GAIN

OIP3

+25°C

+85°C

–40°C

+85°C

15.5

15.0

14.5

14.0

13.5

GAIN (dB)

13.0

12.5

12.0

11.5

11.0

2500 2520 2540 2560 2580 2600 2620 2640 2660 2680 2700

Figure 19. Gain, OIP3, and P1dB vs. Temperature

42
40
38
36
34
32
30
28

OIP3 (dBm)

26
24
22
20
18

–6 –4 0–2 2 4 6 8 10 12 14 16 18 20 22

+85°C

Figure 20. OIP3 vs. Output Power (P

–40°C

+25°C

P

PER TONE (dBm)

OUT

) and Temperature

OUT

–40°C

06829-018

40
38
36
34
32
30
28
26

OIP3 AND P1dB (dBm)

24
22
20
18

06829-020

06829-019

Rev. A | Page 9 of 24

ADL5523

3500 MHz, VPOS = 5 V

Matched for optimal noise figure, external matching circuit included.

15

10

5

0

–5

–10

S-PARAMETERS ( dB)

–15

–20

–25

2800 2900 3000 3100 3200 3300 3400 3500 3600 3700

S11

S22

FREQUENCY (MHz)

Figure 21. Typical S-Parameters, Log Magnitude

14

12

OIP3

10

8

6

4

NOISE FI GURE AND GAIN (d B)

2

0
3400 3420 3440 3460 3480 35203500 3540 3560 3580 3600

GAIN

P1dB

NOISE FI GURE

FREQUENCY (MHz )

Figure 22. Noise Figure, Gain, OIP3, and P1dB vs. Frequency

2.0

1.8

1.6

1.4

1.2

1.0

0.8

NOISE FI G URE (dB)

0.6

0.4

0.2

0
3400 3420 3440 3460 3480 3500 3520 3540 3560 3580 3600

+85°C

+25°C

–40°C

FREQUENCY (MHz)

Figure 23. Noise Figure vs. Temperature

S12

S21

06829-021

45

40

35

30

25

OIP3 AND P1dB (dBm)

20

15

10

06829-022

06829-023

2.0

1.8

1.6

1.4

1.2

1.0

0.8

NOISE FI G URE (dB)

0.6

0.4

0.2

0
3400 3420 3440 3460 3480 3500 3520 3540 3560 3580 3600

FREQUENCY (MHz)

Figure 24. Noise Figure vs. Frequency at 25°C, Multiple Devices

19
18
17
16
15
14
13
12

GAIN (dB)

11

P1dB

10

9
8
7
6

3400 3420 3440 3460 3480 3500 3520 3540 3560 3580 3600

OIP3

GAIN

–40°C

+25°C

+85°C

FREQUENCY (MHz )

+85°C

+25°C

Figure 25. Gain, OIP3, and P1dB vs. Temperature

42
40
38
36
34
32
30

OIP3 (dBm)

28
26
24
22
20

–14 –12 –8–10 –6–4–20246810121416

+25°C

+85°C

P

PER TONE (dBm)

OUT

Figure 26. OIP3 vs. Output Power (P

–40°C

) and Temperature

OUT

–40°C

+25°C

–40°C

+85°C

06829-024

41
39
37
35
33
31
29
27
25
23

OIP3 AND P1dB (dBm)

21
19
17
15

06829-025

06829-026

Rev. A | Page 10 of 24

ADL5523

900 MHz, VPOS = 3 V

Matched for optimal noise figure, external matching circuit included.

25
20
15
10

5

S11

0

–5

–10

S22

–15

S-PARAMETERS ( dB)

–20
–25
–30
–35

600 650 700 800 900750 850 950 1000 1050 1100 1150 1200

FREQUENCY (MHz)

S12

Figure 27. Typical S-Parameters, Log Magnitude

22
20
18
16
14
12
10

8
6

NOISE FI GURE AND GAIN (d B)

4
2
0

850 860 870 880 890 910900 920 930 940 950

GAIN

OIP3

P1dB

NOISE FI GURE

FREQUENCY (MHz )

Figure 28. Noise Figure, Gain, OIP3, and P1dB vs. Frequency

2.0

1.8

1.6

1.4

1.2

1.0

0.8

NOISE FI G URE (dB)

0.6

0.4

0.2

0

800 820 840 860 880 900 920 940 960 980 1000

+85°C

+25°C

–40°C

FREQUENCY (MHz)

Figure 29. Noise Figure vs. Temperature

S21

06829-027

34
32
30
28
26
24
22
20

OIP3 AND P1dB (dBm)

18
16
14
12

06829-028

06829-029

2.0

1.8

1.6

1.4

1.2

1.0

0.8

NOISE FI G URE (dB)

0.6

0.4

0.2

0

800 820 840 860 880 900 920 940 960 980 1000

FREQUENCY (MHz)

Figure 30. Noise Figure vs. Frequency at 25°C, Multiple Devices

23.0

22.5

22.0

–40°C

21.5

21.0

+85°C

20.5

GAIN (dB)

20.0

19.5

19.0

18.5

P1dB

850 860 870 880 890 900 910 920 930 940 950

FREQUENCY (MHz )

+25°C

–40°C

+25°C

–40°C

+25°C

+85°C

GAIN

Figure 31. Gain, OIP3, and P1dB vs. Temperature

32
31
30
29
28
27
26
25
24

OIP3 (dBm)

23
22
21
20
19
18

+85°C

–4 –2 20 4 6 8 10 12 14 16 18 20

P

OUT

Figure 32. OIP3 vs. Output Power (P

–40°C

+25°C

PER TONE (dBm)

) and Temperature

OUT

OIP3

+85°C

06829-030

32

30

28

26

24

22

20

OIP3 AND P1dB (dBm)

18

16

14

06829-032

06829-031

Rev. A | Page 11 of 24

ADL5523

1950 MHz, VPOS = 3 V

Matched for optimal noise figure, external matching circuit included.

20
15
10

5
0

S11

–5
–10
–15

S-PARAMETERS ( dB)

–20
–25
–30
–35

1800 1850 1900 2050 21001950 2000 2150 2200

S22

FREQUENCY (MHz)

Figure 33. Typical S-Parameters, Log Magnitude

18

16

14

12

10

8

6

4

NOISE FI GURE AND GAIN (d B)

2

0
1920 1930 1940 1950 1960 1970 1980

GAIN

OIP3

P1dB

NOISE FI GURE

FREQUENCY (MHz )

Figure 34. Noise Figure, Gain, OIP3, and P1dB vs. Frequency

2.0

1.8

1.6

1.4

1.2

1.0

0.8

NOISE FI G URE (dB)

0.6

0.4

0.2

0
1800 1820 1840 1860 1880 1900 1920 1940 1960 1980 2000

+85°C

+25°C

–40°C

FREQUENCY (MHz)

Figure 35. Noise Figure vs. Temperature

S12

S21

06829-033

32

30

28

26

24

22

20

OIP3 AND P1dB (dBm)

18

16

14

06829-034

06829-035

2.0

1.8

1.6

1.4

1.2

1.0

0.8

NOISE FI G URE (dB)

0.6

0.4

0.2

0
1800 1820 1840 1860 1880 1900 1920 1940 1960 1980 2000

FREQUENCY (MHz)

Figure 36. Noise Figure vs. Frequency at 25°C, Multiple Devices

18.5

18.0

17.5

17.0

16.5

GAIN (dB)

16.0

15.5

15.0

14.5
1920 1930 1940 1950 1960 1970 1980

GAIN

+85°C

–40°C

+25°C

FREQUENCY (MHz )

+25°C

+25°C

–40°C

–40°C

OIP3

+85°C

P1dB

Figure 37. Gain, OIP3, and P1dB vs. Temperature

30
29
28
27
26
25
24
23

OIP3 (dBm)

22
21
20
19
18

–8 –2–4–6 20 4 6 8 10 12 14 16 18

Figure 38. OIP3 vs. Output Power (P

+25°C

–40°C

+85°C

P

PER TONE (dBm)

OUT

) and Temperature

OUT

+85°C

06829-036

30

28

26

24

22

20

OIP3 AND P1dB (dBm)

18

16

14

06829-037

06829-038

Rev. A | Page 12 of 24

ADL5523

2600 MHz, VPOS = 3 V

Matched for optimal noise figure, external matching circuit included.

20

15

10

5

0

–5

–10

–15

S-PARAMETERS ( dB)

–20

–25

–30

2100 2200 2300 2600 27002400 2500 2800 2900

S21

S11

S22

S12

FREQUENCY (MHz)

Figure 39. Typical S-Parameters, Log Magnitude

18

16

14

12

10

8

6

4

NOISE FI GURE AND GAIN (d B)

2

0
2500 2520 2560 2600 2640 26802540 2580 2620 2660 2700

OIP3

GAIN

P1dB

NOISE FI GURE

FREQUENCY (MHz )

Figure 40. Noise Figure, Gain, OIP3, and P1dB vs. Frequency

2.0

1.8

1.6

1.4

1.2

1.0

0.8

NOISE FI G URE (dB)

0.6

0.4

0.2

0
2500 2520 2540 2560 2580 2600 2620 2640 2660 2680 2700

+85°C

+25°C

–40°C

FREQUENCY (MHz)

Figure 41. Noise Figure vs. Temperature

06829-039

32

30

28

26

24

22

20

OIP3 AND P1dB (dBm)

18

16

14

06829-040

06829-041

2.0

1.8

1.6

1.4

1.2

1.0

0.8

NOISE FI G URE (dB)

0.6

0.4

0.2

0
2500 2520 2540 2560 2580 2600 2620 2640 2660 2680 2700

FREQUENCY (MHz)

Figure 42. Noise Figure vs. Frequency at 25°C, Multiple Devices

15.5

15.0

14.5

14.0

13.5

13.0

GAIN (dB)

12.5

12.0

11.5

11.0
2500 2520 2540 2560 2580 2600 2620 2640 2660 2680 2700

P1dB

–40°C

+25°C

+85°C

–40°C

+85°C

FREQUENCY (MHz )

GAIN

OIP3

–40°C

+25°C

+85°C

+25°C

Figure 43. Gain, OIP3, and P1dB vs. Temperature

33
32
31

+25°C

30
29
28
27
26
25
24
23

OIP3 (dBm)

22
21
20
19
18
17
16

–6 0–2–4 42 6 8 1012141618

Figure 44. OIP3 vs. Output Power (P

–40°C

P

OUT

+85°C

PER TONE (dBm)

) and Temperature

OUT

06829-042

33

31

29

27

25

23

21

OIP3 AND P1dB (dBm)

19

17

15

06829-044

06829-043

Rev. A | Page 13 of 24

ADL5523

3500 MHz, VPOS = 3 V

Matched for optimal noise figure, external matching circuit included.

15

10

5

0

–5

–10

S-PARAMETERS ( dB)

–15

–20

–25

2800 2900 3000 3300 34003100 3200 3500 3600 3700

S11

S22

S21

S12

FREQUENCY (MHz)

Figure 45. Typical S-Parameters, Log Magnitude

18

16

14

12

10

8

6

4

NOISE FI GURE AND GAIN (d B)

2

0
3400 3420 3460 3500 3540 35803440 3480 3520 3560 3600

OIP3

GAIN

P1dB

NOISE FI GURE

FREQUENCY (MHz )

Figure 46. Noise Figure, Gain, OIP3, and P1dB vs. Frequency

2.0

1.8

1.6

1.4

1.2

1.0

0.8

NOISE FI G URE (dB)

0.6

0.4

0.2

0
3400 3420 3440 3460 3480 3500 3520 3540 3560 3580 3600

+85°C

+25°C

–40°C

FREQUENCY (MHz)

Figure 47. Noise Figure vs. Temperature

06829-045

32

30

28

26

24

22

20

OIP3 AND P1dB (dBm)

18

16

14

06829-046

06829-047

2.0

1.8

1.6

1.4

1.2

1.0

0.8

NOISE FI G URE (dB)

0.6

0.4

0.2

0
3400 3420 3440 3460 3480 3500 3520 3540 3560 3580 3600

FREQUENCY (MHz)

Figure 48. Noise Figure vs. Frequency at 25°C, Multiple Devices

16

–40°C

15

+25°C

14

+85°C

13

12

11

GAIN (dB)

10

GAIN

9

8

+85°C

7
3400 3420 3440 3460 3480 3500 3520 3540 3560 3580 3600

–40°C

+25°C

+85°C

–40°C

+25°C

FREQUENCY (MHz )

OIP3

P1dB

Figure 49. Gain, OIP3, and P1dB vs. Temperature

33
32
31
30
29
28
27
26

OIP3 (dBm)

25
24
23
22
21
20

–14 –8–10–12 –4–6 –2 0 2 4 8 126101416

+85°C

Figure 50. OIP3 vs. Output Power (P

–40°C

+25°C

P

PER TONE (dBm)

OUT

) and Temperature

OUT

06829-048

33

31

29

27

25

23

21

OIP3 AND P1dB (dBm)

19

17

15

06829-049

06829-050

Rev. A | Page 14 of 24

ADL5523

DC CHARACTERISTICS

75
70
65
60
55
50
45
40
35

SUPPLY CURRENT ( mA)

30
25
20

–40 –30 –10 50 6010 30–20 0 20 40 70 80 90

Figure 51. Supply Current vs. Temperature, 3 V and 5 V

VPOS = 5V

VPOS = 3V

TEMPERATURE ( °C)

06829-051

Rev. A | Page 15 of 24

ADL5523

V

BASIC CONNECTIONS

The basic connections for operating the ADL5523 are shown in
Figure 52. Capacitor C5 provides the power supply decoupling.
Inductor L1 (Coilcraft 0403HQ or 0402HP series) and Capacitor C1
(Murata High-Q GJM series or equivalent) provide the input
impedance matching, and the output impedance matching is
provided by either L2 or C3. Resistor R1 is used to set the supply
current, and the value of R1 is indirectly proportional to the
supply current (that is, increasing the value of R1 reduces the
supply current). The recommended external components for
selected frequencies are listed in Table 7.

For 5 V applications where the input power exceeds the input
compression point of approximately 7 dBm, a series resistor
(R2) of at least 8 Ω, with a high power rating (0.2 W minimum),
should be inserted on the VPOS line to protect the device from
the input power overdrive. In this case, reduce Resistor R1 from

1.3 kΩ to 600 Ω to keep the supply current at around 60 mA.
With R2 = 8.2 Ω (Susumu RP1608S-8R2-F) and R1 = 600 Ω, the
gain and noise figure for the ADL5523 are mostly unchanged.
Tabl e 6 lists OIP3 and P1dB at selected frequencies. For 3 V
power supply applications, a series resistor is not necessary for
the expected input overdrive powers up to 20 dBm.

POS GND

R1

ADL5523

RFIN RFOUT

L1

C1

1 VBIAS
2RFIN
3NC
4NC

Z1

Figure 52. ADL5523 Basic Connections

8VPOS
7RFOUT
6NC
5NC

TR1

TR2

W1

R2

C5

100nF

L2

C3

06829-052

Table 6. ADL5523 Performance at VPOS = 5 V, 25°C with
R2 = 8.2 Ω and R1 = 600 Ω

Frequency
(MHz)

Noise
Figure (dB)

Gain
(dB)

P1dB
(dBm)

OIP3 (dBm)

= 0 dBm)

(P

OUT

900 0.8 21.5 20.3 32.5
1950 1.0 17.0 20.7 34.0
2600 0.9 13.5 20.5 35.0
3500 1.0 11.3 20.1 35.0

Rev. A | Page 16 of 24

ADL5523

V

m

EVALUATION BOARD

Figure 53 shows the schematic of the ADL5523 evaluation board.
The board is powered by a single supply, and dc bias can be
applied to the board through clip-on leads at VPOS and GND
or through a 2-pin connector, W1.

The evaluation board comes optimized at 1950 MHz from the
factory, but it can be easily modified to work at any frequency
between 400 MHz and 4 GHz. Tabl e 7 lists the recommended
components at various frequencies.

POS GND

R1

ADL5523

RFIN RFOUT

L1

C1

1 VBIAS
2RFIN
3NC
4NC

Z1

8VPOS
7RFOUT
6NC
5NC

Figure 53. Evaluation Board Schematic

TR1

TR2

W1

R2

C5

100nF

L2

SOLDERING INFORMATION AND RECOMMENDED

Figure 55. Evaluation Board Layout (Bottom View)

06829-054

PCB LAND PATTERN

C4

DNP

C3

C2
0Ω

06829-152

Figure 56 shows the recommended land pattern for ADL5523.
To minimize thermal impedance, the exposed pad on the
package underside is soldered down to a ground plane. If
multiple ground layers exist, they are stitched together using
vias (a minimum of five vias is recommended). Pin 3 to Pin 6
can be left unconnected or can be connected to ground. For
more information on land pattern design and layout, refer to
the AN-772 Application Note, A Design and Manufacturing
Guide for the Lead Frame Chip Scale Package (LFCSP).

2.03mm

1

8

0.5m

0.71mm

1.85mm

4 5

1.53mm

1.78mm

06829-055

Figure 56. Recommended Land Pattern

06829-053

Figure 54. Evaluation Board Layout (Top View)

Table 7. Recommended Components and Positions of Matching Components for Basic Connections Tuned for Optimal Noise

1

C1
Frequency
(MHz)

(Size

0402)

C2
(Size

0402)

C3
(Size

0402)

C4
(Size

0402)

C5
(Size

0402)

L12
(Size

0403)

500 Open 0 Ω Open Open 100 nF 9 nH 12 nH 1.3 kΩ 0 Ω 0 0 C1 N/A
900 2.4 pF 0 Ω Open Open 100 nF 8.2 nH 3.4 nH 1.3 kΩ 0 Ω 0 0 C1 N/A
1300 2.7 pF 0 Ω 1.0 nF Open 100 nF 3.4 nH 0 Ω 1.3 kΩ 0 Ω 0 8.0 × 0.6 C1 6
1950 1.6 pF 0 Ω 1.0 nF Open 100 nF 1.0 nH 0 Ω 1.3 kΩ 0 Ω 2.5 × 0.6 5.5 × 0.6 C1 4
2140 1.6 pF 0 Ω 1.0 nF Open 100 nF 1.0 nH 0 Ω 1.3 kΩ 0 Ω 5.0 × 0.6 3.0 × 0.6 C1 2
2600 0.75 pF 0 Ω 1.0 nF Open 100 nF 1.0 nH 0 Ω 1.3 kΩ 0 Ω 8.0 × 0.6 0 C1 C3
3500 0.5 pF 0 Ω 1.0 nF Open 100 nF 2.4 pF5 0 Ω 1.3 kΩ 0 Ω 7.0 × 0.6 1 × 0.6 C1 1

1

The Murata GJM High-Q series capacitor is recommended for C1.

2

The Coilcraft High Q 0403HQ or 0402HP inductors are recommended for L1 and L2.

3

If R2 = 8 Ω, reduce R1 to 600 Ω.

4

If R2 = 8 Ω, use a high power resistor (0.2 W rating minimum).

5

Note that at 3500 MHz, a capacitor, not an inductor, is used at L1.

2

L2
Size

0403)

3

R1
(Size

0603)

4

R2
(Size

0603)

TR1
(mm)

TR2
(mm)

C1
Position

C3
Position

Rev. A | Page 17 of 24

ADL5523

TUNING THE ADL5523 FOR OPTIMAL NOISE FIGURE

The ADL5523 is a monolithic low noise amplifier (LNA) in a
3 mm × 3 mm LFCSP. The evaluation board, as shipped from
the factory, gives a noise figure of 0.9 dB over a bandwidth of
several hundred megahertz. The specific frequency where optimal
noise is reached depends on the tuning.

The bandwidth of the ADL5523 is 400 MHz to 4 GHz, although
noise figure degrades above 2.5 GHz as the gain begins to roll off.

This section is based on Analog Devices, Inc., lab measurements.
Although there are plots in which the Agilent Advanced Design
System (ADS) environment is used, the data in these plots come
entirely from Analog Devices lab measurements.

TUNING S22

Tuning of the LNA begins with S22 (output tuning). Tuning of
the LNA output is done by placing reactive components on the
bias line, referred to in the schematic in Figure 53 as VPOS.

On the LNA evaluation board, S22 tuning is achieved by either
the use of an inductor (L2) on the bias line or a shunt capacitor
(C3) on the bias line to ground. Typically, either L2 is required
or C3 but not both.

The evaluation board uses a slider on the bias line to make tuning
for S22 as easy as possible. The slider is an area of ground etch
adjacent to the bias line that is clear of solder mask. The bias
line in this area is also free of solder mask. This allows a capacitor
(C3) to be placed anywhere on the bias line to ground, which
provides easy and accurate tuning for S22.

Note that the PCB layout shows two capacitors, C3 and C4.
Typically, only one of these capacitors is needed for good
S22 tuning.

The slider is seen in the LNA PCB layout in Figure 57 as the
area near the red arrows to the right of the bias line. With a 0 Ω
resistor in place of L2, moving a 1 nF capacitor from the top to
the bottom effectively tunes S22 from 1400 MHz to 3500 MHz.
Tabl e 8 shows the component values and placement required for
S22 tuning from 800 MHz to 3200 MHz. For lower frequencies,
higher values of L2 can be used to tune S22, and for frequencies
from 3.2 GHz to 4.0 GHz, smaller values of capacitors can be
used on the slider.

Table 8. Capacitor and Inductor Tuning and Placement for
LNA S22 Tuning

Frequency (MHz) L2 (nH) C3 (nF) C3 Placement

800 3.4 Open N/A
1400 0 Ω 1 nF 6
2000 0 Ω 1 nF 4
2400 0 Ω 1 nF 3
2800 0 Ω 1 nF 2
3200 0 Ω 1 nF 1

Figure 57. PCB Layout for LNA Evaluation Board (Note Slider on Bias Line

Rev. A | Page 18 of 24

06829-056

with Capacitor Placement for S22 Tuning Noted by Arrows)

ADL5523

TUNING THE LNA INPUT FOR OPTIMAL GAIN

LNAs are generally tuned for either gain or noise optimization,
or some trade-off between the two. One figure of merit of an LNA
is how much trade-off must be made for one of these parameters to
optimize the other. With the ADL5523, an S11 of 6 dB to 8 dB
at the input to the matching network can still be achieved
typically when optimizing for noise.

For optimal gain matching, the goal is to use a matching network
that converts the input impedance of the LNA to the characteristic
impedance of the system, typically 50 Ω. Correct tuning for gain
matching results in a conjugate match. That is, the impedance of
the matching network at the LNA input, looking back toward
the generator, is always the complex conjugate of the LNA input
impedance when matched for gain.

Once S11*, the complex conjugate of S11, is known, a matching
circuit must be found that transforms the 50 Ω system impedance
into the conjugate S11 impedance. To do this, the designer starts at
the origin of the Smith Chart circle and finds components that
move the 50 Ω match to S11*.

The related impedances for gain matching are shown in Figure 58.
A Smith Chart representation of the conjugate match is shown
in Figure 59.

50Ω

MATCHING
NETWORK

50Ω

Figure 58. Matching LNA Input for Gain

S11

S11*

LNA

06829-057

TUNING THE LNA INPUT FOR OPTIMAL NOISE FIGURE

The point in the Smith Chart at which matching for optimal

OPT

OPT

. This

OPT

is a

.

noise occurs is typically referred to as gamma optimal or Γ
Typically, it is significantly different from the gain matching
point; finding Γ

is not as obvious as the gain match. Γ

OPT

function of the semiconductor structure and characteristics of
the LNA. The fabrication facility that produces the LNA typically
has this information. Γ

can also be determined by doing

OPT

source pull testing in the lab.

Noise matching for the ADL5523 is actually very easy because
the area of the Smith Chart where the noise figure is optimal or
near optimal is not confined to a narrow area around Γ
is very advantageous because it means that component variations
play a smaller part in the board-to-board variation of noise figure.

The matching area for optimal noise for the ADL5523 is shown
in Figure 60. Note that textbooks usually define noise circles as
a conjugate match. However, for the purpose of this data sheet,
the circle is a direct match. To find the correct matching circuit,
the designer must start with the S11 of the LNA and select
components that move the S11 to within this circle.

An important aspect of the overall ADL5523 ease of tuning is
that as long as S22 is matched for a particular frequency, the
noise matching area remains very consistent in its placement for
that frequency. If S22 is matched, take the measured S11 and
move it into the red circle shown in Figure 60 for optimal noise
matching.

1

S11*

S11

Figure 59. Smith Chart Representation of Conjugate Match

06829-058

Rev. A | Page 19 of 24

0.5

0.2

0.2

0.2

0.5

Figure 60. Area of Optimal Noise Matching for ADL5523

0.5 1 5 10

1

5

10

10

5

06829-059

ADL5523

S11 OF THE LNA WITH S22 MATCHED

To determine the correct matching circuit for optimal noise,
look at the results of S11 for the various frequencies at which
S22 was tuned earlier in the Tun i ng S 22 section. Once S11 is
determined for a particular frequency, find the matching
components that provided that match. Figure 62 and Figure 63
show S11 for the various frequencies. Again, these measurements
are all based on S22 being matched at that particular frequency.
Note that, for the examples shown in Figure 62 and Figure 63, S11
is either in the lower left quadrant of the Smith Chart or slightly
into the upper left. To move the impedance in the given noise
circle, a series L component at the LNA input is required. The L
values in the examples differ but a correct L value moves the match
along the constant R circle up into the upper left quadrant of the
Smith Chart.

A shunt capacitor can then be added to move the match along a
constant admittance line, down and to the right, directly into
the center of the noise circle given in Figure 60.

The solution for the structure of the match for the examples in
Figure 62 and Figure 63 is a series L to the input of the LNA
and a shunt capacitor at the generator end of this inductor. The
recommended components for matching at various frequencies
are shown in Ta bl e 7 .

An example of the effect of the series L, shunt C match, based
on the 800 MHz example, is given in Figure 61. This example
uses the output from the Agilent ADS Smith Chart tool.

Figure 62. S11 of ADL5523 with S22 Matched at 2 GHz

M1
FREQUENCY 400M Hz
S11 = 0.877/–44.639
IMPEDANCE = Z0 × (0.443 – j 2.365)

M2
FREQUENCY 2GHz
S11 = 0.615/–170.569
IMPEDANCE = Z0 × (0.240 – j 0.078)

M2

FREQUENCY (400M H z TO 4GHz)

M1
FREQUENCY 400M Hz
S11 = 0.864/–40.186
IMPEDANCE = Z0 × (0.594 – j2.615)

M2
FREQUENCY 3. 2GHz
S11 = 0.595/163.164

M2

IMPEDANCE = Z0 × (0.259 + j 0.138)

M1

06829-061

Figure 61. Example of Series L, Shunt C Matching Network for Γ

OPT

M1

FREQUENCY (400M H z TO 4GHz)

06829-062

Figure 63. S11 of ADL5523 with S22 Matched at 3.2 GHz

06829-060

Rev. A | Page 20 of 24

ADL5523

OUTLINE DIMENSIONS

3.25

3.00 SQ

INDICATOR

0.90 MAX

0.85 NOM

SEATING

PLANE

PIN 1

12° MAX

2.75

TOP

VIEW

0.70 MAX

0.65TYP

0.30

0.23

0.18

2.95

2.75 SQ

2.55

0.05 MAX

0.01 NOM

0.20 REF

0.60 MAX

Figure 64. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]

3 mm × 3 mm Body, Very Thin, Dual Lead

(CP-8-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

ADL5523ACPZ-R71 −40°C to +85°C 8-Lead LFCSP_VD, 7” Tape and Reel CP-8-2 Q1J
ADL5523-EVALZ1 Evaluation Board

1

Z = RoHS Compliant Part.

0.60 MAX

5

EXPOSED

PAD

(BOTT OM VIEW)

0.50

0.40

0.30

4

FOR PROPE R CONNECTION O F
THE EXPOSE D PAD, REF ER T O
THE PIN CONFIGURATION AND
FUNCTION DE SCRIPTIO NS
SECTION OF THIS DATA SHEET.

0.50
BSC

8

1.60

1.45

1.30

1

1.89

1.74

1.59

PIN 1
INDICATOR

72408-B

Rev. A | Page 21 of 24

ADL5523

NOTES

Rev. A | Page 22 of 24

ADL5523

NOTES

Rev. A | Page 23 of 24

ADL5523

NOTES

©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06829-0-9/09(A)

Rev. A | Page 24 of 24