Datasheet ADL5521 Datasheet (ANALOG DEVICES)

400 MHz to 4000 MHz

FEATURES

Operation from 400 MHz to 4000 MHz
Noise figure of 0.8 dB at 900 MHz
Requires few external components
Integrated active bias control circuit
Integrated dc blocking capacitors
Adjustable bias for low power applications
Single-supply operation from 3 V to 5 V
Gain of 20.8 dB at 900 MHz
OIP3 of 37.0 dBm at 900 MHz
P1dB of 21.8 dBm at 900 MHz
Small footprint LFCSP
Pin-compatible version with 21.5 dB gain available

GENERAL DESCRIPTION

The ADL5521 is a high performance GaAs pHEMT low noise
amplifier. It provides high gain and low noise figure for single­downconversion IF sampling receiver architectures as well as
direct-downconversion receivers.

The ADL5521 provides a high level of integration by incorporating
the active bias and dc blocking capacitors, making it very easy
to use while not sacrificing design flexibility.

Low Noise Amplifier

ADL5521

FUNCTIONAL BLOCK DIAGRAM

ACTIVE

1VBIAS

BIAS

2RFIN
3NC

ADL5521

4NC

NC = NO CONNECT

Figure 1.

The ADL5521 is easy to tune, requiring only a few external
components. The device can support operation from 3 V to 5 V,
and the current draw can be adjusted with the external bias
resistor for applications requiring low power consumption.

The ADL5521 comes in a compact, thermally enhanced, 3 mm ×
3 mm LFCSP and operates over the temperature range of

−40°C to +85°C.

A fully populated evaluation board is also available.

8 VPOS
7RFOUT
6NC
5NC

06828-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2008–2009 Analog Devices, Inc. All rights reserved.

ADL5521

TABLE OF CONTENTS

Features .............................................................................................. 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

AC Specifications .......................................................................... 3

DC Specifications ......................................................................... 4

De-Embedded S-Parameters, VPOS = 3 V to 5 V, RFIN =

Port 1, VPOS = Port 2, RFOUT = Port 3 .................................. 4

Absolute Maximum Ratings ............................................................ 5

ESD Caution .................................................................................. 5

Pin Configuration and Function Descriptions ............................. 6

Typical Performance Characteristics ............................................. 7

900 MHz, VPOS = 5 V ................................................................. 7

1950 MHz, VPOS = 5 V .............................................................. 8

2600 MHz, VPOS = 5 V .............................................................. 9

3500 MHz, VPOS = 5 V ............................................................ 10

900 MHz, VPOS = 3 V .............................................................. 11

1950 MHz, VPOS = 3 V ............................................................ 12

2600 MHz, VPOS = 3 V ............................................................ 13

3500 MHz, VPOS = 3 V ............................................................ 14

DC Characteristics ..................................................................... 15

Basic Connections .......................................................................... 16

Evaluation Board ............................................................................ 17

Soldering Information and Recommended PCB

Land Pattern ................................................................................ 17

Tuning the ADL5521 for Optimal Noise Figure ........................ 18

Tuning S22 ................................................................................... 18

Tuning the LNA Input for Optimal Gain ................................ 19

Tuning the LNA Input for Optimal Noise Figure .................. 19

S11 of the LNA with S22 Matched ........................................... 20

Outline Dimensions ....................................................................... 21

Ordering Guide .......................................................................... 21

REVISION HISTORY

9/09—Rev. 0 to Rev. A

Updated Maximum Junction Temperature Unit (Table 4) ......... 5

10/08—Revision 0: Initial Version

Rev. A | Page 2 of 24

ADL5521

SPECIFICATIONS

AC SPECIFICATIONS

TA = 25°C, R1 = 1.3 kΩ; parameters include matching circuit, matched for optimal noise, unless otherwise noted.

Table 1.

3 V 5 V
Parameter Conditions Min Typ Max Min Typ Max Unit

FREQUENCY = 900 MHz

Gain (S21) 20.3 20.8 dB

vs. Frequency ±50 MHz ±0.28 ±0.33 dB

vs. Temperature −40°C ≤ TA ≤ +85°C ±0.53 ±0.46 dB
Noise Figure1 0.8 0.9 dB
Output Third-Order Intercept (OIP3) Δf = 1 MHz, P
Output 1 dB Compression Point (P1dB) 17.8 21.8 dBm
Input Return Loss (S11) −8.0 −9.0 dB
Output Return Loss (S22) −14.7 −15.3 dB
Isolation (S12) −23.8 −25.0 dB

FREQUENCY = 1950 MHz

Gain (S21) 15.4 14.7 15.8 17.0 dB

vs. Frequency ±30 MHz ±0.04 ±0.06 dB

vs. Temperature −40°C ≤ TA ≤ +85°C ±0.43 ±0.40 dB
Noise Figure1 1.0 1.0 dB
Output Third-Order Intercept (OIP3) Δf = MHz, P
Output 1 dB Compression Point (P1dB) 17.6 21.8 dBm
Input Return Loss (S11) −10.5 −12.5 dB
Output Return Loss (S22) −25.5 −25.5 dB
Isolation (S12) −20.2 −21.0 dB

FREQUENCY = 2600 MHz

Gain (S21) 12.4 12.8 dB

vs. Frequency ±100 MHz ±0.35 ±0.35 dB

vs. Temperature −40°C ≤ TA ≤ +85°C ±0.46 ±0.45 dB
Noise Figure1 0.9 1.0 dB
Output Third-Order Intercept (OIP3) Δf = 1 MHz, P
Output 1 dB Compression Point (P1dB) 17.1 21.5 dBm
Input Return Loss (S11) −7.1 −7.7 dB
Output Return Loss (S22) −14.1 −13.5 dB
Isolation (S12) −20.0 −20.5 dB

FREQUENCY = 3500 MHz

Gain (S21) 10.0 10.3 dB

vs. Frequency ±100 MHz ±0.56 ±0.59 dB

vs. Temperature −40°C ≤ TA ≤ +85°C ±0.66 ±0.63 dB
Noise Figure1 1.0 1.1 dB
Output Third-Order Intercept (OIP3) Δf = 1 MHz, P
Output 1 dB Compression Point (P1dB) 17.0 20.9 dBm
Input Return Loss (S11) −18.0 −18.3 dB
Output Return Loss (S22) −10.5 −11.0 dB
Isolation (S12) −17.8 −18.1 dB

1

Noise figure de-embedded to first matching component on input side.

= 0 dBm per tone 28.0 37.0 dBm

OUT

= 0 dBm per tone 29.0 35.0 dBm

OUT

= 0 dBm per tone 30.5 35.5 dBm

OUT

= 0 dBm per tone 31.0 36.0 dBm

OUT

Rev. A | Page 3 of 24

ADL5521

DC SPECIFICATIONS

Table 2.

3 V 5 V

Parameter Conditions

Supply Current 30 60 mA

vs. Temperature −40°C ≤ TA ≤ +85°C ±4 ±7 mA

DE-EMBEDDED S-PARAMETERS, VPOS = 3 V TO 5 V, RFIN = PORT 1, VPOS = PORT 2, RFOUT = PORT 3

Table 3.

Frequency
(GHz)

0.125 −3.8/−11.3 −34.5/+8.9 −37.2/+51.8 +21.5/+161 −11.4/−133 −4.4/+32 +18.8/−155 +4.3/+32 −4.8/−80.9

0.25 −3.8/−24.5 −34.4/+26.6 −35.0/+50.5 +20.2/+158 −10.4/−153 −3.5/+19.8 +19.5/−178 −3.4/+20.1 −8.0/−111

0.375 −4.0/−37.1 −33.3/+39.6 −33.3/+54.2 +19.5/+154 −9.5/−158 −3.5/+16.5 +19.4/+170 −3.4/+17.0 −9.2/−126

0.5 −4.4/−48.9 −32.2/+48.9 −31.9/+57.7 +18.7/+150 −8.7/−158 −3.6/+16.2 +19.0/+161 −3.5/+16.7 −9.7/−133

0.625 −4.7/−60.0 −31.2/+55.8 −30.7/+60.2 +18.0/+146 −7.9/−155 −3.8/+17.2 +18.5/+153 −3.7/+17.7 −9.7/−137

0.75 −5.0/−70.2 −30.4/+61.3 −29.7/+61.9 +17.2/+143 −7.2/−150 −4.1/+19.1 +18.0/+147 −3.9/+19.5 −9.5/−139

0.875 −5.3/−79.1 −29.7/+66.6 −28.9/+63.5 +16.4/+141 −6.8/−144 −4.3/+21.6 +17.3/+141 −4.2/+22.1 −9.3/−139

1.0 −5.5/−86.9 −29.0/+71.2 −28.2/+64.7 +15.7/+140 −6.4/−137 −4.6/+24.8 +16.7/+137 −4.4/+25.1 −9.0/−138

1.125 −5.6/−93.3 −28.4/+75.6 −27.6/+65.6 +14.9/+138 −6.2/−129 −4.8/+28.0 +16.0/+132 −4.6/+28.3 −8.6/−137

1.25 −5.7/−98.0 −27.9/+79.8 −27.2/+66.9 +14.3/+138 −6.1/−121 −4.9/+31.9 +15.3/+129 −4.7/+32.1 −8.2/−135

1.375 −5.7/−102 −27.3/+84.0 −26.8/+68.0 +13.7/+138 −6.3/−113 −4.9/+35.7 +14.5/+126 −4.8/+35.8 −7.9/−133

1.5 −5.8/−104 −26.8/+87.8 −26.5/+69.4 +13.1/+138 −6.6/−105 −5.0/+39.4 +13.7/+123 −4.8/+39.4 −7.5/−131

1.625 −5.9/−104 −26.2/+91.6 −26.3/+71.5 +12.6/+138 −7.2/−97.2 −5.0/+43.5 +12.9/+122 −4.8/+43.5 −7.2/−129

1.75 −5.8/−104 −25.7/+94.8 −26.2/+73.9 +12.2/+138 −8.0/−91.0 −4.9/+47.0 +12.1/+121 −4.7/+47.0 −6.9/−127

1.875 −5.8/−103 −25.1/+98.2 −26.0/+76.8 +11.8/+139 −9.2/−86.4 −4.7/+50.5 +11.3/+122 −4.5/+50.5 −6.7/−126

2.0 −5.6/−101 −24.6/+101 −26.0/+80.1 +11.5/+139 −10.7/−85.8 −4.5/+53.6 +10.5/+123 −4.4/+53.6 −6.6/−125

2.125 −5.5/−99.3 −24.0/+104 −25.9/+85.1 +11.2/+139 −12.4/−92.3 −4.4/+56.6 +9.8/+125 −4.2/+56.6 −6.5/−125

2.25 −5.3/−97.2 −23.6/+106 −25.7/+91.0 +10.8/+139 −13.4/−110 −4.3/+59.1 +9.3/+129 −4.1/+59.1 −6.6/−125

2.375 −5.1/−95.9 −23.2/+109 −25.3/+96.7 +10.4/+139 −12.0/−129 −4.3/+61.6 +8.9/+132 −4.1/+61.7 −6.9/−127

2.5 −4.9/−94.8 −23.0/+111 −24.6/+103 +9.9/+140 −9.4/−136 −4.4/+64.3 +8.9/+136 −4.2/+64.4 −7.4/−128

2.625 −4.8/−94.4 −22.9/+114 −23.8/+108 +9.2/+141 −6.9/−135 −4.6/+67.3 +9.0/+139 −4.4/+67.4 −8.2/−130

2.75 −4.8/−94.8 −23.0/+118 −22.8/+111 +8.4/+143 −4.9/−127 −5.1/+70.9 +9.3/+140 −4.9/+71.0 −9.2/−132

2.875 −4.9/−95.4 −23.3/+122 −21.8/+114 +7.5/+146 −3.4/−117 −5.7/+75.0 +9.6/+141 −5.5/+75.2 −10.5/−133

3.0 −5.2/−96.9 −23.8/+127 −20.9/+114 +6.4/+149 −2.2/−104 −6.4/+79.7 +9.9/+140 −6.2/+79.8 −12.2/−133

3.125 −5.6/−98.9 −24.5/+133 −20.0/+114 +5.1/+153 −1.4/−89.0 −7.5/+85.2 +10.2/+138 −7.2/+85.0 −14.2/−132

3.25 −6.1/−102 −25.4/+139 −19.2/+114 +3.5/+157 −0.89/−73.4 −8.8/+90.4 +10.3/+136 −8.5/+90.4 −16.2/−126

3.375 −6.6/−105 −26.4/+144 −18.6/+112 +1.9/+162 −0.59/−57.8 −10.2/+95.5 +10.4/+133 −9.9/+95.4 −177/−116

3.5 −7.2/−110 −27.5/+149 −18.0/+111 +0.27/+165 −0.41/−42.6 −11.6/+100 +10.3/+130 −11.4/+99.7 −18.1/−104

3.625 −7.7/−115 −28.6/+154 −17.6/+109 −1.3/+169 −0.23/−27.6 −13.1/+104 +10.2/+127 −12.7/+104 −17.1/−93.5

3.75 −8.1/−123 −29.4/+158 −17.3/+106 −2.7/+172 +0.035/−12.8 −14.3/+109 +10.0/+124 −14.0/+108 −15.7/−88.0

3.875 −8.3/−132 −30.1/+163 −17.0/+103 −3.9/+175 +0.45/+2.3 −15.4/+114 +9.7/+119 −15.1/+113 −14.0/−87.7

4.0 −8.2/−140 −30.6/+168 −16.9/+99.8 −4.8/−180 +1.0/+18.9 −16.3/+120 +9.4/+115 −16.0/+120 −12.5/−89.2

S11
(dB/Ang)

S12
(dB/Ang)

S13
(dB/Ang)

S21
(dB/Ang)

Min Typ Max Min Typ Max Unit

S22
(dB/Ang)

S23
(dB/Ang)

S31
(dB/Ang)

S32
(dB/Ang)

S33
(dB/Ang)

Rev. A | Page 4 of 24

ADL5521

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Rating

Supply Voltage, VPOS 5.5 V
RF Input Level 7 dBm
RF Input Level (with 8 Ω Series Resistor on VPOS) 20 dBm
Internal Power Dissipation 500 mW
θJA (Junction to Air) 50°C/W
Maximum Junction Temperature 150°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. A | Page 5 of 24

ADL5521

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1VBIAS

ADL5521

2RFIN
3NC
4NC

NOTES

1. NC = NO CONNEC T.

2. CONNECT THE EXPOSED PAD TO A LOW
IMPEDANCE GROUND PL ANE .

TOP VIEW

(Not to S cale)

EXPOSED PAD

8 VPOS
7RFOUT
6NC
5NC

06828-002

Figure 2. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 VBIAS Internal DC Bias. This pin should be connected to VPOS through the R1 resistor.
2 RFIN RF Input. This is the input to the LNA.
3, 4, 5, 6 NC No Connection. No internal connection.
7 RFOUT RF Output.
8 VPOS

Supply Voltage. DC bias needs to be bypassed to ground using a low inductance capacitor. This pin is
also used for output matching. See the Basic Connections section.

9 (EPAD) Exposed Pad (EPAD) GND. Connect the exposed pad to a low impedance ground plane.

Rev. A | Page 6 of 24

ADL5521

TYPICAL PERFORMANCE CHARACTERISTICS

900 MHz, VPOS = 5 V

Matched for optimal noise figure, external matching circuit included.

25
20
15
10

5
0

–5
–10
–15

S-PARAMETERS ( dB)

–20
–25
–30
–35

600 650 700 750 800 850 900 950 1000 1050 1100 1150 1200

S21

S11

S22

S12

FREQUENCY (MHz)

Figure 3. Typical S-Parameters, Log Magnitude

22
20
18
16
14
12
10

8
6

NOISE FI GURE AND GAIN (d B)

4
2
0

850 860 870 880 890 900 910 920 930 940 950

GAIN

OIP3

P1dB

NOISE FI GURE

FREQUENCY (MHz)

Figure 4. Noise Figure, Gain, OIP3, and P1dB vs. Frequency

2.0

1.8

1.6

1.4
+85°C

+25°C

–40°C

FREQUENCY (MHz)

NOISE FIGURE (dB)

1.2

1.0

0.8

0.6

0.4

0.2

0

800 1000980960940920900880860840820

Figure 5. Noise Figure vs. Temperature

06828-003

55
50
45
40
35
30
25
20

OIP3 AND P1dB ( dBm)

15
10
5
0

06828-004

06828-005

2.0

1.8

1.6

1.4

1.2

1.0

0.8

NOISE FIGURE (dB)

0.6

0.4

0.2

0

800 820 840 860 880 900 920 940 960 1000980

FREQUENCY (MHz)

Figure 6. Noise Figure vs. Frequency at 25°C, Multiple Devices

23.0
+25°C

22.5

22.0

21.5

21.0

20.5

GAIN (dB)

20.0

19.5

19.0

18.5

18.0

850 860 870 880 890 900 910 920 930 940 950

+85°C

–40°C

+25°C

FREQUENCY (MHz)

–40°C
+25°C

+85°C

GAIN

–40°C

+85°C

Figure 7. Gain, OIP3, and P1dB vs. Temperature

42
40
38
36
34
32
30

OIP3 (dBm)

28
26
24
22
20

–4 –2 2220181614121086420

P

OUT

Figure 8. OIP3 vs. Output Power (P

+85°C

PER TONE (dBm)

+25°C

) and Temperature

OUT

OIP3

P1dB

–40°C

06828-006

39

37

35

33

31

29

27

25

OIP3 AND P1dB ( dBm)

23

21

19

06828-008

06828-007

Rev. A | Page 7 of 24

ADL5521

1950 MHz, VPOS = 5 V

Matched for optimal noise figure, external matching circuit included.

20
15
10

5
0

–5
–10
–15

S-PARAMETERS ( dB)

–20
–25
–30
–35

1800 1850 1900 1950 2000 2050 2100 2150 2200

S11

Figure 9. Typical S-Parameters, Log Magnitude

18

16

14

12

10

8

6

4

NOISE FI GURE AND GAIN (d B)

2

0
1920 1930 1940 1950 1960 1970 1980

Figure 10. Noise Figure, Gain, OIP3, and P1dB vs. Frequency

2.0

1.8

1.6

1.4

1.2

1.0

0.8

NOISE FI G URE (dB)

0.6

0.4

0.2

0
1800 2000198019601940192019001880186018401820

Figure 11. Noise Figure vs. Temperature

S21

S12

S22

FREQUENCY (MHz)

GAIN

OIP3

P1dB

NOISE FI GURE

FREQUENCY (MHz)

+85°C

+25°C

–40°C

FREQUENCY (MHz)

06828-009

45

40

35

30

25

20

15

OIP3 AND P1dB (dBm)

10

5

0

06828-010

06828-011

2.0

1.8

1.6

1.4

1.2

1.0

0.8

NOISE FI G URE (dB)

0.6

0.4

0.2

0
1800 1820 1840 1860 1880 1900 1920 1940 1960 20001980

FREQUENCY (MHz)

Figure 12. Noise Figure vs. Frequency at 25°C, Multiple Devices

18.0

17.5

17.0

16.5

16.0

15.5

GAIN (dB)

15.0

14.5

14.0

13.5

13.0

+25°C

GAIN

1920 1930 1940 1950 1960 1970 1980

–40°C

+85°C

+25°C

+85°C

FREQUENCY (MHz)

–40°C
+25°C
+85°C

–40°C

OIP3

P1dB

Figure 13. Gain, OIP3, and P1dB vs. Temperature

40

38

36

34

32

30

28

OIP3 (dBm)

26

24

22

20

–8 –4–6 –2 20181614121086420

Figure 14. OIP3 vs. Output Power (P

+85°C

+25°C

P

PER TONE (dBm)

OUT

) and Temperature

OUT

–40°C

06828-012

39

37

35

33

31

29

27

25

OIP3 AND P1dB (dBm)

23

21

19

06828-013

06828-014

Rev. A | Page 8 of 24

ADL5521

2600 MHZ, VPOS = 5 V

Matched for optimal noise figure, external matching circuit included.

20

15

10

5

0

–5

–10

S-PARAMETERS ( dB)

–15

–20

–25

2100 2200 2300 2400 2500 2600 2700 2800 2900

S11

S22

S12

FREQUENCY (MHz)

S21

Figure 15. Typical S-Parameters, Log Magnitude

14

12

10

8

6

4

NOISE FI GURE AND GAIN (d B)

2

0
2500 2520 2540 2560 2580 2600 2620 2640 2660 2680 2700

GAIN

OIP3

P1dB

NOISE FI GURE

FREQUENCY (MHz)

Figure 16. Noise Figure, Gain, OIP3, and P1dB vs. Frequency

2.0

1.8

1.6

1.4

1.2

1.0

0.8

NOISE FI G URE (dB)

0.6

0.4

0.2

0

2500 2700268026602640262026002580256025402520

+85°C

+25°C

–40°C

FREQUENCY (MHz)

Figure 17. Noise Figure vs. Temperature

06828-015

45

40

35

30

25

OIP3 AND P1dB (dBm)

20

15

10

06828-016

06828-017

2.0

1.8

1.6

1.4

1.2

1.0

0.8

NOISE FI G URE (dB)

0.6

0.4

0.2

0
2500 2520 2540 2560 2580 2600 2620 2640 2660 27002680

FREQUENCY (MHz)

Figure 18. Noise Figure vs. Frequency at 25°C, Multiple Devices

15.0

14.5

14.0

13.5

13.0

12.5

GAIN (dB)

12.0

11.5

11.0

10.5

10.0
2500 2540 2560 2580 2600 2620 2640 2660 26802520 2700

–40°C

+25°C

GAIN

+25°C

+85°C

–40°C

+85°C

FREQUENCY (MHz)

OIP3

–40°C

+25°C
+85°C

P1dB

Figure 19. Gain, OIP3, and P1dB vs. Temperature

40

38

36

34

32

30

28

OIP3 (dBm)

26

24

22

20

–6 –4 –2 20181614121086420

P

OUT

Figure 20. OIP3 vs. Output Power (P

PER TONE (dBm)

OUT

–40°C

+85°C

) and Temperature

+25°C

06828-018

39

37

35

33

31

29

27

25

OIP3 AND P1dB ( dBm)

23

21

19

06828-020

06828-019

Rev. A | Page 9 of 24

ADL5521

3500 MHz, VPOS = 5 V

Matched for optimal noise figure, external matching circuit included.

15

10

5

0

–5

–10

S-PARAMETERS ( dB)

–15

–20

–25

2800 2900 3000 3100 3200 3300 3400 3500 3600 3700

S11

Figure 21. Typical S-Parameters, Log Magnitude

12

10

8

6

4

NOISE FI GURE AND GAIN (d B)

2

0
3400 3420 3440 3460 3480 3500 3520 3540 3560 3580 3600

Figure 22. Noise Figure, Gain, OIP3, and P1dB vs. Frequency

2.0

1.8

1.6

1.4

1.2

1.0

0.8

NOISE FIGURE (dB)

0.6

0.4

0.2

0
3400 3600358035603540352035003480346034403420

Figure 23. Noise Figure vs. Temperature

S21

S12

S22

FREQUENCY (MHz)

GAIN

OIP3

P1dB

NOISE FI GURE

FREQUENCY (MHz)

+85°C

+25°C

–40°C

FREQUENCY (MHz)

06828-021

45

40

35

30

25

OIP3 AND P1dB ( dBm)

20

15

06828-022

06828-023

2.0

1.8

1.6

1.4

1.2

1.0

0.8

NOISE FIGURE (dB)

0.6

0.4

0.2

0
3400 3420 3440 3460 3480 3500 3520 3540 3560 36003580

FREQUENCY (MHz)

Figure 24. Noise Figure vs. Frequency at 25°C, Multiple Devices

13.0

12.5

12.0

11.5

11.0

10.5

10.0

GAIN (dB)

9.5

9.0

8.5

8.0

7.5
3400 3440 3460 3480 3500 3520 3540 3560 35803420 3600

+85°C

GAIN

+25°C

–40°C

+25°C

–40°C

+85°C

FREQUENCY (MHz)

OIP3

–40°C

+25°C

+85°C

P1dB

Figure 25. Gain, OIP3, and P1dB vs. Temperature

40
39
38
37
36
35
34
33

OIP3 (dBm)

32
31
30
29
28
27

–14–12–10–8–6–4–20246810121416

+85°C

P

PER TONE (dBm)

OUT

Figure 26. OIP3 vs. Output Power (P

–40°C

+25°C

) and Temperature

OUT

06828-024

40
38
36
34
32
30
28
26

OIP3 AND P1dB ( dBm)

24
22
20
18

06828-025

06828-026

Rev. A | Page 10 of 24

ADL5521

900 MHz, VPOS = 3 V

Matched for optimal noise figure, external matching circuit included.

25
20
15
10

5
0

–5
–10
–15
–20

S-PARAMETERS ( dB)

–25
–30
–35
–40
–45

600 650 700 750 800 850 900 950 1000 1050 1100 1150 1200

S11

S12

FREQUENCY (MHz)

S21

S22

Figure 27. Typical S-Parameters, Log Magnitude

22
20
18
16
14
12
10

8
6

NOISE FI GURE AND GAIN (d B)

4
2
0

850 860 870 880 890 900 910 920 930 940 950

GAIN

OIP3

P1dB

NOISE FI GURE

FREQUENCY (MHz)

Figure 28. Noise Figure, Gain, OIP3, and P1dB vs. Frequency

2.0

1.8

1.6

1.4
+85°C

+25°C

–40°C

FREQUENCY (MHz)

NOISE FIGURE (dB)

1.2

1.0

0.8

0.6

0.4

0.2

0

800 1000980960940920900880860840820

Figure 29. Noise Figure vs. Temperature

06828-027

34
32
30
28
26
24
22
20

OIP3 AND P1dB ( dBm)

18
16
14
12

06828-028

06828-029

2.0

1.8

1.6

1.4

1.2

1.0

0.8

NOISE FIGURE (dB)

0.6

0.4

0.2

0

800 820 840 860 880 900 920 940 960 1000980

FREQUENCY (MHz)

Figure 30. Noise Figure vs. Frequency at 25°C, Multiple Devices

22.5

22.0

21.5

21.0

20.5

GAIN (dB)

20.0

19.5

19.0

18.5

+25°C

850 870 880 890 900 910 920 930 940860 950

–40°C

+25°C

–40°C

+85°C

+25°C

–40°C

+85°C

GAIN

+85°C

FREQUENCY (MHz)

OIP3

P1dB

Figure 31. Gain, OIP3, and P1dB vs. Temperature

31
30
29
28
27
26
25
24

OIP3 (dBm)

23
22
21
20
19
18

–4–202468101214161820

+25°C

+85°C

P

PER TONE (dBm)

OUT

Figure 32. OIP3 vs. Output Power (P

–40°C

) and Temperature

OUT

06828-030

32

30

28

26

24

22

OIP3 AND P1dB ( dBm)

20

18

16

06828-032

06828-031

Rev. A | Page 11 of 24

ADL5521

1950 MHz, VPOS = 3 V

Matched for optimal noise figure, external matching circuit included.

20
15
10

5
0

–5
–10
–15

S-PARAMETERS ( dB)

–20
–25
–30
–35

1800 1850 1900 1950 2000 2050 2100 2150 2200

Figure 33. Typical S-Parameters, Log Magnitude

16

14

12

10

8

6

4

NOISE FI GURE AND GAIN (d B)

2

0
1920 1930 1940 1950 1960 1970 1980

Figure 34. Noise Figure, Gain, OIP3, and P1dB vs. Frequency

2.0

1.8

1.6

1.4

1.2

1.0

0.8

NOISE FIGURE (dB)

0.6

0.4

0.2

0
1800 2000198019601940192019001880186018401820

Figure 35. Noise Figure vs. Temperature

S21

S11

S12

S22

FREQUENCY (MHz)

GAIN

OIP3

P1dB

NOISE FI GURE

FREQUENCY (MHz)

+85°C

+25°C

–40°C

FREQUENCY (MHz)

06828-033

32

30

28

26

24

22

OIP3 AND P1dB ( dBm)

20

18

16

06828-034

06828-035

2.0

1.8

1.6

1.4

1.2

1.0

0.8

NOISE FIGURE (dB)

0.6

0.4

0.2

0
1800 1820 1840 1960 1980 1900 1920 1940 1960 20001980

FREQUENCY (MHz)

Figure 36. Noise Figure vs. Frequency at 25°C, Multiple Devices

17.5

17.0

16.5

16.0

15.5

GAIN (dB)

15.0

14.5

14.0

13.5
1920 1930 1940 1950 1960 1970 1980

–40°C

+25°C

GAIN

+25°C

+85°C

–40°C

+25°C

+85°C

–40°C

+85°C

FREQUENCY (MHz )

OIP3

P1dB

Figure 37. Gain, OIP3, and P1dB vs. Temperature

32
31
20
29
28
27
26
25
24

OIP3 (dBm)

23
22
21
20
19
18

–8 –6 –4 –2 0 2 4 6 8 10 12 14 1816

+25°C

P

OUT

+85°C

PER TONE (dBm)

Figure 38. OIP3 vs. Output Power (P

–40°C

) and Temperature

OUT

06828-036

32

30

28

26

24

22

OIP3 AND P1dB ( dBm)

20

18

16

06828-037

06828-038

Rev. A | Page 12 of 24

ADL5521

2600 MHZ, VPOS = 3 V

Matched for optimal noise figure, external matching circuit included.

20

15

10

5

0

–5

–10

S-PARAMETERS ( dB)

–15

–20

–25

2100 2200 2300 2400 2500 2600 2700 2800 2900

S21

S11

S22

S12

FREQUENCY (MHz)

Figure 39. Typical S-Parameters, Log Magnitude

20

18

16

14

12

10

8

6

NOISE FI GURE AND GAIN (d B)

4

2

0
2500 2520 2540 2560 2580 2600 2620 2640 2660 2680 2700

OIP3

GAIN

P1dB

NOISE FI GURE

FREQUENCY (MHz)

Figure 40. Noise Figure, Gain, OIP3, and P1dB vs. Frequency

2.0

1.8

1.6

1.4

1.2

1.0

0.8

NOISE FIGURE (dB)

0.6

0.4

0.2

0

2500 2700268026602640262026002580256025402520

+85°C

+25°C

–40°C

FREQUENCY (MHz)

Figure 41. Noise Figure vs. Temperature

06828-039

34

32

30

28

26

24

22

20

OIP3 AND P1dB ( dBm)

18

16

14

06828-040

06828-041

2.0

1.8

1.6

1.4

1.2

1.0

0.8

NOISE FIGURE (dB)

0.6

0.4

0.2

0
2500 2520 2540 2560 2580 2600 2620 2640 2660 27002680

FREQUENCY (MHz)

Figure 42. Noise Figure vs. Frequency at 25°C, Multiple Devices

14.5

14.0

13.5

13.0

12.5

12.0

GAIN (dB)

11.5

11.0

10.5

10.0
2500 2520 2560 2580 2620 2660 27002540 2600 2640 2680

GAIN

+25°C

–40°C

+25°C

–40°C

FREQUENCY (MHz)

+85°C

+85°C

OIP3

–40°C

+25°C

+85°C

P1dB

Figure 43. Gain, OIP3, and P1dB vs. Temperature

33
32
31
30
29
28
27
26
25
24

OIP3 (dBm)

23
22
21
20
19
18
17

–6–4–202468101214 1816

+85°C

+25°C

P

PER TONE (dBm)

OUT

Figure 44. OIP3 vs. Output Power (P

–40°C

) and Temperature

OUT

06828-042

34

32

30

28

26

24

22

OIP3 AND P1dB ( dBm)

20

18

16

06828-044

06828-043

Rev. A | Page 13 of 24

ADL5521

3500 MHZ, VPOS = 3 V

Matched for optimal noise figure, external matching circuit included.

15

10

5

0

–5

–10

S-PARAMETERS ( dB)

–15

–20

–25

2800 2900 3000 3100 3200 3300 3400 3500 37003600

Figure 45. Typical S-Parameters, Log Magnitude

20

18

16

14

12

10

8

6

NOISE FI GURE AND GAIN (d B)

4

2

0
3400 3420 3440 3460 3480 3500 3520 3540 3560 3580 3600

Figure 46. Noise Figure, Gain, OIP3, and P1dB vs. Frequency

2.0

1.8

1.6

1.4

1.2

1.0

0.8

NOISE FIGURE (dB)

0.6

0.4

0.2

0
3400 3600358035603540352035003480346034403420

Figure 47. Noise Figure vs. Temperature

S21

S11

S12

S22

FREQUENCY (MHz)

OIP3

GAIN

P1dB

NOISE FI GURE

FREQUENCY (MHz)

FREQUENCY (MHz)

+85°C

+25°C

–40°C

06828-045

34

32

30

28

26

24

22

20

OIP3 AND P1dB ( dBm)

18

16

14

06828-046

06828-047

2.0

1.8

1.6

1.4

1.2

1.0

0.8

NOISE FIGURE (dB)

0.6

0.4

0.2

0
3400 3420 3440 3460 3480 3500 3520 3540 3560 36003580

FREQUENCY (MHz)

Figure 48. Noise Figure vs. Frequency at 25°C, Multiple Devices

13.0

12.5

12.0

11.5

11.0

10.5

GAIN (dB)

10.0

9.5

9.0

8.5

8.0
3400 3420 3460 3480 3520 3560 36003440 3500 3540 3580

GAIN

P1dB

+25°C

–40°C

+25°C

+85°C

+25°C

–40°C

+85°C

FREQUENCY (MHz)

–40°C

+85°C

OIP3

Figure 49. Gain, OIP3, and P1dB vs. Temperature

35
34
33
32
31
30
29
28
27

OIP3 (dBm)

26
25
24
23
22
21

–14–12–10–8–6–4–20246810121416

P

OUT

Figure 50. OIP3 vs. Output Power (P

+25°C

+85°C

PER TONE (dBm)

OUT

) and Temperature

–40°C

06828-048

35

33

31

29

27

25

23

21

OIP3 AND P1dB ( dBm)

19

17

15

06828-049

06828-050

Rev. A | Page 14 of 24

ADL5521

DC CHARACTERISTICS

75
70
65
60
55
50
45
40
35

SUPPLY CURRENT ( mA)

30
25
20

–40–30–20–100 102030405060708090

Figure 51. Supply Current vs. Temperature, 3 V and 5 V

VPOS = 5V

VPOS = 3V

TEMPERATURE (°C)

06828-051

Rev. A | Page 15 of 24

ADL5521

V

BASIC CONNECTIONS

The basic connections for operating the ADL5521 are shown in
Figure 52. Capacitor C5 provides the power supply decoupling.
Inductor L1 (Coilcraft 0403HQ or 0402HP series) and Capacitor C1
(Murata High-Q GJM series or equivalent) provide the input
impedance matching, and the output impedance matching is
provided by either L2 or C3. Resistor R1 is used to set the supply
current, and the value of R1 is indirectly proportional to the
supply current (that is, increasing the value of R1 reduces the
supply current). The recommended external components for
the selected frequencies are listed in Tabl e 7.

For 5 V applications where the input power exceeds the input
compression point of approximately 7 dBm, a series resistor
(R2) of at least 8 Ω, with a high power rating (0.2 W minimum),
should be inserted on the VPOS line to protect the device from
the input power overdrive. In this case, reduce resistor R1 from

1.3 kΩ to 600 Ω to keep the supply current at around 60 mA.
With R2 = 8.2 Ω (Susumu RP1608S-8R2-F) and R1 = 600 Ω, the
gain and noise figure for the ADL5521 are mostly unchanged.
Tabl e 6 lists OIP3 and P1dB at selected frequencies. For 3 V
power supply applications, a series resistor is not necessary for
the expected input overdrive powers up to 20 dBm.

POS GND

R1

ADL5521

RFIN RFOUT

L1

C1

1 VBIAS
2RFIN
3NC
4NC

Z1

Figure 52. ADL5521 Basic Connections

8VPOS
7RFOUT
6NC
5NC

TR1

TR2

W1

R2

C5

100nF

L2

C3

06828-052

Table 6. ADL5521 Performance at VPOS = 5 V, 25°C with
R2 = 8.2 Ω and R1 = 600 Ω

Frequency
(MHz)

Noise
Figure (dB)

Gain
(dB)

P1dB
(dBm)

OIP3 (dBm)

= 0 dBm)

(P

OUT

900 0.9 20.8 20.8 34.0
1950 1.0 15.8 21.0 35.0
2600 1.0 13.0 20.6 35.0
3500 1.1 10.5 20.3 36.0

Rev. A | Page 16 of 24

ADL5521

V

m

EVALUATION BOARD

Figure 53 shows the schematic of the ADL5521 evaluation board.
The board is powered by a single supply, and dc bias can be
applied to the board through clip-on leads at VPOS and GND or
through a 2-pin connector, W1.

The evaluation board comes optimized at 1950 MHz from the
factory, but it can be easily modified to work at any frequency
between 400 MHz and 4 GHz. Tabl e 7 lists the recommended
components at various frequencies.

POS GND

R1

ADL5521

RFIN RFOUT

L1

C1

1 VBIAS
2RFIN
3NC
4NC

Z1

8VPOS
7RFOUT
6NC
5NC

Figure 53. Evaluation Board Schematic

TR1

TR2

W1

R2

06828-054

Figure 55. Evaluation Board Layout (Bottom View)

C5

100nF

L2

C4

DNP

C3

SOLDERING INFORMATION AND RECOMMENDED PCB LAND PATTERN

Figure 56 shows the recommended land pattern for ADL5521.
To minimize thermal impedance, the exposed pad on the
package underside is soldered down to a ground plane. If
multiple ground layers exist, they are stitched together using
vias (a minimum of five vias is recommended). Pin 3 to Pin 6
can be left unconnected or can be connected to ground. For

C2
0Ω

more information on land pattern design and layout, refer to
the AN-772 Application Note, A Design and Manufacturing
Guide for the Lead Frame Chip Scale Package (LFCSP).

2.03mm

06828-152

1

8

0.5m

0.71mm

1.85mm

4 5

1.53mm

1.78mm

06828-055

Figure 56. Recommended Land Pattern

06828-053

Figure 54. Evaluation Board Layout (Top View)

Table 7. Recommended Components and Positions of Matching Components for Basic Connections Tuned for Optimal Noise

1

C1
Frequency
(MHz)

(Size

0402)

C2
(Size

0402)

C3
(Size

0402)

C4
(Size

0402)

C5
(Size

0402)

L12
(Size

0403)

500 Open 0 Ω Open Open 100 nF 9 nH 12 nH 1.3 kΩ 0 Ω 0 0 C1 N/A
900 2.4 pF 0 Ω Open Open 100 nF 8.2 nH 3.4 nH 1.3 kΩ 0 Ω 0 0 C1 N/A
1300 2.7 pF 0 Ω 1.0 nF Open 100 nF 3.4 nH 0 Ω 1.3 kΩ 0 Ω 0 8.0 × 0.6 C1 6
1950 1.6 pF 0 Ω 1.0 nF Open 100 nF 1.0 nH 0 Ω 1.3 kΩ 0 Ω 2.5 × 0.6 5.5 × 0.6 C1 4
2140 1.6 pF 0 Ω 1.0 nF Open 100 nF 1.0 nH 0 Ω 1.3 kΩ 0 Ω 5.0 × 0.6 3.0 × 0.6 C1 2
2600 0.75 pF 0 Ω 1.0 nF Open 100 nF 1.0 nH 0 Ω 1.3 kΩ 0 Ω 8.0 × 0.6 0 C1 C3
3500 0.5 pF 0 Ω 1.0 nF Open 100 nF 2.4 pF5 0 Ω 1.3 kΩ 0 Ω 7.0 × 0.6 1 × 0.6 C1 1

1

The Murata High-Q GJM series capacitor is recommended for C1.

2

Coilcraft High Q 0403HQ or 0402HP inductors are recommended for L1 and L2.

3

If R2 = 8 Ω, reduce R1 to 600 Ω.

4

If R2 = 8 Ω, use a high power resistor (0.2 W rating minimum).

5

Note that at 3500 MHz, a capacitor, not an inductor, is used at L1.

Rev. A | Page 17 of 24

2

L2
(Size

0403)

3

R1
(Size

0603)

R24
(Size

0603)

TR1
(mm)

TR2
(mm)

C1
Position

C3
Position

ADL5521

TUNING THE ADL5521 FOR OPTIMAL NOISE FIGURE

The ADL5521 is a monolithic low noise amplifier (LNA) in a
3 mm × 3 mm LFCSP. The evaluation board, as shipped from
the factory, gives a noise figure of 0.9 dB over a bandwidth of
several hundred megahertz. The specific frequency where optimal
noise is reached depends on the tuning.

The bandwidth of the ADL5521 is 400 MHz to 4 GHz, although
noise figure degrades above 2.5 GHz as the gain begins to roll off.

This section is based on Analog Devices, Inc., lab measurements.
Although there are plots in which the Agilent Advanced Design
System (ADS) environment is used, the data in these plots comes
from Analog Devices lab measurements.

TUNING S22

Tuning of the LNA begins with S22 (output tuning). Tuning of
the LNA output is done by placing reactive components on the
bias line, referred to in the schematic in Figure 53 as VPOS.

On the LNA evaluation board, S22 tuning is achieved by either
the use of an inductor (L2) on the bias line or a shunt capacitor
(C3) on the bias line to ground. Typically, either L2 is required
or C3, but not both.

The evaluation board uses a slider on the bias line to make tuning
for S22 as easy as possible. The slider is an area of ground etch
adjacent to the bias line that is clear of solder mask. The bias
line in this area is also free of solder mask. This allows a capacitor
(C3) to be placed anywhere on the bias line to ground, which
provides easy and accurate tuning for S22.

Note that the PCB layout shows two capacitors, C3 and C4.
Typically, only one of these capacitors is needed for good S22
tuning.

The slider can be seen in the LNA PCB layout in Figure 57 as
the area near the red arrows to the right of the bias line. With a
0 Ω resistor in place of L2, moving a 1 nF capacitor from the top
to the bottom effectively tunes S22 from 1400 MHz to 3500 MHz.
Tabl e 8 shows the component values and placement required for
S22 tuning from 800 MHz to 3200 MHz. For lower frequencies,
higher values of L2 can be used to tune S22, and for frequencies
from 3.2 GHz to 4.0 GHz, smaller values of capacitors can be
used on the slider.

Table 8. Capacitor and Inductor Tuning and Placement for
LNA S22 Tuning

Frequency (MHz) L2 C3 C3 Placement

800 3.4 nH Open N/A
1400 0 Ω 1 nF 6
2000 0 Ω 1 nF 4
2400 0 Ω 1 nF 3
2800 0 Ω 1 nF 2
3200 0 Ω 1 nF 1

Figure 57. PCB Layout for LNA Evaluation Board (Note Slider on Bias Line

Rev. A | Page 18 of 24

06828-056

with Capacitor Placement for S22 Tuning Noted by Arrows)

ADL5521

TUNING THE LNA INPUT FOR OPTIMAL GAIN

LNAs are generally tuned for either gain or noise optimization,
or some trade-off between the two. One figure of merit of an LNA
is how much trade-off must be made for one of these
parameters to optimize the other. With the ADL5521, an S11 of
6 dB to 8 dB at the input to the matching network can still be
achieved typically when optimizing for noise.

For optimal gain matching, the goal is to use a matching network
that converts the input impedance of the LNA to the characteristic
impedance of the system, typically 50 Ω. Correct tuning for gain
matching results in a conjugate match. That is, the impedance of
the matching network at the LNA input, looking back toward
the generator, is always the complex conjugate of the LNA input
impedance when matched for gain.

Once S11*, the complex conjugate of S11, is known, a matching
circuit must be found that transforms the 50 Ω system impedance
into the conjugate S11 impedance. To do this, the designer starts at
the origin of the Smith Chart circle and finds components that
move the 50 Ω match to S11*.

The related impedances for gain matching are shown in Figure 58.
A Smith Chart representation of the conjugate match is shown
in Figure 59.

50Ω

MATCHING
NETWORK

50Ω

Figure 58. Matching LNA Input for Gain

S11

S11*

LNA

06828-057

TUNING THE LNA INPUT FOR OPTIMAL NOISE FIGURE

The point in the Smith Chart at which matching for optimal

OPT

OPT

is a

.

noise occurs is typically referred to as gamma optimal or Γ
Typically, it is significantly different from the gain matching
point; finding Γ

is not as obvious as the gain match. Γ

OPT

function of the semiconductor structure and characteristics of
the LNA. The fabrication facility that produces the LNA typically
has this information. Γ

can also be determined by doing

OPT

source pull testing in the lab.

Noise matching for the ADL5521 is very easy because the area
of the Smith Chart where the noise figure is optimal or near
optimal is not confined to a narrow area around Γ

. This is

OPT

very advantageous because it means that component variations
play a smaller part in the board-to-board variation of noise figure.

The matching area for optimal noise for the ADL5521 is shown
in Figure 60. Note that textbooks usually define noise circles as
a conjugate match. However, for the purpose of this data sheet,
the circle is a direct match. To find the correct matching circuit,
the designer must start with the S11 of the LNA and select
components that move the S11 to within this circle.

An important aspect of the overall ADL5521 ease of tuning is
that as long as S22 is matched for a particular frequency, the
noise matching area remains very consistent in its placement for
that frequency. If S22 is matched, take the measured S11 and
move it into the red circle shown in Figure 60 for optimal noise
matching.

1

S11*

S11

Figure 59. Smith Chart Representation of Conjugate Match

06828-058

Rev. A | Page 19 of 24

0.5

0.2

0.2

0.2

0.5

Figure 60. Area of Optimal Noise Matching for ADL5521

0.5 1 5 10

1

5

10

10

5

06828-059

ADL5521

S11 OF THE LNA WITH S22 MATCHED

To determine the correct matching circuit for optimal noise,
look at the results of S11 for the various frequencies at which
S22 was tuned earlier in the Tun i ng S 22 section. Once S11
is determined for a particular frequency, find the matching
components that provided that match. Figure 62 and Figure 63
show S11 for the various frequencies. Again, these measurements
are all based on S22 being matched at that particular frequency.
Note that, for the examples shown in Figure 62 and Figure 63, S11
is either in the lower left quadrant of the Smith Chart or slightly
into the upper left. To move the impedance in the given noise
circle, a series L component at the LNA input is required. The L
values in the examples differ, but a correct L value moves the match
along the constant R circle up into the upper left quadrant of the
Smith Chart.

A shunt capacitor can then be added to move the match along a
constant admittance line, down and to the right, directly into
the center of the noise circle given in Figure 60.

The solution for the structure of the match for the examples
in Figure 62 and Figure 63 is a series L to the input of the LNA
and a shunt capacitor at the generator end of this inductor. The
recommended components for matching at various frequencies
are shown in Ta bl e 7 .

An example of the effect of the series L, shunt C match, based
on the 800 MHz example, is given in Figure 61. This example
uses the output from the Agilent ADS Smith Chart tool.

M1
FREQUENCY 400M Hz
S11 = 0.877/–44.639
IMPEDANCE = Z0 × (0.443 – j 2.365)

M2
FREQUENCY 2GHz
S11 = 0.615/–170.569
IMPEDANCE = Z0 × (0.240 – j 0.078)

M2

M1

FREQUENCY (400M H z TO 4GHz)

Figure 62. S11 of ADL5521 with S22 Matched at 2 GHz

M1
FREQUENCY 400M Hz
S11 = 0.864/–40.186
IMPEDANCE = Z0 × (0.594 – j2.615)

M2
FREQUENCY 3. 2GHz
S11 = 0.595/163.164

M2

IMPEDANCE = Z0 × (0.259 + j 0.138)

06828-061

Figure 61. Example of Series L, Shunt C Matching Network for Γ

OPT

M1

FREQUENCY (400M H z TO 4GHz)

Figure 63. S11 of ADL5521 with S22 Matched at 3.2 GHz

06828-062

06828-060

Rev. A | Page 20 of 24

ADL5521

OUTLINE DIMENSIONS

3.25

3.00 SQ

INDICATOR

0.90 MAX

0.85 NOM

SEATING

PLANE

PIN 1

12° MAX

2.75

TOP

VIEW

0.70 MAX

0.65TYP

0.30

0.23

0.18

2.95

2.75 SQ

2.55

0.05 MAX

0.01 NOM

0.20 REF

0.60 MAX

Figure 64. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]

3 mm × 3 mm Body, Very Thin, Dual Lead

(CP-8-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

ADL5521ACPZ-R71 −40°C to +85°C 8-Lead LFCSP_VD, 7” Tape and Reel CP-8-2 Q1G
ADL5521-EVALZ1 Evaluation Board

1

Z = RoHS Compliant Part.

0.60 MAX

5

EXPOSED

PAD

(BOTT OM VIEW)

0.50

0.40

0.30

4

FOR PROPE R CONNECTION O F
THE EXPOSE D PAD, REF ER T O
THE PIN CONFIGURATION AND
FUNCTION DE SCRIPTIO NS
SECTION OF THIS DATA SHEET.

0.50
BSC

8

1.60

1.45

1.30

1

1.89

1.74

1.59

PIN 1
INDICATOR

72408-B

Rev. A | Page 21 of 24

ADL5521

NOTES

Rev. A | Page 22 of 24

ADL5521

NOTES

Rev. A | Page 23 of 24

ADL5521

NOTES

©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06828-0-9/09(A)

Rev. A | Page 24 of 24